Lines Matching +full:0 +full:xffffffff
35 OP_RD = 0x1, /* read a single register */
150 MODE_ASIC = 0x00000001,
151 MODE_FPGA = 0x00000002,
152 MODE_EMUL = 0x00000004,
153 MODE_E2 = 0x00000008,
154 MODE_E3 = 0x00000010,
155 MODE_PORT2 = 0x00000020,
156 MODE_PORT4 = 0x00000040,
157 MODE_SF = 0x00000080,
158 MODE_MF = 0x00000100,
159 MODE_MF_SD = 0x00000200,
160 MODE_MF_SI = 0x00000400,
161 MODE_MF_AFEX = 0x00000800,
162 MODE_E3_A0 = 0x00001000,
163 MODE_E3_B0 = 0x00002000,
164 MODE_COS3 = 0x00004000,
165 MODE_COS6 = 0x00008000,
166 MODE_LITTLE_ENDIAN = 0x00010000,
167 MODE_BIG_ENDIAN = 0x00020000,
221 #define ECORE_ETH_Q 0
268 for (vnic = 0; vnic < num_vnics; vnic++) { in ecore_map_q_cos()
271 uint32_t q_bit_map = 1 << (pf_q_num & 0x1f); in ecore_map_q_cos()
287 (E2/E3A0 only, valid COS values are 0/1) */ in ecore_map_q_cos()
291 q_bit_map = 1 << (2 * (pf_q_num & 0xf)); in ecore_map_q_cos()
401 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { in ecore_init_max()
462 vnicWeightSum = 0; in ecore_init_min()
464 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) in ecore_init_min()
468 if (vnicWeightSum > 0) { in ecore_init_min()
470 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { in ecore_init_min()
494 uint32_t cosWeightSum = 0; in ecore_init_fw_wrr()
498 for (cos = 0; cos < MAX_COS_NUMBER; cos++) in ecore_init_fw_wrr()
501 if (cosWeightSum > 0) { in ecore_init_fw_wrr()
503 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { in ecore_init_fw_wrr()
509 for (cos = 0; cos < MAX_COS_NUMBER; cos++) { in ecore_init_fw_wrr()
541 ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init)); in ecore_init_cmng()
564 #define INITOP_SET 0 /* set the HW directly */
583 #define ILT_CLIENT_SKIP_INIT 0x1
584 #define ILT_CLIENT_SKIP_MEM 0x2
591 #define ILT_CLIENT_CDU 0
644 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
646 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
648 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
649 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
650 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
655 BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff,
656 0x7ffffff),
657 BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
658 0xffffffff),
659 BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff),
660 BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0),
661 BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0),
662 BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff),
663 BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff),
664 BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff),
665 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
666 BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff),
667 BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f),
668 BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3),
669 BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3),
671 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
672 {0xf, 0xf, 0xf, 0xf}, "UPB"},
674 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
675 {0xf, 0xf, 0xf, 0xf}, "XPB"},
676 BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7),
677 BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f),
678 BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f),
679 BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1),
680 BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf),
681 BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf),
682 BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff),
683 BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff),
684 BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f),
685 BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
686 BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
687 BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
688 BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff),
689 BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
690 BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
691 BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff),
692 BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff),
693 BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
694 0xffffffff),
695 BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
696 BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
697 0xffffffff),
698 BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
699 BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
700 0xffffffff),
701 BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f),
702 BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff,
703 0xffffffff),
704 BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f),
749 for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) { in ecore_set_mcp_parity()
777 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { in ecore_disable_blocks_parity()
806 REG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
807 REG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
808 REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
809 REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
811 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { in ecore_clear_blocks_parity()
819 "Parity errors in %s: 0x%x\n", in ecore_clear_blocks_parity()
828 ECORE_MSG(sc, "Parity error in MCP: 0x%x\n", in ecore_clear_blocks_parity()
837 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780); in ecore_clear_blocks_parity()
844 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { in ecore_enable_blocks_parity()