Lines Matching +full:0 +full:xd4000000
33 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
39 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
40 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
41 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
47 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
48 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
49 #define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
61 #define PIN_CFG_NA 0x00000000
62 #define PIN_CFG_GPIO0_P0 0x00000001
63 #define PIN_CFG_GPIO1_P0 0x00000002
64 #define PIN_CFG_GPIO2_P0 0x00000003
65 #define PIN_CFG_GPIO3_P0 0x00000004
66 #define PIN_CFG_GPIO0_P1 0x00000005
67 #define PIN_CFG_GPIO1_P1 0x00000006
68 #define PIN_CFG_GPIO2_P1 0x00000007
69 #define PIN_CFG_GPIO3_P1 0x00000008
70 #define PIN_CFG_EPIO0 0x00000009
71 #define PIN_CFG_EPIO1 0x0000000a
72 #define PIN_CFG_EPIO2 0x0000000b
73 #define PIN_CFG_EPIO3 0x0000000c
74 #define PIN_CFG_EPIO4 0x0000000d
75 #define PIN_CFG_EPIO5 0x0000000e
76 #define PIN_CFG_EPIO6 0x0000000f
77 #define PIN_CFG_EPIO7 0x00000010
78 #define PIN_CFG_EPIO8 0x00000011
79 #define PIN_CFG_EPIO9 0x00000012
80 #define PIN_CFG_EPIO10 0x00000013
81 #define PIN_CFG_EPIO11 0x00000014
82 #define PIN_CFG_EPIO12 0x00000015
83 #define PIN_CFG_EPIO13 0x00000016
84 #define PIN_CFG_EPIO14 0x00000017
85 #define PIN_CFG_EPIO15 0x00000018
86 #define PIN_CFG_EPIO16 0x00000019
87 #define PIN_CFG_EPIO17 0x0000001a
88 #define PIN_CFG_EPIO18 0x0000001b
89 #define PIN_CFG_EPIO19 0x0000001c
90 #define PIN_CFG_EPIO20 0x0000001d
91 #define PIN_CFG_EPIO21 0x0000001e
92 #define PIN_CFG_EPIO22 0x0000001f
93 #define PIN_CFG_EPIO23 0x00000020
94 #define PIN_CFG_EPIO24 0x00000021
95 #define PIN_CFG_EPIO25 0x00000022
96 #define PIN_CFG_EPIO26 0x00000023
97 #define PIN_CFG_EPIO27 0x00000024
98 #define PIN_CFG_EPIO28 0x00000025
99 #define PIN_CFG_EPIO29 0x00000026
100 #define PIN_CFG_EPIO30 0x00000027
101 #define PIN_CFG_EPIO31 0x00000028
104 #define EPIO_CFG_NA 0x00000000
105 #define EPIO_CFG_EPIO0 0x00000001
106 #define EPIO_CFG_EPIO1 0x00000002
107 #define EPIO_CFG_EPIO2 0x00000003
108 #define EPIO_CFG_EPIO3 0x00000004
109 #define EPIO_CFG_EPIO4 0x00000005
110 #define EPIO_CFG_EPIO5 0x00000006
111 #define EPIO_CFG_EPIO6 0x00000007
112 #define EPIO_CFG_EPIO7 0x00000008
113 #define EPIO_CFG_EPIO8 0x00000009
114 #define EPIO_CFG_EPIO9 0x0000000a
115 #define EPIO_CFG_EPIO10 0x0000000b
116 #define EPIO_CFG_EPIO11 0x0000000c
117 #define EPIO_CFG_EPIO12 0x0000000d
118 #define EPIO_CFG_EPIO13 0x0000000e
119 #define EPIO_CFG_EPIO14 0x0000000f
120 #define EPIO_CFG_EPIO15 0x00000010
121 #define EPIO_CFG_EPIO16 0x00000011
122 #define EPIO_CFG_EPIO17 0x00000012
123 #define EPIO_CFG_EPIO18 0x00000013
124 #define EPIO_CFG_EPIO19 0x00000014
125 #define EPIO_CFG_EPIO20 0x00000015
126 #define EPIO_CFG_EPIO21 0x00000016
127 #define EPIO_CFG_EPIO22 0x00000017
128 #define EPIO_CFG_EPIO23 0x00000018
129 #define EPIO_CFG_EPIO24 0x00000019
130 #define EPIO_CFG_EPIO25 0x0000001a
131 #define EPIO_CFG_EPIO26 0x0000001b
132 #define EPIO_CFG_EPIO27 0x0000001c
133 #define EPIO_CFG_EPIO28 0x0000001d
134 #define EPIO_CFG_EPIO29 0x0000001e
135 #define EPIO_CFG_EPIO30 0x0000001f
136 #define EPIO_CFG_EPIO31 0x00000020
146 uint8_t part_num[16]; /* 0x104 */
148 uint32_t config; /* 0x114 */
149 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
150 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
151 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
152 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
154 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
156 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
158 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
159 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
161 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
165 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
166 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
167 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
168 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
169 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
171 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
172 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
174 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
175 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
177 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
180 backwards compatibility, value of 0 is disabling this feature.
181 That means that though 0 is a valid value, it cannot be
183 #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000
186 #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000
188 #define SHARED_HW_CFG_LED_MAC1 0x00000000
189 #define SHARED_HW_CFG_LED_PHY1 0x00010000
190 #define SHARED_HW_CFG_LED_PHY2 0x00020000
191 #define SHARED_HW_CFG_LED_PHY3 0x00030000
192 #define SHARED_HW_CFG_LED_MAC2 0x00040000
193 #define SHARED_HW_CFG_LED_PHY4 0x00050000
194 #define SHARED_HW_CFG_LED_PHY5 0x00060000
195 #define SHARED_HW_CFG_LED_PHY6 0x00070000
196 #define SHARED_HW_CFG_LED_MAC3 0x00080000
197 #define SHARED_HW_CFG_LED_PHY7 0x00090000
198 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
199 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
200 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
201 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
202 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
203 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000
205 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
206 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
207 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
209 #define SHARED_HW_CFG_ATC_MASK 0x80000000
210 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
211 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
213 uint32_t config2; /* 0x118 */
215 #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100
217 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
218 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
220 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
221 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
222 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
224 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
228 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
229 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
230 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
232 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
234 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
235 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
236 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
237 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
246 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
248 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
249 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
250 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
253 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
255 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
256 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
257 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
258 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
261 tl_control_0 (register 0x2800) */
262 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
263 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
264 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
282 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
283 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
286 uint32_t config_3; /* 0x11C */
287 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F
288 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0
292 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00
294 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000
295 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100
297 uint32_t ump_nc_si_config; /* 0x120 */
298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
302 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
303 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
309 uint32_t board; /* 0x124 */
310 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
311 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
325 uint32_t wc_lane_config; /* 0x128 */
326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
333 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
334 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
335 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
336 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
340 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
341 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
342 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
343 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
345 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
346 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
347 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
348 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
358 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
359 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000
366 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
369 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF
370 #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0
372 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000
376 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF
377 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0
379 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000
383 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF
384 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
385 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00
387 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000
389 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000
393 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF
394 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
395 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00
397 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000
399 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000
403 uint32_t mac_lower; /* 0x140 */
404 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF
405 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
415 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
416 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
418 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
425 uint32_t vf_config; /* 0x15C */
426 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
429 uint32_t mf_pci_id; /* 0x160 */
430 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
431 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
434 uint32_t sfp_ctrl; /* 0x164 */
435 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
436 #define PORT_HW_CFG_TX_LASER_SHIFT 0
437 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
438 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
439 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
440 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
441 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
444 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
450 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
454 uint32_t e3_sfp_ctrl; /* 0x168 */
455 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
456 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
459 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
464 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
469 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
476 uint32_t e3_cmn_pin_cfg; /* 0x16C */
477 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
478 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
482 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
489 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
494 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
495 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
502 uint32_t e3_cmn_pin_cfg1; /* 0x170 */
503 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
504 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
507 uint32_t generic_features; /* 0x174 */
508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001
509 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000
511 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001
513 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
514 * LOM recommended and tested value is 0xBEB2. Using a different
517 uint32_t sfi_tap_values; /* 0x178 */
518 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF
519 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0
522 * value is 0x2. LOM recommended and tested value is 0x2. Using a
525 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
528 #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
532 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000
536 #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000
539 uint32_t reserved0[5]; /* 0x17c */
541 uint32_t aeu_int_mask; /* 0x190 */
543 uint32_t media_type; /* 0x194 */
544 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
545 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
547 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
550 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
558 uint16_t xgxs_config_rx[4]; /* 0x198 */
559 uint16_t xgxs_config_tx[4]; /* 0x1A0 */
564 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
565 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
575 uint32_t wwpn_for_npiv_config; /* 0x1C0 */
576 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001
577 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0
578 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000
579 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001
582 uint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */
583 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF
584 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0
591 uint32_t pf_allocation; /* 0x280 */
592 /* number of vfs per PF, if 0 - sriov disabled */
593 #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF
594 #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0
596 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
598 uint32_t xgbt_phy_cfg; /* 0x284 */
599 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
600 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
602 uint32_t default_cfg; /* 0x288 */
603 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
604 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
605 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
606 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
607 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
608 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
610 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
612 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
613 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
614 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
615 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
617 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
619 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
620 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
621 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
622 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
624 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
626 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
627 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
628 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
629 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
637 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
639 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
640 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
641 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
642 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
643 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
644 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
645 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
646 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
647 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
648 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
650 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
652 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
653 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
654 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
655 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
656 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
657 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
658 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
659 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
660 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
663 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
665 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
666 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
669 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
671 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
672 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
675 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
677 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
678 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
679 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
680 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
681 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
682 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
685 #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000
687 #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000
688 #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000
689 #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000
690 #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000
691 #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000
692 #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000
694 uint32_t speed_capability_mask2; /* 0x28C */
695 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
696 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
697 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
698 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002
699 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
700 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
701 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
702 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020
703 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
704 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
706 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
708 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
709 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000
710 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000
711 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
712 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
713 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000
714 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
715 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
722 uint32_t multi_phy_config; /* 0x290 */
723 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
724 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
725 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
726 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
727 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
728 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
729 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
733 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
735 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
736 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
740 uint32_t external_phy_config2; /* 0x294 */
741 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
742 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
745 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
747 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
748 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
749 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
750 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
751 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
752 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
753 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
754 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
755 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
756 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
757 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
758 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
759 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
760 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
761 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
762 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
763 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
764 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
765 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858 0x00001200
766 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
767 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
772 uint16_t xgxs_config2_rx[4]; /* 0x296 */
773 uint16_t xgxs_config2_tx[4]; /* 0x2A0 */
776 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
777 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
779 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
781 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
783 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
785 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
786 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
787 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
788 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
790 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000
794 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
795 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
796 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
800 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF
801 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
803 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00
805 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
806 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
807 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
808 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
809 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
810 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
811 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
812 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
813 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
814 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
815 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
816 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
817 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
818 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
819 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
820 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
821 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
822 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
823 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858 0x00001200
824 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
825 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
826 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
828 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000
831 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000
833 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
834 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
835 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
836 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
839 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF
840 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
841 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
842 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
843 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
844 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
845 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
846 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
847 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
848 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
849 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
851 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000
853 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
854 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
855 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
856 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
857 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
858 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
859 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
860 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
861 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
864 uint32_t backup_mac_upper; /* 0x2B4 */
865 uint32_t backup_mac_lower; /* 0x2B8 */
875 uint32_t config; /* 0x450 */
876 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
880 0x00000002
882 0x00000000
884 0x00000002
886 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
887 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
888 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
890 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
894 high means only SF, 0 is according to CLP configuration */
895 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
897 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
898 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
899 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
900 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
901 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
902 #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
903 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
904 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
907 #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000
910 #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000
913 #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000
915 #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000
916 #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000
920 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000
924 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000
933 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
936 #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F
937 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0
938 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000
939 #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001
940 #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002
941 #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003
942 #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004
943 #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005
944 #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006
945 #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007
946 #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008
947 #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009
948 #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a
949 #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b
950 #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c
951 #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d
952 #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e
953 #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f
954 #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0
956 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000
957 #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010
958 #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020
959 #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030
960 #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040
961 #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050
962 #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060
963 #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070
964 #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080
965 #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090
966 #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0
967 #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0
968 #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0
969 #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0
970 #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0
971 #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0
973 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
974 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
975 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
977 #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200
979 #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000
980 #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200
982 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00
984 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000
985 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400
986 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
987 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00
989 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
991 #define PORT_FEATURE_WOL_ENABLED 0x01000000
992 #define PORT_FEATURE_MBA_ENABLED 0x02000000
993 #define PORT_FEATURE_MFW_ENABLED 0x04000000
996 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
997 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
998 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
1002 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
1005 0x00000000
1007 0x20000000
1008 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
1009 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
1013 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
1016 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
1017 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
1018 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
1019 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
1020 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
1021 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
1022 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
1023 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
1025 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
1028 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
1029 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
1030 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
1031 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
1033 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000
1035 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
1036 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
1037 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
1038 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
1039 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
1040 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
1041 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
1042 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
1043 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
1044 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
1045 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
1046 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
1047 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
1048 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
1049 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
1050 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
1051 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000
1053 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
1055 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
1056 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
1057 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
1058 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
1059 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000
1061 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
1062 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000
1063 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000
1064 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000
1065 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000
1066 #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000
1067 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000
1068 #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000
1069 #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000
1071 uint32_t Reserved0; /* 0x460 */
1074 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF
1075 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1076 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1077 #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000
1078 #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000
1079 #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000
1083 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1087 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F
1088 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1089 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1090 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1091 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1092 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1093 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1094 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1095 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1096 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1097 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1098 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1099 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1100 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1101 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1102 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1103 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1104 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1108 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1110 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1111 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1112 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1113 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1114 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1115 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500
1116 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600
1117 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700
1119 #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000
1121 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1122 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000
1123 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000
1124 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1125 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1126 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1127 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1128 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1129 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1131 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1134 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1136 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1137 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1138 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1147 uint32_t link_config2; /* 0x47C */
1151 uint32_t mfw_wol_link_cfg2; /* 0x480 */
1155 uint32_t eee_power_mode; /* 0x484 */
1156 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1157 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1158 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1159 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1160 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1161 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1164 uint32_t Reserved2[16]; /* 0x48C */
1187 uint32_t temperature_monitor1; /* 0x4000 */
1188 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F
1189 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0
1192 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00
1196 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000
1198 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000
1199 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000
1200 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000
1201 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000
1202 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000
1203 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000
1204 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000
1205 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000
1206 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000
1207 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000
1208 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000
1209 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000
1210 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000
1211 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000
1212 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000
1213 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000
1214 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000
1215 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000
1216 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000
1217 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000
1218 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000
1219 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000
1220 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000
1221 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000
1222 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000
1223 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000
1224 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000
1225 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000
1226 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000
1227 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000
1228 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000
1229 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000
1230 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000
1233 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000
1235 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000
1236 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000
1237 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000
1238 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000
1239 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000
1240 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000
1241 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000
1242 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000
1243 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000
1244 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000
1245 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000
1246 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000
1247 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000
1248 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000
1249 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000
1250 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000
1251 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000
1252 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000
1253 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000
1254 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000
1255 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000
1256 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000
1257 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000
1258 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000
1259 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000
1260 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000
1261 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000
1262 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000
1263 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000
1264 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000
1265 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000
1266 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000
1267 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000
1271 uint32_t temperature_monitor2; /* 0x4004 */
1272 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF
1273 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0
1276 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000
1278 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED 0x00000000
1279 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000
1282 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000
1286 uint32_t mfw_cfg; /* 0x4008 */
1287 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF
1288 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0
1289 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000
1290 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001
1293 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100
1295 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000
1296 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100
1299 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200
1301 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000
1302 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200
1305 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400
1307 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000
1308 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400
1313 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000
1315 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000
1316 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000
1318 uint32_t smbus_config; /* 0x400C */
1319 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF
1320 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0
1323 uint32_t board_cfg; /* 0x4010 */
1324 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F
1325 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0
1326 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000
1327 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008
1328 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009
1329 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a
1330 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b
1331 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c
1332 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d
1333 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e
1334 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f
1337 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100
1339 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000
1340 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100
1343 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200
1345 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000
1346 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200
1349 revision ID will set to B1=='0x11' */
1350 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400
1352 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000
1353 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400
1356 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800
1358 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000
1359 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800
1361 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000
1363 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000
1364 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000
1365 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000
1366 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000
1368 uint32_t temperature_report; /* 0x4014 */
1369 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F
1370 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0
1373 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00
1376 /* wwn node prefix to be used (unless value is 0) */
1377 uint32_t wwn_prefix; /* 0x4018 */
1378 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF
1379 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0
1381 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00
1384 /* wwn port prefix to be used (unless value is 0) */
1385 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000
1388 /* wwn port prefix to be used (unless value is 0) */
1389 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000
1393 uint32_t dbg_cfg_flags; /* 0x401C */
1394 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF
1395 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0
1396 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001
1397 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002
1398 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004
1399 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008
1400 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010
1401 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020
1402 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040
1403 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080
1404 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100
1405 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200
1406 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400
1407 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800
1408 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000
1409 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000
1410 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000
1411 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000
1412 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000
1413 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000
1414 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000
1415 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000
1420 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000
1422 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000
1423 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000
1426 uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */
1427 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007
1428 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0
1431 uint32_t iffe_features; /* 0x4024 */
1432 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001
1433 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0
1434 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000
1435 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001
1438 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E
1442 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010
1444 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000
1445 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010
1448 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020
1450 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000
1451 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020
1454 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000
1456 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000
1457 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000
1460 uint32_t current_iffe_mask; /* 0x4028 */
1461 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E
1465 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010
1467 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000
1468 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010
1471 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020
1473 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000
1474 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020
1476 /* FW set this pin to "0" (assert) these signal if either of its MAC
1480 uint32_t threshold_pin; /* 0x402C */
1481 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF
1482 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0
1483 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00
1485 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000
1489 uint32_t mac_threshold_val; /* 0x4030 */
1490 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF
1491 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0
1492 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00
1494 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000
1498 uint32_t phy_threshold_val; /* 0x4034 */
1499 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF
1500 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0
1501 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00
1503 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000
1509 uint32_t host_pin; /* 0x4038 */
1510 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF
1511 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0
1512 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00
1514 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000
1516 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000
1520 uint32_t manufacture_ver; /* 0x403C */
1523 uint32_t manufacture_data; /* 0x4040 */
1526 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000
1528 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000
1529 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000
1532 uint32_t mcp_crash_dump; /* 0x4044 */
1533 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF
1534 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0
1535 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000
1536 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001
1539 uint32_t mbi_version; /* 0x4048 */
1542 uint32_t mbi_date; /* 0x404C */
1550 #define FUNC_0 0
1562 #define VN_0 0
1586 #define MFW_TRACE_SIGNATURE 0x54524342
1596 #define LINK_STATUS_NONE (0<<0)
1597 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1598 #define LINK_STATUS_LINK_UP 0x00000001
1599 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1600 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1617 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1618 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1620 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1621 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1622 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1624 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1625 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1626 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1627 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1628 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1629 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1630 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1632 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1633 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1635 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1636 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1638 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1639 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1644 #define LINK_STATUS_SERDES_LINK 0x00100000
1646 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1647 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1648 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1649 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1651 #define LINK_STATUS_PFC_ENABLED 0x20000000
1653 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1654 #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1669 #define DRV_MSG_CODE_MASK 0xffff0000
1670 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1671 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1672 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1673 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1674 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1675 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1676 #define DRV_MSG_CODE_DCC_OK 0x30000000
1677 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1678 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1679 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1680 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1681 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1682 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1683 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1684 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1685 #define DRV_MSG_CODE_OEM_OK 0x00010000
1686 #define DRV_MSG_CODE_OEM_FAILURE 0x00020000
1687 #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000
1688 #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000
1695 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1696 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1697 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1698 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1699 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1700 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1701 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1702 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
1703 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1704 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1706 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1707 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1708 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1710 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1712 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1713 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1714 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1715 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1716 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1718 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1719 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1721 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1723 #define DRV_MSG_CODE_RMMOD 0xdb000000
1724 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f
1726 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1727 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1728 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1730 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1732 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1733 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1735 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1736 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1737 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1738 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1740 #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000
1741 #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000
1743 #define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000
1745 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1747 #define DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000
1750 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1751 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1753 #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001
1754 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1756 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1757 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
1759 #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001
1760 #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002
1761 #define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003
1763 #define DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001
1764 #define DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002
1765 #define DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003
1766 #define DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004
1767 #define DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005
1770 #define FW_MSG_CODE_MASK 0xffff0000
1771 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1772 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1773 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1774 /* Load common chip is supported from bc 6.0.0 */
1775 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1776 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1778 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1779 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1780 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1781 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1782 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1783 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1784 #define FW_MSG_CODE_DCC_DONE 0x30100000
1785 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1786 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1787 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1788 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1789 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1790 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1791 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1792 #define FW_MSG_CODE_NO_KEY 0x80f00000
1793 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1794 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1795 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1796 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1797 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1798 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1799 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1800 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1801 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1802 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1803 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1805 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1806 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1807 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1808 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1809 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1811 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1812 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1814 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1816 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000
1818 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1819 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1821 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1823 #define FW_MSG_CODE_FLR_ACK 0x02000000
1824 #define FW_MSG_CODE_FLR_NACK 0x02100000
1826 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1827 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1828 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1829 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1831 #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000
1832 #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000
1834 #define FW_MSG_CODE_OEM_ACK 0x00010000
1835 #define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000
1837 #define FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000
1839 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1843 #define FW_PARAM_INVALID_IMG 0xffffffff
1846 #define DRV_PULSE_SEQ_MASK 0x00007fff
1847 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1852 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1860 #define MCP_PULSE_SEQ_MASK 0x00007fff
1861 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1864 #define MCP_EVENT_MASK 0xffff0000
1865 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1871 #define DRV_STATUS_PMF 0x00000001
1872 #define DRV_STATUS_VF_DISABLED 0x00000002
1873 #define DRV_STATUS_SET_MF_BW 0x00000004
1874 #define DRV_STATUS_LINK_EVENT 0x00000008
1876 #define DRV_STATUS_OEM_EVENT_MASK 0x00000070
1877 #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010
1878 #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020
1879 #define DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040
1881 #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080
1883 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1884 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1885 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1886 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1887 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1888 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1889 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1891 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1892 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1893 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1894 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1895 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1896 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1897 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1899 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1901 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1904 #define VIRT_MAC_SIGN_MASK 0xffff0000
1905 #define VIRT_MAC_SIGNATURE 0x564d0000
1928 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1930 #define SHARED_MF_CLP_EXIT 0x00000001
1932 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1939 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1940 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1951 /* function 0 of each port cannot be hidden */
1952 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1954 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1955 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1956 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1957 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1958 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1962 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1963 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1965 #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060
1966 #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000
1967 #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020
1968 #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040
1971 /* 0 - low priority, 3 - high priority */
1972 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1974 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1977 /* value range - 0..100, increments in 100Mbps */
1978 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1980 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1981 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1983 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1986 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1987 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1990 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1993 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1994 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1998 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
2002 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
2003 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
2004 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
2006 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
2007 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
2011 /* number of vfs in function, if 0 - sriov disabled */
2012 #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF
2013 #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0
2017 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
2025 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F
2026 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
2027 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
2028 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
2029 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
2030 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
2031 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080
2046 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
2056 struct shared_mf_cfg shared_mf_config; /* 0x4 */
2058 /* 0x10*2=0x20 */
2060 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
2065 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
2066 }; /* 0x224 */
2073 uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
2074 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
2077 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
2078 #define SHR_MEM_VALIDITY_MB 0x00200000
2079 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
2080 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
2082 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
2083 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
2084 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
2085 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
2087 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
2088 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
2089 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
2090 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
2091 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
2092 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
2094 struct shm_dev_info dev_info; /* 0x8 (0x438) */
2096 license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
2099 uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */
2100 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
2102 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
2108 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
2111 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
2114 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
2170 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
2176 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
2182 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
2199 } while (0)
2219 #define FCOE_APP_IDX 0
2239 #define DCBX_PFC_PRI_0 0x01
2240 #define DCBX_PFC_PRI_1 0x02
2241 #define DCBX_PFC_PRI_2 0x04
2242 #define DCBX_PFC_PRI_3 0x08
2243 #define DCBX_PFC_PRI_4 0x10
2244 #define DCBX_PFC_PRI_5 0x20
2245 #define DCBX_PFC_PRI_6 0x40
2246 #define DCBX_PFC_PRI_7 0x80
2255 #define DCBX_PFC_PRI_0 0x01
2256 #define DCBX_PFC_PRI_1 0x02
2257 #define DCBX_PFC_PRI_2 0x04
2258 #define DCBX_PFC_PRI_3 0x08
2259 #define DCBX_PFC_PRI_4 0x10
2260 #define DCBX_PFC_PRI_5 0x20
2261 #define DCBX_PFC_PRI_6 0x40
2262 #define DCBX_PFC_PRI_7 0x80
2271 #define DCBX_APP_ENTRY_VALID 0x01
2272 #define DCBX_APP_ENTRY_SF_MASK 0x30
2274 #define DCBX_APP_SF_ETH_TYPE 0x10
2275 #define DCBX_APP_SF_PORT 0x20
2276 #define DCBX_APP_PRI_0 0x01
2277 #define DCBX_APP_PRI_1 0x02
2278 #define DCBX_APP_PRI_2 0x04
2279 #define DCBX_APP_PRI_3 0x08
2280 #define DCBX_APP_PRI_4 0x10
2281 #define DCBX_APP_PRI_5 0x20
2282 #define DCBX_APP_PRI_6 0x40
2283 #define DCBX_APP_PRI_7 0x80
2286 #define DCBX_APP_ENTRY_VALID 0x01
2287 #define DCBX_APP_ENTRY_SF_MASK 0x30
2289 #define DCBX_APP_SF_ETH_TYPE 0x10
2290 #define DCBX_APP_SF_PORT 0x20
2331 #define LLDP_TX_ONLY 0x01
2332 #define LLDP_RX_ONLY 0x02
2333 #define LLDP_TX_RX 0x03
2334 #define LLDP_DISABLED 0x04
2341 #define LLDP_TX_ONLY 0x01
2342 #define LLDP_RX_ONLY 0x02
2343 #define LLDP_TX_RX 0x03
2344 #define LLDP_DISABLED 0x04
2377 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
2378 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
2379 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
2380 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
2381 #define DCBX_ETS_RECO_VALID 0x00000010
2382 #define DCBX_ETS_WILLING 0x00000020
2383 #define DCBX_PFC_WILLING 0x00000040
2384 #define DCBX_APP_WILLING 0x00000080
2385 #define DCBX_VERSION_CEE 0x00000100
2386 #define DCBX_VERSION_IEEE 0x00000200
2387 #define DCBX_DCBX_ENABLED 0x00000400
2388 #define DCBX_CEE_VERSION_MASK 0x0000f000
2390 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
2399 #define DCBX_ETS_TLV_RX 0x00000001
2400 #define DCBX_PFC_TLV_RX 0x00000002
2401 #define DCBX_APP_TLV_RX 0x00000004
2402 #define DCBX_ETS_RX_ERROR 0x00000010
2403 #define DCBX_PFC_RX_ERROR 0x00000020
2404 #define DCBX_APP_RX_ERROR 0x00000040
2405 #define DCBX_ETS_REM_WILLING 0x00000100
2406 #define DCBX_PFC_REM_WILLING 0x00000200
2407 #define DCBX_APP_REM_WILLING 0x00000400
2408 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
2409 #define DCBX_REMOTE_MIB_VALID 0x00002000
2419 #define DCBX_LOCAL_ETS_ERROR 0x00000001
2420 #define DCBX_LOCAL_PFC_ERROR 0x00000002
2421 #define DCBX_LOCAL_APP_ERROR 0x00000004
2422 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
2423 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
2424 #define DCBX_REMOTE_MIB_ERROR 0x00000040
2425 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
2426 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
2427 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
2446 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
2447 #define REQ_DUPLEX_PHY0_SHIFT 0
2448 #define REQ_DUPLEX_PHY1_MASK 0xffff0000
2451 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
2452 #define REQ_FLOW_CTRL_PHY0_SHIFT 0
2453 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
2456 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
2457 #define REQ_LINE_SPD_PHY0_SHIFT 0
2458 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
2462 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
2463 #define REQ_FC_AUTO_ADV0_SHIFT 0
2464 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
2466 #define LFA_LINK_FLAP_REASON_OFFSET 0
2467 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
2468 #define LFA_LINK_DOWN 0x1
2469 #define LFA_LOOPBACK_ENABLED 0x2
2470 #define LFA_DUPLEX_MISMATCH 0x3
2471 #define LFA_MFW_IS_TOO_OLD 0x4
2472 #define LFA_LINK_SPEED_MISMATCH 0x5
2473 #define LFA_FLOW_CTRL_MISMATCH 0x6
2474 #define LFA_SPEED_CAP_MISMATCH 0x7
2475 #define LFA_DCC_LFA_DISABLED 0x8
2476 #define LFA_EEE_MISMATCH 0x9
2479 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
2482 #define LINK_FLAP_COUNT_MASK 0x00ff0000
2484 #define LFA_FLAGS_MASK 0xff000000
2492 On driver unload driver value of 0x0 will be set
2495 #define DRV_VER_NOT_LOADED 0
2497 #define DRV_PERS_ETHERNET 0
2505 #define OEM_I2C_UUID_STR_ADDR 0x9f
2506 #define OEM_I2C_CARD_SKU_STR_ADDR 0x3c
2507 #define OEM_I2C_CARD_FN_STR_ADDR 0x48
2508 #define OEM_I2C_CARD_NAME_STR_ADDR 0x10e
2526 CURR_CFG_MET_NONE = 0, /* default config */
2560 #define FIRST_DUMP_VALID (1 << 0)
2564 #define ENABLE_ALL_TRIGGERS (0x7fffffff)
2570 uint32_t size; /* 0x0000 */
2572 uint32_t dcc_support; /* 0x0004 */
2573 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2574 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2575 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2576 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2577 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2578 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2580 uint32_t ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */
2583 * (the size filed is smaller than 0xc) the mf_cfg resides at the
2586 uint32_t mf_cfg_addr; /* 0x0010 */
2587 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2589 struct fw_flr_mb flr_mb; /* 0x0014 */
2590 uint32_t dcbx_lldp_params_offset; /* 0x0028 */
2591 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2592 uint32_t dcbx_neg_res_offset; /* 0x002c */
2593 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2594 uint32_t dcbx_remote_mib_offset; /* 0x0030 */
2595 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2602 uint32_t other_shmem_base_addr; /* 0x0034 */
2603 uint32_t other_shmem2_base_addr; /* 0x0038 */
2608 uint32_t mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
2614 uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2616 uint32_t dcbx_lldp_dcbx_stat_offset; /* 0x0064 */
2617 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2624 * bits 0-2 - function number / instance of driver to perform request
2628 uint32_t edebug_driver_if[2]; /* 0x0068 */
2633 uint32_t nvm_retain_bitmap_addr; /* 0x0070 */
2636 uint32_t afex_driver_support; /* 0x0074 */
2637 #define SHMEM_AFEX_VERSION_MASK 0x100f
2638 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2639 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2648 uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
2649 uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
2651 uint32_t swim_base_addr; /* 0x00a8 */
2652 uint32_t swim_funcs; /* 0x00ac */
2653 uint32_t swim_main_cb; /* 0x00b0 */
2659 uint32_t afex_profiles_enabled[2]; /* 0x00b4 */
2662 uint32_t drv_flags; /* 0x00bc */
2663 #define DRV_FLAGS_DCB_CONFIGURED 0x0
2664 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
2665 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
2671 #define DRV_FLAGS_P0_OFFSET 0
2673 #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \
2684 uint32_t extended_dev_info_shared_addr; /* 0x00c0 */
2685 uint32_t ncsi_oem_data_addr; /* 0x00c4 */
2687 uint32_t sensor_data_addr; /* 0x00c8 */
2688 uint32_t buffer_block_addr; /* 0x00cc */
2689 uint32_t sensor_data_req_update_interval; /* 0x00d0 */
2690 uint32_t temperature_in_half_celsius; /* 0x00d4 */
2691 uint32_t glob_struct_in_host; /* 0x00d8 */
2693 uint32_t dcbx_neg_res_ext_offset; /* 0x00dc */
2694 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2696 uint32_t drv_capabilities_flag[E2_FUNC_MAX]; /* 0x00e0 */
2697 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2698 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2699 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2700 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2701 #define DRV_FLAGS_MTU_MASK 0xffff0000
2704 uint32_t extended_dev_info_shared_cfg_size; /* 0x00f0 */
2706 uint32_t dcbx_en[PORT_MAX]; /* 0x00f4 */
2709 uint32_t multi_thread_data_offset; /* 0x00fc */
2712 uint32_t drv_info_host_addr_lo; /* 0x0100 */
2713 uint32_t drv_info_host_addr_hi; /* 0x0104 */
2716 uint32_t drv_info_control; /* 0x0108 */
2717 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2718 #define DRV_INFO_CONTROL_VER_SHIFT 0
2719 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2721 uint32_t ibft_host_addr; /* initialized by option ROM */ /* 0x010c */
2723 struct eee_remote_vals eee_remote_vals[PORT_MAX]; /* 0x0110 */
2724 uint32_t pf_allocation[E2_FUNC_MAX]; /* 0x0120 */
2725 …#define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show …
2726 #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0
2729 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2739 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2742 uint32_t eee_status[PORT_MAX]; /* 0x0130 */
2743 #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2744 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2746 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2747 #define SHMEM_EEE_100M_ADV (1<<0)
2751 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2753 #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2754 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2755 #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2756 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2758 uint32_t sizeof_port_stats; /* 0x0138 */
2761 uint32_t lfa_host_addr[PORT_MAX]; /* 0x013c */
2764 uint32_t extphy_temps_in_celsius; /* 0x0144 */
2765 #define EXTPHY1_TEMP_MASK 0x0000ffff
2766 #define EXTPHY1_TEMP_SHIFT 0
2767 #define ON_BOARD_TEMP_MASK 0xffff0000
2770 uint32_t ocdata_info_addr; /* Offset 0x148 */
2771 uint32_t drv_func_info_addr; /* Offset 0x14C */
2772 uint32_t drv_func_info_size; /* Offset 0x150 */
2773 uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */
2774 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
2775 #define LINK_ATTR_84858 0x00000002
2776 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
2778 #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
2779 #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000
2780 #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000
2782 uint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM Offset 0x158 */
2783 uint32_t fcode_ver; /* Offset 0x15c */
2784 uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
2785 #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */
2787 struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
2790 uint32_t mfw_drv_indication; /* Offset 0x19c */
2792 /* We use inidcation for each PF (0..3) */
2795 union { /* For various OEMs */ /* Offset 0x1a0 */
2797 #define STORAGE_BOOT_PROG_MASK 0x000000FF
2798 #define STORAGE_BOOT_PROG_NONE 0x00000000
2799 #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
2800 #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
2801 #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
2802 #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
2803 #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
2804 #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
2805 #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
2806 #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
2807 #define STORAGE_BOOT_PROG_COMPLETED 0x00000080
2813 /* For PCP values 0-3 use the map lower */
2814 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
2815 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
2817 uint32_t c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */
2820 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
2821 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
2823 uint32_t c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */
2826 uint32_t c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */
2829 uint32_t fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */
2832 enum curr_cfg_method_e curr_cfg; /* 0x1dc */
2834 /* Storm FW version, shold be kept in the format 0xMMmmbbdd:
2837 uint32_t netproc_fw_ver; /* 0x1e0 */
2840 uint32_t clp_ver; /* 0x1e4 */
2842 uint32_t pcie_bus_num; /* 0x1e8 */
2844 uint32_t sriov_switch_mode; /* 0x1ec */
2845 #define SRIOV_SWITCH_MODE_NONE 0x0
2846 #define SRIOV_SWITCH_MODE_VEB 0x1
2847 #define SRIOV_SWITCH_MODE_VEPA 0x2
2849 uint8_t rsrv2[E2_FUNC_MAX]; /* 0x1f0 */
2851 uint32_t img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */
2853 uint32_t mtu_size[E2_FUNC_MAX]; /* 0x1f8 */
2855 uint32_t os_driver_state[E2_FUNC_MAX]; /* 0x208 */
2856 #define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */
2862 struct mdump_driver_info drv_info; /* 0x218 */
2864 /* 0x22c */
3501 uint32_t enabled; /* 0 =Disabled, 1= Enabled */
3504 uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/
3531 uint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled.
3544 #define BCM_5710_FW_ENGINEERING_VERSION 0
3577 …#define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0) /* …
3578 #define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0
3579 … (0x1<<8) /* BitField agg_vars1Various aggregative variables The connection is currentl…
3581 …#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9) /* B…
3583 …#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10) /* …
3585 …#define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11) /* …
3587 …#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12) /* …
3589 …#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13) /* …
3591 …#define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14) /* …
3593 …#define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16) /* …
3595 …#define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18) /* …
3597 …#define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19) /* …
3599 …#define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20) /* …
3601 …#define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21) /* …
3603 …#define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22) /* …
3605 …Q_RULE (0x7<<23) /* BitField agg_vars1Various aggregative va…
3607 …RULE (0x3<<26) /* BitField agg_vars1Various aggregative va…
3609 …ED52 (0x3<<28) /* BitField agg_vars1Various aggregative va…
3611 …ED53 (0x3<<30) /* BitField agg_vars1Various aggregative va…
3733 … (0x1<<0) /* BitField opcode Whether the source is the PCIe…
3734 #define DMAE_CMD_SRC_SHIFT 0
3735 … (0x3<<1) /* BitField opcode The destination of the DMA…
3737 … (0x1<<3) /* BitField opcode The destination of the com…
3739 … (0x1<<4) /* BitField opcode Whether to write a completion word to the …
3741 … (0x1<<5) /* BitField opcode Whether to write a CRC word to the com…
3743 …#define DMAE_CMD_C_TYPE_CRC_OFFSET (0x7<<6) /* B…
3745 …#define DMAE_CMD_ENDIANITY (0x3<<9) /* B…
3747 …#define DMAE_CMD_PORT (0x1<<11) /* …
3749 …#define DMAE_CMD_CRC_RESET (0x1<<12) /* …
3751 …#define DMAE_CMD_SRC_RESET (0x1<<13) /* …
3753 …#define DMAE_CMD_DST_RESET (0x1<<14) /* …
3755 …#define DMAE_CMD_E1HVN (0x3<<15) /* …
3757 …#define DMAE_CMD_DST_VN (0x3<<17) /* …
3759 … (0x1<<19) /* BitField opcode E2 and onwards which function gets the c…
3761 … (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a comple…
3763 …#define DMAE_CMD_RESERVED0 (0x3FF<<22) /…
3771 … (0x3F<<0) /* BitField opcode_iovE2 and onward, set…
3772 #define DMAE_CMD_SRC_VFID_SHIFT 0
3773 … (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibili…
3775 … (0x1<<7) /* BitField opcode_iovE2 and onward, set…
3777 … (0x3F<<8) /* BitField opcode_iovE2 and onward, set…
3779 … (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility…
3781 … (0x1<<15) /* BitField opcode_iovE2 and onward, set…
3787 … (0x3F<<0) /* BitField opcode_iovE2 and onward, set…
3788 #define DMAE_CMD_SRC_VFID_SHIFT 0
3789 … (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibili…
3791 … (0x1<<7) /* BitField opcode_iovE2 and onward, set…
3793 … (0x3F<<8) /* BitField opcode_iovE2 and onward, set…
3795 … (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility…
3797 … (0x1<<15) /* BitField opcode_iovE2 and onward, set…
3835 … (0x1<<0) /* BitField data 1 for rx doorbell, …
3836 #define DOORBELL_HDR_T_RX_SHIFT 0
3837 …DB_TYPE (0x1<<1) /* BitField data 0 for norm…
3839 …#define DOORBELL_HDR_T_DPM_SIZE (0x3<<2) /* B…
3841 …#define DOORBELL_HDR_T_CONN_TYPE (0xF<<4) /* B…
3853 …#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* …
3854 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3855 …#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* B…
3857 …#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* B…
3863 …#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* …
3864 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3865 …#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* B…
3867 …#define ETH_TX_DOORBELL_SPARE (0x1<<7) /* B…
3940 …US_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15…
3941 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3942 …RM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:…
3944 …#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* B…
3946 …#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* B…
3948 …#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /*…
3954 …US_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15…
3955 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3956 …RM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:…
3958 …#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* B…
3960 …#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* B…
3962 …#define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /*…
3974 …#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /…
3975 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3976 …#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /*…
3978 …LE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:…
3980 …#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* …
3982 …#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* …
3984 …#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /*…
3996 …#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) …
3997 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3998 …#define IGU_REGULAR_RESERVED0 (0x1<<20) /* …
4000 …#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* …
4002 …#define IGU_REGULAR_BUPDATE (0x1<<24) /* …
4004 …#define IGU_REGULAR_ENABLE_INT (0x3<<25) /* …
4006 …#define IGU_REGULAR_RESERVED_1 (0x1<<27) /* …
4008 …#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* …
4010 …#define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* …
4012 …#define IGU_REGULAR_BCLEANUP (0x1<<31) /* …
4043 …#define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /*…
4044 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
4045 …#define IGU_CTRL_REG_FID (0x7F<<12) /*…
4047 …#define IGU_CTRL_REG_RESERVED (0x1<<19) /* …
4049 …#define IGU_CTRL_REG_TYPE (0x1<<20) /* …
4051 …#define IGU_CTRL_REG_UNUSED (0x7FF<<21) /…
4087 …#define ISCSI_TX_DOORBELL_NUM_WQES (0x3F<<0) /* …
4088 #define ISCSI_TX_DOORBELL_NUM_WQES_SHIFT 0
4089 …#define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* B…
4091 …#define ISCSI_TX_DOORBELL_SPARE (0x1<<7) /* B…
4097 …#define ISCSI_TX_DOORBELL_NUM_WQES (0x3F<<0) /* …
4098 #define ISCSI_TX_DOORBELL_NUM_WQES_SHIFT 0
4099 …#define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* B…
4101 …#define ISCSI_TX_DOORBELL_SPARE (0x1<<7) /* B…
4114 …_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=n…
4115 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
4116 …AN_EXIST (0x1<<1) /* BitField flagscontext flags 0 o…
4118 …AN_EXIST (0x1<<2) /* BitField flagscontext flags 0 o…
4120 …ERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=u…
4122 …NS (0x1<<5) /* BitField flagscontext flags 0=n…
4124 …ATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=n…
4126 …PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=u…
4128 …_INDICATION (0x1<<9) /* BitField flagscontext flags 0=p…
4130 …ONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=…
4132 …#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* …
4134 …#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* …
4136 …#define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* …
4138 …#define PARSING_FLAGS_RESERVED0 (0x3<<14) /* …
4192 …#define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* …
4193 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
4194 …#define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* B…
4196 …#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* …
4198 …#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* …
4200 …#define SDM_OP_GEN_RESERVED (0x7FFF<<17) …
4210 uint32_t __client0 /* data of client 0 of the timers block*/;
4214 …#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* B…
4215 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
4216 …#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* B…
4218 …#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<…
4248 …#define TOE_RX_BDS_DOORBELL_RESERVED (0x1F<<0) /* …
4249 #define TOE_RX_BDS_DOORBELL_RESERVED_SHIFT 0
4250 …#define TOE_RX_BDS_DOORBELL_OPCODE (0x7<<5) /* B…
4256 …#define TOE_RX_BDS_DOORBELL_RESERVED (0x1F<<0) /* …
4257 #define TOE_RX_BDS_DOORBELL_RESERVED_SHIFT 0
4258 …#define TOE_RX_BDS_DOORBELL_OPCODE (0x7<<5) /* B…
4273 …#define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS (0x1F<<0) /* …
4274 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS_SHIFT 0
4275 …#define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE (0x7<<5) /* B…
4281 …#define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS (0x1F<<0) /* …
4282 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS_SHIFT 0
4283 …#define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE (0x7<<5) /* B…
4296 uint16_t nbytes_lsb /* bits [0:15] of nbytes */;
4298 …#define TOE_RX_BYTE_DOORBELL_NBYTES_MSB (0x1F<<0) /* …
4299 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB_SHIFT 0
4300 … (0x7<<5) /* BitField params rx bytes doorbell opco…
4306 …#define TOE_RX_BYTE_DOORBELL_NBYTES_MSB (0x1F<<0) /* …
4307 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB_SHIFT 0
4308 … (0x7<<5) /* BitField params rx bytes doorbell opco…
4310 uint16_t nbytes_lsb /* bits [0:15] of nbytes */;
4321 uint16_t nbytes_lsb /* bits [0:15] of nbytes */;
4323 …#define TOE_RX_GRQ_DOORBELL_NBYTES_MSB (0x1F<<0) /* …
4324 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB_SHIFT 0
4325 …#define TOE_RX_GRQ_DOORBELL_OPCODE (0x7<<5) /* B…
4331 …#define TOE_RX_GRQ_DOORBELL_NBYTES_MSB (0x1F<<0) /* …
4332 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB_SHIFT 0
4333 …#define TOE_RX_GRQ_DOORBELL_OPCODE (0x7<<5) /* B…
4335 uint16_t nbytes_lsb /* bits [0:15] of nbytes */;
4348 …#define TOE_TX_DOORBELL_NUM_BDS (0x3F<<0) /* …
4349 #define TOE_TX_DOORBELL_NUM_BDS_SHIFT 0
4350 …#define TOE_TX_DOORBELL_TX_FIN_FLAG (0x1<<6) /* B…
4352 …#define TOE_TX_DOORBELL_FLUSH (0x1<<7) /* B…
4358 …#define TOE_TX_DOORBELL_NUM_BDS (0x3F<<0) /* …
4359 #define TOE_TX_DOORBELL_NUM_BDS_SHIFT 0
4360 …#define TOE_TX_DOORBELL_TX_FIN_FLAG (0x1<<6) /* B…
4362 …#define TOE_TX_DOORBELL_FLUSH (0x1<<7) /* B…
4408 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* B…
4409 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4410 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* B…
4412 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* B…
4414 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* B…
4416 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* B…
4418 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* B…
4420 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* B…
4422 …#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9) /* B…
4424 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* …
4426 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* …
4428 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* …
4430 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* …
4432 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* …
4434 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* …
4436 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* …
4438 …#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* …
4440 …#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* …
4442 …#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* …
4444 …#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* …
4446 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* …
4448 …#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* …
4463 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
4464 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4465 …#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
4467 …#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* B…
4469 …#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* B…
4471 …#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) /* B…
4473 …#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* B…
4475 …#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* B…
4481 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
4482 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4483 …#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
4485 …#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* B…
4487 …#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* B…
4489 …#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) /* B…
4491 …#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* B…
4493 …#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* B…
4500 …#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* B…
4501 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4502 …#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* B…
4504 …#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* B…
4506 …#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* B…
4508 …#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* B…
4510 …#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* B…
4512 …#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* …
4514 …#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) /* …
4516 …#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) /* …
4518 …#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) /* …
4520 …#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* …
4522 …#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* …
4526 …#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* B…
4527 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4528 …#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* B…
4530 …#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* B…
4532 …#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* B…
4534 …#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* B…
4536 …#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* B…
4538 …#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* …
4540 …#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) /* …
4542 …#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) /* …
4544 …#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) /* …
4546 …#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* …
4548 …#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* …
4586 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* B…
4587 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4588 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* B…
4590 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* B…
4592 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* B…
4594 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* B…
4596 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* B…
4598 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* B…
4600 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* B…
4602 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* …
4604 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* …
4606 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* …
4608 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* …
4610 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* …
4612 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* …
4614 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* …
4616 …#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* …
4618 …#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* …
4620 …#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* …
4622 …#define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* …
4624 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* …
4626 …#define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* …
4641 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
4642 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4643 …#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
4645 …#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* B…
4647 …#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* B…
4649 …#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* B…
4651 …#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* B…
4653 …#define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) /* B…
4659 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
4660 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4661 …#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
4663 …#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* B…
4665 …#define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* B…
4667 …#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* B…
4669 …#define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* B…
4671 …#define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) /* B…
4678 …#define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) /* B…
4679 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
4680 …#define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) /* B…
4682 …#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) /* B…
4684 …#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) /* B…
4686 …#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) /* B…
4688 …#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) /* B…
4690 …#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* …
4692 …#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* …
4694 …#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) /* …
4696 …#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) /* …
4698 …#define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* …
4700 …#define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* …
4704 …#define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) /* B…
4705 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
4706 …#define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) /* B…
4708 …#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) /* B…
4710 …#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) /* B…
4712 …#define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) /* B…
4714 …#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) /* B…
4716 …#define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* …
4718 …#define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* …
4720 …#define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) /* …
4722 …#define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) /* …
4724 …#define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* …
4726 …#define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* …
4764 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* B…
4765 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4766 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* B…
4768 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* B…
4770 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* B…
4772 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* B…
4774 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* B…
4776 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* B…
4778 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* B…
4780 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* …
4782 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* …
4784 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* …
4786 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* …
4788 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* …
4790 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* …
4792 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* …
4794 …#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* …
4796 …#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* …
4798 …#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* …
4800 …#define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* …
4802 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* …
4804 …#define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* …
4842 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* B…
4843 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4844 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* B…
4846 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52 (0x3<<2) /* B…
4848 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* B…
4850 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN (0x1<<6) /* B…
4852 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* B…
4854 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* B…
4856 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* B…
4858 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE (0x1<<10) /* …
4860 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55 (0x1<<11) /* …
4862 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN (0x1<<12) /* …
4864 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN (0x1<<13) /* …
4866 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56 (0x3<<14) /* …
4868 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57 (0x3<<16) /* …
4870 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* …
4872 …#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* …
4874 …#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* …
4876 …#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* …
4878 …#define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* …
4880 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* …
4882 …#define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* …
4897 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
4898 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4899 …#define TSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<1) /* B…
4901 …#define TSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<2) /* B…
4903 …#define TSTORM_TOE_AG_CONTEXT_RESERVED53 (0x1<<3) /* B…
4905 …#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* B…
4907 …#define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* B…
4909 …#define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* B…
4915 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
4916 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4917 …#define TSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<1) /* B…
4919 …#define TSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<2) /* B…
4921 …#define TSTORM_TOE_AG_CONTEXT_RESERVED53 (0x1<<3) /* B…
4923 …#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* B…
4925 …#define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* B…
4927 …#define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* B…
4934 …#define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* B…
4935 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4936 …#define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* B…
4938 …#define __TSTORM_TOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* B…
4940 …#define __TSTORM_TOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* B…
4942 …#define __TSTORM_TOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* B…
4944 …#define __TSTORM_TOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* B…
4946 …#define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* …
4948 …#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* …
4950 …#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN (0x1<<12) /* …
4952 …#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN (0x1<<13) /* …
4954 …#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN (0x1<<14) /* …
4956 …#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN (0x1<<15) /* …
4960 …#define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* B…
4961 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4962 …#define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* B…
4964 …#define __TSTORM_TOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* B…
4966 …#define __TSTORM_TOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* B…
4968 …#define __TSTORM_TOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* B…
4970 …#define __TSTORM_TOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* B…
4972 …#define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* …
4974 …#define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* …
4976 …#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN (0x1<<12) /* …
4978 …#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN (0x1<<13) /* …
4980 …#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN (0x1<<14) /* …
4982 …#define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN (0x1<<15) /* …
5017 …#define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) /* B…
5018 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
5019 …#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) /* B…
5021 …_RULE (0x7<<4) /* BitField agg_vars2various aggregation var…
5023 … (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision r…
5026 … (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currentl…
5027 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5028 …#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
5030 …#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* B…
5032 …#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* B…
5034 …#define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) /* B…
5036 …#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* B…
5042 … (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currentl…
5043 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5044 …#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
5046 …#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* B…
5048 …#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* B…
5050 …#define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) /* B…
5052 …#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* B…
5055 …#define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) /* B…
5056 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
5057 …#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) /* B…
5059 …_RULE (0x7<<4) /* BitField agg_vars2various aggregation var…
5061 … (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision r…
5096 …#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) /* B…
5097 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
5098 …#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* B…
5100 …#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) /* B…
5102 …#define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* B…
5105 …#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) /* B…
5106 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
5107 …#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* B…
5109 …#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) /* B…
5111 …#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* B…
5113 …#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) /* B…
5115 …#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) /* B…
5117 …#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* B…
5119 …#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* B…
5123 …#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) /* B…
5124 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
5125 …#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* B…
5127 …#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) /* B…
5129 …#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* B…
5131 …#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) /* B…
5133 …#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) /* B…
5135 …#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* B…
5137 …#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* B…
5140 …#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) /* B…
5141 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
5142 …#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* B…
5144 …#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) /* B…
5146 …#define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* B…
5161 …#define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) /* B…
5162 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
5163 …#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) /* B…
5165 …4_RULE (0x7<<4) /* BitField agg_vars2various aggregation var…
5167 … (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision r…
5170 … (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currentl…
5171 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5172 …#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
5174 …#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* B…
5176 …#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* B…
5178 …#define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) /* B…
5180 …#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* B…
5186 … (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currentl…
5187 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5188 …#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
5190 …#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* B…
5192 …#define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* B…
5194 …#define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) /* B…
5196 …#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* B…
5199 …#define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) /* B…
5200 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
5201 …#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) /* B…
5203 …4_RULE (0x7<<4) /* BitField agg_vars2various aggregation var…
5205 … (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision r…
5240 …#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* B…
5241 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5242 …#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* B…
5244 …#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* B…
5246 …#define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) /* B…
5249 …#define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) /* B…
5250 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
5251 …#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* B…
5253 …#define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) /* B…
5255 …#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* B…
5257 …#define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) /* B…
5259 …#define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) /* B…
5261 …#define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* B…
5263 …#define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* B…
5267 …#define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) /* B…
5268 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
5269 …#define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* B…
5271 …#define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) /* B…
5273 …#define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* B…
5275 …#define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) /* B…
5277 …#define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) /* B…
5279 …#define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* B…
5281 …#define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* B…
5284 …#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* B…
5285 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5286 …#define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* B…
5288 …#define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* B…
5290 …#define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) /* B…
5344 …#define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* B…
5345 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5346 …#define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* B…
5348 …#define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* B…
5350 …#define __USTORM_TOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* B…
5356 …#define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* B…
5357 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5358 …#define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* B…
5360 …#define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* B…
5362 …#define __USTORM_TOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* B…
5395 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) /* B…
5396 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
5397 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* B…
5399 …#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* B…
5401 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) /* B…
5403 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) /* B…
5411 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) /* B…
5412 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
5413 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* B…
5415 …#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* B…
5417 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) /* B…
5419 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) /* B…
5430 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) /* B…
5431 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
5432 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) /* B…
5434 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) /* B…
5436 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* B…
5438 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* B…
5440 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) /* B…
5442 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) /* B…
5444 …#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* B…
5446 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) /* B…
5448 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* B…
5450 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* …
5452 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* …
5454 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* …
5458 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) /* B…
5459 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
5460 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) /* B…
5462 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) /* B…
5464 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* B…
5466 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* B…
5468 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) /* B…
5470 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) /* B…
5472 …#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* B…
5474 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) /* B…
5476 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* B…
5478 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* …
5480 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* …
5482 …#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* …
5538 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
5539 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5540 …#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
5542 …#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* B…
5544 …#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* B…
5546 … (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the dec…
5548 …#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* B…
5550 …#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* B…
5552 …#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) /* B…
5558 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
5559 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5560 …#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
5562 …#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* B…
5564 …#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* B…
5566 … (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the dec…
5568 …#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* B…
5570 …#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* B…
5572 …#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) /* B…
5580 …#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* …
5581 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
5582 …#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) /* B…
5585 …#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) /* B…
5586 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
5587 …#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* B…
5589 …#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* B…
5591 …#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* B…
5593 …RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative var…
5595 …#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* B…
5599 …#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) /* B…
5600 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
5601 …#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* B…
5603 …#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* B…
5605 …#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* B…
5607 …RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative var…
5609 …#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* B…
5612 …#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* …
5613 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
5614 …#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) /* B…
5622 …RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative var…
5623 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
5624 … (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical …
5626 …#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* …
5628 …EC_RULE (0x3<<14) /* BitField agg_vars5Various aggregative va…
5634 …RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative var…
5635 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
5636 … (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical …
5638 …#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* …
5640 …EC_RULE (0x3<<14) /* BitField agg_vars5Various aggregative va…
5646 …11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative var…
5647 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
5648 …#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* B…
5650 …#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) /* B…
5652 …RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative var…
5654 …#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) /* B…
5656 …#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) /* …
5658 …#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* …
5660 …#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* …
5662 …#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* …
5664 …#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* …
5666 …#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) /* …
5670 …RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative var…
5671 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
5672 …C_RULE (0x7<<3) /* BitField agg_vars6Various aggregative var…
5674 …RULE (0x3<<6) /* BitField agg_vars6Various aggregative var…
5678 …RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative var…
5679 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
5680 …C_RULE (0x7<<3) /* BitField agg_vars6Various aggregative var…
5682 …RULE (0x3<<6) /* BitField agg_vars6Various aggregative var…
5686 …11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative var…
5687 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
5688 …#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* B…
5690 …#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) /* B…
5692 …RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative var…
5694 …#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) /* B…
5696 …#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) /* …
5698 …#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* …
5700 …#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* …
5702 …#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* …
5704 …#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* …
5706 …#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) /* …
5733 …#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)…
5734 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0
5735 …#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24) /*…
5738 uint16_t __cache_wqe_db /* Misc aggregated variable 0 */;
5742 uint16_t __cache_wqe_db /* Misc aggregated variable 0 */;
5756 …OTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is …
5760 …OTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is …
5775 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* B…
5776 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
5777 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* B…
5779 …#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* B…
5781 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* B…
5783 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* B…
5791 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* B…
5792 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
5793 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* B…
5795 …#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* B…
5797 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* B…
5799 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* B…
5810 …#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* B…
5811 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
5812 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* B…
5814 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* B…
5816 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* B…
5818 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* B…
5820 …#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* B…
5822 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* B…
5824 …#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* B…
5826 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* B…
5828 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* B…
5830 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* …
5832 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* …
5834 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* …
5838 …#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* B…
5839 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
5840 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* B…
5842 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* B…
5844 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* B…
5846 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* B…
5848 …#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* B…
5850 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* B…
5852 …#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* B…
5854 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* B…
5856 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* B…
5858 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* …
5860 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* …
5862 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* …
5890 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) /* B…
5891 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
5892 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1) /* B…
5894 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) /* B…
5896 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) /* B…
5898 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) /* B…
5900 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) /* B…
5902 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) /* B…
5904 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) /* B…
5906 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) /* …
5908 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) /* …
5910 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) /* …
5912 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) /* …
5914 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) /* …
5916 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) /* …
5918 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) /* …
5920 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) /* …
5922 …#define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) /* …
5924 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) /* …
5926 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) /* …
5928 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) /* …
5930 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) /* …
5932 …#define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) /* …
5962 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
5963 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5964 …#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
5966 …#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* B…
5968 …#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* B…
5970 … (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the dec…
5972 …#define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) /* B…
5974 …#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* B…
5976 …#define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* B…
5982 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
5983 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5984 …#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* B…
5986 …#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* B…
5988 …#define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* B…
5990 … (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the dec…
5992 …#define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) /* B…
5994 …#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* B…
5996 …#define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* B…
6004 …#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* …
6005 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6006 …#define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) /* B…
6009 …#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) /* B…
6010 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
6011 …#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* B…
6013 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* B…
6015 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* B…
6017 …_RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative var…
6019 …#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* B…
6023 …#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) /* B…
6024 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
6025 …#define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* B…
6027 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* B…
6029 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* B…
6031 …_RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative var…
6033 …#define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* B…
6036 …#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* …
6037 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6038 …#define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) /* B…
6046 …_RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative var…
6047 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
6048 … (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical …
6050 …#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* …
6052 …_RULE2 (0x3<<14) /* BitField agg_vars5Various aggregative va…
6058 …_RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative var…
6059 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
6060 … (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical …
6062 …#define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* …
6064 …_RULE2 (0x3<<14) /* BitField agg_vars5Various aggregative va…
6070 …L11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative var…
6071 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
6072 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* B…
6074 …#define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) /* B…
6076 …_RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative var…
6078 …#define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) /* B…
6080 …#define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) /* …
6082 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* …
6084 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* …
6086 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* …
6088 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* …
6090 …#define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) /* …
6094 …_RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative var…
6095 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
6096 …_RULE7 (0x7<<3) /* BitField agg_vars6Various aggregative var…
6098 …_RULE4 (0x3<<6) /* BitField agg_vars6Various aggregative var…
6102 …_RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative var…
6103 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
6104 …_RULE7 (0x7<<3) /* BitField agg_vars6Various aggregative var…
6106 …_RULE4 (0x3<<6) /* BitField agg_vars6Various aggregative var…
6110 …L11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative var…
6111 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
6112 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* B…
6114 …#define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) /* B…
6116 …_RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative var…
6118 …#define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) /* B…
6120 …#define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) /* …
6122 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* …
6124 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* …
6126 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* …
6128 …#define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* …
6130 …#define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) /* …
6157 …#define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0)…
6158 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0
6159 …#define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24) /*…
6162 uint16_t r2tq_prod /* Misc aggregated variable 0 */;
6166 uint16_t r2tq_prod /* Misc aggregated variable 0 */;
6180 …OTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is …
6184 …OTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is …
6199 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* B…
6200 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
6201 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* B…
6203 …#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* B…
6205 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* B…
6207 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* B…
6215 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* B…
6216 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
6217 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* B…
6219 …#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* B…
6221 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* B…
6223 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* B…
6234 …#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* B…
6235 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
6236 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* B…
6238 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* B…
6240 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* B…
6242 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* B…
6244 …#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* B…
6246 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* B…
6248 …#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* B…
6250 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* B…
6252 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* B…
6254 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* …
6256 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* …
6258 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* …
6262 …#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* B…
6263 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
6264 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* B…
6266 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* B…
6268 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* B…
6270 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* B…
6272 …#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* B…
6274 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* B…
6276 …#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* B…
6278 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* B…
6280 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* B…
6282 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* …
6284 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* …
6286 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* …
6314 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) /* B…
6315 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
6316 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1) /* B…
6318 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) /* B…
6320 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) /* B…
6322 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) /* B…
6324 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) /* B…
6326 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) /* B…
6328 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) /* B…
6330 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) /* …
6332 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) /* …
6334 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) /* …
6336 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) /* …
6338 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) /* …
6340 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) /* …
6342 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) /* …
6344 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) /* …
6346 …#define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) /* …
6348 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) /* …
6350 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) /* …
6352 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) /* …
6354 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) /* …
6356 …#define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) /* …
6386 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
6387 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
6388 …#define __XSTORM_TOE_AG_CONTEXT_RESERVED50 (0x1<<1) /* B…
6390 …#define __XSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* B…
6392 …#define __XSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* B…
6394 … (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the dec…
6396 …#define XSTORM_TOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* B…
6398 …#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG (0x1<<6) /* B…
6400 …#define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* B…
6406 … (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currentl…
6407 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
6408 …#define __XSTORM_TOE_AG_CONTEXT_RESERVED50 (0x1<<1) /* B…
6410 …#define __XSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* B…
6412 …#define __XSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* B…
6414 … (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the dec…
6416 …#define XSTORM_TOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* B…
6418 …#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG (0x1<<6) /* B…
6420 …#define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* B…
6428 …#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* …
6429 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6430 …#define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF (0x3<<6) /* B…
6433 …#define __XSTORM_TOE_AG_CONTEXT_DQ_CF (0x3<<0) /* B…
6434 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_SHIFT 0
6435 …#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN (0x1<<2) /* B…
6437 …#define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* B…
6439 …#define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* B…
6441 … (0x3<<5) /* BitField agg_vars2Various aggregative var…
6443 …#define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* B…
6447 …#define __XSTORM_TOE_AG_CONTEXT_DQ_CF (0x3<<0) /* B…
6448 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_SHIFT 0
6449 …#define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN (0x1<<2) /* B…
6451 …#define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* B…
6453 …#define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* B…
6455 … (0x3<<5) /* BitField agg_vars2Various aggregative var…
6457 …#define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* B…
6460 …#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* …
6461 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6462 …#define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF (0x3<<6) /* B…
6470 …54 (0x3<<0) /* BitField agg_vars5Various aggregative var…
6471 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54_SHIFT 0
6472 … (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical …
6474 …#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* …
6476 …56 (0x3<<14) /* BitField agg_vars5Various aggregative va…
6482 …54 (0x3<<0) /* BitField agg_vars5Various aggregative var…
6483 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54_SHIFT 0
6484 … (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical …
6486 …#define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* …
6488 …56 (0x3<<14) /* BitField agg_vars5Various aggregative va…
6526 uint16_t __agg_misc0 /* Misc aggregated variable 0 */;
6530 uint16_t __agg_misc0 /* Misc aggregated variable 0 */;
6544 …OTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is …
6548 …OTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is …
6635 …uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit …
6639 uint8_t func_id /* PCI function ID (0-71) */;
6653 …#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* B…
6654 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
6655 …#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* B…
6657 …#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* B…
6659 …#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* …
6665 … SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled…
6669 uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */;
6689 …#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* B…
6690 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
6691 …#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* B…
6693 …#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* B…
6695 …#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* B…
6697 …#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* B…
6699 …#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* B…
6701 …#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* B…
6703 …#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /*…
6733 …#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* B…
6734 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
6735 …#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* B…
6737 …#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* B…
6739 …#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* B…
6741 …#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /*…
6768 uint8_t func_id /* PCI function ID this client belongs to (0-71) */;
6775 …uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit …
6840 …#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* B…
6841 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
6842 …#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* B…
6844 …#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* B…
6846 …#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* B…
6848 …#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* B…
7011 …#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* B…
7012 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
7013 …#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* B…
7015 …#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* …
7037 …#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* B…
7038 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
7039 …#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* B…
7041 …#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* B…
7043 …#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* B…
7045 …#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* B…
7047 …#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6) /* B…
7049 …#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7) /* B…
7052 …#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* B…
7053 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
7054 …#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* B…
7056 …#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* B…
7058 …#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* B…
7060 …#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* B…
7062 …#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* B…
7068 …_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */;
7087 …#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* B…
7088 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
7089 …#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* B…
7091 …#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* …
7097 …#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* B…
7098 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
7099 …#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* B…
7101 …#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* B…
7103 …#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* B…
7105 …#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* B…
7107 …#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* B…
7109 …#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* B…
7111 …#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /*…
7197 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */;
7200 …#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0) /* B…
7201 #define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
7202 … (0x7F<<1) /* BitField flags Should be set with…
7222 …#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* B…
7223 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
7224 …#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* B…
7226 …D (0x1<<2) /* BitField cmd_general_data 1 for add ru…
7228 …#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* …
7231 uint8_t bin_id /* the bin to add this function to (0-255) */;
7304 …#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* B…
7305 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
7306 …#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* B…
7308 …#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* B…
7310 …#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3) /* B…
7312 …#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4) /* B…
7314 …#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5) /* B…
7316 …#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6) /* B…
7318 …#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7) /* B…
7320 …#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8) /* B…
7322 …#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9) /* B…
7324 …#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10) /*…
7326 … defines which section of the indirection table will be used. To enable all table put here 0x7F */;
7360 …#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* B…
7361 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
7362 …#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* B…
7364 …#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* …
7369 …#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)…
7370 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
7371 …#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /*…
7438 …#define SPE_HDR_T_CID (0xFFFFFF<<0)…
7439 #define SPE_HDR_T_CID_SHIFT 0
7440 …#define SPE_HDR_T_CMD_ID (0xFFUL<<24) …
7443 …#define SPE_HDR_T_CONN_TYPE (0xFF<<0) /* …
7444 #define SPE_HDR_T_CONN_TYPE_SHIFT 0
7445 …#define SPE_HDR_T_FUNCTION_ID (0xFF<<8) /* …
7564 …#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* B…
7565 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
7566 …#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* B…
7568 …#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* B…
7570 …#define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* B…
7572 …#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* B…
7574 …#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* B…
7576 …#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* B…
7592 …#define ETH_TX_START_BD_HDR_NBDS (0x7<<0) /* B…
7593 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
7594 …#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3) /* B…
7596 …#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* B…
7598 …#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* B…
7600 …#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* B…
7610 …#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* B…
7611 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
7612 …#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* B…
7614 …#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* B…
7616 …#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* B…
7618 …#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* B…
7620 … (0x7F<<9) /* BitField global_data reserved bit, should b…
7623 …#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* B…
7624 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
7625 …#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* B…
7627 …#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* B…
7629 …#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* B…
7631 …#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* B…
7633 …#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* B…
7635 …#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* B…
7637 …#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* B…
7641 uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */;
7654 …#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /*…
7655 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
7656 …#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* …
7658 …#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* …
7660 …#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) …
7662 …#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* …
7672 …#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* B…
7673 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
7674 …0 (0x1<<4) /* BitField global_data should be set wi…
7676 …#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* B…
7678 …#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* B…
7680 …#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* B…
7682 …#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* …
7684 …1 (0x7<<13) /* BitField global_data should be set w…
7687 …#define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0) /* B…
7688 #define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
7689 …#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4) /* B…
7693 …#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* B…
7694 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
7695 …#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* B…
7697 …#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* B…
7699 …#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* B…
7701 …#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* B…
7703 …#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* B…
7705 …#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* B…
7707 …#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* B…
7794 …#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* B…
7795 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
7796 …#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* B…
7798 …#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* B…
7800 …_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0…
7802 …BROADCAST (0x1<<5) /* BitField flags BitField flags 0…
7804 …#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* B…
7849 … SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled…
7877 …#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* B…
7878 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
7879 …#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* B…
7881 …#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* B…
7883 …#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* B…
7885 …#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* B…
7887 …G_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuratio…
7889 …#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* …
7891 … defines which section of the indirection table will be used. To enable all table put here 0x7F */;
8009 …#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) /* B…
8010 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
8011 …#define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1) /* B…
8013 …#define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2) /* B…
8015 …#define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3) /* B…
8017 …#define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4) /* B…
8019 …#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5) /* B…
8191 uint32_t completion_status /* 0=command completed successfully, 1=command failed */;
8197 …#define FCOE_KCQE_RESERVED0 (0x7<<0) /* B…
8198 #define FCOE_KCQE_RESERVED0_SHIFT 0
8199 …#define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3) /* B…
8201 …#define FCOE_KCQE_LAYER_CODE (0x7<<4) /* B…
8203 …#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) /* B…
8215 …#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) /* B…
8216 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
8217 …#define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4) /* B…
8219 …#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) /* B…
8241 …#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) /* B…
8242 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
8243 …#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4) /* B…
8245 …#define FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED (0x1<<7) /* B…
8273 uint32_t error_bit_map_lo /* 32 lower bits of error bitmap: 1=error, 0=warning */;
8274 uint32_t error_bit_map_hi /* 32 upper bits of error bitmap: 1=error, 0=warning */;
8275 …uint8_t perf_config /* 0= no performance acceleration, 1=cached connection, 2=cached tasks, 3=both…
8319 …#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) /*…
8320 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
8321 …#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) /* …
8323 …#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) /* …
8330 …#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) /* B…
8331 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
8332 …_E_D_TOV_RES (0x1<<1) /* BitField flags E_D_TOV resolution …
8334 …#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2) /* B…
8336 …#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3) /* B…
8338 …#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4) /* B…
8340 …#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5) /* B…
8342 …#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6) /* B…
8344 …#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) /* B…
8387 …#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) /*…
8388 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
8389 …#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12) /* …
8391 …#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) /* …
8485 … (0x1<<0) /* BitField flags Active Sequence indicat…
8486 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
8487 …#define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1) /* B…
8489 … (0x1<<2) /* BitField flags ABTS (on Sequence) protocol comple…
8491 …#define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3) /* B…
8493 …#define FCOE_S_STAT_CTX_P_RJT (0x1<<4) /* B…
8495 … (0x1<<5) /* BitField flags ACK (EOFt) transmitted indi…
8497 …#define FCOE_S_STAT_CTX_RSRV1 (0x3<<6) /* B…
8515 * FCoE RX statistics parameters section#0 $$KEEP_ENDIANNESS$$
8567 …#define FCOE_SQE_TASK_ID (0x7FFF<<0) /…
8568 #define FCOE_SQE_TASK_ID_SHIFT 0
8569 …#define FCOE_SQE_TOGGLE_BIT (0x1<<15) /* …
8591 struct fcoe_rx_stat_params_section0 rx_stat0 /* FCoE RX statistics parameters section#0 */;
8625 …#define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0) /* B…
8626 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
8627 …#define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3) /* B…
8629 …#define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4) /* B…
8631 …CACHED_SGE (0x3<<5) /* BitField init_flags Num of cached sg…
8633 …#define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7) /* B…
8636 …#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0) /* B…
8637 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
8638 …#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1) /* B…
8640 …#define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5) /* B…
8642 …#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6) /* B…
8644 …#define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS (0x1<<7) /* B…
8666 …#define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0)…
8667 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
8668 …#define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24) /*…
8678 …#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0) /* B…
8679 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
8680 …#define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4) /* B…
8682 …#define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7) /* B…
8684 …#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8) /* B…
8686 …#define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12) /* …
8688 …#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13) /* …
8690 …#define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14) /* …
8692 …#define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15) /* …
8734 …#define FCOE_XFRQE_TASK_ID (0x7FFF<<0) /…
8735 #define FCOE_XFRQE_TASK_ID_SHIFT 0
8736 …#define FCOE_XFRQE_TOGGLE_BIT (0x1<<15) /* …
8828 …#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) /* B…
8829 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
8830 …TOV_RES (0x1<<1) /* BitField flags E_D_TOV resolution …
8832 …#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) /* B…
8834 …#define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) /* B…
8836 …#define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) /* B…
8838 …#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) /* B…
8840 …#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) /* B…
8842 …#define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT (0x1<<7) /* B…
8844 …#define USTORM_FCOE_PARAMS_RSRV0 (0xFF<<8) /* …
8848 …#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) /* B…
8849 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
8850 …TOV_RES (0x1<<1) /* BitField flags E_D_TOV resolution …
8852 …#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) /* B…
8854 …#define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) /* B…
8856 …#define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) /* B…
8858 …#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) /* B…
8860 …#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) /* B…
8862 …#define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT (0x1<<7) /* B…
8864 …#define USTORM_FCOE_PARAMS_RSRV0 (0xFF<<8) /* …
8903 …#define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0) /…
8904 #define FCOE_IDX16_FIELDS_IDX_SHIFT 0
8905 …#define FCOE_IDX16_FIELDS_MSB (0x1<<15) /* …
8926 uint8_t sge_idx /* 0xFF value indicated loading SGL */;
8928 uint8_t sge_idx /* 0xFF value indicated loading SGL */;
8939 struct ustorm_fcoe_data_place_mng cached_mng /* 0xFF value indicated loading SGL */;
9079 …#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /*…
9080 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
9081 …#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* …
9083 …#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* …
9087 …#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /*…
9088 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
9089 …#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* …
9091 …#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* …
9114 …#define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0) /* B…
9115 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0
9116 …#define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2) /* B…
9118 …#define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3) /* B…
9120 …#define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4) /* B…
9122 …#define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5) /* B…
9124 …#define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6) /* B…
9126 …#define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7) /* B…
9145 uint8_t cached_sge_idx /* 0xFF value indicated loading SGL */;
9147 uint8_t cached_sge_idx /* 0xFF value indicated loading SGL */;
9186 …#define XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE (0x1<<0) /* B…
9187 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE_SHIFT 0
9188 …#define XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG (0x1<<1) /* B…
9190 …#define XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED (0x3F<<2) /* …
9200 …#define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY (0x7<<0) /* B…
9201 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY_SHIFT 0
9202 …#define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3) /* B…
9204 …#define XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY (0x7<<4) /* B…
9206 …#define XSTORM_FCOE_VLAN_CONF_RESERVED (0x1<<7) /* B…
9216 …#define FCOE_VLAN_FIELDS_VID (0xFFF<<0) /*…
9217 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
9218 …#define FCOE_VLAN_FIELDS_CLI (0x1<<12) /* …
9220 …#define FCOE_VLAN_FIELDS_PRI (0x7<<13) /* …
9467 uint32_t completion_status /* 0=command completed successfully, 1=command failed */;
9472 …#define ISCSI_KCQE_RESERVED0 (0x7<<0) /* B…
9473 #define ISCSI_KCQE_RESERVED0_SHIFT 0
9474 …#define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3) /* B…
9476 …#define ISCSI_KCQE_LAYER_CODE (0x7<<4) /* B…
9478 …#define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7) /* B…
9486 …#define ISCSI_KCQE_RESERVED0 (0x7<<0) /* B…
9487 #define ISCSI_KCQE_RESERVED0_SHIFT 0
9488 …#define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3) /* B…
9490 …#define ISCSI_KCQE_LAYER_CODE (0x7<<4) /* B…
9492 …#define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7) /* B…
9505 …#define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0) /* B…
9506 #define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0
9507 …#define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4) /* B…
9509 …#define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7) /* B…
9515 …#define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0) /* B…
9516 #define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0
9517 …#define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4) /* B…
9519 …#define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7) /* B…
9557 …#define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0) /* B…
9558 #define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0
9559 …#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4) /* B…
9561 …#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5) /* B…
9563 …#define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6) /* B…
9569 …#define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0) /* B…
9570 #define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0
9571 …#define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4) /* B…
9573 …#define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5) /* B…
9575 …#define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6) /* B…
9607 uint32_t error_bit_map[2] /* bit per error type, 0=error, 1=warning */;
9692 …DATE_HEADER_DIGEST (0x1<<0) /* BitField conn_flags 0=off, …
9693 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0
9694 …DATE_DATA_DIGEST (0x1<<1) /* BitField conn_flags 0=off, …
9696 …DATE_INITIAL_R2T (0x1<<2) /* BitField conn_flags 0=no, 1…
9698 …DATE_IMMEDIATE_DATA (0x1<<3) /* BitField conn_flags 0=no, 1…
9700 …#define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4) /* B…
9702 …#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6) /* B…
9706 …DATE_HEADER_DIGEST (0x1<<0) /* BitField conn_flags 0=off, …
9707 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0
9708 …DATE_DATA_DIGEST (0x1<<1) /* BitField conn_flags 0=off, …
9710 …DATE_INITIAL_R2T (0x1<<2) /* BitField conn_flags 0=no, 1…
9712 …DATE_IMMEDIATE_DATA (0x1<<3) /* BitField conn_flags 0=no, 1…
9714 …#define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4) /* B…
9716 …#define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6) /* B…
9793 …#define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0) /*…
9794 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0
9795 …#define TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN (0x1<<12) /* …
9797 …#define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13) /* …
9799 …#define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14) /* …
9839 …#define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) /* B…
9840 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
9841 …#define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) /* B…
9843 …#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) /* B…
9845 …#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) /* B…
9847 …#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) /* B…
9849 …#define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) /*…
9855 …#define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) /* B…
9856 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
9857 …#define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) /* B…
9859 …#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) /* B…
9861 …#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) /* B…
9863 …#define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) /* B…
9865 …#define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) /*…
9880 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) /* B…
9881 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
9882 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) /* B…
9884 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) /* B…
9886 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) /* B…
9888 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* B…
9894 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) /* B…
9895 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
9896 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) /* B…
9898 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) /* B…
9900 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) /* B…
9902 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* B…
9907 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)…
9908 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
9909 …#define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /*…
10018 …#define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0)…
10019 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0
10020 …#define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24) /*…
10023 …#define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0)…
10024 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0
10025 …#define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24) /*…
10028 …#define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0)…
10029 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0
10030 …#define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24) /*…
10058 …#define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) /* B…
10059 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
10060 …#define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) /* B…
10062 …#define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) /* B…
10064 …#define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) /* …
10072 …#define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) /* B…
10073 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
10074 …#define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) /* B…
10076 …#define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) /* B…
10078 …#define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) /* …
10102 …#define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0)…
10103 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0
10104 …#define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24) /*…
10107 …#define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0)…
10108 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0
10109 …#define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24) /* …
10111 …#define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25) /* …
10113 …#define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26) /* …
10115 …#define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27) /* …
10117 …#define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28) /* …
10119 …YPE (0x3<<29) /* BitField negotiated_rx_and_flags Task …
10121 …#define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31) /* …
10131 …#define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0)…
10132 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0
10133 …#define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24) /* …
10135 …#define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25) /* …
10137 …#define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26) /* …
10139 …#define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27) /* …
10141 …#define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28) /* …
10143 …#define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29) /* …
10145 …#define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30) /* …
10147 …#define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31) /* …
10150 …#define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0)…
10151 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0
10152 …#define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24) /* …
10154 …#define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25) /* …
10156 …#define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26) /* …
10158 …#define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27) /* …
10160 …#define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28) /* …
10162 …#define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29) /* …
10164 …#define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30) /* …
10166 …#define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31) /* …
10253 …#define ISCSI_TERM_VARS_TCP_STATE (0xF<<0) /* B…
10254 #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0
10255 …#define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) /* B…
10257 …#define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) /* B…
10259 …#define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6) /* B…
10261 …#define ISCSI_TERM_VARS_RSRV (0x1<<7) /* B…
10275 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) /* B…
10276 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
10277 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) /* B…
10279 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) /* B…
10281 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) /* B…
10283 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) /* B…
10285 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5) /* B…
10287 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7) /* B…
10293 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) /* B…
10294 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
10295 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) /* B…
10297 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) /* B…
10299 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) /* B…
10301 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) /* B…
10303 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5) /* B…
10305 …#define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7) /* B…
10361 …#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /*…
10362 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
10363 …#define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* …
10365 …#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* …
10369 …#define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /*…
10370 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
10371 …#define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* …
10373 …#define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* …
10449 …#define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0) …
10450 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0
10451 …#define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20) /*…
10453 …#define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28) /* …
10488 …#define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) /* …
10489 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
10490 …#define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) /* B…
10492 …#define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) /* B…
10494 …#define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) /* …
10496 …#define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) /* …
10498 …#define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) /* …
10500 …#define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) /* …
10502 …#define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) /* …
10506 …#define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) /* …
10507 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
10508 …#define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) /* B…
10510 …#define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) /* B…
10512 …#define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) /* …
10514 …#define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) /* …
10516 …#define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) /* …
10518 …#define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) /* …
10520 …#define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) /* …
10536 …#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) /* B…
10537 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
10538 …#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) /* B…
10540 …#define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2) /* …
10544 …#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) /* B…
10545 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
10546 …#define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) /* B…
10548 …#define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2) /* …
10568 …#define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0) /* B…
10569 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
10570 …#define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1) /* B…
10572 …#define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4) /* B…
10574 …#define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5) /* B…
10577 …#define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI (0x7<<0) /* B…
10578 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI_SHIFT 0
10579 …#define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI (0x7<<3) /* B…
10581 …#define XSTORM_COMMON_CONTEXT_SECTION_RESERVED (0x3<<6) /* B…
10587 …#define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI (0x7<<0) /* B…
10588 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI_SHIFT 0
10589 …#define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI (0x7<<3) /* B…
10591 …#define XSTORM_COMMON_CONTEXT_SECTION_RESERVED (0x3<<6) /* B…
10594 …#define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0) /* B…
10595 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
10596 …#define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1) /* B…
10598 …#define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4) /* B…
10600 …#define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5) /* B…
10612 …#define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0) /* B…
10613 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0
10614 …#define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1) /* B…
10616 …#define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2) /* B…
10618 …#define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3) /* B…
10620 …#define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4) /* B…
10622 …#define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5) /* B…
10624 …#define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6) /* B…
10626 …#define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7) /* B…
10699 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) /* B…
10700 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
10701 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) /* B…
10703 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) /* B…
10705 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) /* B…
10707 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) /* B…
10709 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) /* B…
10711 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) /* B…
10717 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) /* B…
10718 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
10719 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) /* B…
10721 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) /* B…
10723 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) /* B…
10725 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) /* B…
10727 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) /* B…
10729 …#define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) /* B…
10772 …#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* …
10773 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10774 …#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* B…
10780 …#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* …
10781 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10782 …#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* B…
10787 …#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)…
10788 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10789 …#define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /*…
10811 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) /* B…
10812 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
10813 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) /* B…
10815 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) /* B…
10817 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* B…
10819 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) /* B…
10827 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) /* B…
10828 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
10829 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) /* B…
10831 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) /* B…
10833 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* B…
10835 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) /* B…
10840 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)…
10841 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10842 …#define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /*…
10873 …#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) /* …
10874 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
10875 …#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* B…
10881 …#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) /* …
10882 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
10883 …#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* B…
10888 …#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)…
10889 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10890 …#define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /*…
10914 …#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) /* …
10915 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
10916 …#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* B…
10922 …#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) /* …
10923 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
10924 …#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* B…
10929 …#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)…
10930 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10931 …#define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /*…
10951 …#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) /* …
10952 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10953 …#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* B…
10955 …#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) /* B…
10961 …#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) /* …
10962 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10963 …#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* B…
10965 …#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) /* B…
10970 …#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)…
10971 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10972 …#define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /*…
10990 …#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* …
10991 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10992 …#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) /* B…
10998 …#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* …
10999 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
11000 …#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) /* B…
11005 …#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0)…
11006 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
11007 …#define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /*…
11177 …#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* B…
11178 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
11179 …#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* B…
11181 …#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* B…
11183 …#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* B…
11185 …#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4…
11430 …uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units …
11449 …#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* B…
11450 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
11451 …#define E2_INTEG_DATA_LB_TX (0x1<<1) /* B…
11453 …#define E2_INTEG_DATA_COS_TX (0x1<<2) /* B…
11455 …#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* B…
11457 …#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* B…
11459 …#define E2_INTEG_DATA_RESERVED (0x7<<5) /* B…
11462 …uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational co…
11463 …uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operati…
11465 …uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operati…
11466 …uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational co…
11469 …#define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* B…
11470 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
11471 …#define E2_INTEG_DATA_LB_TX (0x1<<1) /* B…
11473 …#define E2_INTEG_DATA_COS_TX (0x1<<2) /* B…
11475 …#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* B…
11477 …#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* B…
11479 …#define E2_INTEG_DATA_RESERVED (0x7<<5) /* B…
11510 uint8_t vf_id /* VF ID (0-63) */;
11522 uint8_t vf_id /* VF ID (0-63) */;
11534 uint8_t vf_id /* VF ID (0-63) */;
11684 …uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware won…
11710 …uint16_t vxlan_dst_port /* UDP Destination Port to be recognised as VXLAN tunneled packets (0 is d…
11711 …uint16_t geneve_dst_port /* UDP Destination Port to be recognised as GENEVE tunneled packets (0 is…
11715 …case of switch dependent multi-function mode. Setting this to 0 uses the default value of 0x8100 *…
11748 …uint16_t vxlan_dst_port /* UDP Destination Port to be recognised as VXLAN tunneled packets (0 is d…
11749 …uint16_t geneve_dst_port /* UDP Destination Port to be recognised as GENEVE tunneled packets (0 is…
11757 …se of switch dependent multi-function mode. Setting this to 0 restores the default value of 0x8100…
11780 …#define FW_VERSION_OPTIMIZED (0x1<<0) /* B…
11781 #define FW_VERSION_OPTIMIZED_SHIFT 0
11782 …#define FW_VERSION_BIG_ENDIEN (0x1<<1) /* B…
11784 …_VERSION (0x3<<2) /* BitField flags 0 - E1, 1…
11786 …#define __FW_VERSION_RESERVED (0xFFFFFFF<<4…
11807 … (0x1<<0) /* BitField flags Index to a state machine. …
11808 #define HC_INDEX_DATA_SM_ID_SHIFT 0
11809 …#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* B…
11811 …#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* B…
11813 …#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* …
11819 … (0x1<<0) /* BitField flags Index to a state machine. …
11820 #define HC_INDEX_DATA_SM_ID_SHIFT 0
11821 …#define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* B…
11823 …#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* B…
11825 …#define HC_INDEX_DATA_RESERVE (0x1F<<3) /* …
11857 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
11858 uint8_t vnic_id /* Virtual NIC ID (0-3) */;
11859 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
11861 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
11862 uint8_t vnic_id /* Virtual NIC ID (0-3) */;
11863 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
11983 ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */,
12060 uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */;
12118 …#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* B…
12119 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
12120 …#define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* B…
12122 …#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* B…
12124 …_CHIP_VERSION (0x3<<4) /* BitField flags 0 - E1, 1…
12126 …#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* B…
12159 …uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Of…
12462 TCP_EVENT_ADD_PEN=0,
12532 …Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is n…
12534 …Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is n…
12567 …#define __USTORM_TOE_PREFETCHED_BD_START (0x1<<0) /* B…
12568 #define __USTORM_TOE_PREFETCHED_BD_START_SHIFT 0
12569 …#define __USTORM_TOE_PREFETCHED_BD_END (0x1<<1) /* B…
12571 …#define __USTORM_TOE_PREFETCHED_BD_NO_PUSH (0x1<<2) /* B…
12573 …#define USTORM_TOE_PREFETCHED_BD_SPLIT (0x1<<3) /* B…
12575 …#define __USTORM_TOE_PREFETCHED_BD_RESERVED1 (0xFFF<<4) /*…
12577 …Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is n…
12579 …Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is n…
12581 …#define __USTORM_TOE_PREFETCHED_BD_START (0x1<<0) /* B…
12582 #define __USTORM_TOE_PREFETCHED_BD_START_SHIFT 0
12583 …#define __USTORM_TOE_PREFETCHED_BD_END (0x1<<1) /* B…
12585 …#define __USTORM_TOE_PREFETCHED_BD_NO_PUSH (0x1<<2) /* B…
12587 …#define USTORM_TOE_PREFETCHED_BD_SPLIT (0x1<<3) /* B…
12589 …#define __USTORM_TOE_PREFETCHED_BD_RESERVED1 (0xFFF<<4) /*…
12603 …#define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH (0x1<<0) /* B…
12604 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH_SHIFT 0
12605 …#define USTORM_TOE_ST_CONTEXT_PUSH_FLAG (0x1<<1) /* B…
12607 …#define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED (0x1<<2) /* B…
12609 …#define USTORM_TOE_ST_CONTEXT_RESERVED0 (0x1F<<3) /* …
12617 …#define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH (0x1<<0) /* B…
12618 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH_SHIFT 0
12619 …#define USTORM_TOE_ST_CONTEXT_PUSH_FLAG (0x1<<1) /* B…
12621 …#define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED (0x1<<2) /* B…
12623 …#define USTORM_TOE_ST_CONTEXT_RESERVED0 (0x1F<<3) /* …
12756 …#define TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED (0x1<<0) /* B…
12757 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED_SHIFT 0
12758 …#define TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE (0x1<<1) /* B…
12760 …#define TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0 (0x3FFFFFFF<<…
12824 …uint16_t toe_rss_bitmap /* The bitmap specifies which toe rss chains to complete the ramrod on (0 …
12826 …uint16_t toe_rss_bitmap /* The bitmap specifies which toe rss chains to complete the ramrod on (0 …
12842 …#define TOE_RX_BD_START (0x1<<0) /* B…
12843 #define TOE_RX_BD_START_SHIFT 0
12844 …#define TOE_RX_BD_END (0x1<<1) /* B…
12846 …#define TOE_RX_BD_NO_PUSH (0x1<<2) /* B…
12848 …#define TOE_RX_BD_SPLIT (0x1<<3) /* B…
12850 …#define TOE_RX_BD_RESERVED1 (0xFFF<<4) /*…
12856 …#define TOE_RX_BD_START (0x1<<0) /* B…
12857 #define TOE_RX_BD_START_SHIFT 0
12858 …#define TOE_RX_BD_END (0x1<<1) /* B…
12860 …#define TOE_RX_BD_NO_PUSH (0x1<<2) /* B…
12862 …#define TOE_RX_BD_SPLIT (0x1<<3) /* B…
12864 …#define TOE_RX_BD_RESERVED1 (0xFFF<<4) /*…
12893 …#define TOE_RX_CQE_OOO_PARAMS_NBYTES (0xFFFFFF<<0)…
12894 #define TOE_RX_CQE_OOO_PARAMS_NBYTES_SHIFT 0
12895 …#define TOE_RX_CQE_OOO_PARAMS_ISLE_NUM (0xFF<<24) /*…
12905 …QE_IN_ORDER_PARAMS_NBYTES (0xFFFFFFFF<<0) /* BitField i…
12906 #define TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES_SHIFT 0
12925 …#define TOE_RX_CQE_CID (0xFFFFFF<<0)…
12926 #define TOE_RX_CQE_CID_SHIFT 0
12927 …#define TOE_RX_CQE_COMPLETION_OPCODE (0xFF<<24) /*…
12943 …#define TOE_RX_DB_DATA_IGNORE_WND_UPDATES (0x1<<0) /* B…
12944 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES_SHIFT 0
12945 …#define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF (0x1<<1) /* B…
12947 …#define TOE_RX_DB_DATA_RESERVED0 (0x3F<<2) /* …
12953 …#define TOE_RX_DB_DATA_IGNORE_WND_UPDATES (0x1<<0) /* B…
12954 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES_SHIFT 0
12955 …#define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF (0x1<<1) /* B…
12957 …#define TOE_RX_DB_DATA_RESERVED0 (0x3F<<2) /* …
12997 * TOE slow path opcodes (opcode 0 is illegal) - includes commands and completions
13058 struct xstorm_toe_stats_section statistics[2] /* 0 - ipv4 , 1 - ipv6 */;
13081 struct tstorm_toe_stats_section statistics[2] /* 0 - ipv4 , 1 - ipv6 */;
13105 …#define TOE_TX_BD_PUSH (0x1<<0) /* B…
13106 #define TOE_TX_BD_PUSH_SHIFT 0
13107 …#define TOE_TX_BD_NOTIFY (0x1<<1) /* B…
13109 …#define TOE_TX_BD_FIN (0x1<<2) /* B…
13111 …#define TOE_TX_BD_LARGE_IO (0x1<<3) /* B…
13113 …#define TOE_TX_BD_RESERVED1 (0xFFF<<4) /*…
13119 …#define TOE_TX_BD_PUSH (0x1<<0) /* B…
13120 #define TOE_TX_BD_PUSH_SHIFT 0
13121 …#define TOE_TX_BD_NOTIFY (0x1<<1) /* B…
13123 …#define TOE_TX_BD_FIN (0x1<<2) /* B…
13125 …#define TOE_TX_BD_LARGE_IO (0x1<<3) /* B…
13127 …#define TOE_TX_BD_RESERVED1 (0xFFF<<4) /*…
13140 …#define TOE_TX_CQE_CID (0xFFFFFF<<0)…
13141 #define TOE_TX_CQE_CID_SHIFT 0
13142 …#define TOE_TX_CQE_COMPLETION_OPCODE (0xFF<<24) /*…
13156 …#define TOE_TX_DB_DATA_FIN (0x1<<0) /* B…
13157 #define TOE_TX_DB_DATA_FIN_SHIFT 0
13158 …#define TOE_TX_DB_DATA_FLUSH (0x1<<1) /* B…
13160 …#define TOE_TX_DB_DATA_RESERVE (0x3FFF<<2) /…
13166 …#define TOE_TX_DB_DATA_FIN (0x1<<0) /* B…
13167 #define TOE_TX_DB_DATA_FIN_SHIFT 0
13168 …#define TOE_TX_DB_DATA_FLUSH (0x1<<1) /* B…
13170 …#define TOE_TX_DB_DATA_RESERVE (0x3FFF<<2) /…
13182 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED (0x1<<0) /* B…
13183 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED_SHIFT 0
13184 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED (0x1<<1) /* B…
13186 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED (0x1<<2) /* B…
13188 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED (0x1<<3) /* B…
13190 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED (0x1<<4) /* B…
13192 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED (0x1<<5) /* B…
13194 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED (0x1<<6) /* B…
13196 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED (0x1<<7) /* B…
13198 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED (0x1<<8) /* B…
13200 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED (0x1<<9) /* B…
13202 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED (0x1<<10) /* …
13204 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED (0x1<<11) /* …
13206 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED (0x1<<12) /* …
13208 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED (0x1<<13) /* …
13210 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED (0x1<<14) /* …
13212 …#define TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED (0x1<<15) /* …