1059 						     speed_cap_mask[cfg_idx]));  in elink_check_lfa()
1061 		if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {  in elink_check_lfa()
1064 				       params->speed_cap_mask[cfg_idx]);  in elink_check_lfa()
4265 		params->phy[actual_phy_idx].speed_cap_mask =  in set_phy_vars()
4266 			params->speed_cap_mask[link_cfg_idx];  in set_phy_vars()
4279 			   params->phy[actual_phy_idx].speed_cap_mask);  in set_phy_vars()
4593 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||  in elink_warpcore_enable_AN_KR()
4603 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||  in elink_warpcore_enable_AN_KR()
4666 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||  in elink_warpcore_enable_AN_KR()
5320 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)  in elink_sfp_e3_set_transmitter()
5822 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)  in elink_set_parallel_detection()
5827 		phy->speed_cap_mask, control2);  in elink_set_parallel_detection()
5834 	     (phy->speed_cap_mask &  in elink_set_parallel_detection()
5946 		if (phy->speed_cap_mask &  in elink_set_autoneg()
5949 		if (phy->speed_cap_mask &  in elink_set_autoneg()
6026 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)  in elink_set_brcm_cl37_advertisement()
6028 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)  in elink_set_brcm_cl37_advertisement()
6844 	     (phy->speed_cap_mask >=  in elink_prepare_xgxs()
6846 	     (phy->speed_cap_mask <  in elink_prepare_xgxs()
8347 		if (phy->speed_cap_mask &  in elink_8073_config_init()
8352 		if (phy->speed_cap_mask &  in elink_8073_config_init()
8362 	if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&  in elink_8073_config_init()
10012 		   (phy->speed_cap_mask &  in elink_8726_config_init()
10014 		   ((phy->speed_cap_mask &  in elink_8726_config_init()
10171 		   ((phy->speed_cap_mask &  in elink_8727_config_speed()
10173 		   ((phy->speed_cap_mask &  in elink_8727_config_speed()
10713 	     (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10730 		if (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10739 		if (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10748 		if ((phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10756 		if ((phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
10807 	    (phy->speed_cap_mask &  in elink_848xx_cmn_config_init()
11923 			(phy->speed_cap_mask &  in elink_54618se_config_init()
11943 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11949 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11955 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
11961 		if (phy->speed_cap_mask &  in elink_54618se_config_init()
12436 	.speed_cap_mask	= 0,
12471 	.speed_cap_mask	= 0,
12507 	.speed_cap_mask	= 0,
12545 	.speed_cap_mask	= 0,
12576 	.speed_cap_mask	= 0,
12607 	.speed_cap_mask	= 0,
12635 	.speed_cap_mask	= 0,
12664 	.speed_cap_mask	= 0,
12696 	.speed_cap_mask	= 0,
12727 	.speed_cap_mask	= 0,
12762 	.speed_cap_mask	= 0,
12799 	.speed_cap_mask	= 0,
12835 	.speed_cap_mask	= 0,
12869 	.speed_cap_mask	= 0,
12903 	.speed_cap_mask	= 0,
12938 	.speed_cap_mask	= 0,
13308 		phy->speed_cap_mask = REG_RD(sc, params->shmem_base +  in elink_phy_def_cfg()
13316 		phy->speed_cap_mask = REG_RD(sc, params->shmem_base +  in elink_phy_def_cfg()
13323 	   phy_index, link_config, phy->speed_cap_mask);  in elink_phy_def_cfg()
13921 				speed_cap_mask[cfg_idx]),  in elink_cannot_avoid_link_flap()
13922 		       params->speed_cap_mask[cfg_idx]);  in elink_cannot_avoid_link_flap()
14980 		     (phy->speed_cap_mask &  in elink_period_func()