2250 				   params->phy[phy_index].mdio_ctrl);  in elink_set_mdio_emac_per_phy()
3420 	mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in elink_cl22_write()
3421 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in elink_cl22_write()
3428 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl22_write()
3433 		tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl22_write()
3443 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in elink_cl22_write()
3456 	mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in elink_cl22_read()
3457 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in elink_cl22_read()
3464 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl22_read()
3469 		val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl22_read()
3482 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in elink_cl22_read()
3499 		elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);  in elink_cl45_read()
3503 		elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_read()
3509 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl45_read()
3514 		val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl45_read()
3531 		REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in elink_cl45_read()
3536 			val = REG_RD(sc, phy->mdio_ctrl +  in elink_cl45_read()
3561 		elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_read()
3576 		elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);  in elink_cl45_write()
3580 		elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_write()
3587 	REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl45_write()
3592 		tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl45_write()
3608 		REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in elink_cl45_write()
3613 			tmp = REG_RD(sc, phy->mdio_ctrl +  in elink_cl45_write()
3636 		elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in elink_cl45_write()
9202 	fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);  in elink_verify_sfp_module()
12430 	.mdio_ctrl	= 0,
12456 	.mdio_ctrl	= 0,
12491 	.mdio_ctrl	= 0,
12526 	.mdio_ctrl	= 0,
12566 	.mdio_ctrl	= 0,
12595 	.mdio_ctrl	= 0,
12626 	.mdio_ctrl	= 0,
12654 	.mdio_ctrl	= 0,
12685 	.mdio_ctrl	= 0,
12717 	.mdio_ctrl	= 0,
12747 	.mdio_ctrl	= 0,
12784 	.mdio_ctrl	= 0,
12822 	.mdio_ctrl	= 0,
12856 	.mdio_ctrl	= 0,
12890 	.mdio_ctrl	= 0,
12924 	.mdio_ctrl	= 0,
13142 	phy->mdio_ctrl = elink_get_emac_base(sc,  in elink_populate_int_phy()
13151 		   port, phy->addr, phy->mdio_ctrl);  in elink_populate_int_phy()
13265 	phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);  in elink_populate_ext_phy()
13281 		   phy->addr, phy->mdio_ctrl);  in elink_populate_ext_phy()