953 	uint32_t val = REG_RD(sc, reg);  in elink_bits_en()
962 	uint32_t val = REG_RD(sc, reg);  in elink_bits_dis()
985 		REG_RD(sc, params->lfa_base +  in elink_check_lfa()
1000 	link_status = REG_RD(sc, params->shmem_base +  in elink_check_lfa()
1029 	saved_val = REG_RD(sc, params->lfa_base +  in elink_check_lfa()
1038 	saved_val = REG_RD(sc, params->lfa_base +  in elink_check_lfa()
1047 	saved_val = REG_RD(sc, params->lfa_base +  in elink_check_lfa()
1057 		cur_speed_cap_mask = REG_RD(sc, params->lfa_base +  in elink_check_lfa()
1070 		REG_RD(sc, params->lfa_base +  in elink_check_lfa()
1080 	eee_status = REG_RD(sc, params->shmem2_base +  in elink_check_lfa()
1111 	gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);  in elink_get_epio()
1114 	*en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;  in elink_get_epio()
1128 	gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);  in elink_set_epio()
1137 	gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);  in elink_set_epio()
2158 	val_xoff = REG_RD(sc, emac_base +  in elink_emac_get_pfc_stat()
2161 	val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);  in elink_emac_get_pfc_stat()
2167 	val_xoff = REG_RD(sc, emac_base +  in elink_emac_get_pfc_stat()
2170 	val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);  in elink_emac_get_pfc_stat()
2206 	cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);  in elink_set_mdio_clk()
2232 	port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);  in elink_is_4_port_mode()
2238 	return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);  in elink_is_4_port_mode()
2271 	val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);  in elink_emac_init()
2276 		val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);  in elink_emac_init()
2317 	if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &  in elink_set_umac_rxtx()
2320 	val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);  in elink_set_umac_rxtx()
2445 	    (REG_RD(sc, MISC_REG_RESET_REG_2) &  in elink_xmac_init()
2499 	if (REG_RD(sc, MISC_REG_RESET_REG_2) &  in elink_set_xmac_rxtx()
2505 		pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);  in elink_set_xmac_rxtx()
2511 		val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);  in elink_set_xmac_rxtx()
2652 		val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);  in elink_emac_enable()
2683 	val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);  in elink_emac_enable()
2712 	val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);  in elink_emac_enable()
2951 	xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :  in elink_update_pfc_nig()
3060 		val = REG_RD(sc, MISC_REG_RESET_REG_2);  in elink_update_pfc()
3271 	uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4);  in elink_set_bmac_rx()
3278 	if (REG_RD(sc, MISC_REG_RESET_REG_2) &  in elink_set_bmac_rx()
3304 	init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port*4);  in elink_pbf_update()
3305 	crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);  in elink_pbf_update()
3310 		crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);  in elink_pbf_update()
3313 	crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);  in elink_pbf_update()
3385 		if (REG_RD(sc, NIG_REG_PORT_SWAP))  in elink_get_emac_base()
3391 		if (REG_RD(sc, NIG_REG_PORT_SWAP))  in elink_get_emac_base()
3420 	mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in elink_cl22_write()
3433 		tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl22_write()
3456 	mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in elink_cl22_read()
3469 		val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl22_read()
3497 		chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |  in elink_cl45_read()
3498 			  ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);  in elink_cl45_read()
3514 		val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl45_read()
3536 			val = REG_RD(sc, phy->mdio_ctrl +  in elink_cl45_read()
3574 		chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |  in elink_cl45_write()
3575 			  ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);  in elink_cl45_write()
3592 		tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in elink_cl45_write()
3613 			tmp = REG_RD(sc, phy->mdio_ctrl +  in elink_cl45_write()
3648 	if (REG_RD(sc, params->shmem2_base) <=  in elink_eee_has_cap()
3713 		eee_mode = ((REG_RD(sc, params->shmem_base +  in elink_eee_calc_timer()
3889 	board_cfg = REG_RD(sc, params->shmem_base +  in elink_bsc_module_sel()
3897 	sfp_ctrl = REG_RD(sc, params->shmem_base +  in elink_bsc_module_sel()
3926 	val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);  in elink_bsc_read()
3943 	val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);  in elink_bsc_read()
3946 		val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);  in elink_bsc_read()
3967 	val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);  in elink_bsc_read()
3970 		val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);  in elink_bsc_read()
3981 		data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));  in elink_bsc_read()
4058 		path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);  in elink_get_warpcore_lane()
4062 			path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);  in elink_get_warpcore_lane()
4068 		port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);  in elink_get_warpcore_lane()
4072 			port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);  in elink_get_warpcore_lane()
4082 			REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);  in elink_get_warpcore_lane()
4087 				REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);  in elink_get_warpcore_lane()
4645 	if (REG_RD(sc, params->shmem_base +  in elink_warpcore_enable_AN_KR()
4685 		wc_lane_config = REG_RD(sc, params->shmem_base +  in elink_warpcore_enable_AN_KR()
4836 		cfg_tap_val = REG_RD(sc, params->shmem_base +  in elink_warpcore_set_10G_XFI()
5171 		cfg_pin = (REG_RD(sc, shmem_base +  in elink_get_mod_abs_int_cfg()
5248 		serdes_net_if = (REG_RD(sc, params->shmem_base +  in elink_warpcore_config_runtime()
5311 	cfg_pin = REG_RD(sc, params->shmem_base +  in elink_sfp_e3_set_transmitter()
5332 	serdes_net_if = (REG_RD(sc, params->shmem_base +  in elink_warpcore_config_init()
5648 	vars->link_status = REG_RD(sc, params->shmem_base +  in elink_link_status_update()
5658 		vars->eee_status = REG_RD(sc, params->shmem2_base +  in elink_link_status_update()
5668 	media_types = REG_RD(sc, sync_offset);  in elink_link_status_update()
5686 	vars->aeu_int_mask = REG_RD(sc, sync_offset);  in elink_link_status_update()
6938 		 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));  in elink_link_int_enable()
6940 		 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),  in elink_link_int_enable()
6941 		 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),  in elink_link_int_enable()
6942 		 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));  in elink_link_int_enable()
6944 	   REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),  in elink_link_int_enable()
6945 	   REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));  in elink_link_int_enable()
6958 	latch_status = REG_RD(sc,  in elink_rearm_latch_signal()
7082 	spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);  in elink_get_ext_phy_fw_version()
7092 		spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);  in elink_get_ext_phy_fw_version()
7121 			md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +  in elink_set_xgxs_loopback()
7662 		val = REG_RD(sc, addr) + 1;  in elink_chng_link_count()
7709 		 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));  in elink_link_update()
7712 		 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),  in elink_link_update()
7713 		 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18) > 0,  in elink_link_update()
7714 		 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));  in elink_link_update()
7717 	  REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),  in elink_link_update()
7718 	  REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));  in elink_link_update()
8314 	if (REG_RD(sc, params->shmem_base +  in elink_8073_config_init()
8674 	swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);  in elink_get_gpio_port()
8675 	swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);  in elink_get_gpio_port()
8689 	tx_en_mode = REG_RD(sc, params->shmem_base +  in elink_sfp_e1e2_set_transmitter()
8821 	pin_cfg = (REG_RD(sc, params->shmem_base +  in elink_warpcore_power_module()
9128 	media_types = REG_RD(sc, sync_offset);  in elink_get_edc_mode()
9173 	val = REG_RD(sc, params->shmem_base +  in elink_verify_sfp_module()
9438 	uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +  in elink_set_e1e2_module_fault_led()
9471 	pin_cfg = (REG_RD(sc, params->shmem_base +  in elink_set_e3_module_fault_led()
9593 	uint32_t val = REG_RD(sc, params->shmem_base +  in elink_sfp_module_detection()
9887 	tx_en_mode = REG_RD(sc, params->shmem_base +  in elink_8706_config_init()
10135 	swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);  in elink_8727_hw_reset()
10136 	swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);  in elink_8727_hw_reset()
10260 	tx_en_mode = REG_RD(sc, params->shmem_base +  in elink_8727_config_init()
10290 	uint32_t val = REG_RD(sc, params->shmem_base +  in elink_8727_handle_mod_abs()
11015 	    (REG_RD(sc, params->shmem2_base +  in elink_848xx_cmd_hdlr()
11036 	pair_swap = REG_RD(sc, params->shmem_base +  in elink_848xx_pair_swap_cfg()
11067 			reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +  in elink_84833_get_reset_gpios()
11080 			reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +  in elink_84833_get_reset_gpios()
11099 	uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +  in elink_84833_hw_reset_phy()
11288 		uint32_t cms_enable = REG_RD(sc, params->shmem_base +  in elink_848x3_config_init()
11623 				if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +  in elink_848xx_set_link_led()
11691 				if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +  in elink_848xx_set_link_led()
11858 	cfg_pin = (REG_RD(sc, params->shmem_base +  in elink_54618se_config_init()
12099 	cfg_pin = (REG_RD(sc, params->shmem_base +  in elink_54618se_link_reset()
12968 			rx = REG_RD(sc, shmem_base +  in elink_populate_preemphasis()
12972 			tx = REG_RD(sc, shmem_base +  in elink_populate_preemphasis()
12976 			rx = REG_RD(sc, shmem_base +  in elink_populate_preemphasis()
12980 			tx = REG_RD(sc, shmem_base +  in elink_populate_preemphasis()
13001 		ext_phy_config = REG_RD(sc, shmem_base +  in elink_get_ext_phy_config()
13006 		ext_phy_config = REG_RD(sc, shmem_base +  in elink_get_ext_phy_config()
13022 	uint32_t switch_cfg = (REG_RD(sc, shmem_base +  in elink_populate_int_phy()
13026 	chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |  in elink_populate_int_phy()
13027 		((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);  in elink_populate_int_phy()
13032 		phy_addr = REG_RD(sc,  in elink_populate_int_phy()
13035 		if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)  in elink_populate_int_phy()
13040 		serdes_net_if = (REG_RD(sc, shmem_base +  in elink_populate_int_phy()
13125 			phy_addr = REG_RD(sc,  in elink_populate_int_phy()
13131 			phy_addr = REG_RD(sc,  in elink_populate_int_phy()
13239 	config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,  in elink_populate_ext_phy()
13250 		uint32_t size = REG_RD(sc, shmem2_base);  in elink_populate_ext_phy()
13271 		uint32_t raw_ver = REG_RD(sc, phy->ver_addr);  in elink_populate_ext_phy()
13305 		link_config = REG_RD(sc, params->shmem_base +  in elink_phy_def_cfg()
13308 		phy->speed_cap_mask = REG_RD(sc, params->shmem_base +  in elink_phy_def_cfg()
13313 		link_config = REG_RD(sc, params->shmem_base +  in elink_phy_def_cfg()
13316 		phy->speed_cap_mask = REG_RD(sc, params->shmem_base +  in elink_phy_def_cfg()
13461 		media_types = REG_RD(sc, sync_offset);  in elink_phy_probe()
13846 	lfa_sts = REG_RD(sc, params->lfa_base +  in elink_avoid_link_flap()
13925 	tmp_val = REG_RD(sc, params->lfa_base +  in elink_cannot_avoid_link_flap()
13933 	lfa_sts = REG_RD(sc, params->lfa_base +  in elink_cannot_avoid_link_flap()
14166 		if (REG_RD(sc, MISC_REG_RESET_REG_2) &  in elink_link_reset()
14241 	swap_val = REG_RD(sc,  NIG_REG_PORT_SWAP);  in elink_8073_common_init_phy()
14242 	swap_override = REG_RD(sc,  NIG_REG_STRAP_OVERRIDE);  in elink_8073_common_init_phy()
14366 	val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);  in elink_8726_common_init_phy()
14409 	uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +  in elink_get_ext_phy_reset_gpio()
14461 	swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);  in elink_8727_common_init_phy()
14462 	swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);  in elink_8727_common_init_phy()
14638 		val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);  in elink_common_init_phy()
14642 	phy_ver = REG_RD(sc, shmem_base_path[0] +  in elink_common_init_phy()
14674 	cfg_pin = (REG_RD(sc, params->shmem_base +  in elink_check_over_curr()
14790 	    (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))  in elink_check_half_open_conn()
14794 	    (REG_RD(sc, MISC_REG_RESET_REG_2) &  in elink_check_half_open_conn()
14808 		if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))  in elink_check_half_open_conn()
14814 	} else if (REG_RD(sc, MISC_REG_RESET_REG_2) &  in elink_check_half_open_conn()
14845 	cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,  in elink_sfp_tx_fault_detection()
14988 		if ((REG_RD(sc, params->shmem_base +  in elink_period_func()
15088 	swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);  in elink_init_mod_abs_int()
15089 	swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);  in elink_init_mod_abs_int()
15109 	aeu_mask = REG_RD(sc, offset);  in elink_init_mod_abs_int()
15114 	val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);  in elink_init_mod_abs_int()