335 #define	MDIO_PMA_REG_CTRL		0x0  macro
6882 				MDIO_PMA_REG_CTRL, &ctrl);  in elink_wait_reset_complete()
6886 				MDIO_PMA_REG_CTRL, &ctrl);  in elink_wait_reset_complete()
8207 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);  in elink_807x_force_10G()
8590 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);  in elink_8705_config_init()
9810 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);  in elink_8706_config_init()
9919 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);  in elink_8726_config_loopback()
9988 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);  in elink_8726_config_init()
10003 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);  in elink_8726_config_init()
10152 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);  in elink_8727_config_speed()
10192 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);  in elink_8727_config_speed()
10693 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);  in elink_848xx_cmn_config_init()
10843 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);  in elink_8481_config_init()
11193 				MDIO_PMA_REG_CTRL, 0x8000);  in elink_848x3_config_init()
11507 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);  in elink_8481_link_reset()
11872 			 MDIO_PMA_REG_CTRL, 0x8000);  in elink_54618se_config_init()
11914 			MDIO_PMA_REG_CTRL,  in elink_54618se_config_init()
12042 			MDIO_PMA_REG_CTRL, autoneg_val);  in elink_54618se_config_init()
12094 	elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);  in elink_54618se_link_reset()
14284 				 MDIO_PMA_REG_CTRL,  in elink_8073_common_init_phy()
14518 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);  in elink_8727_common_init_phy()