Lines Matching +full:ports +full:- +full:lane +full:- +full:control
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
970 * elink_check_lfa - This function checks if link reinitialization is required,
982 struct bxe_softc *sc = params->sc; in elink_check_lfa()
985 REG_RD(sc, params->lfa_base + in elink_check_lfa()
988 /* NOTE: must be first condition checked - in elink_check_lfa()
993 REG_WR(sc, params->lfa_base + in elink_check_lfa()
1000 link_status = REG_RD(sc, params->shmem_base + in elink_check_lfa()
1002 port_mb[params->port].link_status)); in elink_check_lfa()
1009 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN) in elink_check_lfa()
1013 if (params->loopback_mode) in elink_check_lfa()
1017 if (!params->lfa_base) in elink_check_lfa()
1020 if (params->num_phys == 3) { in elink_check_lfa()
1029 saved_val = REG_RD(sc, params->lfa_base + in elink_check_lfa()
1031 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); in elink_check_lfa()
1037 /* Compare Flow Control */ in elink_check_lfa()
1038 saved_val = REG_RD(sc, params->lfa_base + in elink_check_lfa()
1040 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); in elink_check_lfa()
1042 ELINK_DEBUG_P2(sc, "Flow control mismatch %x vs. %x\n", in elink_check_lfa()
1047 saved_val = REG_RD(sc, params->lfa_base + in elink_check_lfa()
1049 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); in elink_check_lfa()
1057 cur_speed_cap_mask = REG_RD(sc, params->lfa_base + in elink_check_lfa()
1061 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { in elink_check_lfa()
1064 params->speed_cap_mask[cfg_idx]); in elink_check_lfa()
1070 REG_RD(sc, params->lfa_base + in elink_check_lfa()
1074 if ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) { in elink_check_lfa()
1076 cur_req_fc_auto_adv, params->req_fc_auto_adv); in elink_check_lfa()
1080 eee_status = REG_RD(sc, params->shmem2_base + in elink_check_lfa()
1082 eee_status[params->port])); in elink_check_lfa()
1085 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) || in elink_check_lfa()
1087 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) { in elink_check_lfa()
1088 ELINK_DEBUG_P2(sc, "EEE mismatch %x vs. %x\n", params->eee_mode, in elink_check_lfa()
1146 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val); in elink_set_cfg_pin()
1148 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; in elink_set_cfg_pin()
1149 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; in elink_set_cfg_pin()
1159 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val); in elink_get_cfg_pin()
1161 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; in elink_get_cfg_pin()
1162 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; in elink_get_cfg_pin()
1174 struct bxe_softc *sc = params->sc; in elink_ets_e2e3a0_disabled()
1178 /* mapping between entry priority to client number (0,1,2 -debug and in elink_ets_e2e3a0_disabled()
1179 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) in elink_ets_e2e3a0_disabled()
1182 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 in elink_ets_e2e3a0_disabled()
1187 * as strict. Bits 0,1,2 - debug and management entries, 3 - in elink_ets_e2e3a0_disabled()
1188 * COS0 entry, 4 - COS1 entry. in elink_ets_e2e3a0_disabled()
1233 if (vars->link_up) { in elink_ets_get_min_w_val_nig()
1234 if (vars->line_speed == ELINK_SPEED_20000) in elink_ets_get_min_w_val_nig()
1265 struct bxe_softc *sc = params->sc; in elink_ets_e3b0_set_credit_upper_bound_nig()
1266 const uint8_t port = params->port; in elink_ets_e3b0_set_credit_upper_bound_nig()
1303 struct bxe_softc *sc = params->sc; in elink_ets_e3b0_nig_disabled()
1304 const uint8_t port = params->port; in elink_ets_e3b0_nig_disabled()
1306 /* Mapping between entry priority to client number (0,1,2 -debug and in elink_ets_e3b0_nig_disabled()
1307 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - in elink_ets_e3b0_nig_disabled()
1308 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by in elink_ets_e3b0_nig_disabled()
1338 * as strict. Bits 0,1,2 - debug and management entries, 3 - in elink_ets_e3b0_nig_disabled()
1339 * COS0 entry, 4 - COS1 entry. in elink_ets_e3b0_nig_disabled()
1353 * for here is note appropriate.In 2 port mode port0 only COS0-5 in elink_ets_e3b0_nig_disabled()
1355 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT in elink_ets_e3b0_nig_disabled()
1387 struct bxe_softc *sc = params->sc; in elink_ets_e3b0_set_credit_upper_bound_pbf()
1390 const uint8_t port = params->port; in elink_ets_e3b0_set_credit_upper_bound_pbf()
1394 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 in elink_ets_e3b0_set_credit_upper_bound_pbf()
1395 * port mode port1 has COS0-2 that can be used for WFQ. in elink_ets_e3b0_set_credit_upper_bound_pbf()
1419 struct bxe_softc *sc = params->sc; in elink_ets_e3b0_pbf_disabled()
1420 const uint8_t port = params->port; in elink_ets_e3b0_pbf_disabled()
1426 /* Mapping between entry priority to client number 0 - COS0 in elink_ets_e3b0_pbf_disabled()
1427 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. in elink_ets_e3b0_pbf_disabled()
1428 * TODO_ETS - Should be done by reset value or init tool in elink_ets_e3b0_pbf_disabled()
1437 /* TODO_ETS - Should be done by reset value or init tool */ in elink_ets_e3b0_pbf_disabled()
1454 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. in elink_ets_e3b0_pbf_disabled()
1455 * In 4 port mode port1 has COS0-2 that can be used for WFQ. in elink_ets_e3b0_pbf_disabled()
1478 struct bxe_softc *sc = params->sc; in elink_ets_e3b0_disabled()
1501 struct bxe_softc *sc = params->sc; in elink_ets_disabled()
1509 ELINK_DEBUG_P0(sc, "elink_ets_disabled - chip not supported\n"); in elink_ets_disabled()
1526 struct bxe_softc *sc = params->sc; in elink_ets_e3b0_cli_map()
1527 const uint8_t port = params->port; in elink_ets_e3b0_cli_map()
1565 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ in elink_ets_e3b0_set_cos_bw()
1632 struct bxe_softc *sc = params->sc; in elink_ets_e3b0_get_total_bw()
1638 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { in elink_ets_e3b0_get_total_bw()
1639 if (ets_params->cos[cos_idx].state == elink_cos_state_bw) { in elink_ets_e3b0_get_total_bw()
1641 if (!ets_params->cos[cos_idx].params.bw_params.bw) { in elink_ets_e3b0_get_total_bw()
1647 ets_params->cos[cos_idx].params.bw_params.bw in elink_ets_e3b0_get_total_bw()
1651 ets_params->cos[cos_idx].params.bw_params.bw; in elink_ets_e3b0_get_total_bw()
1692 struct bxe_softc *sc = params->sc; in elink_ets_e3b0_sp_pri_to_cos_set()
1693 const uint8_t port = params->port; in elink_ets_e3b0_sp_pri_to_cos_set()
1773 struct bxe_softc *sc = params->sc; in elink_ets_e3b0_sp_set_pri_cli_reg()
1775 const uint8_t port = params->port; in elink_ets_e3b0_sp_set_pri_cli_reg()
1784 uint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1; in elink_ets_e3b0_sp_set_pri_cli_reg()
1867 struct bxe_softc *sc = params->sc; in elink_ets_e3b0_config()
1869 const uint8_t port = params->port; in elink_ets_e3b0_config()
1886 if ((ets_params->num_of_cos > max_num_of_cos)) { in elink_ets_e3b0_config()
1911 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { in elink_ets_e3b0_config()
1912 if (elink_cos_state_bw == ets_params->cos[cos_entry].state) { in elink_ets_e3b0_config()
1920 ets_params->cos[cos_entry].params.bw_params.bw, in elink_ets_e3b0_config()
1923 ets_params->cos[cos_entry].state){ in elink_ets_e3b0_config()
1929 ets_params->cos[cos_entry].params.sp_params.pri, in elink_ets_e3b0_config()
1968 struct bxe_softc *sc = params->sc; in elink_ets_bw_limit_common()
1979 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 in elink_ets_bw_limit_common()
1994 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 in elink_ets_bw_limit_common()
1995 * entry, 4 - COS1 entry. in elink_ets_bw_limit_common()
2013 struct bxe_softc *sc = params->sc; in elink_ets_bw_limit()
2044 struct bxe_softc *sc = params->sc; in elink_ets_strict()
2049 * as strict. Bits 0,1,2 - debug and management entries, in elink_ets_strict()
2050 * 3 - COS0 entry, 4 - COS1 entry. in elink_ets_strict()
2068 /* Mapping between entry priority to client number (0,1,2 -debug and in elink_ets_strict()
2069 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) in elink_ets_strict()
2072 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 in elink_ets_strict()
2073 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 in elink_ets_strict()
2088 struct bxe_softc *sc = params->sc; in elink_update_pfc_xmac()
2093 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in elink_update_pfc_xmac()
2101 if (!(params->feature_config_flags & in elink_update_pfc_xmac()
2104 /* RX flow control - Process pause frame in receive direction in elink_update_pfc_xmac()
2106 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) in elink_update_pfc_xmac()
2109 /* TX flow control - Send pause packet when buffer is full */ in elink_update_pfc_xmac()
2110 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) in elink_update_pfc_xmac()
2134 ((params->mac_addr[2] << 24) | in elink_update_pfc_xmac()
2135 (params->mac_addr[3] << 16) | in elink_update_pfc_xmac()
2136 (params->mac_addr[4] << 8) | in elink_update_pfc_xmac()
2137 (params->mac_addr[5]))); in elink_update_pfc_xmac()
2139 ((params->mac_addr[0] << 8) | in elink_update_pfc_xmac()
2140 (params->mac_addr[1]))); in elink_update_pfc_xmac()
2150 struct bxe_softc *sc = params->sc; in elink_emac_get_pfc_stat()
2151 uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; in elink_emac_get_pfc_stat()
2182 struct bxe_softc *sc = params->sc; in elink_pfc_statistic()
2186 if (!vars->link_up) in elink_pfc_statistic()
2189 if (vars->mac_type == ELINK_MAC_TYPE_EMAC) { in elink_pfc_statistic()
2231 /* Check 4-port override enabled */ in elink_is_4_port_mode()
2234 /* Return 4-port mode override value */ in elink_is_4_port_mode()
2237 /* Return 4-port mode from input pin */ in elink_is_4_port_mode()
2247 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; in elink_set_mdio_emac_per_phy()
2249 elink_set_mdio_clk(sc, params->chip_id, in elink_set_mdio_emac_per_phy()
2250 params->phy[phy_index].mdio_ctrl); in elink_set_mdio_emac_per_phy()
2257 struct bxe_softc *sc = params->sc; in elink_emac_init()
2258 uint8_t port = params->port; in elink_emac_init()
2269 /* init emac - use read-modify-write */ in elink_emac_init()
2282 timeout--; in elink_emac_init()
2287 val = ((params->mac_addr[0] << 8) | in elink_emac_init()
2288 params->mac_addr[1]); in elink_emac_init()
2291 val = ((params->mac_addr[2] << 24) | in elink_emac_init()
2292 (params->mac_addr[3] << 16) | in elink_emac_init()
2293 (params->mac_addr[4] << 8) | in elink_emac_init()
2294 params->mac_addr[5]); in elink_emac_init()
2302 struct bxe_softc *sc = params->sc; in elink_set_xumac_nig()
2304 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, in elink_set_xumac_nig()
2306 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, in elink_set_xumac_nig()
2308 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : in elink_set_xumac_nig()
2314 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; in elink_set_umac_rxtx()
2316 struct bxe_softc *sc = params->sc; in elink_set_umac_rxtx()
2318 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) in elink_set_umac_rxtx()
2335 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; in elink_umac_enable()
2336 struct bxe_softc *sc = params->sc; in elink_umac_enable()
2339 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); in elink_umac_enable()
2343 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); in elink_umac_enable()
2348 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in elink_umac_enable()
2354 switch (vars->line_speed) { in elink_umac_enable()
2369 vars->line_speed); in elink_umac_enable()
2372 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) in elink_umac_enable()
2375 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) in elink_umac_enable()
2378 if (vars->duplex == DUPLEX_HALF) in elink_umac_enable()
2385 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { in elink_umac_enable()
2396 ((params->mac_addr[2] << 24) | in elink_umac_enable()
2397 (params->mac_addr[3] << 16) | in elink_umac_enable()
2398 (params->mac_addr[4] << 8) | in elink_umac_enable()
2399 (params->mac_addr[5]))); in elink_umac_enable()
2401 ((params->mac_addr[0] << 8) | in elink_umac_enable()
2402 (params->mac_addr[1]))); in elink_umac_enable()
2419 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame in elink_umac_enable()
2424 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); in elink_umac_enable()
2425 vars->mac_type = ELINK_MAC_TYPE_UMAC; in elink_umac_enable()
2432 struct bxe_softc *sc = params->sc; in elink_xmac_init()
2435 /* In 4-port mode, need to set the mode only once, so if XMAC is in elink_xmac_init()
2438 * ports of the path in elink_xmac_init()
2448 "XMAC already out of reset in 4-port mode\n"); in elink_xmac_init()
2460 ELINK_DEBUG_P0(sc, "Init XMAC to 2 ports x 10G per path\n"); in elink_xmac_init()
2462 /* Set the number of ports on the system side to up to 2 */ in elink_xmac_init()
2465 /* Set the number of ports on the Warp Core to 10G */ in elink_xmac_init()
2468 /* Set the number of ports on the system side to 1 */ in elink_xmac_init()
2473 /* Set the number of ports on the Warp Core to 10G */ in elink_xmac_init()
2477 "Init XMAC to 20G x 2 ports per path\n"); in elink_xmac_init()
2478 /* Set the number of ports on the Warp Core to 20G */ in elink_xmac_init()
2494 uint8_t port = params->port; in elink_set_xmac_rxtx()
2495 struct bxe_softc *sc = params->sc; in elink_set_xmac_rxtx()
2524 struct bxe_softc *sc = params->sc; in elink_xmac_enable()
2527 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in elink_xmac_enable()
2529 elink_xmac_init(params, vars->line_speed); in elink_xmac_enable()
2538 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); in elink_xmac_enable()
2543 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) { in elink_xmac_enable()
2561 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { in elink_xmac_enable()
2572 /* Set MAC in XLGMII mode for dual-mode */ in elink_xmac_enable()
2573 if ((vars->line_speed == ELINK_SPEED_20000) && in elink_xmac_enable()
2574 (params->phy[ELINK_INT_PHY].supported & in elink_xmac_enable()
2583 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); in elink_xmac_enable()
2585 vars->mac_type = ELINK_MAC_TYPE_XMAC; in elink_xmac_enable()
2593 struct bxe_softc *sc = params->sc; in elink_emac_enable()
2594 uint8_t port = params->port; in elink_emac_enable()
2610 /* Use lane 1 (of lanes 0-3) */ in elink_emac_enable()
2619 /* Use lane 1 (of lanes 0-3) */ in elink_emac_enable()
2627 if (vars->phy_flags & PHY_XGXS_FLAG) { in elink_emac_enable()
2628 uint32_t ser_lane = ((params->lane_config & in elink_emac_enable()
2633 /* select the master lanes (out of 0-3) */ in elink_emac_enable()
2663 if (!(params->feature_config_flags & in elink_emac_enable()
2665 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) in elink_emac_enable()
2670 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) in elink_emac_enable()
2686 /* Setting this bit causes MAC control frames (except for pause in elink_emac_enable()
2694 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { in elink_emac_enable()
2738 if ((params->feature_config_flags & in elink_emac_enable()
2740 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) in elink_emac_enable()
2758 vars->mac_type = ELINK_MAC_TYPE_EMAC; in elink_emac_enable()
2766 struct bxe_softc *sc = params->sc; in elink_update_pfc_bmac1()
2767 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : in elink_update_pfc_bmac1()
2771 if ((!(params->feature_config_flags & in elink_update_pfc_bmac1()
2773 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) in elink_update_pfc_bmac1()
2780 /* TX control */ in elink_update_pfc_bmac1()
2782 if (!(params->feature_config_flags & in elink_update_pfc_bmac1()
2784 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) in elink_update_pfc_bmac1()
2795 /* Set rx control: Strip CRC and enable BigMAC to relay in elink_update_pfc_bmac2()
2796 * control packets to the system as well in elink_update_pfc_bmac2()
2799 struct bxe_softc *sc = params->sc; in elink_update_pfc_bmac2()
2800 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : in elink_update_pfc_bmac2()
2804 if ((!(params->feature_config_flags & in elink_update_pfc_bmac2()
2806 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) in elink_update_pfc_bmac2()
2814 /* Tx control */ in elink_update_pfc_bmac2()
2816 if (!(params->feature_config_flags & in elink_update_pfc_bmac2()
2818 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) in elink_update_pfc_bmac2()
2824 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { in elink_update_pfc_bmac2()
2848 * re-sending of PP packets amd enable automatic re-send of in elink_update_pfc_bmac2()
2849 * Per-Priroity Packet as long as pp_gen is asserted and in elink_update_pfc_bmac2()
2853 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) in elink_update_pfc_bmac2()
2854 val |= (1<<16); /* enable automatic re-send */ in elink_update_pfc_bmac2()
2861 /* mac control */ in elink_update_pfc_bmac2()
2868 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) in elink_update_pfc_bmac2()
2926 struct bxe_softc *sc = params->sc; in elink_update_mng()
2928 REG_WR(sc, params->shmem_base + in elink_update_mng()
2930 port_mb[params->port].link_status), link_status); in elink_update_mng()
2940 struct bxe_softc *sc = params->sc; in elink_update_pfc_nig()
2941 uint8_t port = params->port; in elink_update_pfc_nig()
2943 int set_pfc = params->feature_config_flags & in elink_update_pfc_nig()
2948 * MAC control frames (that are not pause packets) in elink_update_pfc_nig()
2970 llfc_out_en = nig_params->llfc_out_en; in elink_update_pfc_nig()
2971 llfc_enable = nig_params->llfc_enable; in elink_update_pfc_nig()
2972 pause_enable = nig_params->pause_enable; in elink_update_pfc_nig()
2973 } else /* Default non PFC mode - PAUSE */ in elink_update_pfc_nig()
3010 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; in elink_update_pfc_nig()
3012 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) in elink_update_pfc_nig()
3014 nig_params->rx_cos_priority_mask[i], port); in elink_update_pfc_nig()
3018 nig_params->llfc_high_priority_classes); in elink_update_pfc_nig()
3022 nig_params->llfc_low_priority_classes); in elink_update_pfc_nig()
3038 struct bxe_softc *sc = params->sc; in elink_update_pfc()
3039 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC); in elink_update_pfc()
3041 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) in elink_update_pfc()
3042 vars->link_status |= LINK_STATUS_PFC_ENABLED; in elink_update_pfc()
3044 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; in elink_update_pfc()
3046 elink_update_mng(params, vars->link_status); in elink_update_pfc()
3051 if (!vars->link_up) in elink_update_pfc()
3057 if (vars->mac_type == ELINK_MAC_TYPE_XMAC) in elink_update_pfc()
3062 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) in elink_update_pfc()
3074 if ((params->feature_config_flags & in elink_update_pfc()
3076 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) in elink_update_pfc()
3078 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); in elink_update_pfc()
3087 struct bxe_softc *sc = params->sc; in elink_bmac1_enable()
3088 uint8_t port = params->port; in elink_bmac1_enable()
3096 /* XGXS control */ in elink_bmac1_enable()
3103 wb_data[0] = ((params->mac_addr[2] << 24) | in elink_bmac1_enable()
3104 (params->mac_addr[3] << 16) | in elink_bmac1_enable()
3105 (params->mac_addr[4] << 8) | in elink_bmac1_enable()
3106 params->mac_addr[5]); in elink_bmac1_enable()
3107 wb_data[1] = ((params->mac_addr[0] << 8) | in elink_bmac1_enable()
3108 params->mac_addr[1]); in elink_bmac1_enable()
3111 /* MAC control */ in elink_bmac1_enable()
3160 struct bxe_softc *sc = params->sc; in elink_bmac2_enable()
3161 uint8_t port = params->port; in elink_bmac2_enable()
3173 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ in elink_bmac2_enable()
3182 wb_data[0] = ((params->mac_addr[2] << 24) | in elink_bmac2_enable()
3183 (params->mac_addr[3] << 16) | in elink_bmac2_enable()
3184 (params->mac_addr[4] << 8) | in elink_bmac2_enable()
3185 params->mac_addr[5]); in elink_bmac2_enable()
3186 wb_data[1] = ((params->mac_addr[0] << 8) | in elink_bmac2_enable()
3187 params->mac_addr[1]); in elink_bmac2_enable()
3212 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2; in elink_bmac2_enable()
3226 uint8_t port = params->port; in elink_bmac_enable()
3227 struct bxe_softc *sc = params->sc; in elink_bmac_enable()
3251 if ((params->feature_config_flags & in elink_bmac_enable()
3253 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) in elink_bmac_enable()
3262 vars->mac_type = ELINK_MAC_TYPE_BMAC; in elink_bmac_enable()
3295 struct bxe_softc *sc = params->sc; in elink_pbf_update()
3296 uint8_t port = params->port; in elink_pbf_update()
3311 count--; in elink_pbf_update()
3329 init_crd = 778; /* (800-18-4) */ in elink_pbf_update()
3340 init_crd = thresh + 553 - 22; in elink_pbf_update()
3363 * elink_get_emac_base - retrive emac base address
3420 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in elink_cl22_write()
3421 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in elink_cl22_write()
3425 tmp = ((phy->addr << 21) | (reg << 16) | val | in elink_cl22_write()
3428 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in elink_cl22_write()
3433 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in elink_cl22_write()
3443 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in elink_cl22_write()
3456 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in elink_cl22_read()
3457 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in elink_cl22_read()
3461 val = ((phy->addr << 21) | (reg << 16) | in elink_cl22_read()
3464 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in elink_cl22_read()
3469 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in elink_cl22_read()
3482 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in elink_cl22_read()
3496 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { in elink_cl45_read()
3499 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl); in elink_cl45_read()
3502 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) in elink_cl45_read()
3503 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in elink_cl45_read()
3506 val = ((phy->addr << 21) | (devad << 16) | reg | in elink_cl45_read()
3509 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in elink_cl45_read()
3514 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in elink_cl45_read()
3528 val = ((phy->addr << 21) | (devad << 16) | in elink_cl45_read()
3531 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in elink_cl45_read()
3536 val = REG_RD(sc, phy->mdio_ctrl + in elink_cl45_read()
3552 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { in elink_cl45_read()
3553 phy->flags ^= ELINK_FLAGS_DUMMY_READ; in elink_cl45_read()
3554 if (phy->flags & ELINK_FLAGS_DUMMY_READ) { in elink_cl45_read()
3560 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) in elink_cl45_read()
3561 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in elink_cl45_read()
3573 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { in elink_cl45_write()
3576 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl); in elink_cl45_write()
3579 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) in elink_cl45_write()
3580 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in elink_cl45_write()
3584 tmp = ((phy->addr << 21) | (devad << 16) | reg | in elink_cl45_write()
3587 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in elink_cl45_write()
3592 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in elink_cl45_write()
3605 tmp = ((phy->addr << 21) | (devad << 16) | val | in elink_cl45_write()
3608 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in elink_cl45_write()
3613 tmp = REG_RD(sc, phy->mdio_ctrl + in elink_cl45_write()
3628 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { in elink_cl45_write()
3629 phy->flags ^= ELINK_FLAGS_DUMMY_READ; in elink_cl45_write()
3630 if (phy->flags & ELINK_FLAGS_DUMMY_READ) { in elink_cl45_write()
3635 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) in elink_cl45_write()
3636 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in elink_cl45_write()
3646 struct bxe_softc *sc = params->sc; in elink_eee_has_cap()
3648 if (REG_RD(sc, params->shmem2_base) <= in elink_eee_has_cap()
3649 offsetof(struct shmem2_region, eee_status[params->port])) in elink_eee_has_cap()
3698 struct bxe_softc *sc = params->sc; in elink_eee_calc_timer()
3700 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) { in elink_eee_calc_timer()
3701 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { in elink_eee_calc_timer()
3702 /* time value in eee_mode --> used directly*/ in elink_eee_calc_timer()
3703 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK; in elink_eee_calc_timer()
3705 /* hsi value in eee_mode --> time */ in elink_eee_calc_timer()
3706 if (elink_eee_nvram_to_time(params->eee_mode & in elink_eee_calc_timer()
3712 /* hsi values in nvram --> time*/ in elink_eee_calc_timer()
3713 eee_mode = ((REG_RD(sc, params->shmem_base + in elink_eee_calc_timer()
3715 port_feature_config[params->port]. in elink_eee_calc_timer()
3731 struct bxe_softc *sc = params->sc; in elink_eee_set_timers()
3736 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), in elink_eee_set_timers()
3738 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) && in elink_eee_set_timers()
3739 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) && in elink_eee_set_timers()
3740 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) { in elink_eee_set_timers()
3745 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); in elink_eee_set_timers()
3746 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { in elink_eee_set_timers()
3747 /* eee_idle in 1u --> eee_status in 16u */ in elink_eee_set_timers()
3749 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | in elink_eee_set_timers()
3754 vars->eee_status |= eee_mode; in elink_eee_set_timers()
3763 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT; in elink_eee_initial_config()
3765 /* Propagate params' bits --> vars (for migration exposure) */ in elink_eee_initial_config()
3766 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) in elink_eee_initial_config()
3767 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; in elink_eee_initial_config()
3769 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; in elink_eee_initial_config()
3771 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) in elink_eee_initial_config()
3772 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; in elink_eee_initial_config()
3774 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; in elink_eee_initial_config()
3783 struct bxe_softc *sc = params->sc; in elink_eee_disable()
3786 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); in elink_eee_disable()
3790 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; in elink_eee_disable()
3799 struct bxe_softc *sc = params->sc; in elink_eee_advertise()
3803 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); in elink_eee_advertise()
3806 ELINK_DEBUG_P0(sc, "Advertise 10GBase-T EEE\n"); in elink_eee_advertise()
3810 ELINK_DEBUG_P0(sc, "Advertise 1GBase-T EEE\n"); in elink_eee_advertise()
3816 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; in elink_eee_advertise()
3817 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); in elink_eee_advertise()
3824 struct bxe_softc *sc = params->sc; in elink_update_mng_eee()
3827 REG_WR(sc, params->shmem2_base + in elink_update_mng_eee()
3829 eee_status[params->port]), eee_status); in elink_update_mng_eee()
3836 struct bxe_softc *sc = params->sc; in elink_eee_an_resolve()
3847 if (vars->line_speed == ELINK_SPEED_100) in elink_eee_an_resolve()
3849 ELINK_DEBUG_P0(sc, "EEE negotiated - 100M\n"); in elink_eee_an_resolve()
3855 if (vars->line_speed == ELINK_SPEED_1000) in elink_eee_an_resolve()
3857 ELINK_DEBUG_P0(sc, "EEE negotiated - 1G\n"); in elink_eee_an_resolve()
3863 if (vars->line_speed == ELINK_SPEED_10000) in elink_eee_an_resolve()
3865 ELINK_DEBUG_P0(sc, "EEE negotiated - 10G\n"); in elink_eee_an_resolve()
3869 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; in elink_eee_an_resolve()
3870 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); in elink_eee_an_resolve()
3874 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; in elink_eee_an_resolve()
3886 struct bxe_softc *sc = params->sc; in elink_bsc_module_sel()
3887 uint8_t port = params->port; in elink_bsc_module_sel()
3889 board_cfg = REG_RD(sc, params->shmem_base + in elink_bsc_module_sel()
3897 sfp_ctrl = REG_RD(sc, params->shmem_base + in elink_bsc_module_sel()
3923 xfer_cnt = 16 - lc_addr; in elink_bsc_read()
4016 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { in elink_phy_read()
4017 if (params->phy[phy_index].addr == phy_addr) { in elink_phy_read()
4018 return elink_cl45_read(params->sc, in elink_phy_read()
4019 ¶ms->phy[phy_index], devad, in elink_phy_read()
4033 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { in elink_phy_write()
4034 if (params->phy[phy_index].addr == phy_addr) { in elink_phy_write()
4035 return elink_cl45_write(params->sc, in elink_phy_write()
4036 ¶ms->phy[phy_index], devad, in elink_phy_write()
4046 uint8_t lane = 0; in elink_get_warpcore_lane() local
4047 struct bxe_softc *sc = params->sc; in elink_get_warpcore_lane()
4052 port = params->port; in elink_get_warpcore_lane()
4077 lane = (port<<1) + path; in elink_get_warpcore_lane()
4078 } else { /* Two port mode - no port swap */ in elink_get_warpcore_lane()
4092 lane = path << 1 ; in elink_get_warpcore_lane()
4094 return lane; in elink_get_warpcore_lane()
4103 struct bxe_softc *sc = params->sc; in elink_set_aer_mmd()
4104 ser_lane = ((params->lane_config & in elink_set_aer_mmd()
4108 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? in elink_set_aer_mmd()
4109 (phy->addr + ser_lane) : 0; in elink_set_aer_mmd()
4113 /* In Dual-lane mode, two lanes are joined together, in elink_set_aer_mmd()
4119 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) in elink_set_aer_mmd()
4122 aer_val = 0x3800 + offset - 1; in elink_set_aer_mmd()
4172 struct bxe_softc *sc = params->sc; in elink_xgxs_specific_func()
4176 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); in elink_xgxs_specific_func()
4177 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, in elink_xgxs_specific_func()
4178 phy->def_md_devad); in elink_xgxs_specific_func()
4185 struct bxe_softc *sc = params->sc; in elink_xgxs_deassert()
4189 port = params->port; in elink_xgxs_deassert()
4197 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params, in elink_xgxs_deassert()
4204 struct bxe_softc *sc = params->sc; in elink_calc_ieee_aneg_adv()
4207 * 28B-3 of the 802.3ab-1999 spec in elink_calc_ieee_aneg_adv()
4210 switch (phy->req_flow_ctrl) { in elink_calc_ieee_aneg_adv()
4212 switch (params->req_fc_auto_adv) { in elink_calc_ieee_aneg_adv()
4245 struct bxe_softc *sc = params->sc; in set_phy_vars()
4247 uint8_t phy_config_swapped = params->multi_phy_config & in set_phy_vars()
4249 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; in set_phy_vars()
4259 params->phy[actual_phy_idx].req_flow_ctrl = in set_phy_vars()
4260 params->req_flow_ctrl[link_cfg_idx]; in set_phy_vars()
4262 params->phy[actual_phy_idx].req_line_speed = in set_phy_vars()
4263 params->req_line_speed[link_cfg_idx]; in set_phy_vars()
4265 params->phy[actual_phy_idx].speed_cap_mask = in set_phy_vars()
4266 params->speed_cap_mask[link_cfg_idx]; in set_phy_vars()
4268 params->phy[actual_phy_idx].req_duplex = in set_phy_vars()
4269 params->req_duplex[link_cfg_idx]; in set_phy_vars()
4271 if (params->req_line_speed[link_cfg_idx] == in set_phy_vars()
4273 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; in set_phy_vars()
4277 params->phy[actual_phy_idx].req_flow_ctrl, in set_phy_vars()
4278 params->phy[actual_phy_idx].req_line_speed, in set_phy_vars()
4279 params->phy[actual_phy_idx].speed_cap_mask); in set_phy_vars()
4288 struct bxe_softc *sc = params->sc; in elink_ext_phy_set_pause()
4294 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ in elink_ext_phy_set_pause()
4295 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in elink_ext_phy_set_pause()
4296 if ((vars->ieee_fc & in elink_ext_phy_set_pause()
4301 if ((vars->ieee_fc & in elink_ext_phy_set_pause()
4315 struct bxe_softc *sc = params->sc; in elink_pause_resolve()
4319 ELINK_DEBUG_P0(sc, "Flow Control: TX only\n"); in elink_pause_resolve()
4320 vars->flow_ctrl = ELINK_FLOW_CTRL_TX; in elink_pause_resolve()
4324 ELINK_DEBUG_P0(sc, "Flow Control: RX only\n"); in elink_pause_resolve()
4325 vars->flow_ctrl = ELINK_FLOW_CTRL_RX; in elink_pause_resolve()
4337 if (params->req_fc_auto_adv == ELINK_FLOW_CTRL_BOTH) { in elink_pause_resolve()
4338 ELINK_DEBUG_P0(sc, "Flow Control: RX & TX\n"); in elink_pause_resolve()
4339 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH; in elink_pause_resolve()
4341 ELINK_DEBUG_P0(sc, "Flow Control: RX only\n"); in elink_pause_resolve()
4342 vars->flow_ctrl = ELINK_FLOW_CTRL_RX; in elink_pause_resolve()
4346 ELINK_DEBUG_P0(sc, "Flow Control: None\n"); in elink_pause_resolve()
4347 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_pause_resolve()
4351 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; in elink_pause_resolve()
4353 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; in elink_pause_resolve()
4364 struct bxe_softc *sc = params->sc; in elink_ext_phy_update_adv_fc()
4365 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { in elink_ext_phy_update_adv_fc()
4370 uint8_t lane = elink_get_warpcore_lane(phy, params); in elink_ext_phy_update_adv_fc() local
4377 lane; in elink_ext_phy_update_adv_fc()
4417 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_ext_phy_resolve_fc()
4418 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { in elink_ext_phy_resolve_fc()
4419 /* Update the advertised flow-controlled of LD/LP in AN */ in elink_ext_phy_resolve_fc()
4420 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) in elink_ext_phy_resolve_fc()
4422 /* But set the flow-control result as the requested one */ in elink_ext_phy_resolve_fc()
4423 vars->flow_ctrl = phy->req_flow_ctrl; in elink_ext_phy_resolve_fc()
4424 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) in elink_ext_phy_resolve_fc()
4425 vars->flow_ctrl = params->req_fc_auto_adv; in elink_ext_phy_resolve_fc()
4426 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { in elink_ext_phy_resolve_fc()
4436 * i.e. reset the lane (if needed), set aer for the
4453 struct bxe_softc *sc = params->sc; in elink_update_link_attr()
4456 REG_WR(sc, params->shmem2_base + in elink_update_link_attr()
4458 link_attr_sync[params->port]), link_attr); in elink_update_link_attr()
4465 struct bxe_softc *sc = params->sc; in elink_warpcore_enable_AN_KR2()
4468 /* Step 1 - Program the TX/RX alignment markers */ in elink_warpcore_enable_AN_KR2()
4475 /* Step 2 - Configure the NP registers */ in elink_warpcore_enable_AN_KR2()
4486 ELINK_DEBUG_P0(sc, "Enabling 20G-KR2\n"); in elink_warpcore_enable_AN_KR2()
4495 /* Start KR2 work-around timer which handles BCM8073 link-parner */ in elink_warpcore_enable_AN_KR2()
4496 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; in elink_warpcore_enable_AN_KR2()
4497 elink_update_link_attr(params, params->link_attr_sync); in elink_warpcore_enable_AN_KR2()
4504 struct bxe_softc *sc = params->sc; in elink_disable_kr2()
4507 /* Step 1 - Program the TX/RX alignment markers */ in elink_disable_kr2()
4524 ELINK_DEBUG_P0(sc, "Disabling 20G-KR2\n"); in elink_disable_kr2()
4529 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; in elink_disable_kr2()
4530 elink_update_link_attr(params, params->link_attr_sync); in elink_disable_kr2()
4532 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT; in elink_disable_kr2()
4538 struct bxe_softc *sc = params->sc; in elink_warpcore_set_lpi_passthrough()
4550 /* Restart autoneg on the leading lane only */ in elink_warpcore_restart_AN_KR()
4551 struct bxe_softc *sc = params->sc; in elink_warpcore_restart_AN_KR()
4552 uint16_t lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_restart_AN_KR() local
4554 MDIO_AER_BLOCK_AER_REG, lane); in elink_warpcore_restart_AN_KR()
4565 uint16_t lane, i, cl72_ctrl, an_adv = 0, val; in elink_warpcore_enable_AN_KR() local
4567 struct bxe_softc *sc = params->sc; in elink_warpcore_enable_AN_KR()
4573 /* Disable Autoneg: re-enable it after adv is done. */ in elink_warpcore_enable_AN_KR()
4592 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && in elink_warpcore_enable_AN_KR()
4593 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || in elink_warpcore_enable_AN_KR()
4594 (vars->line_speed == ELINK_SPEED_1000)) { in elink_warpcore_enable_AN_KR()
4602 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && in elink_warpcore_enable_AN_KR()
4603 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || in elink_warpcore_enable_AN_KR()
4604 (vars->line_speed == ELINK_SPEED_10000)) { in elink_warpcore_enable_AN_KR()
4618 lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_enable_AN_KR()
4620 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, in elink_warpcore_enable_AN_KR()
4622 /* Configure the next lane if dual mode */ in elink_warpcore_enable_AN_KR()
4623 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) in elink_warpcore_enable_AN_KR()
4625 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), in elink_warpcore_enable_AN_KR()
4645 if (REG_RD(sc, params->shmem_base + in elink_warpcore_enable_AN_KR()
4647 port_hw_config[params->port].default_cfg)) & in elink_warpcore_enable_AN_KR()
4657 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; in elink_warpcore_enable_AN_KR()
4661 /* Over 1G - AN local device user page 1 */ in elink_warpcore_enable_AN_KR()
4665 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && in elink_warpcore_enable_AN_KR()
4666 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || in elink_warpcore_enable_AN_KR()
4667 (phy->req_line_speed == ELINK_SPEED_20000)) { in elink_warpcore_enable_AN_KR()
4670 MDIO_AER_BLOCK_AER_REG, lane); in elink_warpcore_enable_AN_KR()
4673 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), in elink_warpcore_enable_AN_KR()
4682 /* Enable Auto-Detect to support 1G over CL37 as well */ in elink_warpcore_enable_AN_KR()
4685 wc_lane_config = REG_RD(sc, params->shmem_base + in elink_warpcore_enable_AN_KR()
4689 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); in elink_warpcore_enable_AN_KR()
4691 * parallel-detect loop when CL73 and CL37 are enabled. in elink_warpcore_enable_AN_KR()
4699 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) in elink_warpcore_enable_AN_KR()
4704 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), in elink_warpcore_enable_AN_KR()
4710 /* Enable Autoneg: only on the main lane */ in elink_warpcore_enable_AN_KR()
4718 struct bxe_softc *sc = params->sc; in elink_warpcore_set_10G_KR()
4719 uint16_t val16, i, lane; in elink_warpcore_set_10G_KR() local
4737 lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_set_10G_KR()
4744 val16 &= ~(0x0011 << lane); in elink_warpcore_set_10G_KR()
4750 val16 |= (0x0303 << (lane << 1)); in elink_warpcore_set_10G_KR()
4786 struct bxe_softc *sc = params->sc; in elink_warpcore_set_10G_XFI()
4787 uint16_t misc1_val, tap_val, tx_driver_val, lane, val; in elink_warpcore_set_10G_XFI() local
4801 /* Disable 100FX Enable and Auto-Detect */ in elink_warpcore_set_10G_XFI()
4813 /* Turn off auto-detect & fiber mode */ in elink_warpcore_set_10G_XFI()
4836 cfg_tap_val = REG_RD(sc, params->shmem_base + in elink_warpcore_set_10G_XFI()
4838 port_hw_config[params->port]. in elink_warpcore_set_10G_XFI()
4886 lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_set_10G_XFI()
4891 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, in elink_warpcore_set_10G_XFI()
4921 struct bxe_softc *sc = params->sc; in elink_warpcore_set_20G_force_KR2()
4922 /* Set global registers, so set AER lane to 0 */ in elink_warpcore_set_20G_force_KR2()
4960 /* Enable sequencer (over lane 0) */ in elink_warpcore_set_20G_force_KR2()
4972 uint16_t lane) in elink_warpcore_set_20G_DXGXS() argument
5020 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, in elink_warpcore_set_20G_DXGXS()
5029 struct bxe_softc *sc = params->sc; in elink_warpcore_set_sgmii_speed()
5032 /* Clear XFI clock comp in non-10G single lane mode. */ in elink_warpcore_set_sgmii_speed()
5038 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { in elink_warpcore_set_sgmii_speed()
5048 switch (phy->req_line_speed) { in elink_warpcore_set_sgmii_speed()
5059 "Speed not supported: 0x%x\n", phy->req_line_speed); in elink_warpcore_set_sgmii_speed()
5063 if (phy->req_duplex == DUPLEX_FULL) in elink_warpcore_set_sgmii_speed()
5070 phy->req_line_speed); in elink_warpcore_set_sgmii_speed()
5095 /* Re-enable parallel detect */ in elink_warpcore_set_sgmii_speed()
5112 /* Take lane out of reset after configuration is finished */ in elink_warpcore_reset_lane()
5128 uint16_t lane) in elink_warpcore_clear_regs() argument
5130 struct bxe_softc *sc = params->sc; in elink_warpcore_clear_regs()
5156 lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_clear_regs()
5158 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); in elink_warpcore_clear_regs()
5191 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; in elink_get_mod_abs_int_cfg()
5192 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; in elink_get_mod_abs_int_cfg()
5204 struct bxe_softc *sc = params->sc; in elink_is_sfp_module_plugged()
5207 if (elink_get_mod_abs_int_cfg(sc, params->chip_id, in elink_is_sfp_module_plugged()
5208 params->shmem_base, params->port, in elink_is_sfp_module_plugged()
5222 uint16_t gp2_status_reg0, lane; in elink_warpcore_get_sigdet() local
5223 struct bxe_softc *sc = params->sc; in elink_warpcore_get_sigdet()
5225 lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_get_sigdet()
5230 return (gp2_status_reg0 >> (8+lane)) & 0x1; in elink_warpcore_get_sigdet()
5237 struct bxe_softc *sc = params->sc; in elink_warpcore_config_runtime()
5241 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; in elink_warpcore_config_runtime()
5243 if (!vars->turn_to_run_wc_rt) in elink_warpcore_config_runtime()
5246 if (vars->rx_tx_asic_rst) { in elink_warpcore_config_runtime()
5247 uint16_t lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_config_runtime() local
5248 serdes_net_if = (REG_RD(sc, params->shmem_base + in elink_warpcore_config_runtime()
5250 port_hw_config[params->port].default_cfg)) & in elink_warpcore_config_runtime()
5258 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ in elink_warpcore_config_runtime()
5260 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; in elink_warpcore_config_runtime()
5263 vars->rx_tx_asic_rst = 0; in elink_warpcore_config_runtime()
5265 /* Reset the lane to see if link comes up.*/ in elink_warpcore_config_runtime()
5273 vars->rx_tx_asic_rst--; in elink_warpcore_config_runtime()
5275 vars->rx_tx_asic_rst); in elink_warpcore_config_runtime()
5283 } /*params->rx_tx_asic_rst*/ in elink_warpcore_config_runtime()
5289 uint16_t lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_config_sfi() local
5290 struct bxe_softc *sc = params->sc; in elink_warpcore_config_sfi()
5291 elink_warpcore_clear_regs(phy, params, lane); in elink_warpcore_config_sfi()
5292 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] == in elink_warpcore_config_sfi()
5294 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) { in elink_warpcore_config_sfi()
5307 struct bxe_softc *sc = params->sc; in elink_sfp_e3_set_transmitter()
5309 uint8_t port = params->port; in elink_sfp_e3_set_transmitter()
5311 cfg_pin = REG_RD(sc, params->shmem_base + in elink_sfp_e3_set_transmitter()
5320 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) in elink_sfp_e3_set_transmitter()
5328 struct bxe_softc *sc = params->sc; in elink_warpcore_config_init()
5331 uint16_t lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_config_init() local
5332 serdes_net_if = (REG_RD(sc, params->shmem_base + in elink_warpcore_config_init()
5334 port_hw_config[params->port].default_cfg)) & in elink_warpcore_config_init()
5338 vars->line_speed, serdes_net_if); in elink_warpcore_config_init()
5341 vars->phy_flags |= PHY_XGXS_FLAG; in elink_warpcore_config_init()
5343 (phy->req_line_speed && in elink_warpcore_config_init()
5344 ((phy->req_line_speed == ELINK_SPEED_100) || in elink_warpcore_config_init()
5345 (phy->req_line_speed == ELINK_SPEED_10)))) { in elink_warpcore_config_init()
5346 vars->phy_flags |= PHY_SGMII_FLAG; in elink_warpcore_config_init()
5348 elink_warpcore_clear_regs(phy, params, lane); in elink_warpcore_config_init()
5354 if (params->loopback_mode != ELINK_LOOPBACK_EXT) in elink_warpcore_config_init()
5357 ELINK_DEBUG_P0(sc, "Setting KR 10G-Force\n"); in elink_warpcore_config_init()
5363 elink_warpcore_clear_regs(phy, params, lane); in elink_warpcore_config_init()
5364 if (vars->line_speed == ELINK_SPEED_10000) { in elink_warpcore_config_init()
5388 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) || in elink_warpcore_config_init()
5389 (params->loopback_mode == ELINK_LOOPBACK_EXT)) { in elink_warpcore_config_init()
5401 if (vars->line_speed != ELINK_SPEED_20000) { in elink_warpcore_config_init()
5406 elink_warpcore_set_20G_DXGXS(sc, phy, lane); in elink_warpcore_config_init()
5412 if (!params->loopback_mode) { in elink_warpcore_config_init()
5415 ELINK_DEBUG_P0(sc, "Setting KR 20G-Force\n"); in elink_warpcore_config_init()
5427 /* Take lane out of reset after configuration is finished */ in elink_warpcore_config_init()
5435 struct bxe_softc *sc = params->sc; in elink_warpcore_link_reset()
5436 uint16_t val16, lane; in elink_warpcore_link_reset() local
5451 /* Update those 1-copy registers */ in elink_warpcore_link_reset()
5454 /* Enable 1G MDIO (1-copy) */ in elink_warpcore_link_reset()
5461 lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_link_reset()
5465 val16 |= (0x11 << lane); in elink_warpcore_link_reset()
5466 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) in elink_warpcore_link_reset()
5467 val16 |= (0x22 << lane); in elink_warpcore_link_reset()
5473 val16 &= ~(0x0303 << (lane << 1)); in elink_warpcore_link_reset()
5474 val16 |= (0x0101 << (lane << 1)); in elink_warpcore_link_reset()
5475 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) { in elink_warpcore_link_reset()
5476 val16 &= ~(0x0c0c << (lane << 1)); in elink_warpcore_link_reset()
5477 val16 |= (0x0404 << (lane << 1)); in elink_warpcore_link_reset()
5490 struct bxe_softc *sc = params->sc; in elink_set_warpcore_loopback()
5492 uint32_t lane; in elink_set_warpcore_loopback() local
5494 params->loopback_mode, phy->req_line_speed); in elink_set_warpcore_loopback()
5496 if (phy->req_line_speed < ELINK_SPEED_10000 || in elink_set_warpcore_loopback()
5497 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { in elink_set_warpcore_loopback()
5498 /* 10/100/1000/20G-KR2 */ in elink_set_warpcore_loopback()
5500 /* Update those 1-copy registers */ in elink_set_warpcore_loopback()
5503 /* Enable 1G MDIO (1-copy) */ in elink_set_warpcore_loopback()
5507 /* Set 1G loopback based on lane (1-copy) */ in elink_set_warpcore_loopback()
5508 lane = elink_get_warpcore_lane(phy, params); in elink_set_warpcore_loopback()
5511 val16 |= (1<<lane); in elink_set_warpcore_loopback()
5512 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) in elink_set_warpcore_loopback()
5513 val16 |= (2<<lane); in elink_set_warpcore_loopback()
5518 /* Switch back to 4-copy registers */ in elink_set_warpcore_loopback()
5521 /* 10G / 20G-DXGXS */ in elink_set_warpcore_loopback()
5535 struct bxe_softc *sc = params->sc; in elink_sync_link()
5537 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) in elink_sync_link()
5538 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; in elink_sync_link()
5539 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); in elink_sync_link()
5540 if (vars->link_up) { in elink_sync_link()
5542 ELINK_DEBUG_P1(sc, "link status = %x\n", vars->link_status); in elink_sync_link()
5544 vars->phy_link_up = 1; in elink_sync_link()
5545 vars->duplex = DUPLEX_FULL; in elink_sync_link()
5546 switch (vars->link_status & in elink_sync_link()
5549 vars->duplex = DUPLEX_HALF; in elink_sync_link()
5552 vars->line_speed = ELINK_SPEED_10; in elink_sync_link()
5556 vars->duplex = DUPLEX_HALF; in elink_sync_link()
5560 vars->line_speed = ELINK_SPEED_100; in elink_sync_link()
5564 vars->duplex = DUPLEX_HALF; in elink_sync_link()
5567 vars->line_speed = ELINK_SPEED_1000; in elink_sync_link()
5571 vars->duplex = DUPLEX_HALF; in elink_sync_link()
5574 vars->line_speed = ELINK_SPEED_2500; in elink_sync_link()
5578 vars->line_speed = ELINK_SPEED_10000; in elink_sync_link()
5581 vars->line_speed = ELINK_SPEED_20000; in elink_sync_link()
5586 vars->flow_ctrl = 0; in elink_sync_link()
5587 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) in elink_sync_link()
5588 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX; in elink_sync_link()
5590 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) in elink_sync_link()
5591 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX; in elink_sync_link()
5593 if (!vars->flow_ctrl) in elink_sync_link()
5594 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_sync_link()
5596 if (vars->line_speed && in elink_sync_link()
5597 ((vars->line_speed == ELINK_SPEED_10) || in elink_sync_link()
5598 (vars->line_speed == ELINK_SPEED_100))) { in elink_sync_link()
5599 vars->phy_flags |= PHY_SGMII_FLAG; in elink_sync_link()
5601 vars->phy_flags &= ~PHY_SGMII_FLAG; in elink_sync_link()
5603 if (vars->line_speed && in elink_sync_link()
5605 (vars->line_speed == ELINK_SPEED_1000)) in elink_sync_link()
5606 vars->phy_flags |= PHY_SGMII_FLAG; in elink_sync_link()
5608 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); in elink_sync_link()
5612 vars->mac_type = ELINK_MAC_TYPE_XMAC; in elink_sync_link()
5614 vars->mac_type = ELINK_MAC_TYPE_BMAC; in elink_sync_link()
5617 vars->mac_type = ELINK_MAC_TYPE_UMAC; in elink_sync_link()
5619 vars->mac_type = ELINK_MAC_TYPE_EMAC; in elink_sync_link()
5624 vars->phy_link_up = 0; in elink_sync_link()
5626 vars->line_speed = 0; in elink_sync_link()
5627 vars->duplex = DUPLEX_FULL; in elink_sync_link()
5628 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_sync_link()
5631 vars->mac_type = ELINK_MAC_TYPE_NONE; in elink_sync_link()
5632 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) in elink_sync_link()
5633 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; in elink_sync_link()
5634 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) in elink_sync_link()
5635 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; in elink_sync_link()
5642 struct bxe_softc *sc = params->sc; in elink_link_status_update()
5643 uint8_t port = params->port; in elink_link_status_update()
5648 vars->link_status = REG_RD(sc, params->shmem_base + in elink_link_status_update()
5653 if (params->loopback_mode != ELINK_LOOPBACK_NONE && in elink_link_status_update()
5654 params->loopback_mode != ELINK_LOOPBACK_EXT) in elink_link_status_update()
5655 vars->link_status |= LINK_STATUS_LINK_UP; in elink_link_status_update()
5658 vars->eee_status = REG_RD(sc, params->shmem2_base + in elink_link_status_update()
5660 eee_status[params->port])); in elink_link_status_update()
5662 vars->phy_flags = PHY_XGXS_FLAG; in elink_link_status_update()
5665 sync_offset = params->shmem_base + in elink_link_status_update()
5670 params->phy[ELINK_INT_PHY].media_type = in elink_link_status_update()
5673 params->phy[ELINK_EXT_PHY1].media_type = in elink_link_status_update()
5676 params->phy[ELINK_EXT_PHY2].media_type = in elink_link_status_update()
5682 sync_offset = params->shmem_base + in elink_link_status_update()
5686 vars->aeu_int_mask = REG_RD(sc, sync_offset); in elink_link_status_update()
5689 if (vars->link_status & LINK_STATUS_PFC_ENABLED) in elink_link_status_update()
5690 params->feature_config_flags |= in elink_link_status_update()
5693 params->feature_config_flags &= in elink_link_status_update()
5697 params->link_attr_sync = SHMEM2_RD(sc, in elink_link_status_update()
5698 link_attr_sync[params->port]); in elink_link_status_update()
5701 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); in elink_link_status_update()
5703 vars->line_speed, vars->duplex, vars->flow_ctrl); in elink_link_status_update()
5709 struct bxe_softc *sc = params->sc; in elink_set_master_ln()
5711 ser_lane = ((params->lane_config & in elink_set_master_ln()
5731 struct bxe_softc *sc = params->sc; in elink_reset_unicore()
5745 elink_set_serdes_access(sc, params->port); in elink_reset_unicore()
5763 …elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not ini… in elink_reset_unicore()
5774 struct bxe_softc *sc = params->sc; in elink_set_swap_lanes()
5775 /* Each two bits represents a lane number: in elink_set_swap_lanes()
5780 rx_lane_swap = ((params->lane_config & in elink_set_swap_lanes()
5783 tx_lane_swap = ((params->lane_config & in elink_set_swap_lanes()
5816 struct bxe_softc *sc = params->sc; in elink_set_parallel_detection()
5822 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) in elink_set_parallel_detection()
5826 ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", in elink_set_parallel_detection()
5827 phy->speed_cap_mask, control2); in elink_set_parallel_detection()
5833 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && in elink_set_parallel_detection()
5834 (phy->speed_cap_mask & in elink_set_parallel_detection()
5871 struct bxe_softc *sc = params->sc; in elink_set_autoneg()
5880 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) in elink_set_autoneg()
5898 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) in elink_set_autoneg()
5912 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) { in elink_set_autoneg()
5946 if (phy->speed_cap_mask & in elink_set_autoneg()
5949 if (phy->speed_cap_mask & in elink_set_autoneg()
5974 struct bxe_softc *sc = params->sc; in elink_program_serdes()
5984 if (phy->req_duplex == DUPLEX_FULL) in elink_program_serdes()
5991 * - needed only if the speed is greater than 1G (2.5G or 10G) in elink_program_serdes()
6002 if (!((vars->line_speed == ELINK_SPEED_1000) || in elink_program_serdes()
6003 (vars->line_speed == ELINK_SPEED_100) || in elink_program_serdes()
6004 (vars->line_speed == ELINK_SPEED_10))) { in elink_program_serdes()
6008 if (vars->line_speed == ELINK_SPEED_10000) in elink_program_serdes()
6022 struct bxe_softc *sc = params->sc; in elink_set_brcm_cl37_advertisement()
6026 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) in elink_set_brcm_cl37_advertisement()
6028 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) in elink_set_brcm_cl37_advertisement()
6043 struct bxe_softc *sc = params->sc; in elink_set_ieee_aneg_advertisement()
6064 struct bxe_softc *sc = params->sc; in elink_restart_autoneg()
6104 struct bxe_softc *sc = params->sc; in elink_initialize_sgmii_process()
6124 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) { in elink_initialize_sgmii_process()
6136 switch (vars->line_speed) { in elink_initialize_sgmii_process()
6151 vars->line_speed); in elink_initialize_sgmii_process()
6156 if (phy->req_duplex == DUPLEX_FULL) in elink_initialize_sgmii_process()
6175 struct bxe_softc *sc = params->sc; in elink_direct_parallel_detect_used()
6177 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) in elink_direct_parallel_detect_used()
6189 params->port); in elink_direct_parallel_detect_used()
6200 params->port); in elink_direct_parallel_detect_used()
6214 struct bxe_softc *sc = params->sc; in elink_update_adv_fc()
6258 struct bxe_softc *sc = params->sc; in elink_flow_ctrl_resolve()
6259 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_flow_ctrl_resolve()
6262 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { in elink_flow_ctrl_resolve()
6263 /* Update the advertised flow-controlled of LD/LP in AN */ in elink_flow_ctrl_resolve()
6264 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) in elink_flow_ctrl_resolve()
6266 /* But set the flow-control result as the requested one */ in elink_flow_ctrl_resolve()
6267 vars->flow_ctrl = phy->req_flow_ctrl; in elink_flow_ctrl_resolve()
6268 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) in elink_flow_ctrl_resolve()
6269 vars->flow_ctrl = params->req_fc_auto_adv; in elink_flow_ctrl_resolve()
6271 (!(vars->phy_flags & PHY_SGMII_FLAG))) { in elink_flow_ctrl_resolve()
6273 vars->flow_ctrl = params->req_fc_auto_adv; in elink_flow_ctrl_resolve()
6278 ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x\n", vars->flow_ctrl); in elink_flow_ctrl_resolve()
6284 struct bxe_softc *sc = params->sc; in elink_check_fallback_to_cl37()
6312 ELINK_DEBUG_P1(sc, "CL73 state-machine is not stable. " in elink_check_fallback_to_cl37()
6336 * restart cl37 auto-neg in elink_check_fallback_to_cl37()
6355 vars->link_status |= in elink_xgxs_an_resolve()
6359 vars->link_status |= in elink_xgxs_an_resolve()
6369 struct bxe_softc *sc = params->sc; in elink_get_link_speed_duplex()
6370 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) in elink_get_link_speed_duplex()
6371 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; in elink_get_link_speed_duplex()
6375 vars->phy_link_up = 1; in elink_get_link_speed_duplex()
6376 vars->link_status |= LINK_STATUS_LINK_UP; in elink_get_link_speed_duplex()
6380 vars->line_speed = ELINK_SPEED_10; in elink_get_link_speed_duplex()
6382 vars->link_status |= ELINK_LINK_10TFD; in elink_get_link_speed_duplex()
6384 vars->link_status |= ELINK_LINK_10THD; in elink_get_link_speed_duplex()
6388 vars->line_speed = ELINK_SPEED_100; in elink_get_link_speed_duplex()
6390 vars->link_status |= ELINK_LINK_100TXFD; in elink_get_link_speed_duplex()
6392 vars->link_status |= ELINK_LINK_100TXHD; in elink_get_link_speed_duplex()
6397 vars->line_speed = ELINK_SPEED_1000; in elink_get_link_speed_duplex()
6399 vars->link_status |= ELINK_LINK_1000TFD; in elink_get_link_speed_duplex()
6401 vars->link_status |= ELINK_LINK_1000THD; in elink_get_link_speed_duplex()
6405 vars->line_speed = ELINK_SPEED_2500; in elink_get_link_speed_duplex()
6407 vars->link_status |= ELINK_LINK_2500TFD; in elink_get_link_speed_duplex()
6409 vars->link_status |= ELINK_LINK_2500THD; in elink_get_link_speed_duplex()
6425 vars->line_speed = ELINK_SPEED_10000; in elink_get_link_speed_duplex()
6426 vars->link_status |= ELINK_LINK_10GTFD; in elink_get_link_speed_duplex()
6430 vars->line_speed = ELINK_SPEED_20000; in elink_get_link_speed_duplex()
6431 vars->link_status |= ELINK_LINK_20GTFD; in elink_get_link_speed_duplex()
6442 vars->phy_link_up = 0; in elink_get_link_speed_duplex()
6444 vars->duplex = DUPLEX_FULL; in elink_get_link_speed_duplex()
6445 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_get_link_speed_duplex()
6446 vars->mac_type = ELINK_MAC_TYPE_NONE; in elink_get_link_speed_duplex()
6448 ELINK_DEBUG_P2(sc, " in elink_get_link_speed_duplex vars->link_status = %x, vars->duplex = %x\n", in elink_get_link_speed_duplex()
6449 vars->link_status, vars->duplex); in elink_get_link_speed_duplex()
6451 vars->phy_link_up, vars->line_speed); in elink_get_link_speed_duplex()
6459 struct bxe_softc *sc = params->sc; in elink_link_settings_status()
6491 vars->duplex = duplex; in elink_link_settings_status()
6493 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) in elink_link_settings_status()
6498 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && in elink_link_settings_status()
6507 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { in elink_link_settings_status()
6514 vars->link_status |= in elink_link_settings_status()
6518 vars->link_status |= in elink_link_settings_status()
6525 vars->link_status |= in elink_link_settings_status()
6528 vars->link_status |= in elink_link_settings_status()
6533 vars->duplex, vars->flow_ctrl, vars->link_status); in elink_link_settings_status()
6541 struct bxe_softc *sc = params->sc; in elink_warpcore_read_status()
6542 uint8_t lane; in elink_warpcore_read_status() local
6545 lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_read_status()
6547 if ((params->loopback_mode) && in elink_warpcore_read_status()
6548 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) { in elink_warpcore_read_status()
6554 ELINK_DEBUG_P1(sc, "params->loopback_mode link_up read = %x\n", in elink_warpcore_read_status()
6556 } else if ((phy->req_line_speed > ELINK_SPEED_10000) && in elink_warpcore_read_status()
6557 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) { in elink_warpcore_read_status()
6563 ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x\n", in elink_warpcore_read_status()
6577 (1 << lane); in elink_warpcore_read_status()
6578 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { in elink_warpcore_read_status()
6590 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { in elink_warpcore_read_status()
6595 if (gp_status4 & ((1<<12)<<lane)) in elink_warpcore_read_status()
6596 vars->link_status |= in elink_warpcore_read_status()
6604 vars->link_status |= in elink_warpcore_read_status()
6607 pd, vars->link_status); in elink_warpcore_read_status()
6610 vars->duplex = duplex; in elink_warpcore_read_status()
6612 vars->duplex, vars->flow_ctrl, vars->link_status); in elink_warpcore_read_status()
6616 vars->duplex, vars->flow_ctrl, vars->link_status); in elink_warpcore_read_status()
6617 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && in elink_warpcore_read_status()
6625 vars->link_status |= in elink_warpcore_read_status()
6629 vars->link_status |= in elink_warpcore_read_status()
6632 val, vars->link_status); in elink_warpcore_read_status()
6637 vars->link_status |= in elink_warpcore_read_status()
6640 vars->link_status |= in elink_warpcore_read_status()
6643 val, vars->link_status); in elink_warpcore_read_status()
6648 if (lane < 2) { in elink_warpcore_read_status()
6655 ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x\n", lane, gp_speed); in elink_warpcore_read_status()
6657 if ((lane & 1) == 0) in elink_warpcore_read_status()
6667 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) && in elink_warpcore_read_status()
6668 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE))) in elink_warpcore_read_status()
6669 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; in elink_warpcore_read_status()
6672 vars->duplex, vars->flow_ctrl, vars->link_status); in elink_warpcore_read_status()
6677 struct bxe_softc *sc = params->sc; in elink_set_gmii_tx_driver()
6678 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; in elink_set_gmii_tx_driver()
6697 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { in elink_set_gmii_tx_driver()
6717 struct bxe_softc *sc = params->sc; in elink_emac_program()
6718 uint8_t port = params->port; in elink_emac_program()
6727 switch (vars->line_speed) { in elink_emac_program()
6747 vars->line_speed); in elink_emac_program()
6751 if (vars->duplex == DUPLEX_HALF) in elink_emac_program()
6757 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); in elink_emac_program()
6766 struct bxe_softc *sc = params->sc; in elink_set_preemphasis()
6769 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { in elink_set_preemphasis()
6773 phy->rx_preemphasis[i]); in elink_set_preemphasis()
6777 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { in elink_set_preemphasis()
6781 phy->tx_preemphasis[i]); in elink_set_preemphasis()
6789 struct bxe_softc *sc = params->sc; in elink_xgxs_config_init()
6791 (params->loopback_mode == ELINK_LOOPBACK_XGXS)); in elink_xgxs_config_init()
6792 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { in elink_xgxs_config_init()
6794 (params->feature_config_flags & in elink_xgxs_config_init()
6799 if (vars->line_speed != ELINK_SPEED_AUTO_NEG || in elink_xgxs_config_init()
6801 params->loopback_mode == ELINK_LOOPBACK_EXT)) { in elink_xgxs_config_init()
6818 vars->ieee_fc); in elink_xgxs_config_init()
6839 vars->phy_flags |= PHY_XGXS_FLAG; in elink_prepare_xgxs()
6840 if ((phy->req_line_speed && in elink_prepare_xgxs()
6841 ((phy->req_line_speed == ELINK_SPEED_100) || in elink_prepare_xgxs()
6842 (phy->req_line_speed == ELINK_SPEED_10))) || in elink_prepare_xgxs()
6843 (!phy->req_line_speed && in elink_prepare_xgxs()
6844 (phy->speed_cap_mask >= in elink_prepare_xgxs()
6846 (phy->speed_cap_mask < in elink_prepare_xgxs()
6848 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) in elink_prepare_xgxs()
6849 vars->phy_flags |= PHY_SGMII_FLAG; in elink_prepare_xgxs()
6851 vars->phy_flags &= ~PHY_SGMII_FLAG; in elink_prepare_xgxs()
6853 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in elink_prepare_xgxs()
6855 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in elink_prepare_xgxs()
6865 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { in elink_prepare_xgxs()
6880 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) in elink_wait_reset_complete()
6893 …elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not ini… in elink_wait_reset_complete()
6896 ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)\n", ctrl, cnt); in elink_wait_reset_complete()
6902 uint8_t port = params->port; in elink_link_int_enable()
6904 struct bxe_softc *sc = params->sc; in elink_link_int_enable()
6911 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { in elink_link_int_enable()
6916 params->phy[ELINK_INT_PHY].type != in elink_link_int_enable()
6926 params->phy[ELINK_INT_PHY].type != in elink_link_int_enable()
6937 (params->switch_cfg == ELINK_SWITCH_CFG_10G), in elink_link_int_enable()
6954 * status register. Link down indication is high-active-signal, in elink_rearm_latch_signal()
6961 /* Handle only those with latched-signal=up.*/ in elink_rearm_latch_signal()
6975 /* For all latched-signal=up : Re-Arm Latch signals */ in elink_rearm_latch_signal()
6979 /* For all latched-signal=up,Write original_signal to status */ in elink_rearm_latch_signal()
6985 struct bxe_softc *sc = params->sc; in elink_link_int_ack()
6986 uint8_t port = params->port; in elink_link_int_ack()
6995 if (vars->phy_link_up) { in elink_link_int_ack()
7001 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { in elink_link_int_ack()
7003 * the relevant lane in the status register in elink_link_int_ack()
7006 ((params->lane_config & in elink_link_int_ack()
7032 (*len)--; in elink_format_ver()
7037 shift -= 4; in elink_format_ver()
7045 *str_ptr = digit - 0xa + 'a'; in elink_format_ver()
7048 (*len)--; in elink_format_ver()
7053 (*len)--; in elink_format_ver()
7064 (*len)--; in elink_null_format_ver()
7078 sc = params->sc; in elink_get_ext_phy_fw_version()
7082 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr); in elink_get_ext_phy_fw_version()
7084 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) { in elink_get_ext_phy_fw_version()
7085 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver, in elink_get_ext_phy_fw_version()
7088 ver_p += (len - remain_len); in elink_get_ext_phy_fw_version()
7090 if ((params->num_phys == ELINK_MAX_PHYS) && in elink_get_ext_phy_fw_version()
7091 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) { in elink_get_ext_phy_fw_version()
7092 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr); in elink_get_ext_phy_fw_version()
7093 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) { in elink_get_ext_phy_fw_version()
7096 remain_len--; in elink_get_ext_phy_fw_version()
7097 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver( in elink_get_ext_phy_fw_version()
7101 ver_p = version + (len - remain_len); in elink_get_ext_phy_fw_version()
7111 uint8_t port = params->port; in elink_set_xgxs_loopback()
7112 struct bxe_softc *sc = params->sc; in elink_set_xgxs_loopback()
7114 if (phy->req_line_speed != ELINK_SPEED_1000) { in elink_set_xgxs_loopback()
7166 uint8_t port = params->port; in elink_set_led()
7167 uint16_t hw_led_mode = params->hw_led_mode; in elink_set_led()
7172 struct bxe_softc *sc = params->sc; in elink_set_led()
7178 if (params->phy[phy_idx].set_link_led) { in elink_set_led()
7179 params->phy[phy_idx].set_link_led( in elink_set_led()
7180 ¶ms->phy[phy_idx], params, mode); in elink_set_led()
7184 if (params->feature_config_flags & in elink_set_led()
7197 if (params->phy[ELINK_EXT_PHY1].type == in elink_set_led()
7212 if (!vars->link_up) in elink_set_led()
7215 if (((params->phy[ELINK_EXT_PHY1].type == in elink_set_led()
7217 (params->phy[ELINK_EXT_PHY1].type == in elink_set_led()
7219 CHIP_IS_E2(sc) && params->num_phys == 2) { in elink_set_led()
7220 /* This is a work-around for E2+8727 Configurations */ in elink_set_led()
7238 /* This is a work-around for HW issue found when link in elink_set_led()
7253 } else if ((params->phy[ELINK_EXT_PHY1].type == in elink_set_led()
7265 uint32_t nig_led_mode = ((params->hw_led_mode << in elink_set_led()
7319 struct bxe_softc *sc = params->sc; in elink_test_link()
7323 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; in elink_test_link()
7335 if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] in elink_test_link()
7345 uint8_t lane = elink_get_warpcore_lane(int_phy, params); in elink_test_link() local
7351 link_up = gp_status & (1 << lane); in elink_test_link()
7365 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) in elink_test_link()
7368 switch (params->num_phys) { in elink_test_link()
7373 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status( in elink_test_link()
7374 ¶ms->phy[ELINK_EXT_PHY1], in elink_test_link()
7378 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; in elink_test_link()
7380 serdes_phy_type = ((params->phy[phy_index].media_type == in elink_test_link()
7382 (params->phy[phy_index].media_type == in elink_test_link()
7384 (params->phy[phy_index].media_type == in elink_test_link()
7386 (params->phy[phy_index].media_type == in elink_test_link()
7391 if (params->phy[phy_index].read_status) { in elink_test_link()
7393 params->phy[phy_index].read_status( in elink_test_link()
7394 ¶ms->phy[phy_index], in elink_test_link()
7409 struct bxe_softc *sc = params->sc; in elink_link_initialize()
7415 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; in elink_link_initialize()
7422 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars); in elink_link_initialize()
7425 (params->loopback_mode == ELINK_LOOPBACK_XGXS)); in elink_link_initialize()
7428 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) || in elink_link_initialize()
7429 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) { in elink_link_initialize()
7430 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; in elink_link_initialize()
7431 if (vars->line_speed == ELINK_SPEED_AUTO_NEG && in elink_link_initialize()
7435 if (params->phy[ELINK_INT_PHY].config_init) in elink_link_initialize()
7436 params->phy[ELINK_INT_PHY].config_init(phy, params, vars); in elink_link_initialize()
7439 /* Re-read this value in case it was changed inside config_init due to in elink_link_initialize()
7442 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; in elink_link_initialize()
7446 if (params->phy[ELINK_INT_PHY].supported & in elink_link_initialize()
7448 vars->link_status |= LINK_STATUS_SERDES_LINK; in elink_link_initialize()
7450 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; in elink_link_initialize()
7457 if (params->phy[phy_index].supported & in elink_link_initialize()
7459 vars->link_status |= LINK_STATUS_SERDES_LINK; in elink_link_initialize()
7468 params->phy[phy_index].config_init( in elink_link_initialize()
7469 ¶ms->phy[phy_index], in elink_link_initialize()
7475 params->port*4, in elink_link_initialize()
7487 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, in elink_int_link_reset()
7488 (0x1ff << (params->port*16))); in elink_int_link_reset()
7494 struct bxe_softc *sc = params->sc; in elink_common_ext_link_reset()
7500 gpio_port = params->port; in elink_common_ext_link_reset()
7513 struct bxe_softc *sc = params->sc; in elink_update_link_down()
7514 uint8_t port = params->port; in elink_update_link_down()
7518 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; in elink_update_link_down()
7520 vars->mac_type = ELINK_MAC_TYPE_NONE; in elink_update_link_down()
7523 vars->link_status &= ~ELINK_LINK_UPDATE_MASK; in elink_update_link_down()
7524 vars->line_speed = 0; in elink_update_link_down()
7525 elink_update_mng(params, vars->link_status); in elink_update_link_down()
7538 elink_set_bmac_rx(sc, params->chip_id, params->port, 0); in elink_update_link_down()
7542 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), in elink_update_link_down()
7544 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), in elink_update_link_down()
7546 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | in elink_update_link_down()
7549 elink_update_mng_eee(params, vars->eee_status); in elink_update_link_down()
7561 struct bxe_softc *sc = params->sc; in elink_update_link_up()
7562 uint8_t phy_idx, port = params->port; in elink_update_link_up()
7565 vars->link_status |= (LINK_STATUS_LINK_UP | in elink_update_link_up()
7567 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; in elink_update_link_up()
7569 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) in elink_update_link_up()
7570 vars->link_status |= in elink_update_link_up()
7573 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) in elink_update_link_up()
7574 vars->link_status |= in elink_update_link_up()
7581 vars->link_up = 0; in elink_update_link_up()
7582 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; in elink_update_link_up()
7583 vars->link_status &= ~LINK_STATUS_LINK_UP; in elink_update_link_up()
7588 ELINK_LED_MODE_OPER, vars->line_speed); in elink_update_link_up()
7590 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && in elink_update_link_up()
7591 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { in elink_update_link_up()
7594 (params->port << 2), 1); in elink_update_link_up()
7597 (params->port << 2), 0xfc20); in elink_update_link_up()
7606 vars->link_up = 0; in elink_update_link_up()
7607 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; in elink_update_link_up()
7608 vars->link_status &= ~LINK_STATUS_LINK_UP; in elink_update_link_up()
7618 if ((vars->link_status & in elink_update_link_up()
7620 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && in elink_update_link_up()
7626 /* PBF - link up */ in elink_update_link_up()
7628 rc |= elink_pbf_update(params, vars->flow_ctrl, in elink_update_link_up()
7629 vars->line_speed); in elink_update_link_up()
7635 elink_update_mng(params, vars->link_status); in elink_update_link_up()
7636 elink_update_mng_eee(params, vars->eee_status); in elink_update_link_up()
7639 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { in elink_update_link_up()
7650 struct bxe_softc *sc = params->sc; in elink_chng_link_count()
7657 addr = params->shmem2_base + in elink_chng_link_count()
7658 offsetof(struct shmem2_region, link_change_count[params->port]); in elink_chng_link_count()
7669 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
7671 * - SINGLE_MEDIA - The link between the 577xx and the external
7674 * - DUAL_MEDIA - The link between the 577xx and the first
7680 struct bxe_softc *sc = params->sc; in elink_link_update()
7682 uint8_t port = params->port; in elink_link_update()
7684 uint32_t prev_link_status = vars->link_status; in elink_link_update()
7687 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; in elink_link_update()
7689 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; in elink_link_update()
7690 vars->link_status &= ~ELINK_LINK_UPDATE_MASK; in elink_link_update()
7691 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; in elink_link_update()
7701 phy_vars[phy_index].eee_status = vars->eee_status; in elink_link_update()
7705 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]); in elink_link_update()
7708 port, (vars->phy_flags & PHY_XGXS_FLAG), in elink_link_update()
7731 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; in elink_link_update()
7733 struct elink_phy *phy = ¶ms->phy[phy_index]; in elink_link_update()
7734 if (!phy->read_status) in elink_link_update()
7737 cur_link_up = phy->read_status(phy, params, in elink_link_update()
7770 * - FIRST_PHY means that second phy wasn't initialized, in elink_link_update()
7772 * - SECOND_PHY means that first phy should not be able in elink_link_update()
7774 * - DEFAULT should be overridden during initialiazation in elink_link_update()
7778 params->multi_phy_config); in elink_link_update()
7784 prev_line_speed = vars->line_speed; in elink_link_update()
7791 if (params->phy[ELINK_INT_PHY].read_status) in elink_link_update()
7792 params->phy[ELINK_INT_PHY].read_status( in elink_link_update()
7793 ¶ms->phy[ELINK_INT_PHY], in elink_link_update()
7795 /* The INT_PHY flow control reside in the vars. This include the in elink_link_update()
7796 * case where the speed or flow control are not set to AUTO. in elink_link_update()
7797 * Otherwise, the active external phy flow control result is set in elink_link_update()
7803 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; in elink_link_update()
7807 vars->link_status |= phy_vars[active_external_phy].link_status; in elink_link_update()
7809 /* if active_external_phy is first PHY and link is up - disable in elink_link_update()
7813 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) { in elink_link_update()
7816 params->phy[ELINK_EXT_PHY2].phy_specific_func( in elink_link_update()
7817 ¶ms->phy[ELINK_EXT_PHY2], in elink_link_update()
7823 vars->duplex = phy_vars[active_external_phy].duplex; in elink_link_update()
7824 if (params->phy[active_external_phy].supported & in elink_link_update()
7826 vars->link_status |= LINK_STATUS_SERDES_LINK; in elink_link_update()
7828 vars->link_status &= ~LINK_STATUS_SERDES_LINK; in elink_link_update()
7830 vars->eee_status = phy_vars[active_external_phy].eee_status; in elink_link_update()
7837 vars->phy_flags, vars->mac_type, vars->phy_link_up); in elink_link_update()
7839 vars->link_up, vars->line_speed, vars->duplex); in elink_link_update()
7841 vars->flow_ctrl, vars->ieee_fc, vars->link_status); in elink_link_update()
7843 vars->eee_status, vars->fault_detected, vars->check_kr2_recovery_cnt); in elink_link_update()
7845 vars->periodic_flags, vars->aeu_int_mask, vars->rx_tx_asic_rst); in elink_link_update()
7847 vars->turn_to_run_wc_rt, vars->rsrv2); in elink_link_update()
7849 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; in elink_link_update()
7851 if (params->phy[phy_index].flags & in elink_link_update()
7859 ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," in elink_link_update()
7860 " ext_phy_line_speed = %d\n", vars->flow_ctrl, in elink_link_update()
7861 vars->link_status, ext_phy_line_speed); in elink_link_update()
7867 if (vars->phy_link_up) { in elink_link_update()
7869 (ext_phy_line_speed != vars->line_speed)) { in elink_link_update()
7872 " link speed %d\n", vars->line_speed, in elink_link_update()
7874 vars->phy_link_up = 0; in elink_link_update()
7876 } else if (prev_line_speed != vars->line_speed) { in elink_link_update()
7877 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, in elink_link_update()
7884 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); in elink_link_update()
7891 * Note that after link down-up as result of cable plug, the xgxs in elink_link_update()
7898 vars->phy_link_up, in elink_link_update()
7899 params->phy[ELINK_EXT_PHY1].flags & in elink_link_update()
7901 if (!(params->phy[ELINK_EXT_PHY1].flags & in elink_link_update()
7903 && ext_phy_link_up && !vars->phy_link_up) { in elink_link_update()
7904 vars->line_speed = ext_phy_line_speed; in elink_link_update()
7905 if (vars->line_speed < ELINK_SPEED_1000) in elink_link_update()
7906 vars->phy_flags |= PHY_SGMII_FLAG; in elink_link_update()
7908 vars->phy_flags &= ~PHY_SGMII_FLAG; in elink_link_update()
7910 if (params->phy[ELINK_INT_PHY].config_init) in elink_link_update()
7911 params->phy[ELINK_INT_PHY].config_init( in elink_link_update()
7912 ¶ms->phy[ELINK_INT_PHY], params, in elink_link_update()
7917 * non-direct board) are up and no fault detected on active PHY. in elink_link_update()
7919 vars->link_up = (vars->phy_link_up && in elink_link_update()
7924 if(vars->link_up) { in elink_link_update()
7931 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) in elink_link_update()
7932 vars->link_status |= LINK_STATUS_PFC_ENABLED; in elink_link_update()
7934 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; in elink_link_update()
7936 if (vars->link_up) in elink_link_update()
7941 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP) in elink_link_update()
7945 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX) in elink_link_update()
7984 phy->ver_addr); in elink_save_bcm_spirom_ver()
7999 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; in elink_ext_phy_10G_an_resolve()
8001 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; in elink_ext_phy_10G_an_resolve()
8011 struct bxe_softc *sc = params->sc; in elink_8073_resolve_fc()
8012 if (phy->req_line_speed == ELINK_SPEED_10 || in elink_8073_resolve_fc()
8013 phy->req_line_speed == ELINK_SPEED_100) { in elink_8073_resolve_fc()
8014 vars->flow_ctrl = phy->req_flow_ctrl; in elink_8073_resolve_fc()
8019 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) { in elink_8073_resolve_fc()
8101 ((fw_msgout & 0xff) != 0x03 && (phy->type == in elink_8073_8727_external_rom_boot()
8171 * system initialization (XAUI work-around not required, as in elink_8073_xaui_wa()
8175 ELINK_DEBUG_P0(sc, "XAUI work-around not required\n"); in elink_8073_xaui_wa()
8199 ELINK_DEBUG_P0(sc, "Warning: XAUI work-around timeout !!!\n"); in elink_8073_xaui_wa()
8221 struct bxe_softc *sc = params->sc; in elink_8073_set_pause_cl37()
8226 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ in elink_8073_set_pause_cl37()
8227 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in elink_8073_set_pause_cl37()
8228 if ((vars->ieee_fc & in elink_8073_set_pause_cl37()
8233 if ((vars->ieee_fc & in elink_8073_set_pause_cl37()
8238 if ((vars->ieee_fc & in elink_8073_set_pause_cl37()
8255 struct bxe_softc *sc = params->sc; in elink_8073_specific_func()
8271 struct bxe_softc *sc = params->sc; in elink_8073_config_init()
8279 gpio_port = params->port; in elink_8073_config_init()
8298 /* Swap polarity if required - Must be done only in non-1G mode */ in elink_8073_config_init()
8299 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { in elink_8073_config_init()
8314 if (REG_RD(sc, params->shmem_base + in elink_8073_config_init()
8316 port_hw_config[params->port].default_cfg)) & in elink_8073_config_init()
8327 if (params->loopback_mode == ELINK_LOOPBACK_EXT) { in elink_8073_config_init()
8335 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) { in elink_8073_config_init()
8336 if (phy->req_line_speed == ELINK_SPEED_10000) { in elink_8073_config_init()
8338 } else if (phy->req_line_speed == ELINK_SPEED_2500) { in elink_8073_config_init()
8347 if (phy->speed_cap_mask & in elink_8073_config_init()
8352 if (phy->speed_cap_mask & in elink_8073_config_init()
8362 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && in elink_8073_config_init()
8363 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) || in elink_8073_config_init()
8364 (phy->req_line_speed == ELINK_SPEED_2500)) { in elink_8073_config_init()
8385 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? in elink_8073_config_init()
8419 struct bxe_softc *sc = params->sc; in elink_8073_read_status()
8435 ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x\n", val2, val1); in elink_8073_read_status()
8436 /* Clear MSG-OUT */ in elink_8073_read_status()
8459 ((phy->req_line_speed != ELINK_SPEED_10000))) { in elink_8073_read_status()
8473 ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x," in elink_8073_read_status()
8495 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ in elink_8073_read_status()
8498 vars->line_speed = ELINK_SPEED_10000; in elink_8073_read_status()
8500 params->port); in elink_8073_read_status()
8503 vars->line_speed = ELINK_SPEED_2500; in elink_8073_read_status()
8505 params->port); in elink_8073_read_status()
8508 vars->line_speed = ELINK_SPEED_1000; in elink_8073_read_status()
8510 params->port); in elink_8073_read_status()
8514 params->port); in elink_8073_read_status()
8519 if (params->lane_config & in elink_8073_read_status()
8528 if (vars->line_speed == ELINK_SPEED_1000) { in elink_8073_read_status()
8542 vars->duplex = DUPLEX_FULL; in elink_8073_read_status()
8545 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { in elink_8073_read_status()
8550 vars->link_status |= in elink_8073_read_status()
8553 vars->link_status |= in elink_8073_read_status()
8563 struct bxe_softc *sc = params->sc; in elink_8073_link_reset()
8568 gpio_port = params->port; in elink_8073_link_reset()
8583 struct bxe_softc *sc = params->sc; in elink_8705_config_init()
8587 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); in elink_8705_config_init()
8589 elink_ext_phy_hw_reset(sc, params->port); in elink_8705_config_init()
8602 elink_save_spirom_version(sc, params->port, params->shmem_base, 0); in elink_8705_config_init()
8612 struct bxe_softc *sc = params->sc; in elink_8705_read_status()
8633 vars->line_speed = ELINK_SPEED_10000; in elink_8705_read_status()
8646 struct bxe_softc *sc = params->sc; in elink_set_disable_pmd_transmit()
8651 if (params->feature_config_flags & in elink_set_disable_pmd_transmit()
8669 struct bxe_softc *sc = params->sc; in elink_get_gpio_port()
8673 gpio_port = params->port; in elink_get_gpio_port()
8684 uint8_t port = params->port; in elink_sfp_e1e2_set_transmitter()
8685 struct bxe_softc *sc = params->sc; in elink_sfp_e1e2_set_transmitter()
8689 tx_en_mode = REG_RD(sc, params->shmem_base + in elink_sfp_e1e2_set_transmitter()
8725 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; in elink_sfp_e1e2_set_transmitter()
8740 struct bxe_softc *sc = params->sc; in elink_sfp_set_transmitter()
8753 struct bxe_softc *sc = params->sc; in elink_8726_read_sfp_module_eeprom()
8819 struct bxe_softc *sc = params->sc; in elink_warpcore_power_module()
8821 pin_cfg = (REG_RD(sc, params->shmem_base + in elink_warpcore_power_module()
8823 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & in elink_warpcore_power_module()
8846 struct bxe_softc *sc = params->sc; in elink_warpcore_read_sfp_module_eeprom()
8870 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { in elink_warpcore_read_sfp_module_eeprom()
8884 struct bxe_softc *sc = params->sc; in elink_8727_read_sfp_module_eeprom()
8893 /* Set 2-wire transfer rate of SFP+ module EEPROM in elink_8727_read_sfp_module_eeprom()
8930 /* Wait appropriate time for two-wire command to finish before in elink_8727_read_sfp_module_eeprom()
8979 struct bxe_softc *sc = params->sc; in elink_read_sfp_module_eeprom()
8988 switch (phy->type) { in elink_read_sfp_module_eeprom()
9008 byte_cnt -= xfer_size; in elink_read_sfp_module_eeprom()
9019 struct bxe_softc *sc = params->sc; in elink_get_edc_mode()
9023 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED; in elink_get_edc_mode()
9034 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; in elink_get_edc_mode()
9035 params->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] << in elink_get_edc_mode()
9037 elink_update_link_attr(params, params->link_attr_sync); in elink_get_edc_mode()
9042 phy->media_type = ELINK_ETH_PHY_DA_TWINAX; in elink_get_edc_mode()
9050 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in elink_get_edc_mode()
9066 "Unknown copper-cable-type\n"); in elink_get_edc_mode()
9084 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER; in elink_get_edc_mode()
9085 if (phy->req_line_speed != ELINK_SPEED_1000) { in elink_get_edc_mode()
9086 uint8_t gport = params->port; in elink_get_edc_mode()
9087 phy->req_line_speed = ELINK_SPEED_1000; in elink_get_edc_mode()
9090 (params->port << 1); in elink_get_edc_mode()
9099 /* Some 1G-baseT modules will not link up, in elink_get_edc_mode()
9111 if (params->phy[idx].type == phy->type) { in elink_get_edc_mode()
9116 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; in elink_get_edc_mode()
9117 phy->req_line_speed = params->req_line_speed[cfg_idx]; in elink_get_edc_mode()
9125 sync_offset = params->shmem_base + in elink_get_edc_mode()
9127 dev_info.port_hw_config[params->port].media_type); in elink_get_edc_mode()
9129 /* Update media type for non-PMF sync */ in elink_get_edc_mode()
9131 if (&(params->phy[phy_idx]) == phy) { in elink_get_edc_mode()
9134 media_types |= ((phy->media_type & in elink_get_edc_mode()
9167 struct bxe_softc *sc = params->sc; in elink_verify_sfp_module()
9172 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED; in elink_verify_sfp_module()
9173 val = REG_RD(sc, params->shmem_base + in elink_verify_sfp_module()
9175 port_feature_config[params->port].config)); in elink_verify_sfp_module()
9182 if (params->feature_config_flags & in elink_verify_sfp_module()
9186 } else if (params->feature_config_flags & in elink_verify_sfp_module()
9188 /* Use first phy request only in case of non-dual media*/ in elink_verify_sfp_module()
9202 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); in elink_verify_sfp_module()
9229 …elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "W… in elink_verify_sfp_module()
9234 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED; in elink_verify_sfp_module()
9244 struct bxe_softc *sc = params->sc; in elink_wait_for_sfp_module_initialized()
9246 /* Initialization time after hot-plug may take up to 300ms for in elink_wait_for_sfp_module_initialized()
9251 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) in elink_wait_for_sfp_module_initialized()
9280 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 in elink_8727_power_module()
9281 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 in elink_8727_power_module()
9282 * where the 1st bit is the over-current(only input), and 2nd bit is in elink_8727_power_module()
9285 * In case of NOC feature is disabled and power is up, set GPIO control in elink_8727_power_module()
9286 * as input to enable listening of over-current indication in elink_8727_power_module()
9288 if (phy->flags & ELINK_FLAGS_NOC) in elink_8727_power_module()
9293 /* Set GPIO control to OUTPUT, and set the power bit in elink_8727_power_module()
9373 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ in elink_8727_set_limiting_mode()
9391 struct bxe_softc *sc = params->sc; in elink_8727_specific_func()
9398 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) in elink_8727_specific_func()
9415 if (phy->flags & ELINK_FLAGS_NOC) in elink_8727_specific_func()
9418 * status which reflect SFP+ module over-current in elink_8727_specific_func()
9420 if (!(phy->flags & ELINK_FLAGS_NOC)) in elink_8727_specific_func()
9421 val &= 0xff8f; /* Reset bits 4-6 */ in elink_8727_specific_func()
9436 struct bxe_softc *sc = params->sc; in elink_set_e1e2_module_fault_led()
9438 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base + in elink_set_e1e2_module_fault_led()
9440 dev_info.port_hw_config[params->port].sfp_ctrl)) & in elink_set_e1e2_module_fault_led()
9451 uint16_t gpio_pin = fault_led_gpio - in elink_set_e1e2_module_fault_led()
9453 ELINK_DEBUG_P3(sc, "Set fault module-detected led " in elink_set_e1e2_module_fault_led()
9469 uint8_t port = params->port; in elink_set_e3_module_fault_led()
9470 struct bxe_softc *sc = params->sc; in elink_set_e3_module_fault_led()
9471 pin_cfg = (REG_RD(sc, params->shmem_base + in elink_set_e3_module_fault_led()
9484 struct bxe_softc *sc = params->sc; in elink_set_sfp_module_fault_led()
9498 struct bxe_softc *sc = params->sc; in elink_warpcore_hw_reset()
9513 struct bxe_softc *sc = params->sc; in elink_power_sfp_module()
9516 switch (phy->type) { in elink_power_sfp_module()
9519 elink_8727_power_module(params->sc, phy, power); in elink_power_sfp_module()
9534 struct bxe_softc *sc = params->sc; in elink_warpcore_set_limiting_mode()
9536 uint8_t lane = elink_get_warpcore_lane(phy, params); in elink_warpcore_set_limiting_mode() local
9540 val &= ~(0xf << (lane << 2)); in elink_warpcore_set_limiting_mode()
9555 val |= (mode << (lane << 2)); in elink_warpcore_set_limiting_mode()
9562 /* Restart microcode to re-read the new mode */ in elink_warpcore_set_limiting_mode()
9572 switch (phy->type) { in elink_set_limiting_mode()
9574 elink_8726_set_limiting_mode(params->sc, phy, edc_mode); in elink_set_limiting_mode()
9578 elink_8727_set_limiting_mode(params->sc, phy, edc_mode); in elink_set_limiting_mode()
9589 struct bxe_softc *sc = params->sc; in elink_sfp_module_detection()
9593 uint32_t val = REG_RD(sc, params->shmem_base + in elink_sfp_module_detection()
9595 port_feature_config[params->port].config)); in elink_sfp_module_detection()
9599 params->port); in elink_sfp_module_detection()
9609 /* Turn on fault module-detected led */ in elink_sfp_module_detection()
9621 /* Turn off fault module-detected led */ in elink_sfp_module_detection()
9643 struct bxe_softc *sc = params->sc; in elink_handle_module_detect_int()
9648 phy = ¶ms->phy[ELINK_INT_PHY]; in elink_handle_module_detect_int()
9652 phy = ¶ms->phy[ELINK_EXT_PHY1]; in elink_handle_module_detect_int()
9654 if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base, in elink_handle_module_detect_int()
9655 params->port, &gpio_num, &gpio_port) == in elink_handle_module_detect_int()
9689 (params->link_flags & in elink_handle_module_detect_int()
9706 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; in elink_handle_module_detect_int()
9742 struct bxe_softc *sc = params->sc; in elink_8706_8726_read_status()
9756 ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); in elink_8706_8726_read_status()
9775 vars->line_speed = ELINK_SPEED_1000; in elink_8706_8726_read_status()
9777 vars->line_speed = ELINK_SPEED_10000; in elink_8706_8726_read_status()
9779 vars->duplex = DUPLEX_FULL; in elink_8706_8726_read_status()
9783 if (vars->line_speed == ELINK_SPEED_10000) { in elink_8706_8726_read_status()
9789 vars->fault_detected = 1; in elink_8706_8726_read_status()
9804 struct bxe_softc *sc = params->sc; in elink_8706_config_init()
9807 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); in elink_8706_config_init()
9809 elink_ext_phy_hw_reset(sc, params->port); in elink_8706_config_init()
9822 if ((params->feature_config_flags & in elink_8706_config_init()
9828 i*(MDIO_XS_8706_REG_BANK_RX1 - in elink_8706_config_init()
9831 /* Clear first 3 bits of the control */ in elink_8706_config_init()
9833 /* Set control bits according to configuration */ in elink_8706_config_init()
9834 val |= (phy->rx_preemphasis[i] & 0x7); in elink_8706_config_init()
9836 " reg 0x%x <-- val 0x%x\n", reg, val); in elink_8706_config_init()
9841 if (phy->req_line_speed == ELINK_SPEED_10000) { in elink_8706_config_init()
9861 /* Enable Full-Duplex advertisement on CL37 */ in elink_8706_config_init()
9881 elink_save_bcm_spirom_ver(sc, phy, params->port); in elink_8706_config_init()
9887 tx_en_mode = REG_RD(sc, params->shmem_base + in elink_8706_config_init()
9889 dev_info.port_hw_config[params->port].sfp_ctrl)) in elink_8706_config_init()
9917 struct bxe_softc *sc = params->sc; in elink_8726_config_loopback()
9925 struct bxe_softc *sc = params->sc; in elink_8726_external_rom_boot()
9929 /* Micro controller re-boot */ in elink_8726_external_rom_boot()
9951 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ in elink_8726_external_rom_boot()
9957 elink_save_bcm_spirom_ver(sc, phy, params->port); in elink_8726_external_rom_boot()
9964 struct bxe_softc *sc = params->sc; in elink_8726_read_status()
9974 vars->line_speed = 0; in elink_8726_read_status()
9985 struct bxe_softc *sc = params->sc; in elink_8726_config_init()
10000 if (phy->req_line_speed == ELINK_SPEED_1000) { in elink_8726_config_init()
10011 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && in elink_8726_config_init()
10012 (phy->speed_cap_mask & in elink_8726_config_init()
10014 ((phy->speed_cap_mask & in elink_8726_config_init()
10018 /* Set Flow control */ in elink_8726_config_init()
10030 /* Enable RX-ALARM control to receive interrupt for 1G speed in elink_8726_config_init()
10039 } else { /* Default 10G. Set only LASI control */ in elink_8726_config_init()
10045 if ((params->feature_config_flags & in elink_8726_config_init()
10049 phy->tx_preemphasis[0], in elink_8726_config_init()
10050 phy->tx_preemphasis[1]); in elink_8726_config_init()
10054 phy->tx_preemphasis[0]); in elink_8726_config_init()
10059 phy->tx_preemphasis[1]); in elink_8726_config_init()
10069 struct bxe_softc *sc = params->sc; in elink_8726_link_reset()
10070 ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d\n", params->port); in elink_8726_link_reset()
10071 /* Set serial boot control for external load */ in elink_8726_link_reset()
10084 struct bxe_softc *sc = params->sc; in elink_8727_set_link_led()
10089 if (!(phy->flags & ELINK_FLAGS_NOC)) in elink_8727_set_link_led()
10134 struct bxe_softc *sc = params->sc; in elink_8727_hw_reset()
10145 struct bxe_softc *sc = params->sc; in elink_8727_config_speed()
10148 if ((phy->req_line_speed == ELINK_SPEED_1000) || in elink_8727_config_speed()
10149 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) { in elink_8727_config_speed()
10158 /* Power down the XAUI until link is up in case of dual-media in elink_8727_config_speed()
10170 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && in elink_8727_config_speed()
10171 ((phy->speed_cap_mask & in elink_8727_config_speed()
10173 ((phy->speed_cap_mask & in elink_8727_config_speed()
10205 struct bxe_softc *sc = params->sc; in elink_8727_config_init()
10223 if (!(phy->flags & ELINK_FLAGS_NOC)) in elink_8727_config_init()
10243 if ((params->feature_config_flags & in elink_8727_config_init()
10246 phy->tx_preemphasis[0], in elink_8727_config_init()
10247 phy->tx_preemphasis[1]); in elink_8727_config_init()
10250 phy->tx_preemphasis[0]); in elink_8727_config_init()
10254 phy->tx_preemphasis[1]); in elink_8727_config_init()
10260 tx_en_mode = REG_RD(sc, params->shmem_base + in elink_8727_config_init()
10262 dev_info.port_hw_config[params->port].sfp_ctrl)) in elink_8727_config_init()
10288 struct bxe_softc *sc = params->sc; in elink_8727_handle_mod_abs()
10290 uint32_t val = REG_RD(sc, params->shmem_base + in elink_8727_handle_mod_abs()
10292 port_feature_config[params->port]. in elink_8727_handle_mod_abs()
10302 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; in elink_8727_handle_mod_abs()
10311 if (!(phy->flags & ELINK_FLAGS_NOC)) in elink_8727_handle_mod_abs()
10336 if (!(phy->flags & ELINK_FLAGS_NOC)) in elink_8727_handle_mod_abs()
10375 struct bxe_softc *sc = params->sc; in elink_8727_read_status()
10391 vars->line_speed = 0; in elink_8727_read_status()
10402 /* Clear MSG-OUT */ in elink_8727_read_status()
10409 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { in elink_8727_read_status()
10410 /* Check over-current using 8727 GPIO0 input*/ in elink_8727_read_status()
10416 uint8_t oc_port = params->port; in elink_8727_read_status()
10418 oc_port = SC_PATH(sc) + (params->port << 1); in elink_8727_read_status()
10446 elink_8727_power_module(params->sc, phy, 0); in elink_8727_read_status()
10460 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { in elink_8727_read_status()
10472 /* Bits 0..2 --> speed detected, in elink_8727_read_status()
10473 * Bits 13..15--> link is down in elink_8727_read_status()
10477 vars->line_speed = ELINK_SPEED_10000; in elink_8727_read_status()
10479 params->port); in elink_8727_read_status()
10482 vars->line_speed = ELINK_SPEED_1000; in elink_8727_read_status()
10484 params->port); in elink_8727_read_status()
10488 params->port); in elink_8727_read_status()
10492 if (vars->line_speed == ELINK_SPEED_10000) { in elink_8727_read_status()
10500 vars->fault_detected = 1; in elink_8727_read_status()
10506 vars->duplex = DUPLEX_FULL; in elink_8727_read_status()
10507 ELINK_DEBUG_P1(sc, "duplex = 0x%x\n", vars->duplex); in elink_8727_read_status()
10511 (phy->req_line_speed == ELINK_SPEED_1000)) { in elink_8727_read_status()
10515 /* In case of dual-media board and 1G, power up the XAUI side, in elink_8727_read_status()
10532 struct bxe_softc *sc = params->sc; in elink_8727_link_reset()
10549 return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || in elink_is_8483x_8485x()
10550 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) || in elink_is_8483x_8485x()
10551 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)); in elink_is_8483x_8485x()
10571 phy->ver_addr); in elink_save_848xx_spirom_version()
10573 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ in elink_save_848xx_spirom_version()
10589 phy->ver_addr); in elink_save_848xx_spirom_version()
10608 phy->ver_addr); in elink_save_848xx_spirom_version()
10618 phy->ver_addr); in elink_save_848xx_spirom_version()
10665 struct bxe_softc *sc = params->sc; in elink_848xx_specific_func()
10670 elink_save_848xx_spirom_version(phy, sc, params->port); in elink_848xx_specific_func()
10676 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port*4, in elink_848xx_specific_func()
10688 struct bxe_softc *sc = params->sc; in elink_848xx_cmn_config_init()
10712 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && in elink_848xx_cmn_config_init()
10713 (phy->speed_cap_mask & in elink_848xx_cmn_config_init()
10715 (phy->req_line_speed == ELINK_SPEED_1000)) { in elink_848xx_cmn_config_init()
10718 if (phy->req_duplex == DUPLEX_FULL) in elink_848xx_cmn_config_init()
10729 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { in elink_848xx_cmn_config_init()
10730 if (phy->speed_cap_mask & in elink_848xx_cmn_config_init()
10736 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n"); in elink_848xx_cmn_config_init()
10739 if (phy->speed_cap_mask & in elink_848xx_cmn_config_init()
10745 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n"); in elink_848xx_cmn_config_init()
10748 if ((phy->speed_cap_mask & in elink_848xx_cmn_config_init()
10750 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) { in elink_848xx_cmn_config_init()
10753 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n"); in elink_848xx_cmn_config_init()
10756 if ((phy->speed_cap_mask & in elink_848xx_cmn_config_init()
10758 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) { in elink_848xx_cmn_config_init()
10761 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n"); in elink_848xx_cmn_config_init()
10766 if ((phy->req_line_speed == ELINK_SPEED_100) && in elink_848xx_cmn_config_init()
10767 (phy->supported & in elink_848xx_cmn_config_init()
10771 /* Enabled AUTO-MDIX when autoneg is disabled */ in elink_848xx_cmn_config_init()
10779 if ((phy->req_line_speed == ELINK_SPEED_10) && in elink_848xx_cmn_config_init()
10780 (phy->supported & in elink_848xx_cmn_config_init()
10783 /* Enabled AUTO-MDIX when autoneg is disabled */ in elink_848xx_cmn_config_init()
10794 if (phy->req_duplex == DUPLEX_FULL) in elink_848xx_cmn_config_init()
10806 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && in elink_848xx_cmn_config_init()
10807 (phy->speed_cap_mask & in elink_848xx_cmn_config_init()
10809 (phy->req_line_speed == ELINK_SPEED_10000)) { in elink_848xx_cmn_config_init()
10834 struct bxe_softc *sc = params->sc; in elink_8481_config_init()
10837 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); in elink_8481_config_init()
10840 elink_ext_phy_hw_reset(sc, params->port); in elink_8481_config_init()
10857 struct bxe_softc *sc = params->sc; in elink_84858_cmd_hdlr()
10933 struct bxe_softc *sc = params->sc; in elink_84833_cmd_hdlr()
11012 struct bxe_softc *sc = params->sc; in elink_848xx_cmd_hdlr()
11014 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) || in elink_848xx_cmd_hdlr()
11015 (REG_RD(sc, params->shmem2_base + in elink_848xx_cmd_hdlr()
11017 link_attr_sync[params->port])) & LINK_ATTR_84858)) { in elink_848xx_cmd_hdlr()
11033 struct bxe_softc *sc = params->sc; in elink_848xx_pair_swap_cfg()
11036 pair_swap = REG_RD(sc, params->shmem_base + in elink_848xx_pair_swap_cfg()
11038 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & in elink_848xx_pair_swap_cfg()
11073 reset_pin[idx] -= PIN_CFG_GPIO0_P0; in elink_84833_get_reset_gpios()
11084 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; in elink_84833_get_reset_gpios()
11097 struct bxe_softc *sc = params->sc; in elink_84833_hw_reset_phy()
11099 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base + in elink_84833_hw_reset_phy()
11113 shmem_base_path[0] = params->shmem_base; in elink_84833_hw_reset_phy()
11117 params->chip_id); in elink_84833_hw_reset_phy()
11132 struct bxe_softc *sc = params->sc; in elink_8483x_disable_eee()
11135 ELINK_DEBUG_P0(sc, "Don't Advertise 10GBase-T EEE\n"); in elink_8483x_disable_eee()
11153 struct bxe_softc *sc = params->sc; in elink_8483x_enable_eee()
11171 struct bxe_softc *sc = params->sc; in elink_848x3_config_init()
11183 port = params->port; in elink_848x3_config_init()
11185 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in elink_848x3_config_init()
11205 temp = vars->line_speed; in elink_848x3_config_init()
11206 vars->line_speed = ELINK_SPEED_10000; in elink_848x3_config_init()
11207 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0); in elink_848x3_config_init()
11208 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars); in elink_848x3_config_init()
11209 vars->line_speed = temp; in elink_848x3_config_init()
11212 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) { in elink_848x3_config_init()
11218 params->link_attr_sync |= LINK_ATTR_84858; in elink_848x3_config_init()
11219 elink_update_link_attr(params, params->link_attr_sync); in elink_848x3_config_init()
11223 /* Set dual-media configuration according to configuration */ in elink_848x3_config_init()
11260 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000) in elink_848x3_config_init()
11265 ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x\n", in elink_848x3_config_init()
11266 params->multi_phy_config, val); in elink_848x3_config_init()
11285 elink_save_848xx_spirom_version(phy, sc, params->port); in elink_848x3_config_init()
11287 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in elink_848x3_config_init()
11288 uint32_t cms_enable = REG_RD(sc, params->shmem_base + in elink_848x3_config_init()
11290 dev_info.port_hw_config[params->port].default_cfg)) & in elink_848x3_config_init()
11317 if ((phy->req_duplex == DUPLEX_FULL) && in elink_848x3_config_init()
11318 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && in elink_848x3_config_init()
11320 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) in elink_848x3_config_init()
11329 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; in elink_848x3_config_init()
11346 struct bxe_softc *sc = params->sc; in elink_848xx_read_status()
11351 /* Check 10G-BaseT link status */ in elink_848xx_read_status()
11362 vars->line_speed = ELINK_SPEED_10000; in elink_848xx_read_status()
11363 vars->duplex = DUPLEX_FULL; in elink_848xx_read_status()
11385 vars->line_speed = ELINK_SPEED_10; in elink_848xx_read_status()
11387 vars->line_speed = ELINK_SPEED_100; in elink_848xx_read_status()
11389 vars->line_speed = ELINK_SPEED_1000; in elink_848xx_read_status()
11391 vars->line_speed = 0; in elink_848xx_read_status()
11395 if (params->feature_config_flags & in elink_848xx_read_status()
11409 vars->duplex = DUPLEX_FULL; in elink_848xx_read_status()
11411 vars->duplex = DUPLEX_HALF; in elink_848xx_read_status()
11415 vars->line_speed, in elink_848xx_read_status()
11416 (vars->duplex == DUPLEX_FULL)); in elink_848xx_read_status()
11423 vars->link_status |= in elink_848xx_read_status()
11430 vars->link_status |= in elink_848xx_read_status()
11436 vars->line_speed); in elink_848xx_read_status()
11443 vars->link_status |= in elink_848xx_read_status()
11446 vars->link_status |= in elink_848xx_read_status()
11449 vars->link_status |= in elink_848xx_read_status()
11452 vars->link_status |= in elink_848xx_read_status()
11455 vars->link_status |= in elink_848xx_read_status()
11462 vars->link_status |= in elink_848xx_read_status()
11465 vars->link_status |= in elink_848xx_read_status()
11472 vars->link_status |= in elink_848xx_read_status()
11495 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, in elink_8481_hw_reset()
11497 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, in elink_8481_hw_reset()
11504 elink_cl45_write(params->sc, phy, in elink_8481_link_reset()
11506 elink_cl45_write(params->sc, phy, in elink_8481_link_reset()
11513 struct bxe_softc *sc = params->sc; in elink_848x3_link_reset()
11520 port = params->port; in elink_848x3_link_reset()
11522 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { in elink_848x3_link_reset()
11540 struct bxe_softc *sc = params->sc; in elink_848xx_set_link_led()
11547 port = params->port; in elink_848xx_set_link_led()
11553 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == in elink_848xx_set_link_led()
11589 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == in elink_848xx_set_link_led()
11618 if (phy->type == in elink_848xx_set_link_led()
11624 params->port*4) & in elink_848xx_set_link_led()
11626 params->link_flags |= in elink_848xx_set_link_led()
11632 params->port*4, in elink_848xx_set_link_led()
11646 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == in elink_848xx_set_link_led()
11648 /* Set control reg */ in elink_848xx_set_link_led()
11686 if (phy->type == in elink_848xx_set_link_led()
11692 params->port*4) & in elink_848xx_set_link_led()
11694 params->link_flags |= in elink_848xx_set_link_led()
11700 params->port*4, in elink_848xx_set_link_led()
11715 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == in elink_848xx_set_link_led()
11718 /* Set control reg */ in elink_848xx_set_link_led()
11760 val = ((params->hw_led_mode << in elink_848xx_set_link_led()
11780 if (phy->type == in elink_848xx_set_link_led()
11783 * and re-enable interrupts. in elink_848xx_set_link_led()
11789 if (params->link_flags & in elink_848xx_set_link_led()
11792 params->link_flags &= in elink_848xx_set_link_led()
11816 struct bxe_softc *sc = params->sc; in elink_54618se_specific_func()
11845 struct bxe_softc *sc = params->sc; in elink_54618se_config_init()
11856 port = params->port; in elink_54618se_config_init()
11858 cfg_pin = (REG_RD(sc, params->shmem_base + in elink_54618se_config_init()
11893 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ in elink_54618se_config_init()
11894 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); in elink_54618se_config_init()
11896 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == in elink_54618se_config_init()
11900 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == in elink_54618se_config_init()
11922 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && in elink_54618se_config_init()
11923 (phy->speed_cap_mask & in elink_54618se_config_init()
11925 (phy->req_line_speed == ELINK_SPEED_1000)) { in elink_54618se_config_init()
11928 if (phy->req_duplex == DUPLEX_FULL) in elink_54618se_config_init()
11942 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { in elink_54618se_config_init()
11943 if (phy->speed_cap_mask & in elink_54618se_config_init()
11947 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n"); in elink_54618se_config_init()
11949 if (phy->speed_cap_mask & in elink_54618se_config_init()
11953 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n"); in elink_54618se_config_init()
11955 if (phy->speed_cap_mask & in elink_54618se_config_init()
11959 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n"); in elink_54618se_config_init()
11961 if (phy->speed_cap_mask & in elink_54618se_config_init()
11965 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n"); in elink_54618se_config_init()
11970 if (phy->req_line_speed == ELINK_SPEED_100) { in elink_54618se_config_init()
11972 /* Enabled AUTO-MDIX when autoneg is disabled */ in elink_54618se_config_init()
11978 if (phy->req_line_speed == ELINK_SPEED_10) { in elink_54618se_config_init()
11979 /* Enabled AUTO-MDIX when autoneg is disabled */ in elink_54618se_config_init()
11986 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) { in elink_54618se_config_init()
12000 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && in elink_54618se_config_init()
12001 (phy->req_duplex == DUPLEX_FULL) && in elink_54618se_config_init()
12003 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) { in elink_54618se_config_init()
12012 ELINK_DEBUG_P0(sc, "Don't Advertise 1GBase-T EEE\n"); in elink_54618se_config_init()
12016 vars->eee_status &= ((uint32_t)(~SHMEM_EEE_1G_ADV) << in elink_54618se_config_init()
12019 if (phy->flags & ELINK_FLAGS_EEE) { in elink_54618se_config_init()
12020 /* Handle legacy auto-grEEEn */ in elink_54618se_config_init()
12021 if (params->feature_config_flags & in elink_54618se_config_init()
12024 ELINK_DEBUG_P0(sc, "Enabling Auto-GrEEEn\n"); in elink_54618se_config_init()
12038 if (phy->req_duplex == DUPLEX_FULL) in elink_54618se_config_init()
12051 struct bxe_softc *sc = params->sc; in elink_5461x_set_link_led()
12087 struct bxe_softc *sc = params->sc; in elink_54618se_link_reset()
12098 port = params->port; in elink_54618se_link_reset()
12099 cfg_pin = (REG_RD(sc, params->shmem_base + in elink_54618se_link_reset()
12113 struct bxe_softc *sc = params->sc; in elink_54618se_read_status()
12134 vars->line_speed = ELINK_SPEED_1000; in elink_54618se_read_status()
12135 vars->duplex = DUPLEX_FULL; in elink_54618se_read_status()
12137 vars->line_speed = ELINK_SPEED_1000; in elink_54618se_read_status()
12138 vars->duplex = DUPLEX_HALF; in elink_54618se_read_status()
12140 vars->line_speed = ELINK_SPEED_100; in elink_54618se_read_status()
12141 vars->duplex = DUPLEX_FULL; in elink_54618se_read_status()
12143 /* Omitting 100Base-T4 for now */ in elink_54618se_read_status()
12145 vars->line_speed = ELINK_SPEED_100; in elink_54618se_read_status()
12146 vars->duplex = DUPLEX_HALF; in elink_54618se_read_status()
12148 vars->line_speed = ELINK_SPEED_10; in elink_54618se_read_status()
12149 vars->duplex = DUPLEX_FULL; in elink_54618se_read_status()
12151 vars->line_speed = ELINK_SPEED_10; in elink_54618se_read_status()
12152 vars->duplex = DUPLEX_HALF; in elink_54618se_read_status()
12154 vars->line_speed = 0; in elink_54618se_read_status()
12158 vars->line_speed, in elink_54618se_read_status()
12159 (vars->duplex == DUPLEX_FULL)); in elink_54618se_read_status()
12166 vars->link_status |= in elink_54618se_read_status()
12172 vars->link_status |= in elink_54618se_read_status()
12176 vars->line_speed); in elink_54618se_read_status()
12180 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { in elink_54618se_read_status()
12185 vars->link_status |= in elink_54618se_read_status()
12188 vars->link_status |= in elink_54618se_read_status()
12191 vars->link_status |= in elink_54618se_read_status()
12194 vars->link_status |= in elink_54618se_read_status()
12197 vars->link_status |= in elink_54618se_read_status()
12202 vars->link_status |= in elink_54618se_read_status()
12205 vars->link_status |= in elink_54618se_read_status()
12208 if ((phy->flags & ELINK_FLAGS_EEE) && in elink_54618se_read_status()
12219 struct bxe_softc *sc = params->sc; in elink_54618se_config_loopback()
12221 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; in elink_54618se_config_loopback()
12248 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in elink_54618se_config_loopback()
12250 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame in elink_54618se_config_loopback()
12262 struct bxe_softc *sc = params->sc; in elink_7101_config_loopback()
12273 struct bxe_softc *sc = params->sc; in elink_7101_config_init()
12278 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); in elink_7101_config_init()
12280 elink_ext_phy_hw_reset(sc, params->port); in elink_7101_config_init()
12303 elink_save_spirom_version(sc, params->port, in elink_7101_config_init()
12304 (uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr); in elink_7101_config_init()
12312 struct bxe_softc *sc = params->sc; in elink_7101_read_status()
12319 ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x\n", in elink_7101_read_status()
12325 ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x\n", in elink_7101_read_status()
12333 vars->line_speed = ELINK_SPEED_10000; in elink_7101_read_status()
12334 vars->duplex = DUPLEX_FULL; in elink_7101_read_status()
12335 ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x\n", in elink_7101_read_status()
12342 vars->link_status |= in elink_7101_read_status()
12357 *len -= 5; in elink_7101_format_ver()
12371 /* Writes a self-clearing reset */ in elink_sfx7101_sp_sw_reset()
12389 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2, in elink_7101_hw_reset()
12390 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); in elink_7101_hw_reset()
12392 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, in elink_7101_hw_reset()
12393 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); in elink_7101_hw_reset()
12400 struct bxe_softc *sc = params->sc; in elink_7101_set_link_led()
12985 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); in elink_populate_preemphasis()
12986 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); in elink_populate_preemphasis()
12988 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); in elink_populate_preemphasis()
12989 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); in elink_populate_preemphasis()
12990 ELINK_DEBUG_P2(sc,"phy->rx_preemphasis = %x, phy->tx_preemphasis = %x\n", in elink_populate_preemphasis()
12991 phy->rx_preemphasis[i << 1], phy->tx_preemphasis[i << 1]); in elink_populate_preemphasis()
13036 phy->flags |= ELINK_FLAGS_4_PORT_MODE; in elink_populate_int_phy()
13038 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE; in elink_populate_int_phy()
13049 phy->supported &= (ELINK_SUPPORTED_10baseT_Half | in elink_populate_int_phy()
13058 phy->media_type = ELINK_ETH_PHY_BASE_T; in elink_populate_int_phy()
13061 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | in elink_populate_int_phy()
13066 phy->media_type = ELINK_ETH_PHY_XFP_FIBER; in elink_populate_int_phy()
13069 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | in elink_populate_int_phy()
13074 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; in elink_populate_int_phy()
13077 phy->media_type = ELINK_ETH_PHY_KR; in elink_populate_int_phy()
13078 phy->supported &= (ELINK_SUPPORTED_1000baseKX_Full | in elink_populate_int_phy()
13086 phy->media_type = ELINK_ETH_PHY_KR; in elink_populate_int_phy()
13087 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; in elink_populate_int_phy()
13088 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full | in elink_populate_int_phy()
13094 phy->media_type = ELINK_ETH_PHY_KR; in elink_populate_int_phy()
13095 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; in elink_populate_int_phy()
13096 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full | in elink_populate_int_phy()
13103 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; in elink_populate_int_phy()
13111 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC in elink_populate_int_phy()
13116 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA; in elink_populate_int_phy()
13118 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0; in elink_populate_int_phy()
13120 phy->media_type, phy->flags, phy->supported); in elink_populate_int_phy()
13141 phy->addr = (uint8_t)phy_addr; in elink_populate_int_phy()
13142 phy->mdio_ctrl = elink_get_emac_base(sc, in elink_populate_int_phy()
13146 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR; in elink_populate_int_phy()
13148 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR; in elink_populate_int_phy()
13151 port, phy->addr, phy->mdio_ctrl); in elink_populate_int_phy()
13189 phy->flags |= ELINK_FLAGS_NOC; in elink_populate_ext_phy()
13215 phy->flags |= ELINK_FLAGS_EEE; in elink_populate_ext_phy()
13232 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config); in elink_populate_ext_phy()
13242 phy->ver_addr = shmem_base + offsetof(struct shmem_region, in elink_populate_ext_phy()
13254 phy->ver_addr = shmem2_base + in elink_populate_ext_phy()
13262 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - in elink_populate_ext_phy()
13265 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port); in elink_populate_ext_phy()
13267 if (elink_is_8483x_8485x(phy) && (phy->ver_addr)) { in elink_populate_ext_phy()
13271 uint32_t raw_ver = REG_RD(sc, phy->ver_addr); in elink_populate_ext_phy()
13274 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half | in elink_populate_ext_phy()
13281 phy->addr, phy->mdio_ctrl); in elink_populate_ext_phy()
13289 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; in elink_populate_phy()
13301 struct bxe_softc *sc = params->sc; in elink_phy_def_cfg()
13305 link_config = REG_RD(sc, params->shmem_base + in elink_phy_def_cfg()
13307 port_feature_config[params->port].link_config2)); in elink_phy_def_cfg()
13308 phy->speed_cap_mask = REG_RD(sc, params->shmem_base + in elink_phy_def_cfg()
13311 port_hw_config[params->port].speed_capability_mask2)); in elink_phy_def_cfg()
13313 link_config = REG_RD(sc, params->shmem_base + in elink_phy_def_cfg()
13315 port_feature_config[params->port].link_config)); in elink_phy_def_cfg()
13316 phy->speed_cap_mask = REG_RD(sc, params->shmem_base + in elink_phy_def_cfg()
13319 port_hw_config[params->port].speed_capability_mask)); in elink_phy_def_cfg()
13323 phy_index, link_config, phy->speed_cap_mask); in elink_phy_def_cfg()
13325 phy->req_duplex = DUPLEX_FULL; in elink_phy_def_cfg()
13328 phy->req_duplex = DUPLEX_HALF; in elink_phy_def_cfg()
13330 phy->req_line_speed = ELINK_SPEED_10; in elink_phy_def_cfg()
13333 phy->req_duplex = DUPLEX_HALF; in elink_phy_def_cfg()
13335 phy->req_line_speed = ELINK_SPEED_100; in elink_phy_def_cfg()
13338 phy->req_line_speed = ELINK_SPEED_1000; in elink_phy_def_cfg()
13341 phy->req_line_speed = ELINK_SPEED_2500; in elink_phy_def_cfg()
13344 phy->req_line_speed = ELINK_SPEED_10000; in elink_phy_def_cfg()
13347 phy->req_line_speed = ELINK_SPEED_AUTO_NEG; in elink_phy_def_cfg()
13352 phy_index, phy->req_duplex); in elink_phy_def_cfg()
13356 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO; in elink_phy_def_cfg()
13359 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX; in elink_phy_def_cfg()
13362 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX; in elink_phy_def_cfg()
13365 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH; in elink_phy_def_cfg()
13368 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_phy_def_cfg()
13372 phy->req_duplex, phy->req_line_speed, phy->req_flow_ctrl); in elink_phy_def_cfg()
13380 phy_config_swapped = params->multi_phy_config & in elink_phy_selection()
13383 prio_cfg = params->multi_phy_config & in elink_phy_selection()
13411 struct bxe_softc *sc = params->sc; in elink_phy_probe()
13413 params->num_phys = 0; in elink_phy_probe()
13419 phy_config_swapped = params->multi_phy_config & in elink_phy_probe()
13434 phy = ¶ms->phy[actual_phy_idx]; in elink_phy_probe()
13435 if (elink_populate_phy(sc, phy_index, params->shmem_base, in elink_phy_probe()
13436 params->shmem2_base, params->port, in elink_phy_probe()
13438 params->num_phys = 0; in elink_phy_probe()
13447 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) in elink_phy_probe()
13450 if (params->feature_config_flags & in elink_phy_probe()
13452 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; in elink_phy_probe()
13454 if (!(params->feature_config_flags & in elink_phy_probe()
13456 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G; in elink_phy_probe()
13458 sync_offset = params->shmem_base + in elink_phy_probe()
13460 dev_info.port_hw_config[params->port].media_type); in elink_phy_probe()
13463 /* Update media type for non-PMF sync only for the first time in elink_phy_probe()
13470 media_types |= ((phy->media_type & in elink_phy_probe()
13478 params->num_phys++; in elink_phy_probe()
13481 ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x\n", params->num_phys); in elink_phy_probe()
13489 struct bxe_softc *sc = params->sc; in elink_init_e3_emul_mac()
13490 vars->line_speed = params->req_line_speed[0]; in elink_init_e3_emul_mac()
13492 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) { in elink_init_e3_emul_mac()
13493 if (params->feature_config_flags & in elink_init_e3_emul_mac()
13495 vars->line_speed = ELINK_SPEED_2500; in elink_init_e3_emul_mac()
13497 vars->line_speed = ELINK_SPEED_10000; in elink_init_e3_emul_mac()
13499 vars->line_speed = ELINK_SPEED_20000; in elink_init_e3_emul_mac()
13501 if (vars->line_speed < ELINK_SPEED_10000) { in elink_init_e3_emul_mac()
13502 if ((params->feature_config_flags & in elink_init_e3_emul_mac()
13505 " disabled!\n", params->req_line_speed[0]); in elink_init_e3_emul_mac()
13508 switch (vars->line_speed) { in elink_init_e3_emul_mac()
13510 vars->link_status = ELINK_LINK_10TFD; in elink_init_e3_emul_mac()
13513 vars->link_status = ELINK_LINK_100TXFD; in elink_init_e3_emul_mac()
13516 vars->link_status = ELINK_LINK_1000TFD; in elink_init_e3_emul_mac()
13519 vars->link_status = ELINK_LINK_2500TFD; in elink_init_e3_emul_mac()
13523 vars->line_speed); in elink_init_e3_emul_mac()
13526 vars->link_status |= LINK_STATUS_LINK_UP; in elink_init_e3_emul_mac()
13528 if (params->loopback_mode == ELINK_LOOPBACK_UMAC) in elink_init_e3_emul_mac()
13534 if (params->feature_config_flags & in elink_init_e3_emul_mac()
13537 " disabled!\n", params->req_line_speed[0]); in elink_init_e3_emul_mac()
13541 switch (vars->line_speed) { in elink_init_e3_emul_mac()
13543 vars->link_status = ELINK_LINK_10GTFD; in elink_init_e3_emul_mac()
13546 vars->link_status = ELINK_LINK_20GTFD; in elink_init_e3_emul_mac()
13550 vars->line_speed); in elink_init_e3_emul_mac()
13553 vars->link_status |= LINK_STATUS_LINK_UP; in elink_init_e3_emul_mac()
13554 if (params->loopback_mode == ELINK_LOOPBACK_XMAC) in elink_init_e3_emul_mac()
13565 struct bxe_softc *sc = params->sc; in elink_init_emul()
13571 if (params->feature_config_flags & in elink_init_emul()
13573 vars->line_speed = ELINK_SPEED_1000; in elink_init_emul()
13574 vars->link_status = (LINK_STATUS_LINK_UP | in elink_init_emul()
13576 if (params->loopback_mode == in elink_init_emul()
13582 vars->line_speed = ELINK_SPEED_10000; in elink_init_emul()
13583 vars->link_status = (LINK_STATUS_LINK_UP | in elink_init_emul()
13585 if (params->loopback_mode == in elink_init_emul()
13592 vars->link_up = 1; in elink_init_emul()
13593 vars->duplex = DUPLEX_FULL; in elink_init_emul()
13594 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_init_emul()
13597 elink_pbf_update(params, vars->flow_ctrl, in elink_init_emul()
13598 vars->line_speed); in elink_init_emul()
13600 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_emul()
13603 elink_update_mng(params, vars->link_status); in elink_init_emul()
13612 struct bxe_softc *sc = params->sc; in elink_init_fpga()
13613 vars->duplex = DUPLEX_FULL; in elink_init_fpga()
13614 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_init_fpga()
13616 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX | in elink_init_fpga()
13618 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | in elink_init_fpga()
13622 vars->line_speed = params->req_line_speed[0]; in elink_init_fpga()
13623 switch (vars->line_speed) { in elink_init_fpga()
13625 vars->line_speed = ELINK_SPEED_2500; in elink_init_fpga()
13627 vars->link_status = ELINK_LINK_2500TFD; in elink_init_fpga()
13630 vars->link_status = ELINK_LINK_1000XFD; in elink_init_fpga()
13633 vars->link_status = ELINK_LINK_100TXFD; in elink_init_fpga()
13636 vars->link_status = ELINK_LINK_10TFD; in elink_init_fpga()
13640 params->req_line_speed[0]); in elink_init_fpga()
13643 vars->link_status |= LINK_STATUS_LINK_UP; in elink_init_fpga()
13644 if (params->loopback_mode == ELINK_LOOPBACK_UMAC) in elink_init_fpga()
13649 vars->line_speed = ELINK_SPEED_10000; in elink_init_fpga()
13650 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD); in elink_init_fpga()
13651 if (params->loopback_mode == ELINK_LOOPBACK_EMAC) in elink_init_fpga()
13656 vars->link_up = 1; in elink_init_fpga()
13659 elink_pbf_update(params, vars->flow_ctrl, in elink_init_fpga()
13660 vars->line_speed); in elink_init_fpga()
13662 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_fpga()
13665 elink_update_mng(params, vars->link_status); in elink_init_fpga()
13672 struct bxe_softc *sc = params->sc; in elink_init_bmac_loopback()
13673 vars->link_up = 1; in elink_init_bmac_loopback()
13674 vars->line_speed = ELINK_SPEED_10000; in elink_init_bmac_loopback()
13675 vars->duplex = DUPLEX_FULL; in elink_init_bmac_loopback()
13676 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_init_bmac_loopback()
13677 vars->mac_type = ELINK_MAC_TYPE_BMAC; in elink_init_bmac_loopback()
13679 vars->phy_flags = PHY_XGXS_FLAG; in elink_init_bmac_loopback()
13686 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_bmac_loopback()
13692 struct bxe_softc *sc = params->sc; in elink_init_emac_loopback()
13693 vars->link_up = 1; in elink_init_emac_loopback()
13694 vars->line_speed = ELINK_SPEED_1000; in elink_init_emac_loopback()
13695 vars->duplex = DUPLEX_FULL; in elink_init_emac_loopback()
13696 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_init_emac_loopback()
13697 vars->mac_type = ELINK_MAC_TYPE_EMAC; in elink_init_emac_loopback()
13699 vars->phy_flags = PHY_XGXS_FLAG; in elink_init_emac_loopback()
13705 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_emac_loopback()
13711 struct bxe_softc *sc = params->sc; in elink_init_xmac_loopback()
13712 vars->link_up = 1; in elink_init_xmac_loopback()
13713 if (!params->req_line_speed[0]) in elink_init_xmac_loopback()
13714 vars->line_speed = ELINK_SPEED_10000; in elink_init_xmac_loopback()
13716 vars->line_speed = params->req_line_speed[0]; in elink_init_xmac_loopback()
13717 vars->duplex = DUPLEX_FULL; in elink_init_xmac_loopback()
13718 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_init_xmac_loopback()
13719 vars->mac_type = ELINK_MAC_TYPE_XMAC; in elink_init_xmac_loopback()
13720 vars->phy_flags = PHY_XGXS_FLAG; in elink_init_xmac_loopback()
13724 elink_set_aer_mmd(params, ¶ms->phy[0]); in elink_init_xmac_loopback()
13725 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0); in elink_init_xmac_loopback()
13726 params->phy[ELINK_INT_PHY].config_loopback( in elink_init_xmac_loopback()
13727 ¶ms->phy[ELINK_INT_PHY], in elink_init_xmac_loopback()
13731 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_xmac_loopback()
13737 struct bxe_softc *sc = params->sc; in elink_init_umac_loopback()
13738 vars->link_up = 1; in elink_init_umac_loopback()
13739 vars->line_speed = ELINK_SPEED_1000; in elink_init_umac_loopback()
13740 vars->duplex = DUPLEX_FULL; in elink_init_umac_loopback()
13741 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_init_umac_loopback()
13742 vars->mac_type = ELINK_MAC_TYPE_UMAC; in elink_init_umac_loopback()
13743 vars->phy_flags = PHY_XGXS_FLAG; in elink_init_umac_loopback()
13746 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_umac_loopback()
13752 struct bxe_softc *sc = params->sc; in elink_init_xgxs_loopback()
13753 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; in elink_init_xgxs_loopback()
13754 vars->link_up = 1; in elink_init_xgxs_loopback()
13755 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_init_xgxs_loopback()
13756 vars->duplex = DUPLEX_FULL; in elink_init_xgxs_loopback()
13757 if (params->req_line_speed[0] == ELINK_SPEED_1000) in elink_init_xgxs_loopback()
13758 vars->line_speed = ELINK_SPEED_1000; in elink_init_xgxs_loopback()
13759 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) || in elink_init_xgxs_loopback()
13760 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) in elink_init_xgxs_loopback()
13761 vars->line_speed = ELINK_SPEED_20000; in elink_init_xgxs_loopback()
13763 vars->line_speed = ELINK_SPEED_10000; in elink_init_xgxs_loopback()
13769 if (params->req_line_speed[0] == ELINK_SPEED_1000) { in elink_init_xgxs_loopback()
13783 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) { in elink_init_xgxs_loopback()
13785 int_phy->config_loopback(int_phy, params); in elink_init_xgxs_loopback()
13790 phy_index < params->num_phys; phy_index++) in elink_init_xgxs_loopback()
13791 if (params->phy[phy_index].config_loopback) in elink_init_xgxs_loopback()
13792 params->phy[phy_index].config_loopback( in elink_init_xgxs_loopback()
13793 ¶ms->phy[phy_index], in elink_init_xgxs_loopback()
13796 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_init_xgxs_loopback()
13798 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); in elink_init_xgxs_loopback()
13803 struct bxe_softc *sc = params->sc; in elink_set_rx_filter()
13809 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); in elink_set_rx_filter()
13812 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, in elink_set_rx_filter()
13816 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : in elink_set_rx_filter()
13824 struct bxe_softc *sc = params->sc; in elink_avoid_link_flap()
13835 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) { in elink_avoid_link_flap()
13836 struct elink_phy *phy = ¶ms->phy[phy_idx]; in elink_avoid_link_flap()
13837 if (phy->phy_specific_func) { in elink_avoid_link_flap()
13839 phy->phy_specific_func(phy, params, ELINK_PHY_INIT); in elink_avoid_link_flap()
13841 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) || in elink_avoid_link_flap()
13842 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) || in elink_avoid_link_flap()
13843 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX)) in elink_avoid_link_flap()
13846 lfa_sts = REG_RD(sc, params->lfa_base + in elink_avoid_link_flap()
13852 /* Re-enable the NIG/MAC */ in elink_avoid_link_flap()
13858 params->port)); in elink_avoid_link_flap()
13862 params->port)); in elink_avoid_link_flap()
13864 if (vars->line_speed < ELINK_SPEED_10000) in elink_avoid_link_flap()
13869 if (vars->line_speed < ELINK_SPEED_10000) in elink_avoid_link_flap()
13883 REG_WR(sc, params->lfa_base + in elink_avoid_link_flap()
13887 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_avoid_link_flap()
13899 struct bxe_softc *sc = params->sc; in elink_cannot_avoid_link_flap()
13903 if (!params->lfa_base) in elink_cannot_avoid_link_flap()
13906 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13908 params->req_duplex[0] | (params->req_duplex[1] << 16)); in elink_cannot_avoid_link_flap()
13910 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13912 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); in elink_cannot_avoid_link_flap()
13914 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13916 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); in elink_cannot_avoid_link_flap()
13919 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13922 params->speed_cap_mask[cfg_idx]); in elink_cannot_avoid_link_flap()
13925 tmp_val = REG_RD(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13928 tmp_val |= params->req_fc_auto_adv; in elink_cannot_avoid_link_flap()
13930 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13933 lfa_sts = REG_RD(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13949 REG_WR(sc, params->lfa_base + in elink_cannot_avoid_link_flap()
13957 struct bxe_softc *sc = params->sc; in elink_phy_init()
13960 params->req_line_speed[0], params->req_flow_ctrl[0]); in elink_phy_init()
13962 params->req_line_speed[1], params->req_flow_ctrl[1]); in elink_phy_init()
13963 ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); in elink_phy_init()
13964 vars->link_status = 0; in elink_phy_init()
13965 vars->phy_link_up = 0; in elink_phy_init()
13966 vars->link_up = 0; in elink_phy_init()
13967 vars->line_speed = 0; in elink_phy_init()
13968 vars->duplex = DUPLEX_FULL; in elink_phy_init()
13969 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; in elink_phy_init()
13970 vars->mac_type = ELINK_MAC_TYPE_NONE; in elink_phy_init()
13971 vars->phy_flags = 0; in elink_phy_init()
13972 vars->check_kr2_recovery_cnt = 0; in elink_phy_init()
13973 params->link_flags = ELINK_PHY_INITIALIZED; in elink_phy_init()
13974 /* Driver opens NIG-BRB filters */ in elink_phy_init()
13981 params->port, params->loopback_mode, params->req_duplex[0]); in elink_phy_init()
13983 params->switch_cfg, params->lane_config, params->req_duplex[1]); in elink_phy_init()
13985 params->chip_id, params->feature_config_flags, params->num_phys); in elink_phy_init()
13987 params->rsrv, params->eee_mode, params->hw_led_mode); in elink_phy_init()
13989 params->multi_phy_config, params->req_fc_auto_adv, params->link_flags); in elink_phy_init()
13991 params->lfa_base, params->link_attr_sync); in elink_phy_init()
14002 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, in elink_phy_init()
14008 if (!(params->feature_config_flags & in elink_phy_init()
14014 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) in elink_phy_init()
14015 vars->link_status |= LINK_STATUS_PFC_ENABLED; in elink_phy_init()
14017 if ((params->num_phys == 0) && in elink_phy_init()
14024 ELINK_DEBUG_P1(sc, "Num of phys on board: %d\n", params->num_phys); in elink_phy_init()
14035 switch (params->loopback_mode) { in elink_phy_init()
14054 if (params->switch_cfg == ELINK_SWITCH_CFG_10G) in elink_phy_init()
14057 elink_serdes_deassert(sc, params->port); in elink_phy_init()
14064 elink_update_mng(params, vars->link_status); in elink_phy_init()
14066 elink_update_mng_eee(params, vars->eee_status); in elink_phy_init()
14073 struct bxe_softc *sc = params->sc; in elink_link_reset()
14074 uint8_t phy_index, port = params->port, clear_latch_ind = 0; in elink_link_reset()
14077 vars->link_status = 0; in elink_link_reset()
14079 elink_update_mng(params, vars->link_status); in elink_link_reset()
14080 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | in elink_link_reset()
14082 elink_update_mng_eee(params, vars->eee_status); in elink_link_reset()
14100 if (!(params->feature_config_flags & in elink_link_reset()
14104 elink_set_bmac_rx(sc, params->chip_id, port, 0); in elink_link_reset()
14107 if (!(params->feature_config_flags & in elink_link_reset()
14128 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; in elink_link_reset()
14130 if (params->phy[phy_index].link_reset) { in elink_link_reset()
14132 ¶ms->phy[phy_index]); in elink_link_reset()
14133 params->phy[phy_index].link_reset( in elink_link_reset()
14134 ¶ms->phy[phy_index], in elink_link_reset()
14137 if (params->phy[phy_index].flags & in elink_link_reset()
14152 if (params->phy[ELINK_INT_PHY].link_reset) in elink_link_reset()
14153 params->phy[ELINK_INT_PHY].link_reset( in elink_link_reset()
14154 ¶ms->phy[ELINK_INT_PHY], params); in elink_link_reset()
14164 uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in elink_link_reset()
14171 vars->link_up = 0; in elink_link_reset()
14172 vars->phy_flags = 0; in elink_link_reset()
14178 struct bxe_softc *sc = params->sc; in elink_lfa_reset()
14179 vars->link_up = 0; in elink_lfa_reset()
14180 vars->phy_flags = 0; in elink_lfa_reset()
14181 params->link_flags &= ~ELINK_PHY_INITIALIZED; in elink_lfa_reset()
14182 if (!params->lfa_base) in elink_lfa_reset()
14188 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in elink_lfa_reset()
14195 elink_set_bmac_rx(sc, params->chip_id, params->port, 0); in elink_lfa_reset()
14204 /* Clean the NIG-BRB using the network filters in a way that will in elink_lfa_reset()
14210 * Re-open the gate between the BMAC and the NIG, after verifying the in elink_lfa_reset()
14216 elink_set_bmac_rx(sc, params->chip_id, params->port, 1); in elink_lfa_reset()
14223 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_lfa_reset()
14245 /* PART1 - Reset both phys */ in elink_8073_common_init_phy()
14246 for (port = PORT_MAX - 1; port >= PORT_0; port--) { in elink_8073_common_init_phy()
14299 /* PART2 - Download firmware to both phys */ in elink_8073_common_init_phy()
14300 for (port = PORT_MAX - 1; port >= PORT_0; port--) { in elink_8073_common_init_phy()
14307 phy_blk[port]->addr); in elink_8073_common_init_phy()
14329 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ in elink_8073_common_init_phy()
14330 for (port = PORT_MAX - 1; port >= PORT_0; port--) { in elink_8073_common_init_phy()
14342 /* Read modify write the SPI-ROM version select register */ in elink_8073_common_init_phy()
14364 /* Use port1 because of the static port-swap */ in elink_8726_common_init_phy()
14467 /* Retrieve the reset gpio/port which control the reset. in elink_8727_common_init_phy()
14485 /* PART1 - Reset both phys */ in elink_8727_common_init_phy()
14486 for (port = PORT_MAX - 1; port >= PORT_0; port--) { in elink_8727_common_init_phy()
14530 /* PART2 - Download firmware to both phys */ in elink_8727_common_init_phy()
14531 for (port = PORT_MAX - 1; port >= PORT_0; port--) { in elink_8727_common_init_phy()
14537 phy_blk[port]->addr); in elink_8727_common_init_phy()
14586 /* GPIO1 affects both ports, so there's need to pull in elink_ext_phy_common_init()
14669 struct bxe_softc *sc = params->sc; in elink_check_over_curr()
14671 uint8_t port = params->port; in elink_check_over_curr()
14674 cfg_pin = (REG_RD(sc, params->shmem_base + in elink_check_over_curr()
14685 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { in elink_check_over_curr()
14686 …elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d… in elink_check_over_curr()
14693 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; in elink_check_over_curr()
14697 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; in elink_check_over_curr()
14705 struct bxe_softc *sc = params->sc; in elink_analyze_link_error()
14708 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0; in elink_analyze_link_error()
14724 ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x\n", vars->link_up, in elink_analyze_link_error()
14728 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) in elink_analyze_link_error()
14731 /* a. Update shmem->link_status accordingly in elink_analyze_link_error()
14732 * b. Update elink_vars->link_up in elink_analyze_link_error()
14735 vars->link_status &= ~LINK_STATUS_LINK_UP; in elink_analyze_link_error()
14736 vars->link_status |= link_flag; in elink_analyze_link_error()
14737 vars->link_up = 0; in elink_analyze_link_error()
14738 vars->phy_flags |= phy_flag; in elink_analyze_link_error()
14741 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in elink_analyze_link_error()
14747 vars->link_status |= LINK_STATUS_LINK_UP; in elink_analyze_link_error()
14748 vars->link_status &= ~link_flag; in elink_analyze_link_error()
14749 vars->link_up = 1; in elink_analyze_link_error()
14750 vars->phy_flags &= ~phy_flag; in elink_analyze_link_error()
14754 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in elink_analyze_link_error()
14761 elink_update_mng(params, vars->link_status); in elink_analyze_link_error()
14764 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT; in elink_analyze_link_error()
14785 struct bxe_softc *sc = params->sc; in elink_check_half_open_conn()
14789 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || in elink_check_half_open_conn()
14790 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) in elink_check_half_open_conn()
14801 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in elink_check_half_open_conn()
14815 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { in elink_check_half_open_conn()
14819 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : in elink_check_half_open_conn()
14840 struct bxe_softc *sc = params->sc; in elink_sfp_tx_fault_detection()
14842 uint8_t led_change, port = params->port; in elink_sfp_tx_fault_detection()
14845 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, in elink_sfp_tx_fault_detection()
14863 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { in elink_sfp_tx_fault_detection()
14865 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; in elink_sfp_tx_fault_detection()
14868 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; in elink_sfp_tx_fault_detection()
14872 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { in elink_sfp_tx_fault_detection()
14873 ELINK_DEBUG_P1(sc, "Change TX_Fault LED: ->%x\n", in elink_sfp_tx_fault_detection()
14883 struct bxe_softc *sc = params->sc; in elink_kr2_recovery()
14893 struct bxe_softc *sc = params->sc; in elink_check_kr2_wa()
14894 uint16_t base_page, next_page, not_kr2_device, lane; in elink_check_kr2_wa() local
14902 if (vars->check_kr2_recovery_cnt > 0) { in elink_check_kr2_wa()
14903 vars->check_kr2_recovery_cnt--; in elink_check_kr2_wa()
14909 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { in elink_check_kr2_wa()
14916 lane = elink_get_warpcore_lane(phy, params); in elink_check_kr2_wa()
14918 MDIO_AER_BLOCK_AER_REG, lane); in elink_check_kr2_wa()
14927 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { in elink_check_kr2_wa()
14935 * but only KX is advertised, declare this link partner as non-KR2 in elink_check_kr2_wa()
14942 /* In case KR2 is already disabled, check if we need to re-enable it */ in elink_check_kr2_wa()
14943 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { in elink_check_kr2_wa()
14956 /* Restart AN on leading lane */ in elink_check_kr2_wa()
14965 struct bxe_softc *sc = params->sc; in elink_period_func()
14967 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { in elink_period_func()
14968 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]); in elink_period_func()
14977 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; in elink_period_func()
14979 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && in elink_period_func()
14980 (phy->speed_cap_mask & in elink_period_func()
14982 (phy->req_line_speed == ELINK_SPEED_20000)) in elink_period_func()
14985 if (vars->rx_tx_asic_rst) in elink_period_func()
14988 if ((REG_RD(sc, params->shmem_base + in elink_period_func()
14990 port_hw_config[params->port].default_cfg)) in elink_period_func()
14995 } else if (vars->link_status & in elink_period_func()
14998 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; in elink_period_func()
14999 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; in elink_period_func()
15001 elink_update_mng(params, vars->link_status); in elink_period_func()
15031 struct bxe_softc *sc = params->sc; in elink_hw_reset_phy()
15033 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, in elink_hw_reset_phy()
15041 if (params->phy[phy_index].hw_reset) { in elink_hw_reset_phy()
15042 params->phy[phy_index].hw_reset( in elink_hw_reset_phy()
15043 ¶ms->phy[phy_index], in elink_hw_reset_phy()
15045 params->phy[phy_index] = phy_null; in elink_hw_reset_phy()
15092 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << in elink_init_mod_abs_int()
15098 REG_WR(sc, sync_offset, vars->aeu_int_mask); in elink_init_mod_abs_int()
15101 gpio_num, gpio_port, vars->aeu_int_mask); in elink_init_mod_abs_int()
15110 aeu_mask |= vars->aeu_int_mask; in elink_init_mod_abs_int()