38 #define MDIO_REG_BANK_CL73_IEEEB0			0x0
39 	#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL		0x0
40 		#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN	0x0200
41 		#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN		0x1000
42 		#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST	0x8000
44 #define MDIO_REG_BANK_CL73_IEEEB1			0x10
45 	#define MDIO_CL73_IEEEB1_AN_ADV1			0x00
46 		#define	MDIO_CL73_IEEEB1_AN_ADV1_PAUSE			0x0400
47 		#define	MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 		0x0800
48 		#define	MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH		0x0C00
49 		#define	MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK		0x0C00
50 	#define MDIO_CL73_IEEEB1_AN_ADV2				0x01
51 		#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M		0x0000
52 		#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX		0x0020
53 		#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4		0x0040
54 		#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR		0x0080
55 	#define	MDIO_CL73_IEEEB1_AN_LP_ADV1			0x03
56 		#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE		0x0400
57 		#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 		0x0800
58 		#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH		0x0C00
59 		#define	MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK		0x0C00
60 	#define	MDIO_CL73_IEEEB1_AN_LP_ADV2			0x04
62 #define	MDIO_REG_BANK_RX0				0x80b0
63 	#define	MDIO_RX0_RX_STATUS				0x10
64 		#define	MDIO_RX0_RX_STATUS_SIGDET			0x8000
65 		#define	MDIO_RX0_RX_STATUS_RX_SEQ_DONE			0x1000
66 	#define	MDIO_RX0_RX_EQ_BOOST				0x1c
67 		#define	MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
68 		#define	MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL		0x10
70 #define	MDIO_REG_BANK_RX1				0x80c0
71 	#define	MDIO_RX1_RX_EQ_BOOST				0x1c
72 		#define	MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
73 		#define	MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL		0x10
75 #define	MDIO_REG_BANK_RX2				0x80d0
76 	#define	MDIO_RX2_RX_EQ_BOOST				0x1c
77 		#define	MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
78 		#define	MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL		0x10
80 #define	MDIO_REG_BANK_RX3				0x80e0
81 	#define	MDIO_RX3_RX_EQ_BOOST				0x1c
82 		#define	MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
83 		#define	MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL		0x10
85 #define	MDIO_REG_BANK_RX_ALL				0x80f0
86 	#define	MDIO_RX_ALL_RX_EQ_BOOST				0x1c
87 		#define	MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK	0x7
88 		#define	MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL	0x10
90 #define	MDIO_REG_BANK_TX0				0x8060
91 	#define	MDIO_TX0_TX_DRIVER				0x17
92 		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
94 		#define	MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
96 		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
98 		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
102 #define	MDIO_REG_BANK_TX1				0x8070
103 	#define	MDIO_TX1_TX_DRIVER				0x17
104 		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
106 		#define	MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
108 		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
110 		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
114 #define	MDIO_REG_BANK_TX2				0x8080
115 	#define	MDIO_TX2_TX_DRIVER				0x17
116 		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
118 		#define	MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
120 		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
122 		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
126 #define	MDIO_REG_BANK_TX3				0x8090
127 	#define	MDIO_TX3_TX_DRIVER				0x17
128 		#define	MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK		0xf000
130 		#define	MDIO_TX0_TX_DRIVER_IDRIVER_MASK			0x0f00
132 		#define	MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK		0x00f0
134 		#define	MDIO_TX0_TX_DRIVER_IFULLSPD_MASK		0x000e
138 #define	MDIO_REG_BANK_XGXS_BLOCK0			0x8000
139 	#define	MDIO_BLOCK0_XGXS_CONTROL			0x10
141 #define	MDIO_REG_BANK_XGXS_BLOCK1			0x8010
142 	#define	MDIO_BLOCK1_LANE_CTRL0				0x15
143 	#define	MDIO_BLOCK1_LANE_CTRL1				0x16
144 	#define	MDIO_BLOCK1_LANE_CTRL2				0x17
145 	#define	MDIO_BLOCK1_LANE_PRBS				0x19
147 #define	MDIO_REG_BANK_XGXS_BLOCK2			0x8100
148 	#define	MDIO_XGXS_BLOCK2_RX_LN_SWAP			0x10
149 		#define	MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE		0x8000
150 		#define	MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE	0x4000
151 		#define	MDIO_XGXS_BLOCK2_TX_LN_SWAP		0x11
152 		#define	MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE		0x8000
153 		#define	MDIO_XGXS_BLOCK2_UNICORE_MODE_10G	0x14
154 		#define	MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS	0x0001
155 		#define	MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS	0x0010
156 		#define	MDIO_XGXS_BLOCK2_TEST_MODE_LANE		0x15
158 #define	MDIO_REG_BANK_GP_STATUS				0x8120
159 #define	MDIO_GP_STATUS_TOP_AN_STATUS1				0x1B
160 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE	0x0001
161 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE	0x0002
162 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS		0x0004
163 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS		0x0008
164 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE	0x0010
165 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE	0x0020
166 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE	0x0040
167 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE	0x0080
168 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK		0x3f00
169 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M		0x0000
170 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M		0x0100
171 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G		0x0200
172 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G		0x0300
173 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G		0x0400
174 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G		0x0500
175 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG	0x0600
176 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4	0x0700
177 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG	0x0800
178 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G	0x0900
179 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G		0x0A00
180 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G		0x0B00
181 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G		0x0C00
182 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX	0x0D00
183 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4	0x0E00
184 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR	0x0F00
185 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI	0x1B00
186 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS	0x1E00
187 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI	0x1F00
188 	#define	MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2	0x3900
191 #define	MDIO_REG_BANK_10G_PARALLEL_DETECT		0x8130
192 #define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS		0x10
193 #define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK		0x8000
194 #define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL		0x11
195 #define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN	0x1
196 #define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK		0x13
197 #define	MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT		(0xb71<<1)
199 #define	MDIO_REG_BANK_SERDES_DIGITAL			0x8300
200 #define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1			0x10
201 #define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE			0x0001
202 #define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF			0x0002
203 #define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN		0x0004
204 #define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT	0x0008
205 #define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET			0x0010
206 #define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE			0x0020
207 #define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL2			0x11
208 #define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN			0x0001
209 #define	MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR			0x0040
210 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1			0x14
211 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII			0x0001
212 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK			0x0002
213 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX			0x0004
214 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK			0x0018
216 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G			0x0018
217 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G			0x0010
218 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M			0x0008
219 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M			0x0000
220 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS2			0x15
221 #define	MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED			0x0002
222 #define	MDIO_SERDES_DIGITAL_MISC1				0x18
223 #define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK			0xE000
224 #define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M			0x0000
225 #define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M			0x2000
226 #define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M			0x4000
227 #define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M			0x6000
228 #define	MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M			0x8000
229 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL			0x0010
230 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK			0x000f
231 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G			0x0000
232 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G			0x0001
233 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G			0x0002
234 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG			0x0003
235 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4			0x0004
236 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G			0x0005
237 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G			0x0006
238 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G			0x0007
239 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G			0x0008
240 #define	MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G			0x0009
242 #define	MDIO_REG_BANK_OVER_1G				0x8320
243 #define	MDIO_OVER_1G_DIGCTL_3_4					0x14
244 #define	MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK				0xffe0
246 #define	MDIO_OVER_1G_UP1					0x19
247 #define	MDIO_OVER_1G_UP1_2_5G						0x0001
248 #define	MDIO_OVER_1G_UP1_5G						0x0002
249 #define	MDIO_OVER_1G_UP1_6G						0x0004
250 #define	MDIO_OVER_1G_UP1_10G						0x0010
251 #define	MDIO_OVER_1G_UP1_10GH						0x0008
252 #define	MDIO_OVER_1G_UP1_12G						0x0020
253 #define	MDIO_OVER_1G_UP1_12_5G						0x0040
254 #define	MDIO_OVER_1G_UP1_13G						0x0080
255 #define	MDIO_OVER_1G_UP1_15G						0x0100
256 #define	MDIO_OVER_1G_UP1_16G						0x0200
257 #define	MDIO_OVER_1G_UP2					0x1A
258 #define	MDIO_OVER_1G_UP2_IPREDRIVER_MASK				0x0007
259 #define	MDIO_OVER_1G_UP2_IDRIVER_MASK					0x0038
260 #define	MDIO_OVER_1G_UP2_PREEMPHASIS_MASK				0x03C0
261 #define	MDIO_OVER_1G_UP3					0x1B
262 #define	MDIO_OVER_1G_UP3_HIGIG2						0x0001
263 #define	MDIO_OVER_1G_LP_UP1					0x1C
264 #define	MDIO_OVER_1G_LP_UP2					0x1D
265 #define	MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK				0x03ff
266 #define	MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK				0x0780
268 #define	MDIO_OVER_1G_LP_UP3						0x1E
270 #define	MDIO_REG_BANK_REMOTE_PHY			0x8330
271 #define	MDIO_REMOTE_PHY_MISC_RX_STATUS				0x10
272 #define	MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG	0x0010
273 #define	MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG	0x0600
275 #define	MDIO_REG_BANK_BAM_NEXT_PAGE			0x8350
276 #define	MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL			0x10
277 #define	MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE			0x0001
278 #define	MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN			0x0002
280 #define	MDIO_REG_BANK_CL73_USERB0		0x8370
281 #define	MDIO_CL73_USERB0_CL73_UCTRL				0x10
282 #define	MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL			0x0002
283 #define	MDIO_CL73_USERB0_CL73_USTAT1				0x11
284 #define	MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK			0x0100
285 #define	MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37		0x0400
286 #define	MDIO_CL73_USERB0_CL73_BAM_CTRL1				0x12
287 #define	MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN				0x8000
288 #define	MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN		0x4000
289 #define	MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN		0x2000
290 #define	MDIO_CL73_USERB0_CL73_BAM_CTRL3				0x14
291 #define	MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR			0x0001
293 #define	MDIO_REG_BANK_AER_BLOCK			0xFFD0
294 #define	MDIO_AER_BLOCK_AER_REG					0x1E
296 #define	MDIO_REG_BANK_COMBO_IEEE0		0xFFE0
297 #define	MDIO_COMBO_IEEE0_MII_CONTROL				0x10
298 #define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK			0x2040
299 #define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10			0x0000
300 #define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100			0x2000
301 #define	MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000			0x0040
302 #define	MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX				0x0100
303 #define	MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN				0x0200
304 #define	MDIO_COMBO_IEEO_MII_CONTROL_AN_EN				0x1000
305 #define	MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK				0x4000
306 #define	MDIO_COMBO_IEEO_MII_CONTROL_RESET				0x8000
307 #define	MDIO_COMBO_IEEE0_MII_STATUS				0x11
308 #define	MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS				0x0004
309 #define	MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE			0x0020
310 #define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV				0x14
311 #define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX			0x0020
312 #define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX			0x0040
313 #define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK			0x0180
314 #define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE			0x0000
315 #define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC			0x0080
316 #define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC			0x0100
317 #define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH			0x0180
318 #define	MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE				0x8000
319 #define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1		0x15
320 #define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE	0x8000
321 #define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK		0x4000
322 #define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK	0x0180
323 #define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE	0x0000
324 #define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH	0x0180
325 #define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP	0x0040
326 #define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP	0x0020
330 #define	MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE	0x0001
333 #define	MDIO_PMA_DEVAD			0x1
335 #define	MDIO_PMA_REG_CTRL		0x0
336 #define	MDIO_PMA_REG_STATUS		0x1
337 #define	MDIO_PMA_REG_10G_CTRL2		0x7
338 #define MDIO_PMA_REG_TX_DISABLE		0x0009
339 #define	MDIO_PMA_REG_RX_SD		0xa
341 #define	MDIO_PMA_REG_BCM_CTRL		0x0096
342 #define MDIO_PMA_REG_FEC_CTRL		0x00ab
343 #define	MDIO_PMA_LASI_RXCTRL		0x9000
344 #define	MDIO_PMA_LASI_TXCTRL		0x9001
345 #define	MDIO_PMA_LASI_CTRL		0x9002
346 #define	MDIO_PMA_LASI_RXSTAT		0x9003
347 #define	MDIO_PMA_LASI_TXSTAT		0x9004
348 #define	MDIO_PMA_LASI_STAT		0x9005
349 #define	MDIO_PMA_REG_PHY_IDENTIFIER	0xc800
350 #define	MDIO_PMA_REG_DIGITAL_CTRL	0xc808
351 #define	MDIO_PMA_REG_DIGITAL_STATUS	0xc809
352 #define	MDIO_PMA_REG_TX_POWER_DOWN	0xca02
353 #define	MDIO_PMA_REG_CMU_PLL_BYPASS	0xca09
354 #define	MDIO_PMA_REG_MISC_CTRL		0xca0a
355 #define	MDIO_PMA_REG_GEN_CTRL		0xca10
356 	#define	MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP	0x0188
357 	#define	MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET		0x018a
358 #define	MDIO_PMA_REG_M8051_MSGIN_REG	0xca12
359 #define	MDIO_PMA_REG_M8051_MSGOUT_REG	0xca13
360 #define	MDIO_PMA_REG_ROM_VER1		0xca19
361 #define	MDIO_PMA_REG_ROM_VER2		0xca1a
362 #define	MDIO_PMA_REG_EDC_FFE_MAIN	0xca1b
363 #define	MDIO_PMA_REG_PLL_BANDWIDTH	0xca1d
364 #define MDIO_PMA_REG_PLL_CTRL 		0xca1e
365 #define MDIO_PMA_REG_MISC_CTRL0 	0xca23
366 #define MDIO_PMA_REG_LRM_MODE	 	0xca3f
367 #define	MDIO_PMA_REG_CDR_BANDWIDTH 	0xca46
368 #define	MDIO_PMA_REG_MISC_CTRL1		0xca85
370 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL		0x8000
371 	#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 	0x000c
372 		#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 		0x0000
373 		#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 	0x0004
374 		#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 	0x0008
375 		#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 	0x000c
376 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 	0x8002
377 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 	0x8003
378 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF	0xc820
379 	#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
380 #define MDIO_PMA_REG_8726_TX_CTRL1		0xca01
381 #define MDIO_PMA_REG_8726_TX_CTRL2		0xca05
383 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR	0x8005
384 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF	0x8007
385 	#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
386 #define MDIO_PMA_REG_8727_MISC_CTRL		0x8309
387 #define MDIO_PMA_REG_8727_TX_CTRL1		0xca02
388 #define MDIO_PMA_REG_8727_TX_CTRL2		0xca05
389 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL		0xc808
390 #define MDIO_PMA_REG_8727_GPIO_CTRL		0xc80e
391 #define MDIO_PMA_REG_8727_PCS_GP		0xc842
392 #define MDIO_PMA_REG_8727_OPT_CFG_REG		0xc8e4
394 #define MDIO_AN_REG_8727_MISC_CTRL		0x8309
395 #define	MDIO_PMA_REG_8073_CHIP_REV			0xc801
396 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS		0xc820
397 #define MDIO_PMA_REG_8073_XAUI_WA 			0xc841
398 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 		0xcd08
400 #define MDIO_PMA_REG_7101_RESET		0xc000
401 #define	MDIO_PMA_REG_7107_LED_CNTL	0xc007
402 #define	MDIO_PMA_REG_7107_LINK_LED_CNTL	0xc009
403 #define	MDIO_PMA_REG_7101_VER1		0xc026
404 #define	MDIO_PMA_REG_7101_VER2		0xc027
406 #define MDIO_PMA_REG_8481_PMD_SIGNAL	0xa811
407 #define MDIO_PMA_REG_8481_LED1_MASK	0xa82c
408 #define MDIO_PMA_REG_8481_LED2_MASK	0xa82f
409 #define MDIO_PMA_REG_8481_LED3_MASK	0xa832
410 #define MDIO_PMA_REG_8481_LED3_BLINK	0xa834
411 #define MDIO_PMA_REG_8481_LED5_MASK	                0xa838
412 #define MDIO_PMA_REG_8481_SIGNAL_MASK	0xa835
413 #define MDIO_PMA_REG_8481_LINK_SIGNAL	0xa83b
414 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK	0x800
419 #define	MDIO_WIS_DEVAD			0x2
421 #define	MDIO_WIS_REG_LASI_CNTL		0x9002
422 #define	MDIO_WIS_REG_LASI_STATUS	0x9005
424 #define	MDIO_PCS_DEVAD			0x3
425 #define	MDIO_PCS_REG_STATUS		0x0020
426 #define MDIO_PCS_REG_LASI_STATUS	0x9005
427 #define MDIO_PCS_REG_7101_DSP_ACCESS	0xD000
428 #define MDIO_PCS_REG_7101_SPI_MUX 	0xD008
429 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
431 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
433 	#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD   (0xC7)
435 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
439 #define	MDIO_XS_DEVAD			0x4
440 #define	MDIO_XS_REG_STATUS		0x0001
441 #define MDIO_XS_PLL_SEQUENCER 		0x8000
442 #define	MDIO_XS_SFX7101_XGXS_TEST1	0xc00a
444 #define MDIO_XS_8706_REG_BANK_RX0	0x80bc
445 #define MDIO_XS_8706_REG_BANK_RX1	0x80cc
446 #define MDIO_XS_8706_REG_BANK_RX2	0x80dc
447 #define MDIO_XS_8706_REG_BANK_RX3	0x80ec
448 #define MDIO_XS_8706_REG_BANK_RXA	0x80fc
450 #define MDIO_XS_REG_8073_RX_CTRL_PCIE	0x80FA
452 #define	MDIO_AN_DEVAD			0x7
454 #define	MDIO_AN_REG_CTRL		0x0000
455 #define	MDIO_AN_REG_STATUS		0x0001
456 	#define	MDIO_AN_REG_STATUS_AN_COMPLETE		0x0020
457 #define	MDIO_AN_REG_ADV_PAUSE		0x0010
458 	#define	MDIO_AN_REG_ADV_PAUSE_PAUSE		0x0400
459 	#define	MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC	0x0800
460 	#define	MDIO_AN_REG_ADV_PAUSE_BOTH		0x0C00
461 	#define	MDIO_AN_REG_ADV_PAUSE_MASK		0x0C00
462 #define	MDIO_AN_REG_ADV			0x0011
463 #define MDIO_AN_REG_ADV2		0x0012
464 #define	MDIO_AN_REG_LP_AUTO_NEG		0x0013
465 #define	MDIO_AN_REG_LP_AUTO_NEG2	0x0014
466 #define	MDIO_AN_REG_MASTER_STATUS	0x0021
467 #define	MDIO_AN_REG_EEE_ADV		0x003c
468 #define	MDIO_AN_REG_LP_EEE_ADV		0x003d
470 #define	MDIO_AN_REG_LINK_STATUS		0x8304
471 #define	MDIO_AN_REG_CL37_CL73		0x8370
472 #define	MDIO_AN_REG_CL37_AN		0xffe0
473 #define	MDIO_AN_REG_CL37_FC_LD		0xffe4
474 #define 	MDIO_AN_REG_CL37_FC_LP		0xffe5
475 #define 	MDIO_AN_REG_1000T_STATUS	0xffea
477 #define MDIO_AN_REG_8073_2_5G		0x8329
478 #define MDIO_AN_REG_8073_BAM		0x8350
480 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL	0x0020
481 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL	0xffe0
482 	#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G	0x40
483 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS	0xffe1
484 #define MDIO_AN_REG_848xx_ID_MSB		0xffe2
485 	#define BCM84858_PHY_ID					0x600d
486 #define MDIO_AN_REG_848xx_ID_LSB		0xffe3
487 #define MDIO_AN_REG_8481_LEGACY_AN_ADV		0xffe4
488 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION	0xffe6
489 #define MDIO_AN_REG_8481_1000T_CTRL		0xffe9
490 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL	0xfff0
491 	#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF	0x0008
492 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW	0xfff5
493 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS	0xfff7
494 #define MDIO_AN_REG_8481_AUX_CTRL		0xfff8
495 #define MDIO_AN_REG_8481_LEGACY_SHADOW		0xfffc
498 #define	MDIO_CTL_DEVAD			0x1e
499 #define MDIO_CTL_REG_84823_MEDIA		0x401a
500 	#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK		0x0018
502 		#define MDIO_CTL_REG_84823_CTRL_MAC_XFI			0x0008
503 		#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M		0x0010
505 	#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK		0x0060
506 		#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L		0x0020
507 		#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI		0x0040
511 	#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN	0x0080
512 	#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK		0x0100
513 		#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER	0x0000
514 		#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER		0x0100
515 	#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G			0x1000
516 #define MDIO_CTL_REG_84823_USER_CTRL_REG			0x4005
517 	#define MDIO_CTL_REG_84823_USER_CTRL_CMS			0x0080
518 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH		0xa82b
519 	#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ	0x2f
520 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1			0xa8e3
521 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1			0xa8ec
522 	#define MDIO_PMA_REG_84823_LED3_STRETCH_EN			0x0080
525 #define MDIO_84833_TOP_CFG_FW_REV			0x400f
526 	#define MDIO_84833_TOP_CFG_FW_EEE		0x10b1
527 	#define MDIO_84833_TOP_CFG_FW_NO_EEE		0x1f81
528 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 		0x401a
529 	#define MDIO_84833_SUPER_ISOLATE 		0x8000
531 #define MDIO_848xx_TOP_CFG_SCRATCH_REG0			0x4005
532 #define MDIO_848xx_TOP_CFG_SCRATCH_REG1 		0x4006
533 #define MDIO_848xx_TOP_CFG_SCRATCH_REG2			0x4007
534 #define MDIO_848xx_TOP_CFG_SCRATCH_REG3			0x4008
535 #define MDIO_848xx_TOP_CFG_SCRATCH_REG4			0x4009
536 #define MDIO_848xx_TOP_CFG_SCRATCH_REG26		0x4037
537 #define MDIO_848xx_TOP_CFG_SCRATCH_REG27		0x4038
538 #define MDIO_848xx_TOP_CFG_SCRATCH_REG28		0x4039
539 #define MDIO_848xx_TOP_CFG_SCRATCH_REG29		0x403a
540 #define MDIO_848xx_TOP_CFG_SCRATCH_REG30		0x403b
541 #define MDIO_848xx_TOP_CFG_SCRATCH_REG31		0x403c
551 #define PHY848xx_CMD_SET_PAIR_SWAP			0x8001
552 #define PHY848xx_CMD_GET_EEE_MODE			0x8008
553 #define PHY848xx_CMD_SET_EEE_MODE			0x8009
554 #define PHY848xx_CMD_GET_CURRENT_TEMP			0x8031
556 #define PHY84833_STATUS_CMD_RECEIVED			0x0001
557 #define PHY84833_STATUS_CMD_IN_PROGRESS			0x0002
558 #define PHY84833_STATUS_CMD_COMPLETE_PASS		0x0004
559 #define PHY84833_STATUS_CMD_COMPLETE_ERROR		0x0008
560 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS		0x0010
561 #define PHY84833_STATUS_CMD_SYSTEM_BOOT			0x0020
562 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS		0x0040
563 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE		0x0080
564 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE		0xa5a5
572 #define PHY84858_STATUS_CMD_RECEIVED			0x0001
573 #define PHY84858_STATUS_CMD_IN_PROGRESS			0x0002
574 #define PHY84858_STATUS_CMD_COMPLETE_PASS		0x0004
575 #define PHY84858_STATUS_CMD_COMPLETE_ERROR		0x0008
576 #define PHY84858_STATUS_CMD_SYSTEM_BUSY                 0xbbbb
580 #define MDIO_WC_DEVAD					0x3
581 #define MDIO_WC_REG_IEEE0BLK_MIICNTL                    0x0
582 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP                  0x7
583 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0       0x10
584 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1       0x11
585 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2       0x12
586 	#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY	0x4000
587 	#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ		0x8000
588 #define MDIO_WC_REG_PCS_STATUS2				0x0021
589 #define MDIO_WC_REG_PMD_KR_CONTROL			0x0096
590 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL                0x8000
591 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1               0x800e
592 #define MDIO_WC_REG_XGXSBLK1_DESKEW                     0x8010
593 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0                  0x8015
594 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1                  0x8016
595 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2                  0x8017
596 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3                  0x8018
597 #define MDIO_WC_REG_XGXSBLK1_LANETEST0                  0x801a
598 #define MDIO_WC_REG_TX0_ANA_CTRL0			0x8061
599 #define MDIO_WC_REG_TX1_ANA_CTRL0			0x8071
600 #define MDIO_WC_REG_TX2_ANA_CTRL0			0x8081
601 #define MDIO_WC_REG_TX3_ANA_CTRL0			0x8091
602 #define MDIO_WC_REG_TX0_TX_DRIVER			0x8067
603 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET			0x01
604 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK				0x000e
605 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET		0x04
606 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK			0x00f0
607 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET		0x08
608 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK				0x0f00
609 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET		0x0c
610 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK			0x7000
611 #define MDIO_WC_REG_TX1_TX_DRIVER			0x8077
612 #define MDIO_WC_REG_TX2_TX_DRIVER			0x8087
613 #define MDIO_WC_REG_TX3_TX_DRIVER			0x8097
614 #define MDIO_WC_REG_RX0_ANARXCONTROL1G                  0x80b9
615 #define MDIO_WC_REG_RX2_ANARXCONTROL1G                  0x80d9
616 #define MDIO_WC_REG_RX0_PCI_CTRL			0x80ba
617 #define MDIO_WC_REG_RX1_PCI_CTRL			0x80ca
618 #define MDIO_WC_REG_RX2_PCI_CTRL			0x80da
619 #define MDIO_WC_REG_RX3_PCI_CTRL			0x80ea
620 #define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI		0x80fa
621 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 		0x8104
622 #define MDIO_WC_REG_XGXSBLK2_LANE_RESET 		0x810a
623 #define MDIO_WC_REG_XGXS_STATUS3			0x8129
624 #define MDIO_WC_REG_PAR_DET_10G_STATUS			0x8130
625 #define MDIO_WC_REG_PAR_DET_10G_CTRL			0x8131
626 #define MDIO_WC_REG_XGXS_STATUS4                        0x813c
627 #define MDIO_WC_REG_XGXS_X2_CONTROL2 		        0x8141
628 #define MDIO_WC_REG_XGXS_X2_CONTROL3 		        0x8142
629 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1		      	0x816B
630 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1		      	0x8169
631 #define MDIO_WC_REG_GP2_STATUS_GP_2_0			0x81d0
632 #define MDIO_WC_REG_GP2_STATUS_GP_2_1			0x81d1
633 #define MDIO_WC_REG_GP2_STATUS_GP_2_2			0x81d2
634 #define MDIO_WC_REG_GP2_STATUS_GP_2_3			0x81d3
635 #define MDIO_WC_REG_GP2_STATUS_GP_2_4			0x81d4
636 	#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
637 	#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
638 	#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
639 	#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
640 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP                0x81EE
641 #define MDIO_WC_REG_UC_INFO_B1_VERSION                  0x81F0
642 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE		0x81F2
643 	#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET	0x0
644 		#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT        0x0
645 		#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR     0x1
646 		#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC        0x2
647 		#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI      0x3
648 		#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G     0x4
649 	#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET	0x4
650 	#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET	0x8
651 	#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET	0xc
652 #define MDIO_WC_REG_UC_INFO_B1_CRC                      0x81FE
653 #define MDIO_WC_REG_DSC1B0_UC_CTRL				0x820e
655 #define MDIO_WC_REG_DSC_SMC				0x8213
656 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0		0x821e
657 #define MDIO_WC_REG_TX_FIR_TAP				0x82e2
658 	#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET		0x00
659 	#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK			0x000f
660 	#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET		0x04
661 	#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK		0x03f0
662 	#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET		0x0a
663 	#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK		0x7c00
664 	#define MDIO_WC_REG_TX_FIR_TAP_ENABLE		0x8000
665 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP		0x82e2
666 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL      0x82e3
667 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL	0x82e6
668 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL	0x82e7
669 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL	0x82e8
670 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL      0x82ec
671 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1         0x8300
672 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2         0x8301
673 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3         0x8302
674 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1          0x8304
675 #define MDIO_WC_REG_SERDESDIGITAL_MISC1                 0x8308
676 #define MDIO_WC_REG_SERDESDIGITAL_MISC2                 0x8309
677 #define MDIO_WC_REG_DIGITAL3_UP1                        0x8329
678 #define MDIO_WC_REG_DIGITAL3_LP_UP1                     0x832c
679 #define MDIO_WC_REG_DIGITAL4_MISC3                      0x833c
680 #define MDIO_WC_REG_DIGITAL4_MISC5                      0x833e
681 #define MDIO_WC_REG_DIGITAL5_MISC6                      0x8345
682 #define MDIO_WC_REG_DIGITAL5_MISC7                      0x8349
683 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS		0x834d
684 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED               0x834e
685 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL           0x8350
686 #define MDIO_WC_REG_CL49_USERB0_CTRL	                0x8368
687 #define MDIO_WC_REG_CL73_USERB0_CTRL                    0x8370
688 #define MDIO_WC_REG_CL73_USERB0_USTAT                   0x8371
689 #define MDIO_WC_REG_CL73_BAM_CTRL1			0x8372
690 #define MDIO_WC_REG_CL73_BAM_CTRL2			0x8373
691 #define MDIO_WC_REG_CL73_BAM_CTRL3			0x8374
692 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD			0x837b
693 #define MDIO_WC_REG_EEE_COMBO_CONTROL0                  0x8390
694 #define MDIO_WC_REG_TX66_CONTROL                        0x83b0
695 #define MDIO_WC_REG_RX66_CONTROL                        0x83c0
696 #define MDIO_WC_REG_RX66_SCW0                           0x83c2
697 #define MDIO_WC_REG_RX66_SCW1                           0x83c3
698 #define MDIO_WC_REG_RX66_SCW2                           0x83c4
699 #define MDIO_WC_REG_RX66_SCW3                           0x83c5
700 #define MDIO_WC_REG_RX66_SCW0_MASK                      0x83c6
701 #define MDIO_WC_REG_RX66_SCW1_MASK                      0x83c7
702 #define MDIO_WC_REG_RX66_SCW2_MASK                      0x83c8
703 #define MDIO_WC_REG_RX66_SCW3_MASK                      0x83c9
704 #define MDIO_WC_REG_FX100_CTRL1				0x8400
705 #define MDIO_WC_REG_FX100_CTRL3				0x8402
706 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5		0x8436
707 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6		0x8437
708 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7		0x8438
709 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9		0x8439
710 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10		0x843a
711 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11		0x843b
712 #define MDIO_WC_REG_ETA_CL73_OUI1			0x8453
713 #define MDIO_WC_REG_ETA_CL73_OUI2			0x8454
714 #define MDIO_WC_REG_ETA_CL73_OUI3			0x8455
715 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE		0x8456
716 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE			0x8457
717 #define MDIO_WC_REG_MICROBLK_CMD                        0xffc2
718 #define MDIO_WC_REG_MICROBLK_DL_STATUS                  0xffc5
719 #define MDIO_WC_REG_MICROBLK_CMD3                       0xffcc
721 #define MDIO_WC_REG_AERBLK_AER                          0xffde
722 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL			0xffe0
723 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT                0xffe1
725 #define MDIO_WC0_XGXS_BLK2_LANE_RESET                   0x810A
726 	#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 	0
729 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2             0x8141
731 #define DIGITAL5_ACTUAL_SPEED_TX_MASK                   0x003f
734 #define MDIO_REG_GPHY_MII_STATUS			0x1
735 #define MDIO_REG_GPHY_PHYID_LSB				0x3
736 #define MDIO_REG_GPHY_CL45_ADDR_REG			0xd
737 	#define MDIO_REG_GPHY_CL45_REG_WRITE		0x4000
738 	#define MDIO_REG_GPHY_CL45_REG_READ		0xc000
739 #define MDIO_REG_GPHY_CL45_DATA_REG			0xe
740 	#define MDIO_REG_GPHY_EEE_RESOLVED		0x803e
741 #define MDIO_REG_GPHY_EXP_ACCESS_GATE			0x15
742 #define MDIO_REG_GPHY_EXP_ACCESS			0x17
743 	#define MDIO_REG_GPHY_EXP_ACCESS_TOP		0xd00
744 	#define MDIO_REG_GPHY_EXP_TOP_2K_BUF		0x40
745 #define MDIO_REG_GPHY_AUX_STATUS			0x19
746 #define MDIO_REG_INTR_STATUS				0x1a
747 #define MDIO_REG_INTR_MASK				0x1b
748 	#define MDIO_REG_INTR_MASK_LINK_STATUS			(0x1 << 1)
749 #define MDIO_REG_GPHY_SHADOW				0x1c
750 	#define MDIO_REG_GPHY_SHADOW_LED_SEL1			(0x0d << 10)
751 	#define MDIO_REG_GPHY_SHADOW_LED_SEL2			(0x0e << 10)
752 	#define MDIO_REG_GPHY_SHADOW_WR_ENA			(0x1 << 15)
753 	#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED		(0x1e << 10)
754 	#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD		(0x1 << 8)
771 #define I2C_BSC0			0
785 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
883 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR		0x2
884 	#define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN	0x0
885 	#define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC	0x7
886 	#define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER	0x21
887 	#define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45	0x22
890 #define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR		0x3
895 #define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR		0x6
896 	#define ELINK_SFP_EEPROM_1G_COMP_CODE_SX	(1<<0)
901 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR		0x8
902 	#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
903 	#define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
905 #define ELINK_SFP_EEPROM_OPTIONS_ADDR			0x40
906 	#define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
909 #define ELINK_EDC_MODE_LINEAR				0x0022
910 #define ELINK_EDC_MODE_LIMITING				0x0044
911 #define ELINK_EDC_MODE_PASSIVE_DAC			0x0055
912 #define ELINK_EDC_MODE_ACTIVE_DAC			0x0066
915 #define DCBX_INVALID_COS					(0xFF)
917 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND		(0x5000)
918 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT		(0x5000)
926 #define DEFAULT_TX_DRV_IFIR		0
937 		(_bank + (_addr & 0xf)), \
943 		(_bank + (_addr & 0xf)), \
974  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
1010 		return 0;  in elink_check_lfa()
1022 		lfa_mask = 0xffffffff;  in elink_check_lfa()
1025 		lfa_mask = 0xffff;  in elink_check_lfa()
1031 	req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);  in elink_check_lfa()
1040 	req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);  in elink_check_lfa()
1049 	req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);  in elink_check_lfa()
1056 	for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {  in elink_check_lfa()
1094 	return 0;  in elink_check_lfa()
1102 	*en = 0;  in elink_get_epio()
1148 		uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;  in elink_set_cfg_pin()
1161 		uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;  in elink_get_cfg_pin()
1178 	/* mapping between entry  priority to client number (0,1,2 -debug and  in elink_ets_e2e3a0_disabled()
1185 	REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);  in elink_ets_e2e3a0_disabled()
1187 	 * as strict.  Bits 0,1,2 - debug and management entries, 3 -  in elink_ets_e2e3a0_disabled()
1194 	REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);  in elink_ets_e2e3a0_disabled()
1196 	REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);  in elink_ets_e2e3a0_disabled()
1200 	REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);  in elink_ets_e2e3a0_disabled()
1204 	REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);  in elink_ets_e2e3a0_disabled()
1205 	REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);  in elink_ets_e2e3a0_disabled()
1206 	REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);  in elink_ets_e2e3a0_disabled()
1208 	REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);  in elink_ets_e2e3a0_disabled()
1209 	REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);  in elink_ets_e2e3a0_disabled()
1210 	REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);  in elink_ets_e2e3a0_disabled()
1212 	REG_WR(sc, PBF_REG_ETS_ENABLED, 0);  in elink_ets_e2e3a0_disabled()
1216 	REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710);  in elink_ets_e2e3a0_disabled()
1217 	REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710);  in elink_ets_e2e3a0_disabled()
1219 	REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680);  in elink_ets_e2e3a0_disabled()
1220 	REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680);  in elink_ets_e2e3a0_disabled()
1222 	REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);  in elink_ets_e2e3a0_disabled()
1231 	uint32_t min_w_val = 0;  in elink_ets_get_min_w_val_nig()
1306 	/* Mapping between entry  priority to client number (0,1,2 -debug and  in elink_ets_e3b0_nig_disabled()
1312 		REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);  in elink_ets_e3b0_nig_disabled()
1313 		REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);  in elink_ets_e3b0_nig_disabled()
1315 		REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);  in elink_ets_e3b0_nig_disabled()
1316 		REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);  in elink_ets_e3b0_nig_disabled()
1322 		   NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);  in elink_ets_e3b0_nig_disabled()
1328 		REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);  in elink_ets_e3b0_nig_disabled()
1329 		REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);  in elink_ets_e3b0_nig_disabled()
1331 		/*Port 0 has 9 COS*/  in elink_ets_e3b0_nig_disabled()
1333 		       0x43210876);  in elink_ets_e3b0_nig_disabled()
1334 		REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);  in elink_ets_e3b0_nig_disabled()
1338 	 * as strict.  Bits 0,1,2 - debug and management entries, 3 -  in elink_ets_e3b0_nig_disabled()
1345 		REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);  in elink_ets_e3b0_nig_disabled()
1347 		REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);  in elink_ets_e3b0_nig_disabled()
1350 		   NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);  in elink_ets_e3b0_nig_disabled()
1359 		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);  in elink_ets_e3b0_nig_disabled()
1361 		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);  in elink_ets_e3b0_nig_disabled()
1363 		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);  in elink_ets_e3b0_nig_disabled()
1365 		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);  in elink_ets_e3b0_nig_disabled()
1367 		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);  in elink_ets_e3b0_nig_disabled()
1369 		   NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);  in elink_ets_e3b0_nig_disabled()
1371 		REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);  in elink_ets_e3b0_nig_disabled()
1372 		REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);  in elink_ets_e3b0_nig_disabled()
1373 		REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);  in elink_ets_e3b0_nig_disabled()
1391 	uint32_t base_upper_bound = 0;  in elink_ets_e3b0_set_credit_upper_bound_pbf()
1392 	uint8_t max_cos = 0;  in elink_ets_e3b0_set_credit_upper_bound_pbf()
1393 	uint8_t i = 0;  in elink_ets_e3b0_set_credit_upper_bound_pbf()
1405 	for (i = 0; i < max_cos; i++)  in elink_ets_e3b0_set_credit_upper_bound_pbf()
1422 	uint8_t i = 0;  in elink_ets_e3b0_pbf_disabled()
1423 	uint32_t base_weight = 0;  in elink_ets_e3b0_pbf_disabled()
1424 	uint8_t max_cos = 0;  in elink_ets_e3b0_pbf_disabled()
1426 	/* Mapping between entry  priority to client number 0 - COS0  in elink_ets_e3b0_pbf_disabled()
1431 		/*  0x688 (|011|0 10|00 1|000) */  in elink_ets_e3b0_pbf_disabled()
1432 		REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);  in elink_ets_e3b0_pbf_disabled()
1434 		/*  (10 1|100 |011|0 10|00 1|000) */  in elink_ets_e3b0_pbf_disabled()
1435 		REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);  in elink_ets_e3b0_pbf_disabled()
1439 		/* 0x688 (|011|0 10|00 1|000)*/  in elink_ets_e3b0_pbf_disabled()
1440 		REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);  in elink_ets_e3b0_pbf_disabled()
1442 	/* 0x2C688 (10 1|100 |011|0 10|00 1|000) */  in elink_ets_e3b0_pbf_disabled()
1443 	REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);  in elink_ets_e3b0_pbf_disabled()
1446 		   PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);  in elink_ets_e3b0_pbf_disabled()
1450 		   PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);  in elink_ets_e3b0_pbf_disabled()
1453 		   PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);  in elink_ets_e3b0_pbf_disabled()
1465 	for (i = 0; i < max_cos; i++)  in elink_ets_e3b0_pbf_disabled()
1466 		REG_WR(sc, base_weight + (0x4 * i), 0);  in elink_ets_e3b0_pbf_disabled()
1528 	const uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);  in elink_ets_e3b0_cli_map()
1563 	uint32_t nig_reg_adress_crd_weight = 0;  in elink_ets_e3b0_set_cos_bw()
1564 	uint32_t pbf_reg_adress_crd_weight = 0;  in elink_ets_e3b0_set_cos_bw()
1565 	/* Calculate and set BW for this COS - use 1 instead of 0 for BW */  in elink_ets_e3b0_set_cos_bw()
1570 	case 0:  in elink_ets_e3b0_set_cos_bw()
1624 *	Calculate the total BW.A value of 0 isn't legal.
1633 	uint8_t cos_idx = 0;  in elink_ets_e3b0_get_total_bw()
1634 	uint8_t is_bw_cos_exist = 0;  in elink_ets_e3b0_get_total_bw()
1636 	*total_bw = 0 ;  in elink_ets_e3b0_get_total_bw()
1638 	for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {  in elink_ets_e3b0_get_total_bw()
1643 						   "was set to 0\n");  in elink_ets_e3b0_get_total_bw()
1657 		if (*total_bw == 0) {  in elink_ets_e3b0_get_total_bw()
1659 			   "elink_ets_E3B0_config total BW shouldn't be 0\n");  in elink_ets_e3b0_get_total_bw()
1678 	uint8_t pri = 0;  in elink_ets_e3b0_sp_pri_to_cos_init()
1679 	for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++)  in elink_ets_e3b0_sp_pri_to_cos_init()
1726 	uint64_t pri_cli_nig = 0;  in elink_e3b0_sp_get_pri_cli_reg()
1756 	const uint8_t pbf_cos_offset = 0;  in elink_e3b0_sp_get_pri_cli_reg_pbf()
1757 	const uint8_t pbf_pri_offset = 0;  in elink_e3b0_sp_get_pri_cli_reg_pbf()
1774 	uint8_t i = 0;  in elink_ets_e3b0_sp_set_pri_cli_reg()
1777 	uint64_t pri_cli_nig = 0x210;  in elink_ets_e3b0_sp_set_pri_cli_reg()
1778 	uint32_t pri_cli_pbf = 0x0;  in elink_ets_e3b0_sp_set_pri_cli_reg()
1779 	uint8_t pri_set = 0;  in elink_ets_e3b0_sp_set_pri_cli_reg()
1780 	uint8_t pri_bitmask = 0;  in elink_ets_e3b0_sp_set_pri_cli_reg()
1787 	for (i = 0; i < max_num_of_cos; i++) {  in elink_ets_e3b0_sp_set_pri_cli_reg()
1816 	for (i = 0; i < max_num_of_cos; i++) {  in elink_ets_e3b0_sp_set_pri_cli_reg()
1847 		const uint32_t pri_cli_nig_msb = (uint32_t) ((pri_cli_nig >> 32) & 0xF);  in elink_ets_e3b0_sp_set_pri_cli_reg()
1870 	uint16_t total_bw = 0;  in elink_ets_e3b0_config()
1873 	uint8_t cos_bw_bitmap = 0;  in elink_ets_e3b0_config()
1874 	uint8_t cos_sp_bitmap = 0;  in elink_ets_e3b0_config()
1875 	uint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0};  in elink_ets_e3b0_config()
1878 	uint8_t cos_entry = 0;  in elink_ets_e3b0_config()
1911 	for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {  in elink_ets_e3b0_config()
1971 	 * COS0 0x8  in elink_ets_bw_limit_common()
1972 	 * COS1 0x10  in elink_ets_bw_limit_common()
1974 	REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);  in elink_ets_bw_limit_common()
1977 	 * client 0)  in elink_ets_bw_limit_common()
1981 	REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);  in elink_ets_bw_limit_common()
1992 	REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);  in elink_ets_bw_limit_common()
1994 	 * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0  in elink_ets_bw_limit_common()
2000 	REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);  in elink_ets_bw_limit_common()
2015 	uint32_t cos0_credit_weight = 0;  in elink_ets_bw_limit()
2016 	uint32_t cos1_credit_weight = 0;  in elink_ets_bw_limit()
2045 	uint32_t val	= 0;  in elink_ets_strict()
2049 	 * as strict.  Bits 0,1,2 - debug and management entries,  in elink_ets_strict()
2055 	REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);  in elink_ets_strict()
2059 	REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);  in elink_ets_strict()
2061 	REG_WR(sc, PBF_REG_ETS_ENABLED, 0);  in elink_ets_strict()
2063 	REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);  in elink_ets_strict()
2068 	/* Mapping between entry  priority to client number (0,1,2 -debug and  in elink_ets_strict()
2075 	val = (!strict_cos) ? 0x2318 : 0x22E0;  in elink_ets_strict()
2096 	pause_val = 0x18000;  in elink_update_pfc_xmac()
2097 	pfc0_val = 0xFFFF8000;  in elink_update_pfc_xmac()
2098 	pfc1_val = 0x2;  in elink_update_pfc_xmac()
2139 	       ((params->mac_addr[0] << 8) |  in elink_update_pfc_xmac()
2152 	uint32_t val_xon = 0;  in elink_emac_get_pfc_stat()
2153 	uint32_t val_xoff = 0;  in elink_emac_get_pfc_stat()
2164 	pfc_frames_received[0] = val_xon + val_xoff;  in elink_emac_get_pfc_stat()
2173 	pfc_frames_sent[0] = val_xon + val_xoff;  in elink_emac_get_pfc_stat()
2204 	 * (a value of 49==0x31) and make sure that the AUTO poll is off  in elink_set_mdio_clk()
2222 	ELINK_DEBUG_P2(sc, "Changing emac_mode from 0x%x to 0x%x\n",  in elink_set_mdio_clk()
2233 	if (port4mode_ovwr_val & (1<<0)) {  in elink_is_4_port_mode()
2287 	val = ((params->mac_addr[0] << 8) |  in elink_emac_init()
2356 		val |= (0<<2);  in elink_umac_enable()
2389 		REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);  in elink_umac_enable()
2391 		REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);  in elink_umac_enable()
2401 	       ((params->mac_addr[0] << 8) |  in elink_umac_enable()
2422 	REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);  in elink_umac_enable()
2424 			    ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);  in elink_umac_enable()
2469 		REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);  in elink_xmac_init()
2538 	REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);  in elink_xmac_enable()
2547 		REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);  in elink_xmac_enable()
2553 	REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);  in elink_xmac_enable()
2556 	REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);  in elink_xmac_enable()
2559 	elink_update_pfc_xmac(params, vars, 0);  in elink_xmac_enable()
2563 		REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);  in elink_xmac_enable()
2564 		REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);  in elink_xmac_enable()
2566 		REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);  in elink_xmac_enable()
2583 			    ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);  in elink_xmac_enable()
2610 		/* Use lane 1 (of lanes 0-3) */  in elink_emac_enable()
2619 		/* Use lane 1 (of lanes 0-3) */  in elink_emac_enable()
2623 		REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);  in elink_emac_enable()
2633 		/* select the master lanes (out of 0-3) */  in elink_emac_enable()
2641 		REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);  in elink_emac_enable()
2693 	elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);  in elink_emac_enable()
2703 			((0x0101 <<  in elink_emac_enable()
2705 			 (0x00ff <<  in elink_emac_enable()
2714 		val |= 0x810;  in elink_emac_enable()
2716 		val &= ~0x810;  in elink_emac_enable()
2728 	REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);  in elink_emac_enable()
2731 	REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x0);  in elink_emac_enable()
2732 	REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);  in elink_emac_enable()
2733 	REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);  in elink_emac_enable()
2736 	REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x1);  in elink_emac_enable()
2737 	val = 0;  in elink_emac_enable()
2744 	REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);  in elink_emac_enable()
2753 		REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);  in elink_emac_enable()
2756 	REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);  in elink_emac_enable()
2770 	uint32_t val = 0x14;  in elink_update_pfc_bmac1()
2776 	wb_data[0] = val;  in elink_update_pfc_bmac1()
2777 	wb_data[1] = 0;  in elink_update_pfc_bmac1()
2781 	val = 0xc0;  in elink_update_pfc_bmac1()
2785 		val |= 0x800000;  in elink_update_pfc_bmac1()
2786 	wb_data[0] = val;  in elink_update_pfc_bmac1()
2787 	wb_data[1] = 0;  in elink_update_pfc_bmac1()
2802 	uint32_t val = 0x14;  in elink_update_pfc_bmac2()
2809 	wb_data[0] = val;  in elink_update_pfc_bmac2()
2810 	wb_data[1] = 0;  in elink_update_pfc_bmac2()
2815 	val = 0xc0;  in elink_update_pfc_bmac2()
2819 		val |= 0x800000;  in elink_update_pfc_bmac2()
2820 	wb_data[0] = val;  in elink_update_pfc_bmac2()
2821 	wb_data[1] = 0;  in elink_update_pfc_bmac2()
2827 		wb_data[0] = 0x0;  in elink_update_pfc_bmac2()
2828 		wb_data[0] |= (1<<0);  /* RX */  in elink_update_pfc_bmac2()
2829 		wb_data[0] |= (1<<1);  /* TX */  in elink_update_pfc_bmac2()
2830 		wb_data[0] |= (1<<2);  /* Force initial Xon */  in elink_update_pfc_bmac2()
2831 		wb_data[0] |= (1<<3);  /* 8 cos */  in elink_update_pfc_bmac2()
2832 		wb_data[0] |= (1<<5);  /* STATS */  in elink_update_pfc_bmac2()
2833 		wb_data[1] = 0;  in elink_update_pfc_bmac2()
2837 		wb_data[0] &= ~(1<<2);  in elink_update_pfc_bmac2()
2841 		wb_data[0] = 0x8;  in elink_update_pfc_bmac2()
2842 		wb_data[1] = 0;  in elink_update_pfc_bmac2()
2852 	val = 0x8000;  in elink_update_pfc_bmac2()
2856 	wb_data[0] = val;  in elink_update_pfc_bmac2()
2857 	wb_data[1] = 0;  in elink_update_pfc_bmac2()
2862 	val = 0x3; /* Enable RX and TX */  in elink_update_pfc_bmac2()
2864 		val |= 0x4; /* Local loopback */  in elink_update_pfc_bmac2()
2871 	wb_data[0] = val;  in elink_update_pfc_bmac2()
2872 	wb_data[1] = 0;  in elink_update_pfc_bmac2()
2885 	uint32_t nig_reg_rx_priority_mask_add = 0;  in elink_pfc_nig_rx_priority_mask()
2888 	case 0:  in elink_pfc_nig_rx_priority_mask()
2937 	uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;  in elink_update_pfc_nig()
2938 	uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;  in elink_update_pfc_nig()
2939 	uint32_t pkt_priority_to_cos = 0;  in elink_update_pfc_nig()
2957 		pause_enable = 0;  in elink_update_pfc_nig()
2958 		llfc_out_en = 0;  in elink_update_pfc_nig()
2959 		llfc_enable = 0;  in elink_update_pfc_nig()
2961 			ppp_enable = 0;  in elink_update_pfc_nig()
2966 		xcm_out_en = 0;  in elink_update_pfc_nig()
2998 	       NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);  in elink_update_pfc_nig()
3009 		uint8_t i = 0;  in elink_update_pfc_nig()
3012 		for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)  in elink_update_pfc_nig()
3058 			elink_update_pfc_xmac(params, vars, 0);  in elink_update_pfc()
3063 		    == 0) {  in elink_update_pfc()
3065 			elink_emac_enable(params, vars, 0);  in elink_update_pfc()
3073 		val = 0;  in elink_update_pfc()
3097 	wb_data[0] = 0x3c;  in elink_bmac1_enable()
3098 	wb_data[1] = 0;  in elink_bmac1_enable()
3103 	wb_data[0] = ((params->mac_addr[2] << 24) |  in elink_bmac1_enable()
3107 	wb_data[1] = ((params->mac_addr[0] << 8) |  in elink_bmac1_enable()
3112 	val = 0x3;  in elink_bmac1_enable()
3114 		val |= 0x4;  in elink_bmac1_enable()
3117 	wb_data[0] = val;  in elink_bmac1_enable()
3118 	wb_data[1] = 0;  in elink_bmac1_enable()
3122 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;  in elink_bmac1_enable()
3123 	wb_data[1] = 0;  in elink_bmac1_enable()
3129 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;  in elink_bmac1_enable()
3130 	wb_data[1] = 0;  in elink_bmac1_enable()
3134 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;  in elink_bmac1_enable()
3135 	wb_data[1] = 0;  in elink_bmac1_enable()
3139 	wb_data[0] = 0x1000200;  in elink_bmac1_enable()
3140 	wb_data[1] = 0;  in elink_bmac1_enable()
3146 		wb_data[0] = 0xf000;  in elink_bmac1_enable()
3147 		wb_data[1] = 0;  in elink_bmac1_enable()
3168 	wb_data[0] = 0;  in elink_bmac2_enable()
3169 	wb_data[1] = 0;  in elink_bmac2_enable()
3174 	wb_data[0] = 0x3c;  in elink_bmac2_enable()
3175 	wb_data[1] = 0;  in elink_bmac2_enable()
3182 	wb_data[0] = ((params->mac_addr[2] << 24) |  in elink_bmac2_enable()
3186 	wb_data[1] = ((params->mac_addr[0] << 8) |  in elink_bmac2_enable()
3194 	wb_data[0] = 0x1000200;  in elink_bmac2_enable()
3195 	wb_data[1] = 0;  in elink_bmac2_enable()
3201 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;  in elink_bmac2_enable()
3202 	wb_data[1] = 0;  in elink_bmac2_enable()
3207 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;  in elink_bmac2_enable()
3208 	wb_data[1] = 0;  in elink_bmac2_enable()
3212 	wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;  in elink_bmac2_enable()
3213 	wb_data[1] = 0;  in elink_bmac2_enable()
3240 	REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);  in elink_bmac_enable()
3247 	REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);  in elink_bmac_enable()
3248 	REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);  in elink_bmac_enable()
3249 	REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);  in elink_bmac_enable()
3250 	val = 0;  in elink_bmac_enable()
3256 	REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);  in elink_bmac_enable()
3257 	REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x0);  in elink_bmac_enable()
3258 	REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);  in elink_bmac_enable()
3259 	REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x1);  in elink_bmac_enable()
3260 	REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);  in elink_bmac_enable()
3284 			wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;  in elink_set_bmac_rx()
3286 			wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;  in elink_set_bmac_rx()
3301 	REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);  in elink_pbf_update()
3306 	ELINK_DEBUG_P2(sc, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);  in elink_pbf_update()
3315 		ELINK_DEBUG_P2(sc, "BUG! init_crd 0x%x != crd 0x%x\n",  in elink_pbf_update()
3327 		REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, 0);  in elink_pbf_update()
3334 		REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);  in elink_pbf_update()
3343 			ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",  in elink_pbf_update()
3353 	REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x1);  in elink_pbf_update()
3355 	REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x0);  in elink_pbf_update()
3358 	REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);  in elink_pbf_update()
3380 	uint32_t emac_base = 0;  in elink_get_emac_base()
3430 	for (i = 0; i < 50; i++) {  in elink_cl22_write()
3466 	for (i = 0; i < 50; i++) {  in elink_cl22_read()
3479 		*ret_val = 0;  in elink_cl22_read()
3498 			  ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);  in elink_cl45_read()
3511 	for (i = 0; i < 50; i++) {  in elink_cl45_read()
3524 		*ret_val = 0;  in elink_cl45_read()
3533 		for (i = 0; i < 50; i++) {  in elink_cl45_read()
3547 			*ret_val = 0;  in elink_cl45_read()
3556 			elink_cl45_read(sc, phy, devad, 0xf, &temp_val);  in elink_cl45_read()
3575 			  ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);  in elink_cl45_write()
3589 	for (i = 0; i < 50; i++) {  in elink_cl45_write()
3610 		for (i = 0; i < 50; i++) {  in elink_cl45_write()
3632 			elink_cl45_read(sc, phy, devad, 0xf, &temp_val);  in elink_cl45_write()
3650 		return 0;  in elink_eee_has_cap()
3668 		*idle_timer = 0;  in elink_eee_nvram_to_time()
3709 				return 0;  in elink_eee_calc_timer()
3721 			return 0;  in elink_eee_calc_timer()
3730 	uint32_t eee_idle = 0, eee_mode;  in elink_eee_set_timers()
3741 		ELINK_DEBUG_P0(sc, "Error: Tx LPI is enabled with timer 0\n");  in elink_eee_set_timers()
3786 	REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);  in elink_eee_disable()
3788 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);  in elink_eee_disable()
3800 	uint16_t val = 0;  in elink_eee_advertise()
3803 	REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);  in elink_eee_advertise()
3807 		val |= 0x8;  in elink_eee_advertise()
3811 		val |= 0x4;  in elink_eee_advertise()
3837 	uint16_t adv = 0, lp = 0;  in elink_eee_an_resolve()
3838 	uint32_t lp_adv = 0;  in elink_eee_an_resolve()
3839 	uint8_t neg = 0;  in elink_eee_an_resolve()
3844 	if (lp & 0x2) {  in elink_eee_an_resolve()
3846 		if (adv & 0x2) {  in elink_eee_an_resolve()
3852 	if (lp & 0x14) {  in elink_eee_an_resolve()
3854 		if (adv & 0x14) {  in elink_eee_an_resolve()
3860 	if (lp & 0x68) {  in elink_eee_an_resolve()
3862 		if (adv & 0x68) {  in elink_eee_an_resolve()
3900 	i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;  in elink_bsc_module_sel()
3901 	i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;  in elink_bsc_module_sel()
3903 	for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)  in elink_bsc_module_sel()
3934 	/* Start xfer with 0 byte to update the address pointer ???*/  in elink_bsc_read()
3938 		(lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);  in elink_bsc_read()
3942 	i = 0;  in elink_bsc_read()
3944 	while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {  in elink_bsc_read()
3948 			ELINK_DEBUG_P1(sc, "wr 0 byte timed out after %d try\n",  in elink_bsc_read()
3966 	i = 0;  in elink_bsc_read()
3968 	while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {  in elink_bsc_read()
3983 		data_array[i] = ((data_array[i] & 0x000000ff) << 24) |  in elink_bsc_read()
3984 				((data_array[i] & 0x0000ff00) << 8) |  in elink_bsc_read()
3985 				((data_array[i] & 0x00ff0000) >> 8) |  in elink_bsc_read()
3986 				((data_array[i] & 0xff000000) >> 24);  in elink_bsc_read()
4016 	for (phy_index = 0; phy_index < params->num_phys; phy_index++) {  in elink_phy_read()
4033 	for (phy_index = 0; phy_index < params->num_phys; phy_index++) {  in elink_phy_write()
4046 	uint8_t lane = 0;  in elink_get_warpcore_lane()
4059 		if (path_swap_ovr & 0x1)  in elink_get_warpcore_lane()
4060 			path_swap = (path_swap_ovr & 0x2);  in elink_get_warpcore_lane()
4069 		if (port_swap_ovr & 0x1)  in elink_get_warpcore_lane()
4070 			port_swap = (port_swap_ovr & 0x2);  in elink_get_warpcore_lane()
4083 		if (path_swap_ovr & 0x1) {  in elink_get_warpcore_lane()
4084 			path_swap = (path_swap_ovr & 0x2);  in elink_get_warpcore_lane()
4109 		(phy->addr + ser_lane) : 0;  in elink_set_aer_mmd()
4116 		 * 0x200 is the broadcast address for lanes 0,1  in elink_set_aer_mmd()
4117 		 * 0x201 is the broadcast address for lanes 2,3  in elink_set_aer_mmd()
4120 			aer_val = (aer_val >> 1) | 0x200;  in elink_set_aer_mmd()
4122 		aer_val = 0x3800 + offset - 1;  in elink_set_aer_mmd()
4124 		aer_val = 0x3800 + offset;  in elink_set_aer_mmd()
4140 	REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);  in elink_set_serdes_access()
4141 	REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);  in elink_set_serdes_access()
4143 	REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);  in elink_set_serdes_access()
4146 	REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);  in elink_set_serdes_access()
4164 	REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,  in elink_serdes_deassert()
4176 		REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);  in elink_xgxs_specific_func()
4177 		REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,  in elink_xgxs_specific_func()
4239 	ELINK_DEBUG_P1(sc, "ieee_fc = 0x%x\n", *ieee_fc);  in elink_calc_ieee_aneg_adv()
4306 	ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x\n", val);  in elink_ext_phy_set_pause()
4318 	case 0xb:				/*   1  0   1  1 */  in elink_pause_resolve()
4323 	case 0xe:				/*   1  1   1  0 */  in elink_pause_resolve()
4328 	case 0x5:				/*   0  1   0  1 */  in elink_pause_resolve()
4329 	case 0x7:				/*   0  1   1  1 */  in elink_pause_resolve()
4330 	case 0xd:				/*   1  1   0  1 */  in elink_pause_resolve()
4331 	case 0xf:				/*   1  1   1  1 */  in elink_pause_resolve()
4350 	if (pause_result & (1<<0))  in elink_pause_resolve()
4366 		elink_cl22_read(sc, phy, 0x4, &ld_pause);  in elink_ext_phy_update_adv_fc()
4367 		elink_cl22_read(sc, phy, 0x5, &lp_pause);  in elink_ext_phy_update_adv_fc()
4407 	ELINK_DEBUG_P1(sc, "Ext PHY pause result 0x%x\n", pause_result);  in elink_ext_phy_update_adv_fc()
4416 	uint8_t ret = 0;  in elink_ext_phy_resolve_fc()
4469 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},  in elink_warpcore_enable_AN_KR2()
4470 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},  in elink_warpcore_enable_AN_KR2()
4471 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},  in elink_warpcore_enable_AN_KR2()
4472 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},  in elink_warpcore_enable_AN_KR2()
4473 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},  in elink_warpcore_enable_AN_KR2()
4474 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},  in elink_warpcore_enable_AN_KR2()
4476 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},  in elink_warpcore_enable_AN_KR2()
4477 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},  in elink_warpcore_enable_AN_KR2()
4478 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},  in elink_warpcore_enable_AN_KR2()
4479 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},  in elink_warpcore_enable_AN_KR2()
4480 		{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},  in elink_warpcore_enable_AN_KR2()
4481 		{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},  in elink_warpcore_enable_AN_KR2()
4482 		{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},  in elink_warpcore_enable_AN_KR2()
4483 		{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},  in elink_warpcore_enable_AN_KR2()
4484 		{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}  in elink_warpcore_enable_AN_KR2()
4491 	for (i = 0; i < ARRAY_SIZE(reg_set); i++)  in elink_warpcore_enable_AN_KR2()
4508 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},  in elink_disable_kr2()
4509 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},  in elink_disable_kr2()
4510 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},  in elink_disable_kr2()
4511 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},  in elink_disable_kr2()
4512 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},  in elink_disable_kr2()
4513 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},  in elink_disable_kr2()
4514 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},  in elink_disable_kr2()
4515 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},  in elink_disable_kr2()
4516 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},  in elink_disable_kr2()
4517 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},  in elink_disable_kr2()
4518 		{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},  in elink_disable_kr2()
4519 		{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},  in elink_disable_kr2()
4520 		{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},  in elink_disable_kr2()
4521 		{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},  in elink_disable_kr2()
4522 		{MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}  in elink_disable_kr2()
4526 	for (i = 0; i < ARRAY_SIZE(reg_set); i++)  in elink_disable_kr2()
4542 			 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);  in elink_warpcore_set_lpi_passthrough()
4544 				 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);  in elink_warpcore_set_lpi_passthrough()
4556 			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);  in elink_warpcore_restart_AN_KR()
4565 	uint16_t lane, i, cl72_ctrl, an_adv = 0, val;  in elink_warpcore_enable_AN_KR()
4569 		{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},  in elink_warpcore_enable_AN_KR()
4570 		{MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},  in elink_warpcore_enable_AN_KR()
4571 		{MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},  in elink_warpcore_enable_AN_KR()
4572 		{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},  in elink_warpcore_enable_AN_KR()
4574 		{MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},  in elink_warpcore_enable_AN_KR()
4575 		{MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},  in elink_warpcore_enable_AN_KR()
4576 		{MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},  in elink_warpcore_enable_AN_KR()
4580 	for (i = 0; i < ARRAY_SIZE(reg_set); i++)  in elink_warpcore_enable_AN_KR()
4586 	cl72_ctrl &= 0x08ff;  in elink_warpcore_enable_AN_KR()
4587 	cl72_ctrl |= 0x3800;  in elink_warpcore_enable_AN_KR()
4599 		elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);  in elink_warpcore_enable_AN_KR()
4609 				  MDIO_AER_BLOCK_AER_REG, 0);  in elink_warpcore_enable_AN_KR()
4620 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,  in elink_warpcore_enable_AN_KR()
4621 			 WC_TX_DRIVER(0x02, 0x06, 0x09, 0));  in elink_warpcore_enable_AN_KR()
4625 				 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),  in elink_warpcore_enable_AN_KR()
4626 				 WC_TX_DRIVER(0x02, 0x06, 0x09, 0));  in elink_warpcore_enable_AN_KR()
4629 			 0x03f0);  in elink_warpcore_enable_AN_KR()
4632 			 0x03f0);  in elink_warpcore_enable_AN_KR()
4659 				 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);  in elink_warpcore_enable_AN_KR()
4663 			MDIO_WC_REG_DIGITAL3_UP1, 0x1f);  in elink_warpcore_enable_AN_KR()
4673 					 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),  in elink_warpcore_enable_AN_KR()
4677 				 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);  in elink_warpcore_enable_AN_KR()
4684 				 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);  in elink_warpcore_enable_AN_KR()
4722 		{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},  in elink_warpcore_set_10G_KR()
4724 			0x3f00},  in elink_warpcore_set_10G_KR()
4725 		{MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},  in elink_warpcore_set_10G_KR()
4726 		{MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},  in elink_warpcore_set_10G_KR()
4727 		{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},  in elink_warpcore_set_10G_KR()
4728 		{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},  in elink_warpcore_set_10G_KR()
4730 		{MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}  in elink_warpcore_set_10G_KR()
4733 	for (i = 0; i < ARRAY_SIZE(reg_set); i++)  in elink_warpcore_set_10G_KR()
4740 			  MDIO_AER_BLOCK_AER_REG, 0);  in elink_warpcore_set_10G_KR()
4744 	val16 &= ~(0x0011 << lane);  in elink_warpcore_set_10G_KR()
4750 	val16 |= (0x0303 << (lane << 1));  in elink_warpcore_set_10G_KR()
4757 			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);  in elink_warpcore_set_10G_KR()
4760 			 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);  in elink_warpcore_set_10G_KR()
4764 			 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);  in elink_warpcore_set_10G_KR()
4768 			 MDIO_WC_REG_TX66_CONTROL, 0x9);  in elink_warpcore_set_10G_KR()
4772 				 MDIO_WC_REG_RX66_CONTROL, 0xF9);  in elink_warpcore_set_10G_KR()
4776 			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);  in elink_warpcore_set_10G_KR()
4778 			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);  in elink_warpcore_set_10G_KR()
4792 				 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);  in elink_warpcore_set_10G_XFI()
4796 				 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);  in elink_warpcore_set_10G_XFI()
4799 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);  in elink_warpcore_set_10G_XFI()
4803 				  MDIO_WC_REG_FX100_CTRL1, 0xFFFA);  in elink_warpcore_set_10G_XFI()
4807 				 MDIO_WC_REG_FX100_CTRL3, 0x0080);  in elink_warpcore_set_10G_XFI()
4811 				  MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);  in elink_warpcore_set_10G_XFI()
4816 				  0xFFEE);  in elink_warpcore_set_10G_XFI()
4823 			 ((val | 0x0006) & 0xFFFE));  in elink_warpcore_set_10G_XFI()
4829 	misc1_val &= ~(0x1f);  in elink_warpcore_set_10G_XFI()
4832 		misc1_val |= 0x5;  in elink_warpcore_set_10G_XFI()
4833 		tap_val = WC_TX_FIR(0x08, 0x37, 0x00);  in elink_warpcore_set_10G_XFI()
4834 		tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);  in elink_warpcore_set_10G_XFI()
4843 		misc1_val |= 0x9;  in elink_warpcore_set_10G_XFI()
4845 		/* TAP values are controlled by nvram, if value there isn't 0 */  in elink_warpcore_set_10G_XFI()
4849 			tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);  in elink_warpcore_set_10G_XFI()
4891 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,  in elink_warpcore_set_10G_XFI()
4896 				 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);  in elink_warpcore_set_10G_XFI()
4900 				 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);  in elink_warpcore_set_10G_XFI()
4906 			 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);  in elink_warpcore_set_10G_XFI()
4911 				  0xFFFE);  in elink_warpcore_set_10G_XFI()
4914 				  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);  in elink_warpcore_set_10G_XFI()
4922 	/* Set global registers, so set AER lane to 0 */  in elink_warpcore_set_20G_force_KR2()
4924 			  MDIO_AER_BLOCK_AER_REG, 0);  in elink_warpcore_set_20G_force_KR2()
4935 			 MDIO_AN_REG_CTRL, 0);  in elink_warpcore_set_20G_force_KR2()
4946 				 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);  in elink_warpcore_set_20G_force_KR2()
4958 			 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);  in elink_warpcore_set_20G_force_KR2()
4960 	/* Enable sequencer (over lane 0) */  in elink_warpcore_set_20G_force_KR2()
4962 			  MDIO_AER_BLOCK_AER_REG, 0);  in elink_warpcore_set_20G_force_KR2()
4976 			 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);  in elink_warpcore_set_20G_DXGXS()
4980 			 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);  in elink_warpcore_set_20G_DXGXS()
4983 			 MDIO_WC_REG_RX66_SCW0, 0xE070);  in elink_warpcore_set_20G_DXGXS()
4986 			 MDIO_WC_REG_RX66_SCW1, 0xC0D0);  in elink_warpcore_set_20G_DXGXS()
4989 			 MDIO_WC_REG_RX66_SCW2, 0xA0B0);  in elink_warpcore_set_20G_DXGXS()
4992 			 MDIO_WC_REG_RX66_SCW3, 0x8090);  in elink_warpcore_set_20G_DXGXS()
4995 			 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);  in elink_warpcore_set_20G_DXGXS()
4998 			 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);  in elink_warpcore_set_20G_DXGXS()
5001 			 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);  in elink_warpcore_set_20G_DXGXS()
5004 			 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);  in elink_warpcore_set_20G_DXGXS()
5008 			 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);  in elink_warpcore_set_20G_DXGXS()
5012 			 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);  in elink_warpcore_set_20G_DXGXS()
5017 			 (WC_TX_FIR(0x12, 0x2d, 0x00) |  in elink_warpcore_set_20G_DXGXS()
5020 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,  in elink_warpcore_set_20G_DXGXS()
5021 			 WC_TX_DRIVER(0x02, 0x02, 0x02, 0));  in elink_warpcore_set_20G_DXGXS()
5042 					 0x1000);  in elink_warpcore_set_sgmii_speed()
5047 		val16 &= 0xcebf;  in elink_warpcore_set_sgmii_speed()
5052 			val16 |= 0x2000;  in elink_warpcore_set_sgmii_speed()
5055 			val16 |= 0x0040;  in elink_warpcore_set_sgmii_speed()
5059 			   "Speed not supported: 0x%x\n", phy->req_line_speed);  in elink_warpcore_set_sgmii_speed()
5064 			val16 |= 0x0100;  in elink_warpcore_set_sgmii_speed()
5082 		digctrl_kx1 &= 0xff4a;  in elink_warpcore_set_sgmii_speed()
5103 			(digctrl_kx1 | 0x10));  in elink_warpcore_set_sgmii_speed()
5116 		val |= 0xC000;  in elink_warpcore_reset_lane()
5118 		val &= 0x3FFF;  in elink_warpcore_reset_lane()
5133 		{MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},  in elink_warpcore_clear_regs()
5134 		{MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},  in elink_warpcore_clear_regs()
5135 		{MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},  in elink_warpcore_clear_regs()
5136 		{MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},  in elink_warpcore_clear_regs()
5138 			0x0195},  in elink_warpcore_clear_regs()
5140 			0x0007},  in elink_warpcore_clear_regs()
5142 			0x0002},  in elink_warpcore_clear_regs()
5143 		{MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},  in elink_warpcore_clear_regs()
5144 		{MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},  in elink_warpcore_clear_regs()
5145 		{MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},  in elink_warpcore_clear_regs()
5146 		{MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}  in elink_warpcore_clear_regs()
5152 	for (i = 0; i < ARRAY_SIZE(wc_regs); i++)  in elink_warpcore_clear_regs()
5158 			 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);  in elink_warpcore_clear_regs()
5168 	*gpio_num = 0;  in elink_get_mod_abs_int_cfg()
5169 	*gpio_port = 0;  in elink_get_mod_abs_int_cfg()
5191 		*gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;  in elink_get_mod_abs_int_cfg()
5210 		return 0;  in elink_is_sfp_module_plugged()
5214 	if (gpio_val == 0)  in elink_is_sfp_module_plugged()
5217 		return 0;  in elink_is_sfp_module_plugged()
5230 	return (gp2_status_reg0 >> (8+lane)) & 0x1;  in elink_warpcore_get_sigdet()
5239 	uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;  in elink_warpcore_config_runtime()
5241 	vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;  in elink_warpcore_config_runtime()
5256 			elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,  in elink_warpcore_config_runtime()
5258 			lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */  in elink_warpcore_config_runtime()
5260 			lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;  in elink_warpcore_config_runtime()
5263 				vars->rx_tx_asic_rst = 0;  in elink_warpcore_config_runtime()
5267 				elink_warpcore_reset_lane(sc, phy, 0);  in elink_warpcore_config_runtime()
5271 					MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);  in elink_warpcore_config_runtime()
5274 				ELINK_DEBUG_P1(sc, "0x%x retry left\n",  in elink_warpcore_config_runtime()
5296 		elink_warpcore_set_10G_XFI(phy, params, 0);  in elink_warpcore_config_sfi()
5299 		elink_warpcore_set_sgmii_speed(phy, params, 1, 0);  in elink_warpcore_config_sfi()
5337 			   "serdes_net_if = 0x%x\n",  in elink_warpcore_config_init()
5349 		elink_warpcore_set_sgmii_speed(phy, params, 0, 1);  in elink_warpcore_config_init()
5373 					fiber_mode = 0;  in elink_warpcore_config_init()
5378 								0);  in elink_warpcore_config_init()
5421 			   "Unsupported Serdes Net Interface 0x%x\n",  in elink_warpcore_config_init()
5428 	elink_warpcore_reset_lane(sc, phy, 0);  in elink_warpcore_config_init()
5437 	elink_sfp_e3_set_transmitter(params, phy, 0);  in elink_warpcore_link_reset()
5446 				  MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);  in elink_warpcore_link_reset()
5449 				  MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);  in elink_warpcore_link_reset()
5453 			  MDIO_AER_BLOCK_AER_REG, 0);  in elink_warpcore_link_reset()
5457 				  ~0x10);  in elink_warpcore_link_reset()
5460 				  MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);  in elink_warpcore_link_reset()
5465 	val16 |= (0x11 << lane);  in elink_warpcore_link_reset()
5467 		val16 |= (0x22 << lane);  in elink_warpcore_link_reset()
5473 	val16 &= ~(0x0303 << (lane << 1));  in elink_warpcore_link_reset()
5474 	val16 |= (0x0101 << (lane << 1));  in elink_warpcore_link_reset()
5476 		val16 &= ~(0x0c0c << (lane << 1));  in elink_warpcore_link_reset()
5477 		val16 |= (0x0404 << (lane << 1));  in elink_warpcore_link_reset()
5502 				  MDIO_AER_BLOCK_AER_REG, 0);  in elink_set_warpcore_loopback()
5506 					 0x10);  in elink_set_warpcore_loopback()
5524 					 0x4000);  in elink_set_warpcore_loopback()
5526 					 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);  in elink_set_warpcore_loopback()
5586 		vars->flow_ctrl = 0;  in elink_sync_link()
5624 		vars->phy_link_up = 0;  in elink_sync_link()
5626 		vars->line_speed = 0;  in elink_sync_link()
5679 	ELINK_DEBUG_P1(sc, "media_types = 0x%x\n", media_types);  in elink_link_status_update()
5700 	ELINK_DEBUG_P3(sc, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",  in elink_link_status_update()
5702 	ELINK_DEBUG_P3(sc, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",  in elink_link_status_update()
5748 	for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {  in elink_reset_unicore()
5776 	 * No swap is 0123 => 0x1b no need to enable the swap  in elink_set_swap_lanes()
5787 	if (rx_lane_swap != 0x1b) {  in elink_set_swap_lanes()
5797 				  MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);  in elink_set_swap_lanes()
5800 	if (tx_lane_swap != 0x1b) {  in elink_set_swap_lanes()
5809 				  MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);  in elink_set_swap_lanes()
5826 	ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",  in elink_set_parallel_detection()
5931 				  0xe);  in elink_set_autoneg()
5962 		reg_val = 0;  in elink_set_autoneg()
5997 	ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);  in elink_program_serdes()
6023 	uint16_t val = 0;  in elink_set_brcm_cl37_advertisement()
6036 			  MDIO_OVER_1G_UP3, 0x400);  in elink_set_brcm_cl37_advertisement()
6089 			 "elink_restart_autoneg mii_control before = 0x%x\n",  in elink_restart_autoneg()
6150 			ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",  in elink_initialize_sgmii_process()
6166 		elink_restart_autoneg(phy, params, 0);  in elink_initialize_sgmii_process()
6233 		ELINK_DEBUG_P1(sc, "pause_result CL73 0x%x\n", pause_result);  in elink_update_adv_fc()
6247 		ELINK_DEBUG_P1(sc, "pause_result CL37 0x%x\n", pause_result);  in elink_update_adv_fc()
6278 	ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x\n", vars->flow_ctrl);  in elink_flow_ctrl_resolve()
6295 			     "rx_status(0x80b0) = 0x%x\n", rx_status);  in elink_check_fallback_to_cl37()
6313 			     "ustat_val(0x8371) = 0x%x\n", ustat_val);  in elink_check_fallback_to_cl37()
6329 			     "misc_rx_status(0x8330) = 0x%x\n",  in elink_check_fallback_to_cl37()
6343 			  0);  in elink_check_fallback_to_cl37()
6345 	elink_restart_autoneg(phy, params, 0);  in elink_check_fallback_to_cl37()
6415 				 "link speed unsupported  gp_status 0x%x\n",  in elink_get_link_speed_duplex()
6435 				  "link speed unsupported gp_status 0x%x\n",  in elink_get_link_speed_duplex()
6442 		vars->phy_link_up = 0;  in elink_get_link_speed_duplex()
6461 	uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;  in elink_link_settings_status()
6482 	ELINK_DEBUG_P3(sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",  in elink_link_settings_status()
6532 	ELINK_DEBUG_P3(sc, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",  in elink_link_settings_status()
6553 		link_up &= 0x1;  in elink_warpcore_read_status()
6563 		ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x\n",  in elink_warpcore_read_status()
6572 		ELINK_DEBUG_P1(sc, "0x81d1 = 0x%x\n", gp_status1);  in elink_warpcore_read_status()
6611 			ELINK_DEBUG_P3(sc, " ELINK_SINGLE_MEDIA_DIRECT duplex %x  flow_ctrl 0x%x link_status 0x%x\n",  in elink_warpcore_read_status()
6615 	ELINK_DEBUG_P3(sc, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",  in elink_warpcore_read_status()
6655 	ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x\n", lane, gp_speed);  in elink_warpcore_read_status()
6657 	if ((lane & 1) == 0)  in elink_warpcore_read_status()
6659 	gp_speed &= 0x3f00;  in elink_warpcore_read_status()
6671 	ELINK_DEBUG_P3(sc, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",  in elink_warpcore_read_status()
6693 	if (lp_up2 == 0)  in elink_set_gmii_tx_driver()
6719 	uint16_t mode = 0;  in elink_emac_program()
6722 	elink_bits_dis(sc, GRCBASE_EMAC0 + port*0x400 +  in elink_emac_program()
6746 		ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",  in elink_emac_program()
6754 		      GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,  in elink_emac_program()
6765 	uint16_t bank, i = 0;  in elink_set_preemphasis()
6768 	for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;  in elink_set_preemphasis()
6776 	for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;  in elink_set_preemphasis()
6805 			elink_set_autoneg(phy, params, vars, 0);  in elink_xgxs_config_init()
6858 	rc = elink_reset_unicore(params, phy, 0);  in elink_prepare_xgxs()
6879 	for (cnt = 0; cnt < 1000; cnt++) {  in elink_wait_reset_complete()
6896 	ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)\n", ctrl, cnt);  in elink_wait_reset_complete()
6936 	ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x\n", port,  in elink_link_int_enable()
6939 	ELINK_DEBUG_P3(sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",  in elink_link_int_enable()
6941 		 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),  in elink_link_int_enable()
6942 		 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));  in elink_link_int_enable()
6944 	   REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),  in elink_link_int_enable()
6945 	   REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));  in elink_link_int_enable()
6951 	uint32_t latch_status = 0;  in elink_rearm_latch_signal()
6960 	ELINK_DEBUG_P1(sc, "latch_status = 0x%x\n", latch_status);  in elink_rearm_latch_signal()
6977 		       (latch_status & 0xfffe) | (latch_status & 1));  in elink_rearm_latch_signal()
7014 		ELINK_DEBUG_P1(sc, "Ack link up interrupt with mask 0x%x\n",  in elink_link_int_ack()
7025 	uint32_t mask = 0xf0000000;  in elink_format_ver()
7031 		*str_ptr = '\0';  in elink_format_ver()
7035 	while (shift > 0) {  in elink_format_ver()
7039 		if (digit == 0 && remove_leading_zeros) {  in elink_format_ver()
7042 		} else if (digit < 0xa)  in elink_format_ver()
7043 			*str_ptr = digit + '0';  in elink_format_ver()
7045 			*str_ptr = digit - 0xa + 'a';  in elink_format_ver()
7046 		remove_leading_zeros = 0;  in elink_format_ver()
7063 	str[0] = '\0';  in elink_null_format_ver()
7072 	uint32_t spirom_ver = 0;  in elink_get_ext_phy_fw_version()
7081 	version[0] = '\0';  in elink_get_ext_phy_fw_version()
7091 	    (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {  in elink_get_ext_phy_fw_version()
7104 	*ver_p = '\0';  in elink_get_ext_phy_fw_version()
7115 		uint32_t md_devad = 0;  in elink_set_xgxs_loopback()
7122 					       port*0x18));  in elink_set_xgxs_loopback()
7124 			REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,  in elink_set_xgxs_loopback()
7125 			       0x5);  in elink_set_xgxs_loopback()
7131 				  (MDIO_AER_BLOCK_AER_REG & 0xf)),  in elink_set_xgxs_loopback()
7132 				 0x2800);  in elink_set_xgxs_loopback()
7137 				  (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),  in elink_set_xgxs_loopback()
7138 				 0x6041);  in elink_set_xgxs_loopback()
7145 			REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,  in elink_set_xgxs_loopback()
7153 				(MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),  in elink_set_xgxs_loopback()
7157 				 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),  in elink_set_xgxs_loopback()
7174 	ELINK_DEBUG_P2(sc, "speed 0x%x, hw_led_mode 0x%x\n",  in elink_set_led()
7192 		REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 0);  in elink_set_led()
7223 				REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);  in elink_set_led()
7249 				REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);  in elink_set_led()
7256 			REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);  in elink_set_led()
7274 		REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);  in elink_set_led()
7297 			       port*4, 0);  in elink_set_led()
7320 	uint16_t gp_status = 0, phy_index = 0;  in elink_test_link()
7321 	uint8_t ext_phy_link_up = 0, serdes_phy_type;  in elink_test_link()
7349 			gp_status = ((gp_status >> 8) & 0xf) |  in elink_test_link()
7350 				((gp_status >> 12) & 0xf);  in elink_test_link()
7488 	       (0x1ff << (params->port*16)));  in elink_int_link_reset()
7517 	elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);  in elink_update_link_down()
7524 	vars->line_speed = 0;  in elink_update_link_down()
7532 		REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);  in elink_update_link_down()
7538 		elink_set_bmac_rx(sc, params->chip_id, params->port, 0);  in elink_update_link_down()
7543 		       0);  in elink_update_link_down()
7545 		       0);  in elink_update_link_down()
7550 		elink_set_xmac_rxtx(params, 0);  in elink_update_link_down()
7551 		elink_set_umac_rxtx(params, 0);  in elink_update_link_down()
7578 			if (elink_xmac_enable(params, vars, 0) ==  in elink_update_link_up()
7581 				vars->link_up = 0;  in elink_update_link_up()
7586 			elink_umac_enable(params, vars, 0);  in elink_update_link_up()
7597 			       (params->port << 2), 0xfc20);  in elink_update_link_up()
7603 			if (elink_bmac_enable(params, vars, 0, 1) ==  in elink_update_link_up()
7606 				vars->link_up = 0;  in elink_update_link_up()
7615 			elink_emac_enable(params, vars, 0);  in elink_update_link_up()
7632 	REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);  in elink_update_link_up()
7640 			elink_check_half_open_conn(params, vars, 0);  in elink_update_link_up()
7660 		val = 0;  in elink_chng_link_count()
7685 	uint8_t ext_phy_link_up = 0, cur_link_up;  in elink_link_update()
7687 	uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;  in elink_link_update()
7693 		phy_vars[phy_index].flow_ctrl = 0;  in elink_link_update()
7694 		phy_vars[phy_index].link_status = 0;  in elink_link_update()
7695 		phy_vars[phy_index].line_speed = 0;  in elink_link_update()
7697 		phy_vars[phy_index].phy_link_up = 0;  in elink_link_update()
7698 		phy_vars[phy_index].link_up = 0;  in elink_link_update()
7699 		phy_vars[phy_index].fault_detected = 0;  in elink_link_update()
7707 	ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x\n",  in elink_link_update()
7711 	ELINK_DEBUG_P3(sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",  in elink_link_update()
7713 		 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18) > 0,  in elink_link_update()
7714 		 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));  in elink_link_update()
7717 	  REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),  in elink_link_update()
7718 	  REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));  in elink_link_update()
7722 		REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);  in elink_link_update()
7777 					   "mpc=0x%x. DISABLING LINK !!!\n",  in elink_link_update()
7779 				ext_phy_link_up = 0;  in elink_link_update()
7859 	ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"  in elink_link_update()
7874 			vars->phy_link_up = 0;  in elink_link_update()
7875 			ELINK_DEBUG_P0(sc, "phy_link_up set to 0\n");  in elink_link_update()
7878 			       0);  in elink_link_update()
7922 			 (phy_vars[active_external_phy].fault_detected == 0));  in elink_link_update()
7942 		elink_chng_link_count(params, 0);  in elink_link_update()
7946 		elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);  in elink_link_update()
7966 	ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d\n",  in elink_save_spirom_version()
8000 	if ((val & (1<<0)) == 0)  in elink_ext_phy_10G_an_resolve()
8036 		ELINK_DEBUG_P1(sc, "Ext PHY CL37 pause result 0x%x\n",  in elink_8073_resolve_fc()
8044 	uint32_t count = 0;  in elink_8073_8727_external_rom_boot()
8053 			 0x0001);  in elink_8073_8727_external_rom_boot()
8059 			 0x008c);  in elink_8073_8727_external_rom_boot()
8063 			 MDIO_PMA_REG_MISC_CTRL1, 0x0001);  in elink_8073_8727_external_rom_boot()
8086 				 "Download failed. fw version = 0x%x\n",  in elink_8073_8727_external_rom_boot()
8100 	} while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||  in elink_8073_8727_external_rom_boot()
8101 			((fw_msgout & 0xff) != 0x03 && (phy->type ==  in elink_8073_8727_external_rom_boot()
8107 			 MDIO_PMA_REG_MISC_CTRL1, 0x0000);  in elink_8073_8727_external_rom_boot()
8112 		 "Download complete. fw version = 0x%x\n",  in elink_8073_8727_external_rom_boot()
8140 	/* SNR should be applied only for version 0x102 */  in elink_8073_is_snr_needed()
8141 	if (val != 0x102)  in elink_8073_is_snr_needed()
8155 	if (val > 0) {  in elink_8073_xaui_wa()
8165 	for (cnt = 0; cnt < 1000; cnt++) {  in elink_8073_xaui_wa()
8170 		  /* If bit [14] = 0 or bit [13] = 0, continue on with  in elink_8073_xaui_wa()
8179 			/* If bit 15 is 0, then poll Dev1, Reg $C841 until it's  in elink_8073_xaui_wa()
8184 			for (cnt1 = 0; cnt1 < 1000; cnt1++) {  in elink_8073_xaui_wa()
8207 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);  in elink_807x_force_10G()
8209 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);  in elink_807x_force_10G()
8211 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);  in elink_807x_force_10G()
8213 			 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);  in elink_807x_force_10G()
8244 		 "Ext phy AN advertize cl37 0x%x\n", cl37_val);  in elink_8073_set_pause_cl37()
8262 				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);  in elink_8073_specific_func()
8272 	uint16_t val = 0, tmp1;  in elink_8073_config_init()
8296 	ELINK_DEBUG_P1(sc, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);  in elink_8073_config_init()
8333 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);  in elink_8073_config_init()
8346 		val = 0;  in elink_8073_config_init()
8356 		ELINK_DEBUG_P1(sc, "807x autoneg val = 0x%x\n", val);  in elink_8073_config_init()
8371 		if (phy_ver > 0)  in elink_8073_config_init()
8374 			tmp1 &= 0xfffe;  in elink_8073_config_init()
8377 		tmp1 &= 0xfffe;  in elink_8073_config_init()
8386 				  0x20 : 0x40)));  in elink_8073_config_init()
8389 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);  in elink_8073_config_init()
8398 				 0xFB0C);  in elink_8073_config_init()
8409 	elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);  in elink_8073_config_init()
8411 		   ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));  in elink_8073_config_init()
8420 	uint8_t link_up = 0;  in elink_8073_read_status()
8422 	uint16_t link_status = 0;  in elink_8073_read_status()
8423 	uint16_t an1000_status = 0;  in elink_8073_read_status()
8428 	ELINK_DEBUG_P1(sc, "8703 LASI status 0x%x\n", val1);  in elink_8073_read_status()
8435 	ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x\n", val2, val1);  in elink_8073_read_status()
8444 	ELINK_DEBUG_P1(sc, "KR 0x9003 0x%x\n", val2);  in elink_8073_read_status()
8449 	ELINK_DEBUG_P1(sc, "KR PCS status 0x%x\n", val2);  in elink_8073_read_status()
8456 	ELINK_DEBUG_P1(sc, "PMA_REG_STATUS=0x%x\n", val1);  in elink_8073_read_status()
8460 		if (elink_8073_xaui_wa(sc, phy) != 0)  in elink_8073_read_status()
8461 			return 0;  in elink_8073_read_status()
8473 	ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x,"  in elink_8073_read_status()
8474 		   "an_link_status=0x%x\n", val2, val1, an1000_status);  in elink_8073_read_status()
8484 				 0x26BC);  in elink_8073_read_status()
8489 				 0x0333);  in elink_8073_read_status()
8495 	/* Bits 0..2 --> speed detected, bits 13..15--> link is down */  in elink_8073_read_status()
8506 	} else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {  in elink_8073_read_status()
8512 		link_up = 0;  in elink_8073_read_status()
8590 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);  in elink_8705_config_init()
8594 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);  in elink_8705_config_init()
8596 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);  in elink_8705_config_init()
8598 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);  in elink_8705_config_init()
8600 			 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);  in elink_8705_config_init()
8601 	/* BCM8705 doesn't have microcode, hence the 0 */  in elink_8705_config_init()
8602 	elink_save_spirom_version(sc, params->port, params->shmem_base, 0);  in elink_8705_config_init()
8610 	uint8_t link_up = 0;  in elink_8705_read_status()
8616 	ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);  in elink_8705_read_status()
8620 	ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);  in elink_8705_read_status()
8626 		      MDIO_PMA_DEVAD, 0xc809, &val1);  in elink_8705_read_status()
8628 		      MDIO_PMA_DEVAD, 0xc809, &val1);  in elink_8705_read_status()
8630 	ELINK_DEBUG_P1(sc, "8705 1.c809 val=0x%x\n", val1);  in elink_8705_read_status()
8631 	link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));  in elink_8705_read_status()
8731 		ELINK_DEBUG_P1(sc, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);  in elink_sfp_e1e2_set_transmitter()
8754 	uint16_t val = 0;  in elink_8726_read_sfp_module_eeprom()
8758 		   "Reading from eeprom is limited to 0xf\n");  in elink_8726_read_sfp_module_eeprom()
8774 			 0x2c0f);  in elink_8726_read_sfp_module_eeprom()
8777 	for (i = 0; i < 100; i++) {  in elink_8726_read_sfp_module_eeprom()
8790 			 "Got bad status 0x%x when reading from SFP+ EEPROM\n",  in elink_8726_read_sfp_module_eeprom()
8796 	for (i = 0; i < byte_cnt; i++) {  in elink_8726_read_sfp_module_eeprom()
8803 	for (i = 0; i < 100; i++) {  in elink_8726_read_sfp_module_eeprom()
8843 	uint8_t i, j = 0, cnt = 0;  in elink_warpcore_read_sfp_module_eeprom()
8855 	addr32 = addr & (~0x3);  in elink_warpcore_read_sfp_module_eeprom()
8858 			elink_warpcore_power_module(params, 0);  in elink_warpcore_read_sfp_module_eeprom()
8865 		rc = elink_bsc_read(sc, dev_addr, addr32, 0, byte_cnt,  in elink_warpcore_read_sfp_module_eeprom()
8889 		   "Reading from eeprom is limited to 0xf\n");  in elink_8727_read_sfp_module_eeprom()
8922 			 0x8004,  in elink_8727_read_sfp_module_eeprom()
8929 			 0x8002);  in elink_8727_read_sfp_module_eeprom()
8936 	for (i = 0; i < 100; i++) {  in elink_8727_read_sfp_module_eeprom()
8949 			 "Got bad status 0x%x when reading from SFP+ EEPROM\n",  in elink_8727_read_sfp_module_eeprom()
8955 	for (i = 0; i < byte_cnt; i++) {  in elink_8727_read_sfp_module_eeprom()
8962 	for (i = 0; i < 100; i++) {  in elink_8727_read_sfp_module_eeprom()
8978 	elink_status_t rc = 0;  in elink_read_sfp_module_eeprom()
8983 	if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {  in elink_read_sfp_module_eeprom()
8984 		ELINK_DEBUG_P1(sc, "invalid dev_addr 0x%x\n", dev_addr);  in elink_read_sfp_module_eeprom()
9003 	while (!rc && (byte_cnt > 0)) {  in elink_read_sfp_module_eeprom()
9007 			       user_data, 0);  in elink_read_sfp_module_eeprom()
9020 	uint32_t sync_offset = 0, phy_idx, media_types;  in elink_get_edc_mode()
9021 	uint8_t val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0;  in elink_get_edc_mode()
9028 					 0,  in elink_get_edc_mode()
9030 					 (uint8_t *)val) != 0) {  in elink_get_edc_mode()
9081 		       ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&  in elink_get_edc_mode()
9082 		    (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {  in elink_get_edc_mode()
9103 				elink_sfp_set_transmitter(params, phy, 0);  in elink_get_edc_mode()
9108 			int idx, cfg_idx = 0;  in elink_get_edc_mode()
9121 		ELINK_DEBUG_P1(sc, "Unable to determine module type 0x%x !!!\n",  in elink_get_edc_mode()
9148 						 options) != 0) {  in elink_get_edc_mode()
9153 		if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))  in elink_get_edc_mode()
9158 	ELINK_DEBUG_P1(sc, "EDC mode is set to 0x%x\n", *edc_mode);  in elink_get_edc_mode()
9216 		vendor_name[0] = '\0';  in elink_verify_sfp_module()
9218 		vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';  in elink_verify_sfp_module()
9225 		vendor_pn[0] = '\0';  in elink_verify_sfp_module()
9227 		vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';  in elink_verify_sfp_module()
9250 	for (timeout = 0; timeout < 60; timeout++) {  in elink_wait_for_sfp_module_initialized()
9259 		if (rc == 0) {  in elink_wait_for_sfp_module_initialized()
9278 	 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for  in elink_8727_power_module()
9280 	 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0  in elink_8727_power_module()
9314 	ELINK_DEBUG_P1(sc, "Current Limiting mode is 0x%x\n",  in elink_8726_set_limiting_mode()
9336 				 0);  in elink_8726_set_limiting_mode()
9340 				 0x128);  in elink_8726_set_limiting_mode()
9344 				 0x4008);  in elink_8726_set_limiting_mode()
9348 				 0xaaaa);  in elink_8726_set_limiting_mode()
9377 			 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));  in elink_8727_set_limiting_mode()
9395 		elink_sfp_set_transmitter(params, phy, 0);  in elink_8727_specific_func()
9407 				 0);  in elink_8727_specific_func()
9409 				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);  in elink_8727_specific_func()
9421 			val &= 0xff8f; /* Reset bits 4-6 */  in elink_8727_specific_func()
9427 		ELINK_DEBUG_P1(sc, "Function 0x%x not supported by 8727\n",  in elink_8727_specific_func()
9460 		ELINK_DEBUG_P1(sc, "Error: Invalid fault led mode 0x%x\n",  in elink_set_e1e2_module_fault_led()
9499 	elink_warpcore_power_module(params, 0);  in elink_warpcore_hw_reset()
9501 	REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);  in elink_warpcore_hw_reset()
9505 	REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);  in elink_warpcore_hw_reset()
9506 	REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);  in elink_warpcore_hw_reset()
9532 	uint16_t val = 0;  in elink_warpcore_set_limiting_mode()
9540 	val &= ~(0xf << (lane << 2));  in elink_warpcore_set_limiting_mode()
9564 	elink_warpcore_reset_lane(sc, phy, 0);  in elink_warpcore_set_limiting_mode()
9602 	if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {  in elink_sfp_module_detection()
9605 	} else if (elink_verify_sfp_module(phy, params) != 0) {  in elink_sfp_module_detection()
9617 			elink_power_sfp_module(params, phy, 0);  in elink_sfp_module_detection()
9633 	if ((rc != 0) &&  in elink_sfp_module_detection()
9636 		elink_sfp_set_transmitter(params, phy, 0);  in elink_sfp_module_detection()
9668 	if (gpio_val == 0) {  in elink_handle_module_detect_int()
9676 		if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {  in elink_handle_module_detect_int()
9693 					elink_warpcore_reset_lane(sc, phy, 0);  in elink_handle_module_detect_int()
9727 	if (alarm_status & (1<<0))  in elink_sfp_mask_fault()
9728 		val &= ~(1<<0);  in elink_sfp_mask_fault()
9730 		val |= (1<<0);  in elink_sfp_mask_fault()
9740 	uint8_t link_up = 0;  in elink_8706_8726_read_status()
9756 	ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);  in elink_8706_8726_read_status()
9767 	ELINK_DEBUG_P3(sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"  in elink_8706_8726_read_status()
9768 			" link_status 0x%x\n", rx_sd, pcs_status, val2);  in elink_8706_8726_read_status()
9769 	/* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status  in elink_8706_8726_read_status()
9772 	link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));  in elink_8706_8726_read_status()
9788 		if (val1 & (1<<0))  in elink_8706_8726_read_status()
9810 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);  in elink_8706_config_init()
9814 	for (cnt = 0; cnt < 100; cnt++) {  in elink_8706_config_init()
9826 		for (i = 0; i < 4; i++) {  in elink_8706_config_init()
9832 			val &= ~0x7;  in elink_8706_config_init()
9834 			val |= (phy->rx_preemphasis[i] & 0x7);  in elink_8706_config_init()
9836 				   " reg 0x%x <-- val 0x%x\n", reg, val);  in elink_8706_config_init()
9846 				 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);  in elink_8706_config_init()
9849 				 0);  in elink_8706_config_init()
9859 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);  in elink_8706_config_init()
9863 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);  in elink_8706_config_init()
9866 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);  in elink_8706_config_init()
9873 				 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);  in elink_8706_config_init()
9876 				 0x0400);  in elink_8706_config_init()
9879 				 0x0004);  in elink_8706_config_init()
9896 		tmp1 |= 0x1;  in elink_8706_config_init()
9919 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);  in elink_8726_config_loopback()
9931 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);  in elink_8726_external_rom_boot()
9941 			 MDIO_PMA_REG_MISC_CTRL1, 0x0001);  in elink_8726_external_rom_boot()
9954 			 MDIO_PMA_REG_MISC_CTRL1, 0x0000);  in elink_8726_external_rom_boot()
9973 			link_up = 0;  in elink_8726_read_status()
9974 			vars->line_speed = 0;  in elink_8726_read_status()
10003 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);  in elink_8726_config_init()
10005 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);  in elink_8726_config_init()
10007 				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);  in elink_8726_config_init()
10010 				 0x400);  in elink_8726_config_init()
10021 				 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);  in elink_8726_config_init()
10023 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);  in elink_8726_config_init()
10025 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);  in elink_8726_config_init()
10027 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);  in elink_8726_config_init()
10029 				MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);  in elink_8726_config_init()
10034 				 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);  in elink_8726_config_init()
10037 				 0x400);  in elink_8726_config_init()
10048 		   "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",  in elink_8726_config_init()
10049 			 phy->tx_preemphasis[0],  in elink_8726_config_init()
10054 				 phy->tx_preemphasis[0]);  in elink_8726_config_init()
10074 			 MDIO_PMA_REG_GEN_CTRL, 0x0001);  in elink_8726_link_reset()
10085 	uint16_t led_mode_bitmask = 0;  in elink_8727_set_link_led()
10086 	uint16_t gpio_pins_bitmask = 0;  in elink_8727_set_link_led()
10094 		led_mode_bitmask = 0;  in elink_8727_set_link_led()
10095 		gpio_pins_bitmask = 0x03;  in elink_8727_set_link_led()
10098 		led_mode_bitmask = 0;  in elink_8727_set_link_led()
10099 		gpio_pins_bitmask = 0x02;  in elink_8727_set_link_led()
10102 		led_mode_bitmask = 0x60;  in elink_8727_set_link_led()
10103 		gpio_pins_bitmask = 0x11;  in elink_8727_set_link_led()
10110 	val &= 0xff8f;  in elink_8727_set_link_led()
10120 	val &= 0xffe0;  in elink_8727_set_link_led()
10152 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);  in elink_8727_config_speed()
10154 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);  in elink_8727_config_speed()
10157 		ELINK_DEBUG_P1(sc, "1.7 = 0x%x\n", tmp1);  in elink_8727_config_speed()
10179 				 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);  in elink_8727_config_speed()
10181 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);  in elink_8727_config_speed()
10188 				 0x0020);  in elink_8727_config_speed()
10190 				 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);  in elink_8727_config_speed()
10192 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);  in elink_8727_config_speed()
10195 				 0x0008);  in elink_8727_config_speed()
10229 	elink_set_disable_pmd_transmit(params, phy, 0);  in elink_8727_config_init()
10245 		ELINK_DEBUG_P2(sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",  in elink_8727_config_init()
10246 			   phy->tx_preemphasis[0],  in elink_8727_config_init()
10250 				 phy->tx_preemphasis[0]);  in elink_8727_config_init()
10270 		tmp2 |= 0x1000;  in elink_8727_config_init()
10271 		tmp2 &= 0xFFEF;  in elink_8727_config_init()
10279 				 (tmp2 & 0x7fff));  in elink_8727_config_init()
10354 			elink_sfp_set_transmitter(params, phy, 0);  in elink_8727_handle_mod_abs()
10356 		if (elink_wait_for_sfp_module_initialized(phy, params) == 0)  in elink_8727_handle_mod_abs()
10365 	ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n",  in elink_8727_handle_mod_abs()
10376 	uint8_t link_up = 0;  in elink_8727_read_status()
10377 	uint16_t link_status = 0;  in elink_8727_read_status()
10385 		return 0;  in elink_8727_read_status()
10391 	vars->line_speed = 0;  in elink_8727_read_status()
10392 	ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);  in elink_8727_read_status()
10400 	ELINK_DEBUG_P1(sc, "8727 LASI status 0x%x\n", val1);  in elink_8727_read_status()
10415 		if ((val1 & (1<<8)) == 0) {  in elink_8727_read_status()
10446 			elink_8727_power_module(params->sc, phy, 0);  in elink_8727_read_status()
10447 			return 0;  in elink_8727_read_status()
10465 		return 0;  in elink_8727_read_status()
10472 	/* Bits 0..2 --> speed detected,  in elink_8727_read_status()
10480 	} else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {  in elink_8727_read_status()
10486 		link_up = 0;  in elink_8727_read_status()
10499 		if (val1 & (1<<0)) {  in elink_8727_read_status()
10507 		ELINK_DEBUG_P1(sc, "duplex = 0x%x\n", vars->duplex);  in elink_8727_read_status()
10538 	elink_sfp_set_transmitter(params, phy, 0);  in elink_8727_link_reset()
10540 	elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);  in elink_8727_link_reset()
10560 		{MDIO_PMA_DEVAD, 0xA819, 0x0014},  in elink_save_848xx_spirom_version()
10561 		{MDIO_PMA_DEVAD, 0xA81A, 0xc200},  in elink_save_848xx_spirom_version()
10562 		{MDIO_PMA_DEVAD, 0xA81B, 0x0000},  in elink_save_848xx_spirom_version()
10563 		{MDIO_PMA_DEVAD, 0xA81C, 0x0300},  in elink_save_848xx_spirom_version()
10564 		{MDIO_PMA_DEVAD, 0xA817, 0x0009}  in elink_save_848xx_spirom_version()
10569 		elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);  in elink_save_848xx_spirom_version()
10570 		elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,  in elink_save_848xx_spirom_version()
10574 		/* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */  in elink_save_848xx_spirom_version()
10575 		for (i = 0; i < ARRAY_SIZE(reg_set); i++)  in elink_save_848xx_spirom_version()
10579 		for (cnt = 0; cnt < 100; cnt++) {  in elink_save_848xx_spirom_version()
10580 			elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);  in elink_save_848xx_spirom_version()
10588 			elink_save_spirom_version(sc, port, 0,  in elink_save_848xx_spirom_version()
10594 		/* 2) read register 0xc200_0000 (SPI_FW_STATUS) */  in elink_save_848xx_spirom_version()
10595 		elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);  in elink_save_848xx_spirom_version()
10596 		elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);  in elink_save_848xx_spirom_version()
10597 		elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);  in elink_save_848xx_spirom_version()
10598 		for (cnt = 0; cnt < 100; cnt++) {  in elink_save_848xx_spirom_version()
10599 			elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);  in elink_save_848xx_spirom_version()
10607 			elink_save_spirom_version(sc, port, 0,  in elink_save_848xx_spirom_version()
10613 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);  in elink_save_848xx_spirom_version()
10615 		elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);  in elink_save_848xx_spirom_version()
10627 		{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},  in elink_848xx_set_led()
10628 		{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},  in elink_848xx_set_led()
10629 		{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},  in elink_848xx_set_led()
10630 		{MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},  in elink_848xx_set_led()
10633 		{MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}  in elink_848xx_set_led()
10639 	val &= 0xFE00;  in elink_848xx_set_led()
10640 	val |= 0x0092;  in elink_848xx_set_led()
10646 	for (i = 0; i < ARRAY_SIZE(reg_set); i++)  in elink_848xx_set_led()
10693 			 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);  in elink_848xx_cmn_config_init()
10774 				 (1<<15 | 1<<9 | 7<<0));  in elink_848xx_cmn_config_init()
10786 				 (1<<15 | 1<<9 | 7<<0));  in elink_848xx_cmn_config_init()
10801 	    ((autoneg_val & (1<<12)) == 0))  in elink_848xx_cmn_config_init()
10817 				0x1000);  in elink_848xx_cmn_config_init()
10820 					 0x3200);  in elink_848xx_cmn_config_init()
10866 	for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {  in elink_84858_cmd_hdlr()
10883 	for (idx = 0; idx < argc; idx++) {  in elink_84858_cmd_hdlr()
10900 	for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {  in elink_84858_cmd_hdlr()
10918 	for (idx = 0; idx < argc; idx++) {  in elink_84858_cmd_hdlr()
10943 	for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {  in elink_84833_cmd_hdlr()
10966 	for (idx = 0; idx < argc; idx++) {  in elink_84833_cmd_hdlr()
10976 	for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {  in elink_84833_cmd_hdlr()
10991 	for (idx = 0; idx < argc; idx++) {  in elink_84833_cmd_hdlr()
11041 	if (pair_swap == 0)  in elink_848xx_pair_swap_cfg()
11051 		ELINK_DEBUG_P1(sc, "Pairswap OK, val=0x%x\n", data[1]);  in elink_848xx_pair_swap_cfg()
11065 		for (idx = 0; idx < 2; idx++) {  in elink_84833_get_reset_gpios()
11069 				dev_info.port_hw_config[0].e3_cmn_pin_cfg));  in elink_84833_get_reset_gpios()
11076 		reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);  in elink_84833_get_reset_gpios()
11079 		for (idx = 0; idx < 2; idx++) {  in elink_84833_get_reset_gpios()
11082 				dev_info.port_hw_config[0].default_cfg));  in elink_84833_get_reset_gpios()
11088 		reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);  in elink_84833_get_reset_gpios()
11113 	shmem_base_path[0] = params->shmem_base;  in elink_84833_hw_reset_phy()
11121 	ELINK_DEBUG_P1(sc, "84833 hw reset on pin values 0x%x\n",  in elink_84833_hw_reset_phy()
11133 	uint16_t cmd_args = 0;  in elink_8483x_disable_eee()
11193 				MDIO_PMA_REG_CTRL, 0x8000);  in elink_848x3_config_init()
11207 		elink_set_autoneg(&params->phy[ELINK_INT_PHY], params, vars, 0);  in elink_848x3_config_init()
11257 		initialize = 0;  in elink_848x3_config_init()
11265 	ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x\n",  in elink_848x3_config_init()
11272 		cmd_args[0] = 0x0;  in elink_848x3_config_init()
11273 		cmd_args[1] = 0x0;  in elink_848x3_config_init()
11348 	uint8_t link_up = 0;  in elink_848xx_read_status()
11354 			MDIO_AN_DEVAD, 0xFFFA, &val1);  in elink_848xx_read_status()
11358 	ELINK_DEBUG_P1(sc, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);  in elink_848xx_read_status()
11369 		/* Enable expansion register 0x42 (Operation mode status) */  in elink_848xx_read_status()
11372 				 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);  in elink_848xx_read_status()
11380 		ELINK_DEBUG_P1(sc, "Legacy speed status = 0x%x\n",  in elink_848xx_read_status()
11384 		if (legacy_speed == (0<<9))  in elink_848xx_read_status()
11391 			vars->line_speed = 0;  in elink_848xx_read_status()
11392 			link_up = 0;  in elink_848xx_read_status()
11404 			link_up |= ((mii_ctrl & 0x3040) == 0x40);  in elink_848xx_read_status()
11429 			if ((val & (1<<0)) == 0)  in elink_848xx_read_status()
11487 	spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);  in elink_848xx_format_ver()
11496 		       MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);  in elink_8481_hw_reset()
11505 			 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);  in elink_8481_link_reset()
11551 		ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF\n", port);  in elink_848xx_set_link_led()
11560 					0x0);  in elink_848xx_set_link_led()
11565 					0x0);  in elink_848xx_set_link_led()
11570 					0x0);  in elink_848xx_set_link_led()
11575 					0x0);  in elink_848xx_set_link_led()
11581 					 0x0);  in elink_848xx_set_link_led()
11586 		ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE FRONT PANEL OFF\n",  in elink_848xx_set_link_led()
11596 					 0x0);  in elink_848xx_set_link_led()
11601 					 0x0);  in elink_848xx_set_link_led()
11606 					 0x0);  in elink_848xx_set_link_led()
11611 					 0x20);  in elink_848xx_set_link_led()
11617 					 0x0);  in elink_848xx_set_link_led()
11638 						 0x0);  in elink_848xx_set_link_led()
11644 		ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON\n", port);  in elink_848xx_set_link_led()
11653 			val &= 0x8000;  in elink_848xx_set_link_led()
11654 			val |= 0x2492;  in elink_848xx_set_link_led()
11665 					 0x0);  in elink_848xx_set_link_led()
11670 					 0x20);  in elink_848xx_set_link_led()
11675 					 0x20);  in elink_848xx_set_link_led()
11680 					 0x0);  in elink_848xx_set_link_led()
11685 					 0x20);  in elink_848xx_set_link_led()
11706 						 0x20);  in elink_848xx_set_link_led()
11713 		ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER\n", port);  in elink_848xx_set_link_led()
11731 						 0xa492);  in elink_848xx_set_link_led()
11738 					 0x10);  in elink_848xx_set_link_led()
11743 					 0x80);  in elink_848xx_set_link_led()
11748 					 0x98);  in elink_848xx_set_link_led()
11753 					 0x40);  in elink_848xx_set_link_led()
11762 			       SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;  in elink_848xx_set_link_led()
11788 						 0x40);  in elink_848xx_set_link_led()
11820 		/* Configure LED4: set to INTR (0x6). */  in elink_54618se_specific_func()
11821 		/* Accessing shadow register 0xe. */  in elink_54618se_specific_func()
11828 		temp &= ~(0xf << 4);  in elink_54618se_specific_func()
11829 		temp |= (0x6 << 4);  in elink_54618se_specific_func()
11872 			 MDIO_PMA_REG_CTRL, 0x8000);  in elink_54618se_config_init()
11880 	/* Flip the signal detect polarity (set 0x1c.0x1e[8]). */  in elink_54618se_config_init()
11895 	fc_val = 0;  in elink_54618se_config_init()
11906 			0x09,  in elink_54618se_config_init()
11910 			0x04,  in elink_54618se_config_init()
11935 			0x09,  in elink_54618se_config_init()
11938 			0x09,  in elink_54618se_config_init()
11974 				0x18,  in elink_54618se_config_init()
11975 				(1<<15 | 1<<9 | 7<<0));  in elink_54618se_config_init()
11981 				0x18,  in elink_54618se_config_init()
11982 				(1<<15 | 1<<9 | 7<<0));  in elink_54618se_config_init()
11993 		temp &= 0xfffe;  in elink_54618se_config_init()
12026 				temp = 0;  in elink_54618se_config_init()
12035 			0x04,  in elink_54618se_config_init()
12060 	temp &= 0xff00;  in elink_5461x_set_link_led()
12066 		temp |= 0x00ee;  in elink_5461x_set_link_led()
12069 		temp |= 0x0001;  in elink_5461x_set_link_led()
12072 		temp |= 0x00ff;  in elink_5461x_set_link_led()
12094 	elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);  in elink_54618se_link_reset()
12106 	elink_set_cfg_pin(sc, cfg_pin, 0);  in elink_54618se_link_reset()
12115 	uint8_t link_up = 0;  in elink_54618se_read_status()
12122 	ELINK_DEBUG_P1(sc, "54618SE read_status: 0x%x\n", legacy_status);  in elink_54618se_read_status()
12154 			vars->line_speed = 0;  in elink_54618se_read_status()
12163 				0x01,  in elink_54618se_read_status()
12169 				0x06,  in elink_54618se_read_status()
12171 		if ((val & (1<<0)) == 0)  in elink_54618se_read_status()
12182 			elink_cl22_read(sc, phy, 0x5, &val);  in elink_54618se_read_status()
12200 			elink_cl22_read(sc, phy, 0xa, &val);  in elink_54618se_read_status()
12227 	elink_cl22_write(sc, phy, 0x09, 3<<11);  in elink_54618se_config_loopback()
12230 	/* set val [mii read 0] */  in elink_54618se_config_loopback()
12233 	/* mii write 0 $val */  in elink_54618se_config_loopback()
12234 	elink_cl22_read(sc, phy, 0x00, &val);  in elink_54618se_config_loopback()
12237 	elink_cl22_write(sc, phy, 0x00, val);  in elink_54618se_config_loopback()
12240 	/* mii write 0x18 7 */  in elink_54618se_config_loopback()
12241 	/* set val [mii read 0x18] */  in elink_54618se_config_loopback()
12242 	/* mii write 0x18 [expr $val | [bits set 10 15]] */  in elink_54618se_config_loopback()
12243 	elink_cl22_write(sc, phy, 0x18, 7);  in elink_54618se_config_loopback()
12244 	elink_cl22_read(sc, phy, 0x18, &val);  in elink_54618se_config_loopback()
12245 	elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15));  in elink_54618se_config_loopback()
12253 	REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);  in elink_54618se_config_loopback()
12265 			 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);  in elink_7101_config_loopback()
12284 			 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);  in elink_7101_config_init()
12293 	val |= 0x200;  in elink_7101_config_init()
12319 	ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x\n",  in elink_7101_read_status()
12325 	ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x\n",  in elink_7101_read_status()
12335 		ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x\n",  in elink_7101_read_status()
12352 	str[0] = (spirom_ver & 0xFF);  in elink_7101_format_ver()
12353 	str[1] = (spirom_ver & 0xFF00) >> 8;  in elink_7101_format_ver()
12354 	str[2] = (spirom_ver & 0xFF0000) >> 16;  in elink_7101_format_ver()
12355 	str[3] = (spirom_ver & 0xFF000000) >> 24;  in elink_7101_format_ver()
12356 	str[4] = '\0';  in elink_7101_format_ver()
12369 	for (cnt = 0; cnt < 10; cnt++) {  in elink_sfx7101_sp_sw_reset()
12381 		if ((val & (1<<15)) == 0)  in elink_sfx7101_sp_sw_reset()
12399 	uint16_t val = 0;  in elink_7101_set_link_led()
12410 		val = 0;  in elink_7101_set_link_led()
12425 	.addr		= 0,
12426 	.def_md_devad	= 0,
12428 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12429 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12430 	.mdio_ctrl	= 0,
12431 	.supported	= 0,
12433 	.ver_addr	= 0,
12434 	.req_flow_ctrl	= 0,
12435 	.req_line_speed	= 0,
12436 	.speed_cap_mask	= 0,
12437 	.req_duplex	= 0,
12438 	.rsrv		= 0,
12451 	.addr		= 0xff,
12452 	.def_md_devad	= 0,
12453 	.flags		= 0,
12454 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12455 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12456 	.mdio_ctrl	= 0,
12468 	.ver_addr	= 0,
12469 	.req_flow_ctrl	= 0,
12470 	.req_line_speed	= 0,
12471 	.speed_cap_mask	= 0,
12472 	.req_duplex	= 0,
12473 	.rsrv		= 0,
12486 	.addr		= 0xff,
12487 	.def_md_devad	= 0,
12488 	.flags		= 0,
12489 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12490 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12491 	.mdio_ctrl	= 0,
12504 	.ver_addr	= 0,
12505 	.req_flow_ctrl	= 0,
12506 	.req_line_speed	= 0,
12507 	.speed_cap_mask	= 0,
12508 	.req_duplex	= 0,
12509 	.rsrv		= 0,
12521 	.addr		= 0xff,
12522 	.def_md_devad	= 0,
12524 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12525 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12526 	.mdio_ctrl	= 0,
12542 	.ver_addr	= 0,
12543 	.req_flow_ctrl	= 0,
12544 	.req_line_speed	= 0,
12545 	.speed_cap_mask	= 0,
12546 	/* req_duplex = */0,
12547 	/* rsrv = */0,
12561 	.addr		= 0xff,
12562 	.def_md_devad	= 0,
12564 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12565 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12566 	.mdio_ctrl	= 0,
12573 	.ver_addr	= 0,
12574 	.req_flow_ctrl	= 0,
12575 	.req_line_speed	= 0,
12576 	.speed_cap_mask	= 0,
12577 	.req_duplex	= 0,
12578 	.rsrv		= 0,
12590 	.addr		= 0xff,
12591 	.def_md_devad	= 0,
12592 	.flags		= 0,
12593 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12594 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12595 	.mdio_ctrl	= 0,
12604 	.ver_addr	= 0,
12605 	.req_flow_ctrl	= 0,
12606 	.req_line_speed	= 0,
12607 	.speed_cap_mask	= 0,
12608 	.req_duplex	= 0,
12609 	.rsrv		= 0,
12621 	.addr		= 0xff,
12622 	.def_md_devad	= 0,
12624 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12625 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12626 	.mdio_ctrl	= 0,
12632 	.ver_addr	= 0,
12633 	.req_flow_ctrl	= 0,
12634 	.req_line_speed	= 0,
12635 	.speed_cap_mask	= 0,
12636 	.req_duplex	= 0,
12637 	.rsrv		= 0,
12649 	.addr		= 0xff,
12650 	.def_md_devad	= 0,
12652 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12653 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12654 	.mdio_ctrl	= 0,
12661 	.ver_addr	= 0,
12662 	.req_flow_ctrl	= 0,
12663 	.req_line_speed	= 0,
12664 	.speed_cap_mask	= 0,
12665 	.req_duplex	= 0,
12666 	.rsrv		= 0,
12679 	.addr		= 0xff,
12680 	.def_md_devad	= 0,
12683 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12684 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12685 	.mdio_ctrl	= 0,
12693 	.ver_addr	= 0,
12694 	.req_flow_ctrl	= 0,
12695 	.req_line_speed	= 0,
12696 	.speed_cap_mask	= 0,
12697 	.req_duplex	= 0,
12698 	.rsrv		= 0,
12711 	.addr		= 0xff,
12712 	.def_md_devad	= 0,
12715 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12716 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12717 	.mdio_ctrl	= 0,
12724 	.ver_addr	= 0,
12725 	.req_flow_ctrl	= 0,
12726 	.req_line_speed	= 0,
12727 	.speed_cap_mask	= 0,
12728 	.req_duplex	= 0,
12729 	.rsrv		= 0,
12741 	.addr		= 0xff,
12742 	.def_md_devad	= 0,
12745 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12746 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12747 	.mdio_ctrl	= 0,
12759 	.ver_addr	= 0,
12760 	.req_flow_ctrl	= 0,
12761 	.req_line_speed	= 0,
12762 	.speed_cap_mask	= 0,
12763 	.req_duplex	= 0,
12764 	.rsrv		= 0,
12777 	.addr		= 0xff,
12778 	.def_md_devad	= 0,
12782 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12783 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12784 	.mdio_ctrl	= 0,
12796 	.ver_addr	= 0,
12797 	.req_flow_ctrl	= 0,
12798 	.req_line_speed	= 0,
12799 	.speed_cap_mask	= 0,
12800 	.req_duplex	= 0,
12801 	.rsrv		= 0,
12814 	.addr		= 0xff,
12815 	.def_md_devad	= 0,
12820 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12821 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12822 	.mdio_ctrl	= 0,
12832 	.ver_addr	= 0,
12833 	.req_flow_ctrl	= 0,
12834 	.req_line_speed	= 0,
12835 	.speed_cap_mask	= 0,
12836 	.req_duplex	= 0,
12837 	.rsrv		= 0,
12850 	.addr		= 0xff,
12851 	.def_md_devad	= 0,
12854 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12855 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12856 	.mdio_ctrl	= 0,
12866 	.ver_addr	= 0,
12867 	.req_flow_ctrl	= 0,
12868 	.req_line_speed	= 0,
12869 	.speed_cap_mask	= 0,
12870 	.req_duplex	= 0,
12871 	.rsrv		= 0,
12884 	.addr		= 0xff,
12885 	.def_md_devad	= 0,
12888 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12889 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12890 	.mdio_ctrl	= 0,
12900 	.ver_addr	= 0,
12901 	.req_flow_ctrl	= 0,
12902 	.req_line_speed	= 0,
12903 	.speed_cap_mask	= 0,
12904 	.req_duplex	= 0,
12905 	.rsrv		= 0,
12919 	.addr		= 0xff,
12920 	.def_md_devad	= 0,
12922 	.rx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12923 	.tx_preemphasis	= {0xffff, 0xffff, 0xffff, 0xffff},
12924 	.mdio_ctrl	= 0,
12935 	.ver_addr	= 0,
12936 	.req_flow_ctrl	= 0,
12937 	.req_line_speed	= 0,
12938 	.speed_cap_mask	= 0,
12939 	/* req_duplex = */0,
12940 	/* rsrv = */0,
12961 	uint32_t rx = 0, tx = 0, i;  in elink_populate_preemphasis()
12962 	for (i = 0; i < 2; i++) {  in elink_populate_preemphasis()
12985 		phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);  in elink_populate_preemphasis()
12986 		phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);  in elink_populate_preemphasis()
12988 		phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);  in elink_populate_preemphasis()
12989 		phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);  in elink_populate_preemphasis()
12998 	uint32_t ext_phy_config = 0;  in elink_get_ext_phy_config()
13027 		((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);  in elink_populate_int_phy()
13029 	ELINK_DEBUG_P1(sc, ":chip_id = 0x%x\n", chip_id);  in elink_populate_int_phy()
13035 		if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)  in elink_populate_int_phy()
13106 			ELINK_DEBUG_P1(sc, "Unknown WC interface type 0x%x\n",  in elink_populate_int_phy()
13127 					  port * 0x10);  in elink_populate_int_phy()
13133 					  port * 0x18);  in elink_populate_int_phy()
13150 	ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",  in elink_populate_int_phy()
13272 		if (((raw_ver & 0x7F) <= 39) &&  in elink_populate_ext_phy()
13273 		    (((raw_ver & 0xF80) >> 7) <= 1))  in elink_populate_ext_phy()
13278 	ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d\n",  in elink_populate_ext_phy()
13280 	ELINK_DEBUG_P2(sc, "             addr=0x%x, mdio_ctl=0x%x\n",  in elink_populate_ext_phy()
13322 	   "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",  in elink_phy_def_cfg()
13413 	params->num_phys = 0;  in elink_phy_probe()
13438 			params->num_phys = 0;  in elink_phy_probe()
13469 				     actual_phy_idx))) == 0) {  in elink_phy_probe()
13490 	vars->line_speed = params->req_line_speed[0];  in elink_init_e3_emul_mac()
13492 	if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {  in elink_init_e3_emul_mac()
13505 				   " disabled!\n", params->req_line_speed[0]);  in elink_init_e3_emul_mac()
13531 			elink_umac_enable(params, vars, 0);  in elink_init_e3_emul_mac()
13537 				   " disabled!\n", params->req_line_speed[0]);  in elink_init_e3_emul_mac()
13557 			elink_xmac_enable(params, vars, 0);  in elink_init_e3_emul_mac()
13580 				elink_emac_enable(params, vars, 0);  in elink_init_emul()
13589 				elink_bmac_enable(params, vars, 0, 1);  in elink_init_emul()
13600 		REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in elink_init_emul()
13622 		vars->line_speed = params->req_line_speed[0];  in elink_init_fpga()
13640 				   params->req_line_speed[0]);  in elink_init_fpga()
13647 			elink_umac_enable(params, vars, 0);  in elink_init_fpga()
13654 			elink_emac_enable(params, vars, 0);  in elink_init_fpga()
13662 	REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in elink_init_fpga()
13686 		REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in elink_init_bmac_loopback()
13705 		REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in elink_init_emac_loopback()
13713 	if (!params->req_line_speed[0])  in elink_init_xmac_loopback()
13716 		vars->line_speed = params->req_line_speed[0];  in elink_init_xmac_loopback()
13724 	elink_set_aer_mmd(params, &params->phy[0]);  in elink_init_xmac_loopback()
13725 	elink_warpcore_reset_lane(sc, &params->phy[0], 0);  in elink_init_xmac_loopback()
13731 	REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in elink_init_xmac_loopback()
13746 	REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in elink_init_umac_loopback()
13757 	if (params->req_line_speed[0] == ELINK_SPEED_1000)  in elink_init_xgxs_loopback()
13759 	else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||  in elink_init_xgxs_loopback()
13769 	if (params->req_line_speed[0] == ELINK_SPEED_1000) {  in elink_init_xgxs_loopback()
13771 			elink_umac_enable(params, vars, 0);  in elink_init_xgxs_loopback()
13774 			elink_emac_enable(params, vars, 0);  in elink_init_xgxs_loopback()
13778 			elink_xmac_enable(params, vars, 0);  in elink_init_xgxs_loopback()
13780 			elink_bmac_enable(params, vars, 0, 1);  in elink_init_xgxs_loopback()
13796 	REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in elink_init_xgxs_loopback()
13804 	uint8_t val = en * 0x1F;  in elink_set_rx_filter()
13808 		val |= en * 0x20;  in elink_set_rx_filter()
13813 		       en*0x3);  in elink_set_rx_filter()
13865 			elink_umac_enable(params, vars, 0);  in elink_avoid_link_flap()
13867 			elink_xmac_enable(params, vars, 0);  in elink_avoid_link_flap()
13870 			elink_emac_enable(params, vars, 0);  in elink_avoid_link_flap()
13872 			elink_bmac_enable(params, vars, 0, !dont_clear_stat);  in elink_avoid_link_flap()
13878 		       LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)  in elink_avoid_link_flap()
13887 	REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in elink_avoid_link_flap()
13908 	       params->req_duplex[0] | (params->req_duplex[1] << 16));  in elink_cannot_avoid_link_flap()
13912 	       params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));  in elink_cannot_avoid_link_flap()
13916 	       params->req_line_speed[0] | (params->req_line_speed[1] << 16));  in elink_cannot_avoid_link_flap()
13918 	for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {  in elink_cannot_avoid_link_flap()
13947 		       LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)  in elink_cannot_avoid_link_flap()
13960 		   params->req_line_speed[0], params->req_flow_ctrl[0]);  in elink_phy_init()
13963 	ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);  in elink_phy_init()
13964 	vars->link_status = 0;  in elink_phy_init()
13965 	vars->phy_link_up = 0;  in elink_phy_init()
13966 	vars->link_up = 0;  in elink_phy_init()
13967 	vars->line_speed = 0;  in elink_phy_init()
13971 	vars->phy_flags = 0;  in elink_phy_init()
13972 	vars->check_kr2_recovery_cnt = 0;  in elink_phy_init()
13981                         params->port, params->loopback_mode, params->req_duplex[0]);  in elink_phy_init()
13992 	if (lfa_status == 0) {  in elink_phy_init()
13997 	ELINK_DEBUG_P1(sc, "Cannot avoid link flap lfa_sta=0x%x\n",  in elink_phy_init()
14017 	if ((params->num_phys == 0) &&  in elink_phy_init()
14074 	uint8_t phy_index, port = params->port, clear_latch_ind = 0;  in elink_link_reset()
14077 	vars->link_status = 0;  in elink_link_reset()
14094 		REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0);  in elink_link_reset()
14095 		REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);  in elink_link_reset()
14104 			elink_set_bmac_rx(sc, params->chip_id, port, 0);  in elink_link_reset()
14112 			elink_set_xmac_rxtx(params, 0);  in elink_link_reset()
14113 			elink_set_umac_rxtx(params, 0);  in elink_link_reset()
14117 		REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);  in elink_link_reset()
14125 	elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);  in elink_link_reset()
14145 		elink_rearm_latch_signal(sc, port, 0);  in elink_link_reset()
14161 		REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0);  in elink_link_reset()
14162 		REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0);  in elink_link_reset()
14165 		elink_set_xumac_nig(params, 0, 0);  in elink_link_reset()
14171 	vars->link_up = 0;  in elink_link_reset()
14172 	vars->phy_flags = 0;  in elink_link_reset()
14179 	vars->link_up = 0;  in elink_lfa_reset()
14180 	vars->phy_flags = 0;  in elink_lfa_reset()
14195 		elink_set_bmac_rx(sc, params->chip_id, params->port, 0);  in elink_lfa_reset()
14198 		elink_set_xmac_rxtx(params, 0);  in elink_lfa_reset()
14199 		elink_set_umac_rxtx(params, 0);  in elink_lfa_reset()
14207 	elink_set_rx_filter(params, 0);  in elink_lfa_reset()
14223 	REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in elink_lfa_reset()
14238 	int8_t port = 0;  in elink_8073_common_init_phy()
14239 	int8_t port_of_path = 0;  in elink_8073_common_init_phy()
14250 			shmem_base = shmem_base_path[0];  in elink_8073_common_init_phy()
14251 			shmem2_base = shmem2_base_path[0];  in elink_8073_common_init_phy()
14256 			port_of_path = 0;  in elink_8073_common_init_phy()
14291 	if (phy[PORT_0].addr & 0x1) {  in elink_8073_common_init_phy()
14304 			port_of_path = 0;  in elink_8073_common_init_phy()
14306 		ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",  in elink_8073_common_init_phy()
14371 	elink_ext_phy_hw_reset(sc, 0);  in elink_8726_common_init_phy()
14373 	for (port = 0; port < PORT_MAX; port++) {  in elink_8726_common_init_phy()
14378 			shmem_base = shmem_base_path[0];  in elink_8726_common_init_phy()
14379 			shmem2_base = shmem2_base_path[0];  in elink_8726_common_init_phy()
14394 				 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);  in elink_8726_common_init_phy()
14414 		*io_gpio = 0;  in elink_get_ext_phy_reset_gpio()
14415 		*io_port = 0;  in elink_get_ext_phy_reset_gpio()
14419 		*io_port = 0;  in elink_get_ext_phy_reset_gpio()
14423 		*io_port = 0;  in elink_get_ext_phy_reset_gpio()
14427 		*io_port = 0;  in elink_get_ext_phy_reset_gpio()
14430 		*io_gpio = 0;  in elink_get_ext_phy_reset_gpio()
14470 	elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],  in elink_8727_common_init_phy()
14491 			shmem_base = shmem_base_path[0];  in elink_8727_common_init_phy()
14492 			shmem2_base = shmem2_base_path[0];  in elink_8727_common_init_phy()
14497 			port_of_path = 0;  in elink_8727_common_init_phy()
14523 	if (phy[PORT_0].addr & 0x1) {  in elink_8727_common_init_phy()
14535 			port_of_path = 0;  in elink_8727_common_init_phy()
14536 		ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",  in elink_8727_common_init_phy()
14561 	ELINK_DEBUG_P1(sc, "84833 reset pulse on pin values 0x%x\n",  in elink_84833_common_init_phy()
14608 			   "ext_phy 0x%x common init not required\n",  in elink_ext_phy_common_init()
14614 		elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"  in elink_ext_phy_common_init()
14626 	uint8_t phy_index = 0;  in elink_common_init_phy()
14642 	phy_ver = REG_RD(sc, shmem_base_path[0] +  in elink_common_init_phy()
14646 		ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x\n",  in elink_common_init_phy()
14651 	/* Read the ext_phy_type for arbitrary port(0) */  in elink_common_init_phy()
14655 							  shmem_base_path[0],  in elink_common_init_phy()
14656 							  phy_index, 0);  in elink_common_init_phy()
14685 		if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {  in elink_check_over_curr()
14694 			elink_warpcore_power_module(params, 0);  in elink_check_over_curr()
14700 /* Returns 0 if no change occurred since last check; 1 otherwise. */
14708 	uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;  in elink_analyze_link_error()
14710 	if ((status ^ old_status) == 0)  in elink_analyze_link_error()
14711 		return 0;  in elink_analyze_link_error()
14728 	if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)  in elink_analyze_link_error()
14737 		vars->link_up = 0;  in elink_analyze_link_error()
14754 		REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in elink_analyze_link_error()
14786 	uint32_t lss_status = 0;  in elink_check_half_open_conn()
14789 	if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||  in elink_check_half_open_conn()
14804 		REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);  in elink_check_half_open_conn()
14828 		lss_status = (wb_data[0] > 0);  in elink_check_half_open_conn()
14841 	uint32_t cfg_pin, value = 0;  in elink_sfp_tx_fault_detection()
14851 		ELINK_DEBUG_P1(sc, "Failed to read pin 0x%02x\n", cfg_pin);  in elink_sfp_tx_fault_detection()
14902 	if (vars->check_kr2_recovery_cnt > 0) {  in elink_check_kr2_wa()
14926 	if (base_page == 0) {  in elink_check_kr2_wa()
14938 	not_kr2_device = (((base_page & 0x8000) == 0) ||  in elink_check_kr2_wa()
14939 			  (((base_page & 0x8000) &&  in elink_check_kr2_wa()
14940 			    ((next_page & 0xe0) == 0x20))));  in elink_check_kr2_wa()
14945 			ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page,  in elink_check_kr2_wa()
14954 		ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page, next_page);  in elink_check_kr2_wa()
15012 	uint8_t phy_index, fan_failure_det_req = 0;  in elink_fan_failure_det_req()
15020 			return 0;  in elink_fan_failure_det_req()
15032 	elink_update_mng(params, 0);  in elink_hw_reset_phy()
15054 	uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;  in elink_init_mod_abs_int()
15082 	if (gpio_num == 0xff)  in elink_init_mod_abs_int()
15100 	ELINK_DEBUG_P3(sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",  in elink_init_mod_abs_int()
15103 	if (port == 0)  in elink_init_mod_abs_int()