Lines Matching +full:x +full:- +full:offset
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
44 bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val) in bxe_reg_write8() argument
46 BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%02x\n", offset, val); in bxe_reg_write8()
47 bus_space_write_1(sc->bar[BAR0].tag, in bxe_reg_write8()
48 sc->bar[BAR0].handle, in bxe_reg_write8()
49 offset, in bxe_reg_write8()
54 bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val) in bxe_reg_write16() argument
56 if ((offset % 2) != 0) { in bxe_reg_write16()
57 BLOGD(sc, DBG_REGS, "Unaligned 16-bit write to 0x%08lx\n", offset); in bxe_reg_write16()
60 BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%04x\n", offset, val); in bxe_reg_write16()
61 bus_space_write_2(sc->bar[BAR0].tag, in bxe_reg_write16()
62 sc->bar[BAR0].handle, in bxe_reg_write16()
63 offset, in bxe_reg_write16()
68 bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val) in bxe_reg_write32() argument
70 if ((offset % 4) != 0) { in bxe_reg_write32()
71 BLOGD(sc, DBG_REGS, "Unaligned 32-bit write to 0x%08lx\n", offset); in bxe_reg_write32()
74 BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%08x\n", offset, val); in bxe_reg_write32()
75 bus_space_write_4(sc->bar[BAR0].tag, in bxe_reg_write32()
76 sc->bar[BAR0].handle, in bxe_reg_write32()
77 offset, in bxe_reg_write32()
82 bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset) in bxe_reg_read8() argument
86 val = bus_space_read_1(sc->bar[BAR0].tag, in bxe_reg_read8()
87 sc->bar[BAR0].handle, in bxe_reg_read8()
88 offset); in bxe_reg_read8()
89 BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%02x\n", offset, val); in bxe_reg_read8()
95 bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset) in bxe_reg_read16() argument
99 if ((offset % 2) != 0) { in bxe_reg_read16()
100 BLOGD(sc, DBG_REGS, "Unaligned 16-bit read from 0x%08lx\n", offset); in bxe_reg_read16()
103 val = bus_space_read_2(sc->bar[BAR0].tag, in bxe_reg_read16()
104 sc->bar[BAR0].handle, in bxe_reg_read16()
105 offset); in bxe_reg_read16()
106 BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%08x\n", offset, val); in bxe_reg_read16()
112 bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset) in bxe_reg_read32() argument
116 if ((offset % 4) != 0) { in bxe_reg_read32()
117 BLOGD(sc, DBG_REGS, "Unaligned 32-bit read from 0x%08lx\n", offset); in bxe_reg_read32()
120 val = bus_space_read_4(sc->bar[BAR0].tag, in bxe_reg_read32()
121 sc->bar[BAR0].handle, in bxe_reg_read32()
122 offset); in bxe_reg_read32()
123 BLOGD(sc, DBG_REGS, "offset=0x%08lx val=0x%08x\n", offset, val); in bxe_reg_read32()
137 if (__predict_false(sc->debug & DBG_PHY)) { in elink_cb_dbg()
139 device_printf(sc->dev, "%s", buf); in elink_cb_dbg()
149 if (__predict_false(sc->debug & DBG_PHY)) { in elink_cb_dbg1()
152 device_printf(sc->dev, "%s", buf); in elink_cb_dbg1()
163 if (__predict_false(sc->debug & DBG_PHY)) { in elink_cb_dbg2()
166 device_printf(sc->dev, "%s", buf); in elink_cb_dbg2()
178 if (__predict_false(sc->debug & DBG_PHY)) { in elink_cb_dbg3()
181 device_printf(sc->dev, "%s", buf); in elink_cb_dbg3()
210 snprintf(c, sizeof(c), "%03x", xx); in bxe_dump_mem()
215 snprintf(c, sizeof(c), "%02x ", *mem); in bxe_dump_mem()
222 BLOGI(sc, "------------ %s\n", tag); in bxe_dump_mem()
244 memp = m->m_data; in bxe_dump_mbuf_data()
246 snprintf(c, sizeof(c), "%03x", xx); in bxe_dump_mbuf_data()
252 for (i = 0; i < m->m_len; i++) in bxe_dump_mbuf_data()
258 snprintf(c, sizeof(c), "%03x", xx); in bxe_dump_mbuf_data()
263 snprintf(c, sizeof(c), "%02x ", *memp); in bxe_dump_mbuf_data()
272 snprintf(c, sizeof(c), "%d", m->m_len); in bxe_dump_mbuf_data()
274 xx += m->m_len; in bxe_dump_mbuf_data()
278 m = m->m_next; in bxe_dump_mbuf_data()
281 BLOGI(sc, "------------ %s\n", tag); in bxe_dump_mbuf_data()
341 db_printf(" dev=%p\n", sc->dev); in DB_COMMAND_FLAGS()
343 sc->pcie_bus, sc->pcie_device, sc->pcie_func); in DB_COMMAND_FLAGS()