Lines Matching refs:sc
642 static void bxe_cmng_fns_init(struct bxe_softc *sc,
645 static int bxe_get_cmng_fns_mode(struct bxe_softc *sc);
646 static void storm_memset_cmng(struct bxe_softc *sc,
649 static void bxe_set_reset_global(struct bxe_softc *sc);
650 static void bxe_set_reset_in_progress(struct bxe_softc *sc);
651 static uint8_t bxe_reset_is_done(struct bxe_softc *sc,
653 static uint8_t bxe_clear_pf_load(struct bxe_softc *sc);
654 static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc,
657 static void bxe_int_disable(struct bxe_softc *sc);
658 static int bxe_release_leader_lock(struct bxe_softc *sc);
659 static void bxe_pf_disable(struct bxe_softc *sc);
660 static void bxe_free_fp_buffers(struct bxe_softc *sc);
661 static inline void bxe_update_rx_prod(struct bxe_softc *sc,
666 static void bxe_link_report_locked(struct bxe_softc *sc);
667 static void bxe_link_report(struct bxe_softc *sc);
668 static void bxe_link_status_update(struct bxe_softc *sc);
670 static void bxe_periodic_start(struct bxe_softc *sc);
671 static void bxe_periodic_stop(struct bxe_softc *sc);
679 static uint8_t bxe_txeof(struct bxe_softc *sc,
682 static __noinline void bxe_dump_mbuf(struct bxe_softc *sc,
685 static int bxe_alloc_mem(struct bxe_softc *sc);
686 static void bxe_free_mem(struct bxe_softc *sc);
687 static int bxe_alloc_fw_stats_mem(struct bxe_softc *sc);
688 static void bxe_free_fw_stats_mem(struct bxe_softc *sc);
689 static int bxe_interrupt_attach(struct bxe_softc *sc);
690 static void bxe_interrupt_detach(struct bxe_softc *sc);
691 static void bxe_set_rx_mode(struct bxe_softc *sc);
692 static int bxe_init_locked(struct bxe_softc *sc);
693 static int bxe_stop_locked(struct bxe_softc *sc);
695 void bxe_parity_recover(struct bxe_softc *sc);
696 void bxe_handle_error(struct bxe_softc *sc);
697 static __noinline int bxe_nic_load(struct bxe_softc *sc,
699 static __noinline int bxe_nic_unload(struct bxe_softc *sc,
706 static int bxe_add_cdev(struct bxe_softc *sc);
707 static void bxe_del_cdev(struct bxe_softc *sc);
708 int bxe_grc_dump(struct bxe_softc *sc);
709 static int bxe_alloc_buf_rings(struct bxe_softc *sc);
710 static void bxe_free_buf_rings(struct bxe_softc *sc);
874 BLOGE(dma->sc, "Failed DMA alloc '%s' (%d)!\n", dma->msg, error); in bxe_dma_map_addr()
890 bxe_dma_alloc(struct bxe_softc *sc, in bxe_dma_alloc() argument
898 BLOGE(sc, "dma block '%s' already has size %lu\n", msg, in bxe_dma_alloc()
904 dma->sc = sc; in bxe_dma_alloc()
908 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ in bxe_dma_alloc()
923 BLOGE(sc, "Failed to create dma tag for '%s' (%d)\n", msg, rc); in bxe_dma_alloc()
933 BLOGE(sc, "Failed to alloc dma mem for '%s' (%d)\n", msg, rc); in bxe_dma_alloc()
947 BLOGE(sc, "Failed to load dma map for '%s' (%d)\n", msg, rc); in bxe_dma_alloc()
958 bxe_dma_free(struct bxe_softc *sc, in bxe_dma_free() argument
962 DBASSERT(sc, (dma->tag != NULL), ("dma tag is NULL")); in bxe_dma_free()
980 bxe_reg_wr_ind(struct bxe_softc *sc, in bxe_reg_wr_ind() argument
984 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4); in bxe_reg_wr_ind()
985 pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4); in bxe_reg_wr_ind()
986 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); in bxe_reg_wr_ind()
990 bxe_reg_rd_ind(struct bxe_softc *sc, in bxe_reg_rd_ind() argument
995 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4); in bxe_reg_rd_ind()
996 val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4); in bxe_reg_rd_ind()
997 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); in bxe_reg_rd_ind()
1003 bxe_acquire_hw_lock(struct bxe_softc *sc, in bxe_acquire_hw_lock() argument
1008 int func = SC_FUNC(sc); in bxe_acquire_hw_lock()
1014 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)" in bxe_acquire_hw_lock()
1027 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_acquire_hw_lock()
1029 BLOGE(sc, "resource (0x%x) in use (status 0x%x bit 0x%x)\n", in bxe_acquire_hw_lock()
1036 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit); in bxe_acquire_hw_lock()
1037 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_acquire_hw_lock()
1044 BLOGE(sc, "Resource 0x%x resource_bit 0x%x lock timeout!\n", in bxe_acquire_hw_lock()
1050 bxe_release_hw_lock(struct bxe_softc *sc, in bxe_release_hw_lock() argument
1055 int func = SC_FUNC(sc); in bxe_release_hw_lock()
1060 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)" in bxe_release_hw_lock()
1073 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_release_hw_lock()
1075 BLOGE(sc, "resource (0x%x) not in use (status 0x%x bit 0x%x)\n", in bxe_release_hw_lock()
1080 REG_WR(sc, hw_lock_control_reg, resource_bit); in bxe_release_hw_lock()
1083 static void bxe_acquire_phy_lock(struct bxe_softc *sc) in bxe_acquire_phy_lock() argument
1085 BXE_PHY_LOCK(sc); in bxe_acquire_phy_lock()
1086 bxe_acquire_hw_lock(sc,HW_LOCK_RESOURCE_MDIO); in bxe_acquire_phy_lock()
1089 static void bxe_release_phy_lock(struct bxe_softc *sc) in bxe_release_phy_lock() argument
1091 bxe_release_hw_lock(sc,HW_LOCK_RESOURCE_MDIO); in bxe_release_phy_lock()
1092 BXE_PHY_UNLOCK(sc); in bxe_release_phy_lock()
1109 bxe_acquire_nvram_lock(struct bxe_softc *sc) in bxe_acquire_nvram_lock() argument
1111 int port = SC_PORT(sc); in bxe_acquire_nvram_lock()
1116 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM); in bxe_acquire_nvram_lock()
1120 if (CHIP_REV_IS_SLOW(sc)) { in bxe_acquire_nvram_lock()
1125 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, in bxe_acquire_nvram_lock()
1129 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); in bxe_acquire_nvram_lock()
1138 BLOGE(sc, "Cannot get access to nvram interface " in bxe_acquire_nvram_lock()
1148 bxe_release_nvram_lock(struct bxe_softc *sc) in bxe_release_nvram_lock() argument
1150 int port = SC_PORT(sc); in bxe_release_nvram_lock()
1156 if (CHIP_REV_IS_SLOW(sc)) { in bxe_release_nvram_lock()
1161 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, in bxe_release_nvram_lock()
1165 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); in bxe_release_nvram_lock()
1174 BLOGE(sc, "Cannot free access to nvram interface " in bxe_release_nvram_lock()
1181 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM); in bxe_release_nvram_lock()
1187 bxe_enable_nvram_access(struct bxe_softc *sc) in bxe_enable_nvram_access() argument
1191 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in bxe_enable_nvram_access()
1194 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE, in bxe_enable_nvram_access()
1199 bxe_disable_nvram_access(struct bxe_softc *sc) in bxe_disable_nvram_access() argument
1203 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in bxe_disable_nvram_access()
1206 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE, in bxe_disable_nvram_access()
1212 bxe_nvram_read_dword(struct bxe_softc *sc, in bxe_nvram_read_dword() argument
1224 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); in bxe_nvram_read_dword()
1227 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR, in bxe_nvram_read_dword()
1231 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); in bxe_nvram_read_dword()
1235 if (CHIP_REV_IS_SLOW(sc)) { in bxe_nvram_read_dword()
1244 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); in bxe_nvram_read_dword()
1247 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ); in bxe_nvram_read_dword()
1259 BLOGE(sc, "nvram read timeout expired " in bxe_nvram_read_dword()
1268 bxe_nvram_read(struct bxe_softc *sc, in bxe_nvram_read() argument
1278 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n", in bxe_nvram_read()
1283 if ((offset + buf_size) > sc->devinfo.flash_size) { in bxe_nvram_read()
1284 BLOGE(sc, "Invalid parameter, " in bxe_nvram_read()
1286 offset, buf_size, sc->devinfo.flash_size); in bxe_nvram_read()
1291 rc = bxe_acquire_nvram_lock(sc); in bxe_nvram_read()
1297 bxe_enable_nvram_access(sc); in bxe_nvram_read()
1302 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags); in bxe_nvram_read()
1314 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags); in bxe_nvram_read()
1319 bxe_disable_nvram_access(sc); in bxe_nvram_read()
1320 bxe_release_nvram_lock(sc); in bxe_nvram_read()
1326 bxe_nvram_write_dword(struct bxe_softc *sc, in bxe_nvram_write_dword() argument
1337 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); in bxe_nvram_write_dword()
1340 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val); in bxe_nvram_write_dword()
1343 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR, in bxe_nvram_write_dword()
1347 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); in bxe_nvram_write_dword()
1351 if (CHIP_REV_IS_SLOW(sc)) { in bxe_nvram_write_dword()
1359 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); in bxe_nvram_write_dword()
1367 BLOGE(sc, "nvram write timeout expired " in bxe_nvram_write_dword()
1378 bxe_nvram_write1(struct bxe_softc *sc, in bxe_nvram_write1() argument
1388 if ((offset + buf_size) > sc->devinfo.flash_size) { in bxe_nvram_write1()
1389 BLOGE(sc, "Invalid parameter, " in bxe_nvram_write1()
1391 offset, buf_size, sc->devinfo.flash_size); in bxe_nvram_write1()
1396 rc = bxe_acquire_nvram_lock(sc); in bxe_nvram_write1()
1402 bxe_enable_nvram_access(sc); in bxe_nvram_write1()
1406 rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags); in bxe_nvram_write1()
1417 rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags); in bxe_nvram_write1()
1421 bxe_disable_nvram_access(sc); in bxe_nvram_write1()
1422 bxe_release_nvram_lock(sc); in bxe_nvram_write1()
1428 bxe_nvram_write(struct bxe_softc *sc, in bxe_nvram_write() argument
1439 return (bxe_nvram_write1(sc, offset, data_buf, buf_size)); in bxe_nvram_write()
1443 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n", in bxe_nvram_write()
1452 if ((offset + buf_size) > sc->devinfo.flash_size) { in bxe_nvram_write()
1453 BLOGE(sc, "Invalid parameter, " in bxe_nvram_write()
1455 offset, buf_size, sc->devinfo.flash_size); in bxe_nvram_write()
1460 rc = bxe_acquire_nvram_lock(sc); in bxe_nvram_write()
1466 bxe_enable_nvram_access(sc); in bxe_nvram_write()
1481 rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags); in bxe_nvram_write()
1491 bxe_disable_nvram_access(sc); in bxe_nvram_write()
1492 bxe_release_nvram_lock(sc); in bxe_nvram_write()
1499 bxe_post_dmae(struct bxe_softc *sc, in bxe_post_dmae() argument
1508 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i)); in bxe_post_dmae()
1511 REG_WR(sc, dmae_reg_go_c[idx], 1); in bxe_post_dmae()
1529 bxe_dmae_opcode(struct bxe_softc *sc, in bxe_dmae_opcode() argument
1542 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); in bxe_dmae_opcode()
1544 opcode |= ((SC_VN(sc) << DMAE_CMD_E1HVN_SHIFT) | in bxe_dmae_opcode()
1545 (SC_VN(sc) << DMAE_CMD_DST_VN_SHIFT)); in bxe_dmae_opcode()
1563 bxe_prep_dmae_with_comp(struct bxe_softc *sc, in bxe_prep_dmae_with_comp() argument
1571 dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type, in bxe_prep_dmae_with_comp()
1575 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp)); in bxe_prep_dmae_with_comp()
1576 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp)); in bxe_prep_dmae_with_comp()
1582 bxe_issue_dmae_with_comp(struct bxe_softc *sc, in bxe_issue_dmae_with_comp() argument
1585 uint32_t *wb_comp = BXE_SP(sc, wb_comp); in bxe_issue_dmae_with_comp()
1586 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000; in bxe_issue_dmae_with_comp()
1588 BXE_DMAE_LOCK(sc); in bxe_issue_dmae_with_comp()
1594 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc)); in bxe_issue_dmae_with_comp()
1601 (sc->recovery_state != BXE_RECOVERY_DONE && in bxe_issue_dmae_with_comp()
1602 sc->recovery_state != BXE_RECOVERY_NIC_LOADING)) { in bxe_issue_dmae_with_comp()
1603 BLOGE(sc, "DMAE timeout! *wb_comp 0x%x recovery_state 0x%x\n", in bxe_issue_dmae_with_comp()
1604 *wb_comp, sc->recovery_state); in bxe_issue_dmae_with_comp()
1605 BXE_DMAE_UNLOCK(sc); in bxe_issue_dmae_with_comp()
1614 BLOGE(sc, "DMAE PCI error! *wb_comp 0x%x recovery_state 0x%x\n", in bxe_issue_dmae_with_comp()
1615 *wb_comp, sc->recovery_state); in bxe_issue_dmae_with_comp()
1616 BXE_DMAE_UNLOCK(sc); in bxe_issue_dmae_with_comp()
1620 BXE_DMAE_UNLOCK(sc); in bxe_issue_dmae_with_comp()
1625 bxe_read_dmae(struct bxe_softc *sc, in bxe_read_dmae() argument
1633 DBASSERT(sc, (len32 <= 4), ("DMAE read length is %d", len32)); in bxe_read_dmae()
1635 if (!sc->dmae_ready) { in bxe_read_dmae()
1636 data = BXE_SP(sc, wb_data[0]); in bxe_read_dmae()
1639 data[i] = (CHIP_IS_E1(sc)) ? in bxe_read_dmae()
1640 bxe_reg_rd_ind(sc, (src_addr + (i * 4))) : in bxe_read_dmae()
1641 REG_RD(sc, (src_addr + (i * 4))); in bxe_read_dmae()
1648 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); in bxe_read_dmae()
1653 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data)); in bxe_read_dmae()
1654 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data)); in bxe_read_dmae()
1658 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) { in bxe_read_dmae()
1659 bxe_panic(sc, ("DMAE failed (%d)\n", rc)); in bxe_read_dmae()
1664 bxe_write_dmae(struct bxe_softc *sc, in bxe_write_dmae() argument
1672 if (!sc->dmae_ready) { in bxe_write_dmae()
1673 DBASSERT(sc, (len32 <= 4), ("DMAE not ready and length is %d", len32)); in bxe_write_dmae()
1675 if (CHIP_IS_E1(sc)) { in bxe_write_dmae()
1676 ecore_init_ind_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32); in bxe_write_dmae()
1678 ecore_init_str_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32); in bxe_write_dmae()
1685 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); in bxe_write_dmae()
1695 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) { in bxe_write_dmae()
1696 bxe_panic(sc, ("DMAE failed (%d)\n", rc)); in bxe_write_dmae()
1701 bxe_write_dmae_phys_len(struct bxe_softc *sc, in bxe_write_dmae_phys_len() argument
1706 int dmae_wr_max = DMAE_LEN32_WR_MAX(sc); in bxe_write_dmae_phys_len()
1710 bxe_write_dmae(sc, in bxe_write_dmae_phys_len()
1718 bxe_write_dmae(sc, in bxe_write_dmae_phys_len()
1725 bxe_set_ctx_validation(struct bxe_softc *sc, in bxe_set_ctx_validation() argument
1731 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid), in bxe_set_ctx_validation()
1735 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid), in bxe_set_ctx_validation()
1740 bxe_storm_memset_hc_timeout(struct bxe_softc *sc, in bxe_storm_memset_hc_timeout() argument
1750 REG_WR8(sc, addr, ticks); in bxe_storm_memset_hc_timeout()
1752 BLOGD(sc, DBG_LOAD, in bxe_storm_memset_hc_timeout()
1758 bxe_storm_memset_hc_disable(struct bxe_softc *sc, in bxe_storm_memset_hc_disable() argument
1772 flags = REG_RD8(sc, addr); in bxe_storm_memset_hc_disable()
1775 REG_WR8(sc, addr, flags); in bxe_storm_memset_hc_disable()
1777 BLOGD(sc, DBG_LOAD, in bxe_storm_memset_hc_disable()
1783 bxe_update_coalesce_sb_index(struct bxe_softc *sc, in bxe_update_coalesce_sb_index() argument
1789 int port = SC_PORT(sc); in bxe_update_coalesce_sb_index()
1792 bxe_storm_memset_hc_timeout(sc, port, fw_sb_id, sb_index, ticks); in bxe_update_coalesce_sb_index()
1795 bxe_storm_memset_hc_disable(sc, port, fw_sb_id, sb_index, disable); in bxe_update_coalesce_sb_index()
1799 elink_cb_udelay(struct bxe_softc *sc, in elink_cb_udelay() argument
1806 elink_cb_reg_read(struct bxe_softc *sc, in elink_cb_reg_read() argument
1809 return (REG_RD(sc, reg_addr)); in elink_cb_reg_read()
1813 elink_cb_reg_write(struct bxe_softc *sc, in elink_cb_reg_write() argument
1817 REG_WR(sc, reg_addr, val); in elink_cb_reg_write()
1821 elink_cb_reg_wb_write(struct bxe_softc *sc, in elink_cb_reg_wb_write() argument
1826 REG_WR_DMAE(sc, offset, wb_write, len); in elink_cb_reg_wb_write()
1830 elink_cb_reg_wb_read(struct bxe_softc *sc, in elink_cb_reg_wb_read() argument
1835 REG_RD_DMAE(sc, offset, wb_write, len); in elink_cb_reg_wb_read()
1839 elink_cb_path_id(struct bxe_softc *sc) in elink_cb_path_id() argument
1841 return (SC_PATH(sc)); in elink_cb_path_id()
1845 elink_cb_event_log(struct bxe_softc *sc, in elink_cb_event_log() argument
1850 BLOGI(sc, "ELINK EVENT LOG (%d)\n", elink_log_id); in elink_cb_event_log()
1854 bxe_set_spio(struct bxe_softc *sc, in bxe_set_spio() argument
1862 BLOGE(sc, "Invalid SPIO 0x%x mode 0x%x\n", spio, mode); in bxe_set_spio()
1866 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO); in bxe_set_spio()
1869 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT); in bxe_set_spio()
1873 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output low\n", spio); in bxe_set_spio()
1880 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output high\n", spio); in bxe_set_spio()
1887 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> input\n", spio); in bxe_set_spio()
1896 REG_WR(sc, MISC_REG_SPIO, spio_reg); in bxe_set_spio()
1897 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO); in bxe_set_spio()
1903 bxe_gpio_read(struct bxe_softc *sc, in bxe_gpio_read() argument
1908 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && in bxe_gpio_read()
1909 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); in bxe_gpio_read()
1916 BLOGE(sc, "Invalid GPIO %d port 0x%x gpio_port %d gpio_shift %d" in bxe_gpio_read()
1923 gpio_reg = REG_RD(sc, MISC_REG_GPIO); in bxe_gpio_read()
1930 bxe_gpio_write(struct bxe_softc *sc, in bxe_gpio_write() argument
1936 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && in bxe_gpio_write()
1937 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); in bxe_gpio_write()
1944 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d" in bxe_gpio_write()
1950 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); in bxe_gpio_write()
1953 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); in bxe_gpio_write()
1957 BLOGD(sc, DBG_PHY, in bxe_gpio_write()
1966 BLOGD(sc, DBG_PHY, in bxe_gpio_write()
1975 BLOGD(sc, DBG_PHY, in bxe_gpio_write()
1986 REG_WR(sc, MISC_REG_GPIO, gpio_reg); in bxe_gpio_write()
1987 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); in bxe_gpio_write()
1993 bxe_gpio_mult_write(struct bxe_softc *sc, in bxe_gpio_mult_write() argument
2001 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); in bxe_gpio_mult_write()
2004 gpio_reg = REG_RD(sc, MISC_REG_GPIO); in bxe_gpio_mult_write()
2011 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output low\n", pins); in bxe_gpio_mult_write()
2017 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output high\n", pins); in bxe_gpio_mult_write()
2023 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> input\n", pins); in bxe_gpio_mult_write()
2029 BLOGE(sc, "Invalid GPIO mode assignment pins 0x%x mode 0x%x" in bxe_gpio_mult_write()
2031 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); in bxe_gpio_mult_write()
2035 REG_WR(sc, MISC_REG_GPIO, gpio_reg); in bxe_gpio_mult_write()
2036 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); in bxe_gpio_mult_write()
2042 bxe_gpio_int_write(struct bxe_softc *sc, in bxe_gpio_int_write() argument
2048 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && in bxe_gpio_int_write()
2049 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); in bxe_gpio_int_write()
2056 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d" in bxe_gpio_int_write()
2062 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); in bxe_gpio_int_write()
2065 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT); in bxe_gpio_int_write()
2069 BLOGD(sc, DBG_PHY, in bxe_gpio_int_write()
2078 BLOGD(sc, DBG_PHY, in bxe_gpio_int_write()
2090 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg); in bxe_gpio_int_write()
2091 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); in bxe_gpio_int_write()
2097 elink_cb_gpio_read(struct bxe_softc *sc, in elink_cb_gpio_read() argument
2101 return (bxe_gpio_read(sc, gpio_num, port)); in elink_cb_gpio_read()
2105 elink_cb_gpio_write(struct bxe_softc *sc, in elink_cb_gpio_write() argument
2110 return (bxe_gpio_write(sc, gpio_num, mode, port)); in elink_cb_gpio_write()
2114 elink_cb_gpio_mult_write(struct bxe_softc *sc, in elink_cb_gpio_mult_write() argument
2118 return (bxe_gpio_mult_write(sc, pins, mode)); in elink_cb_gpio_mult_write()
2122 elink_cb_gpio_int_write(struct bxe_softc *sc, in elink_cb_gpio_int_write() argument
2127 return (bxe_gpio_int_write(sc, gpio_num, mode, port)); in elink_cb_gpio_int_write()
2131 elink_cb_notify_link_changed(struct bxe_softc *sc) in elink_cb_notify_link_changed() argument
2133 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 + in elink_cb_notify_link_changed()
2134 (SC_FUNC(sc) * sizeof(uint32_t))), 1); in elink_cb_notify_link_changed()
2139 elink_cb_fw_command(struct bxe_softc *sc, in elink_cb_fw_command() argument
2143 int mb_idx = SC_FW_MB_IDX(sc); in elink_cb_fw_command()
2147 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10; in elink_cb_fw_command()
2149 BXE_FWMB_LOCK(sc); in elink_cb_fw_command()
2151 seq = ++sc->fw_seq; in elink_cb_fw_command()
2152 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param); in elink_cb_fw_command()
2153 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq)); in elink_cb_fw_command()
2155 BLOGD(sc, DBG_PHY, in elink_cb_fw_command()
2162 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header); in elink_cb_fw_command()
2165 BLOGD(sc, DBG_PHY, in elink_cb_fw_command()
2174 BLOGE(sc, "FW failed to respond!\n"); in elink_cb_fw_command()
2179 BXE_FWMB_UNLOCK(sc); in elink_cb_fw_command()
2184 bxe_fw_command(struct bxe_softc *sc, in bxe_fw_command() argument
2188 return (elink_cb_fw_command(sc, command, param)); in bxe_fw_command()
2192 __storm_memset_dma_mapping(struct bxe_softc *sc, in __storm_memset_dma_mapping() argument
2196 REG_WR(sc, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
2197 REG_WR(sc, (addr + 4), U64_HI(mapping)); in __storm_memset_dma_mapping()
2201 storm_memset_spq_addr(struct bxe_softc *sc, in storm_memset_spq_addr() argument
2207 __storm_memset_dma_mapping(sc, addr, mapping); in storm_memset_spq_addr()
2211 storm_memset_vf_to_pf(struct bxe_softc *sc, in storm_memset_vf_to_pf() argument
2215 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); in storm_memset_vf_to_pf()
2216 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); in storm_memset_vf_to_pf()
2217 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); in storm_memset_vf_to_pf()
2218 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); in storm_memset_vf_to_pf()
2222 storm_memset_func_en(struct bxe_softc *sc, in storm_memset_func_en() argument
2226 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable); in storm_memset_func_en()
2227 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable); in storm_memset_func_en()
2228 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable); in storm_memset_func_en()
2229 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable); in storm_memset_func_en()
2233 storm_memset_eq_data(struct bxe_softc *sc, in storm_memset_eq_data() argument
2242 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)eq_data); in storm_memset_eq_data()
2246 storm_memset_eq_prod(struct bxe_softc *sc, in storm_memset_eq_prod() argument
2252 REG_WR16(sc, addr, eq_prod); in storm_memset_eq_prod()
2317 struct eth_spe *bxe_sp_get_next(struct bxe_softc *sc) in bxe_sp_get_next() argument
2319 struct eth_spe *next_spe = sc->spq_prod_bd; in bxe_sp_get_next()
2321 if (sc->spq_prod_bd == sc->spq_last_bd) { in bxe_sp_get_next()
2323 sc->spq_prod_bd = sc->spq; in bxe_sp_get_next()
2324 sc->spq_prod_idx = 0; in bxe_sp_get_next()
2326 sc->spq_prod_bd++; in bxe_sp_get_next()
2327 sc->spq_prod_idx++; in bxe_sp_get_next()
2335 void bxe_sp_prod_update(struct bxe_softc *sc) in bxe_sp_prod_update() argument
2337 int func = SC_FUNC(sc); in bxe_sp_prod_update()
2346 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)), in bxe_sp_prod_update()
2347 sc->spq_prod_idx); in bxe_sp_prod_update()
2349 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, in bxe_sp_prod_update()
2391 bxe_sp_post(struct bxe_softc *sc, in bxe_sp_post() argument
2404 BXE_SP_LOCK(sc); in bxe_sp_post()
2407 if (!atomic_load_acq_long(&sc->eq_spq_left)) { in bxe_sp_post()
2408 BLOGE(sc, "EQ ring is full!\n"); in bxe_sp_post()
2409 BXE_SP_UNLOCK(sc); in bxe_sp_post()
2413 if (!atomic_load_acq_long(&sc->cq_spq_left)) { in bxe_sp_post()
2414 BLOGE(sc, "SPQ ring is full!\n"); in bxe_sp_post()
2415 BXE_SP_UNLOCK(sc); in bxe_sp_post()
2420 spe = bxe_sp_get_next(sc); in bxe_sp_post()
2424 htole32((command << SPE_HDR_T_CMD_ID_SHIFT) | HW_CID(sc, cid)); in bxe_sp_post()
2429 type |= ((SC_FUNC(sc) << SPE_HDR_T_FUNCTION_ID_SHIFT) & in bxe_sp_post()
2443 atomic_subtract_acq_long(&sc->eq_spq_left, 1); in bxe_sp_post()
2445 atomic_subtract_acq_long(&sc->cq_spq_left, 1); in bxe_sp_post()
2448 BLOGD(sc, DBG_SP, "SPQE -> %#jx\n", (uintmax_t)sc->spq_dma.paddr); in bxe_sp_post()
2449 BLOGD(sc, DBG_SP, "FUNC_RDATA -> %p / %#jx\n", in bxe_sp_post()
2450 BXE_SP(sc, func_rdata), (uintmax_t)BXE_SP_MAPPING(sc, func_rdata)); in bxe_sp_post()
2451 BLOGD(sc, DBG_SP, in bxe_sp_post()
2453 sc->spq_prod_idx, in bxe_sp_post()
2454 (uint32_t)U64_HI(sc->spq_dma.paddr), in bxe_sp_post()
2455 (uint32_t)(U64_LO(sc->spq_dma.paddr) + (uint8_t *)sc->spq_prod_bd - (uint8_t *)sc->spq), in bxe_sp_post()
2458 HW_CID(sc, cid), in bxe_sp_post()
2462 atomic_load_acq_long(&sc->cq_spq_left), in bxe_sp_post()
2463 atomic_load_acq_long(&sc->eq_spq_left)); in bxe_sp_post()
2465 bxe_sp_prod_update(sc); in bxe_sp_post()
2467 BXE_SP_UNLOCK(sc); in bxe_sp_post()
2523 bxe_init_mutexes(struct bxe_softc *sc) in bxe_init_mutexes() argument
2526 snprintf(sc->core_sx_name, sizeof(sc->core_sx_name), in bxe_init_mutexes()
2527 "bxe%d_core_lock", sc->unit); in bxe_init_mutexes()
2528 sx_init(&sc->core_sx, sc->core_sx_name); in bxe_init_mutexes()
2530 snprintf(sc->core_mtx_name, sizeof(sc->core_mtx_name), in bxe_init_mutexes()
2531 "bxe%d_core_lock", sc->unit); in bxe_init_mutexes()
2532 mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF); in bxe_init_mutexes()
2535 snprintf(sc->sp_mtx_name, sizeof(sc->sp_mtx_name), in bxe_init_mutexes()
2536 "bxe%d_sp_lock", sc->unit); in bxe_init_mutexes()
2537 mtx_init(&sc->sp_mtx, sc->sp_mtx_name, NULL, MTX_DEF); in bxe_init_mutexes()
2539 snprintf(sc->dmae_mtx_name, sizeof(sc->dmae_mtx_name), in bxe_init_mutexes()
2540 "bxe%d_dmae_lock", sc->unit); in bxe_init_mutexes()
2541 mtx_init(&sc->dmae_mtx, sc->dmae_mtx_name, NULL, MTX_DEF); in bxe_init_mutexes()
2543 snprintf(sc->port.phy_mtx_name, sizeof(sc->port.phy_mtx_name), in bxe_init_mutexes()
2544 "bxe%d_phy_lock", sc->unit); in bxe_init_mutexes()
2545 mtx_init(&sc->port.phy_mtx, sc->port.phy_mtx_name, NULL, MTX_DEF); in bxe_init_mutexes()
2547 snprintf(sc->fwmb_mtx_name, sizeof(sc->fwmb_mtx_name), in bxe_init_mutexes()
2548 "bxe%d_fwmb_lock", sc->unit); in bxe_init_mutexes()
2549 mtx_init(&sc->fwmb_mtx, sc->fwmb_mtx_name, NULL, MTX_DEF); in bxe_init_mutexes()
2551 snprintf(sc->print_mtx_name, sizeof(sc->print_mtx_name), in bxe_init_mutexes()
2552 "bxe%d_print_lock", sc->unit); in bxe_init_mutexes()
2553 mtx_init(&(sc->print_mtx), sc->print_mtx_name, NULL, MTX_DEF); in bxe_init_mutexes()
2555 snprintf(sc->stats_mtx_name, sizeof(sc->stats_mtx_name), in bxe_init_mutexes()
2556 "bxe%d_stats_lock", sc->unit); in bxe_init_mutexes()
2557 mtx_init(&(sc->stats_mtx), sc->stats_mtx_name, NULL, MTX_DEF); in bxe_init_mutexes()
2559 snprintf(sc->mcast_mtx_name, sizeof(sc->mcast_mtx_name), in bxe_init_mutexes()
2560 "bxe%d_mcast_lock", sc->unit); in bxe_init_mutexes()
2561 mtx_init(&(sc->mcast_mtx), sc->mcast_mtx_name, NULL, MTX_DEF); in bxe_init_mutexes()
2565 bxe_release_mutexes(struct bxe_softc *sc) in bxe_release_mutexes() argument
2568 sx_destroy(&sc->core_sx); in bxe_release_mutexes()
2570 if (mtx_initialized(&sc->core_mtx)) { in bxe_release_mutexes()
2571 mtx_destroy(&sc->core_mtx); in bxe_release_mutexes()
2575 if (mtx_initialized(&sc->sp_mtx)) { in bxe_release_mutexes()
2576 mtx_destroy(&sc->sp_mtx); in bxe_release_mutexes()
2579 if (mtx_initialized(&sc->dmae_mtx)) { in bxe_release_mutexes()
2580 mtx_destroy(&sc->dmae_mtx); in bxe_release_mutexes()
2583 if (mtx_initialized(&sc->port.phy_mtx)) { in bxe_release_mutexes()
2584 mtx_destroy(&sc->port.phy_mtx); in bxe_release_mutexes()
2587 if (mtx_initialized(&sc->fwmb_mtx)) { in bxe_release_mutexes()
2588 mtx_destroy(&sc->fwmb_mtx); in bxe_release_mutexes()
2591 if (mtx_initialized(&sc->print_mtx)) { in bxe_release_mutexes()
2592 mtx_destroy(&sc->print_mtx); in bxe_release_mutexes()
2595 if (mtx_initialized(&sc->stats_mtx)) { in bxe_release_mutexes()
2596 mtx_destroy(&sc->stats_mtx); in bxe_release_mutexes()
2599 if (mtx_initialized(&sc->mcast_mtx)) { in bxe_release_mutexes()
2600 mtx_destroy(&sc->mcast_mtx); in bxe_release_mutexes()
2605 bxe_tx_disable(struct bxe_softc* sc) in bxe_tx_disable() argument
2607 if_t ifp = sc->ifp; in bxe_tx_disable()
2616 bxe_drv_pulse(struct bxe_softc *sc) in bxe_drv_pulse() argument
2618 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb, in bxe_drv_pulse()
2619 sc->fw_drv_pulse_wr_seq); in bxe_drv_pulse()
2623 bxe_tx_avail(struct bxe_softc *sc, in bxe_tx_avail() argument
2635 return (int16_t)(sc->tx_ring_size) - used; in bxe_tx_avail()
2668 bxe_sp_event(struct bxe_softc *sc, in bxe_sp_event() argument
2675 struct ecore_queue_sp_obj *q_obj = &BXE_SP_OBJ(sc, fp).q_obj; in bxe_sp_event()
2677 BLOGD(sc, DBG_SP, "fp=%d cid=%d got ramrod #%d state is %x type is %d\n", in bxe_sp_event()
2678 fp->index, cid, command, sc->state, rr_cqe->ramrod_cqe.ramrod_type); in bxe_sp_event()
2682 BLOGD(sc, DBG_SP, "got UPDATE ramrod. CID %d\n", cid); in bxe_sp_event()
2687 BLOGD(sc, DBG_SP, "got MULTI[%d] setup ramrod\n", cid); in bxe_sp_event()
2692 BLOGD(sc, DBG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); in bxe_sp_event()
2697 BLOGD(sc, DBG_SP, "got MULTI[%d] halt ramrod\n", cid); in bxe_sp_event()
2702 BLOGD(sc, DBG_SP, "got MULTI[%d] teminate ramrod\n", cid); in bxe_sp_event()
2707 BLOGD(sc, DBG_SP, "got MULTI[%d] empty ramrod\n", cid); in bxe_sp_event()
2712 BLOGD(sc, DBG_SP, "ERROR: unexpected MC reply (%d) on fp[%d]\n", in bxe_sp_event()
2718 q_obj->complete_cmd(sc, q_obj, drv_cmd)) { in bxe_sp_event()
2731 atomic_add_acq_long(&sc->cq_spq_left, 1); in bxe_sp_event()
2733 BLOGD(sc, DBG_SP, "sc->cq_spq_left 0x%lx\n", in bxe_sp_event()
2734 atomic_load_acq_long(&sc->cq_spq_left)); in bxe_sp_event()
2743 bxe_tpa_start(struct bxe_softc *sc, in bxe_tpa_start() argument
2757 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA START " in bxe_tpa_start()
2761 max_agg_queues = MAX_AGG_QS(sc); in bxe_tpa_start()
2779 BLOGE(sc, "fp[%02d].tpa[%02d] cons[%d] prod[%d]mbuf not allocated!\n", in bxe_tpa_start()
2781 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n", in bxe_tpa_start()
2802 index = (sc->max_rx_bufs != RX_BD_USABLE) ? in bxe_tpa_start()
2841 bxe_fill_frag_mbuf(struct bxe_softc *sc, in bxe_fill_frag_mbuf() argument
2858 BLOGD(sc, DBG_LRO, in bxe_fill_frag_mbuf()
2867 BLOGE(sc, "fp[%02d].sge[0x%04x] has too many pages (%d)! " in bxe_fill_frag_mbuf()
2872 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n", in bxe_fill_frag_mbuf()
2875 bxe_panic(sc, ("sge page count error\n")); in bxe_fill_frag_mbuf()
2892 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA fill i=%d j=%d " in bxe_fill_frag_mbuf()
2917 BLOGD(sc, DBG_LRO, in bxe_fill_frag_mbuf()
2965 bxe_update_sge_prod(struct bxe_softc *sc, in bxe_update_sge_prod() argument
2984 BLOGD(sc, DBG_LRO, in bxe_update_sge_prod()
3018 BLOGD(sc, DBG_LRO, in bxe_update_sge_prod()
3029 bxe_tpa_stop(struct bxe_softc *sc, in bxe_tpa_stop() argument
3037 if_t ifp = sc->ifp; in bxe_tpa_stop()
3041 BLOGD(sc, DBG_LRO, in bxe_tpa_stop()
3070 rc = bxe_fill_frag_mbuf(sc, fp, tpa_info, queue, pages, m, cqe, cqe_idx); in bxe_tpa_stop()
3146 bxe_update_sge_prod(fp->sc, fp, frags, &cqe_fp->sgl_or_raw_data); in bxe_service_rxsgl()
3152 bxe_rxeof(struct bxe_softc *sc, in bxe_rxeof() argument
3155 if_t ifp = sc->ifp; in bxe_rxeof()
3181 BLOGD(sc, DBG_RX, in bxe_rxeof()
3203 BLOGD(sc, DBG_RX, in bxe_rxeof()
3222 bxe_sp_event(sc, fp, cqe); in bxe_rxeof()
3234 bxe_tpa_start(sc, fp, cqe_fp->queue_index, in bxe_rxeof()
3246 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA STOP\n", in bxe_rxeof()
3253 bxe_tpa_stop(sc, fp, tpa_info, queue, pages, in bxe_rxeof()
3256 bxe_update_sge_prod(sc, fp, pages, &cqe->end_agg_cqe.sgl_or_raw_data); in bxe_rxeof()
3266 BLOGE(sc, "flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons); in bxe_rxeof()
3278 BLOGE(sc, "No mbuf in rx chain descriptor %d for fp[%02d]\n", in bxe_rxeof()
3291 (sc->max_rx_bufs != RX_BD_USABLE) ? in bxe_rxeof()
3298 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n", in bxe_rxeof()
3302 if (sc->max_rx_bufs != RX_BD_USABLE) { in bxe_rxeof()
3397 if (rx_pkts == sc->rx_budget) { in bxe_rxeof()
3409 bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod, fp->rx_sge_prod); in bxe_rxeof()
3420 bxe_free_tx_pkt(struct bxe_softc *sc, in bxe_free_tx_pkt() argument
3454 bxe_watchdog(struct bxe_softc *sc, in bxe_watchdog() argument
3464 BLOGE(sc, "TX watchdog timeout on fp[%02d], resetting!\n", fp->index); in bxe_watchdog()
3467 BXE_SET_ERROR_BIT(sc, BXE_ERR_TXQ_STUCK); in bxe_watchdog()
3469 &sc->sp_err_timeout_task, hz/10); in bxe_watchdog()
3476 bxe_txeof(struct bxe_softc *sc, in bxe_txeof() argument
3479 if_t ifp = sc->ifp; in bxe_txeof()
3492 BLOGD(sc, DBG_TX, in bxe_txeof()
3496 bd_cons = bxe_free_tx_pkt(sc, fp, pkt_cons); in bxe_txeof()
3504 BLOGD(sc, DBG_TX, in bxe_txeof()
3510 tx_bd_avail = bxe_tx_avail(sc, fp); in bxe_txeof()
3530 bxe_drain_tx_queues(struct bxe_softc *sc) in bxe_drain_tx_queues() argument
3536 for (i = 0; i < sc->num_queues; i++) { in bxe_drain_tx_queues()
3537 fp = &sc->fp[i]; in bxe_drain_tx_queues()
3544 bxe_txeof(sc, fp); in bxe_drain_tx_queues()
3548 BLOGE(sc, "Timeout waiting for fp[%d] " in bxe_drain_tx_queues()
3550 bxe_panic(sc, ("tx drain failure\n")); in bxe_drain_tx_queues()
3564 bxe_del_all_macs(struct bxe_softc *sc, in bxe_del_all_macs() argument
3580 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags); in bxe_del_all_macs()
3582 BLOGE(sc, "Failed to delete MACs (%d) mac_type %d wait_for_comp 0x%x\n", in bxe_del_all_macs()
3590 bxe_fill_accept_flags(struct bxe_softc *sc, in bxe_fill_accept_flags() argument
3646 if (IS_MF_SI(sc)) { in bxe_fill_accept_flags()
3655 BLOGE(sc, "Unknown rx_mode (0x%x)\n", rx_mode); in bxe_fill_accept_flags()
3669 bxe_set_q_rx_mode(struct bxe_softc *sc, in bxe_set_q_rx_mode() argument
3684 ramrod_param.rx_mode_obj = &sc->rx_mode_obj; in bxe_set_q_rx_mode()
3685 ramrod_param.func_id = SC_FUNC(sc); in bxe_set_q_rx_mode()
3687 ramrod_param.pstate = &sc->sp_state; in bxe_set_q_rx_mode()
3690 ramrod_param.rdata = BXE_SP(sc, rx_mode_rdata); in bxe_set_q_rx_mode()
3691 ramrod_param.rdata_mapping = BXE_SP_MAPPING(sc, rx_mode_rdata); in bxe_set_q_rx_mode()
3693 bxe_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); in bxe_set_q_rx_mode()
3701 rc = ecore_config_rx_mode(sc, &ramrod_param); in bxe_set_q_rx_mode()
3703 BLOGE(sc, "Set rx_mode %d cli_id 0x%x rx_mode_flags 0x%x " in bxe_set_q_rx_mode()
3705 "ramrod_flags 0x%x rc %d failed\n", sc->rx_mode, cl_id, in bxe_set_q_rx_mode()
3715 bxe_set_storm_rx_mode(struct bxe_softc *sc) in bxe_set_storm_rx_mode() argument
3721 rc = bxe_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags, in bxe_set_storm_rx_mode()
3731 return (bxe_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags, in bxe_set_storm_rx_mode()
3738 bxe_nic_load_no_mcp(struct bxe_softc *sc) in bxe_nic_load_no_mcp() argument
3740 int path = SC_PATH(sc); in bxe_nic_load_no_mcp()
3741 int port = SC_PORT(sc); in bxe_nic_load_no_mcp()
3743 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n", in bxe_nic_load_no_mcp()
3748 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n", in bxe_nic_load_no_mcp()
3762 bxe_nic_unload_no_mcp(struct bxe_softc *sc) in bxe_nic_unload_no_mcp() argument
3764 int port = SC_PORT(sc); in bxe_nic_unload_no_mcp()
3765 int path = SC_PATH(sc); in bxe_nic_unload_no_mcp()
3767 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n", in bxe_nic_unload_no_mcp()
3772 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n", in bxe_nic_unload_no_mcp()
3786 bxe_send_unload_req(struct bxe_softc *sc, in bxe_send_unload_req() argument
3799 if (!BXE_NOMCP(sc)) { in bxe_send_unload_req()
3800 reset_code = bxe_fw_command(sc, reset_code, 0); in bxe_send_unload_req()
3802 reset_code = bxe_nic_unload_no_mcp(sc); in bxe_send_unload_req()
3810 bxe_send_unload_done(struct bxe_softc *sc, in bxe_send_unload_done() argument
3817 if (!BXE_NOMCP(sc)) { in bxe_send_unload_done()
3818 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param); in bxe_send_unload_done()
3823 bxe_func_wait_started(struct bxe_softc *sc) in bxe_func_wait_started() argument
3827 if (!sc->port.pmf) { in bxe_func_wait_started()
3850 while (ecore_func_get_state(sc, &sc->func_obj) != in bxe_func_wait_started()
3855 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) { in bxe_func_wait_started()
3862 BLOGE(sc, "Unexpected function state! " in bxe_func_wait_started()
3865 func_params.f_obj = &sc->func_obj; in bxe_func_wait_started()
3870 ecore_func_state_change(sc, &func_params); in bxe_func_wait_started()
3874 return (ecore_func_state_change(sc, &func_params)); in bxe_func_wait_started()
3881 bxe_stop_queue(struct bxe_softc *sc, in bxe_stop_queue() argument
3884 struct bxe_fastpath *fp = &sc->fp[index]; in bxe_stop_queue()
3888 BLOGD(sc, DBG_LOAD, "stopping queue %d cid %d\n", index, fp->index); in bxe_stop_queue()
3890 q_params.q_obj = &sc->sp_objs[fp->index].q_obj; in bxe_stop_queue()
3898 rc = ecore_queue_state_change(sc, &q_params); in bxe_stop_queue()
3907 rc = ecore_queue_state_change(sc, &q_params); in bxe_stop_queue()
3916 return (ecore_queue_state_change(sc, &q_params)); in bxe_stop_queue()
3921 bxe_wait_sp_comp(struct bxe_softc *sc, in bxe_wait_sp_comp() argument
3929 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) { in bxe_wait_sp_comp()
3938 tmp = atomic_load_acq_long(&sc->sp_state); in bxe_wait_sp_comp()
3940 BLOGE(sc, "Filtering completion timed out: " in bxe_wait_sp_comp()
3950 bxe_func_stop(struct bxe_softc *sc) in bxe_func_stop() argument
3957 func_params.f_obj = &sc->func_obj; in bxe_func_stop()
3966 rc = ecore_func_state_change(sc, &func_params); in bxe_func_stop()
3968 BLOGE(sc, "FUNC_STOP ramrod failed. " in bxe_func_stop()
3971 return (ecore_func_state_change(sc, &func_params)); in bxe_func_stop()
3978 bxe_reset_hw(struct bxe_softc *sc, in bxe_reset_hw() argument
3986 func_params.f_obj = &sc->func_obj; in bxe_reset_hw()
3991 return (ecore_func_state_change(sc, &func_params)); in bxe_reset_hw()
3995 bxe_int_disable_sync(struct bxe_softc *sc, in bxe_int_disable_sync() argument
4000 bxe_int_disable(sc); in bxe_int_disable_sync()
4011 bxe_chip_cleanup(struct bxe_softc *sc, in bxe_chip_cleanup() argument
4015 int port = SC_PORT(sc); in bxe_chip_cleanup()
4020 bxe_drain_tx_queues(sc); in bxe_chip_cleanup()
4026 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC, FALSE); in bxe_chip_cleanup()
4028 BLOGE(sc, "Failed to delete all ETH MACs (%d)\n", rc); in bxe_chip_cleanup()
4032 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC, TRUE); in bxe_chip_cleanup()
4034 BLOGE(sc, "Failed to delete UC MACs list (%d)\n", rc); in bxe_chip_cleanup()
4038 if (!CHIP_IS_E1(sc)) { in bxe_chip_cleanup()
4039 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bxe_chip_cleanup()
4048 BXE_MCAST_LOCK(sc); in bxe_chip_cleanup()
4050 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) { in bxe_chip_cleanup()
4051 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); in bxe_chip_cleanup()
4053 bxe_set_storm_rx_mode(sc); in bxe_chip_cleanup()
4057 rparam.mcast_obj = &sc->mcast_obj; in bxe_chip_cleanup()
4058 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); in bxe_chip_cleanup()
4060 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc); in bxe_chip_cleanup()
4063 BXE_MCAST_UNLOCK(sc); in bxe_chip_cleanup()
4072 reset_code = bxe_send_unload_req(sc, unload_mode); in bxe_chip_cleanup()
4078 rc = bxe_func_wait_started(sc); in bxe_chip_cleanup()
4080 BLOGE(sc, "bxe_func_wait_started failed (%d)\n", rc); in bxe_chip_cleanup()
4087 for (i = 0; i < sc->num_queues; i++) { in bxe_chip_cleanup()
4088 if (bxe_stop_queue(sc, i)) { in bxe_chip_cleanup()
4097 if (!bxe_wait_sp_comp(sc, ~0x0UL)) { in bxe_chip_cleanup()
4098 BLOGE(sc, "Common slow path ramrods got stuck!(%d)\n", rc); in bxe_chip_cleanup()
4103 rc = bxe_func_stop(sc); in bxe_chip_cleanup()
4105 BLOGE(sc, "Function stop failed!(%d)\n", rc); in bxe_chip_cleanup()
4109 bxe_int_disable_sync(sc, TRUE); in bxe_chip_cleanup()
4112 bxe_interrupt_detach(sc); in bxe_chip_cleanup()
4115 rc = bxe_reset_hw(sc, reset_code); in bxe_chip_cleanup()
4117 BLOGE(sc, "Hardware reset failed(%d)\n", rc); in bxe_chip_cleanup()
4121 bxe_send_unload_done(sc, keep_link); in bxe_chip_cleanup()
4125 bxe_disable_close_the_gate(struct bxe_softc *sc) in bxe_disable_close_the_gate() argument
4128 int port = SC_PORT(sc); in bxe_disable_close_the_gate()
4130 BLOGD(sc, DBG_LOAD, in bxe_disable_close_the_gate()
4133 if (CHIP_IS_E1(sc)) { in bxe_disable_close_the_gate()
4136 val = REG_RD(sc, addr); in bxe_disable_close_the_gate()
4138 REG_WR(sc, addr, val); in bxe_disable_close_the_gate()
4140 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK); in bxe_disable_close_the_gate()
4143 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val); in bxe_disable_close_the_gate()
4152 bxe_squeeze_objects(struct bxe_softc *sc) in bxe_squeeze_objects() argument
4156 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj; in bxe_squeeze_objects()
4168 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags, in bxe_squeeze_objects()
4171 BLOGE(sc, "Failed to clean ETH MACs (%d)\n", rc); in bxe_squeeze_objects()
4177 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, in bxe_squeeze_objects()
4180 BLOGE(sc, "Failed to clean UC list MACs (%d)\n", rc); in bxe_squeeze_objects()
4185 rparam.mcast_obj = &sc->mcast_obj; in bxe_squeeze_objects()
4189 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); in bxe_squeeze_objects()
4191 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc); in bxe_squeeze_objects()
4196 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); in bxe_squeeze_objects()
4199 BLOGE(sc, "Failed to clean MCAST object (%d)\n", rc); in bxe_squeeze_objects()
4203 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); in bxe_squeeze_objects()
4209 bxe_nic_unload(struct bxe_softc *sc, in bxe_nic_unload() argument
4217 BXE_CORE_LOCK_ASSERT(sc); in bxe_nic_unload()
4219 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING); in bxe_nic_unload()
4221 for (i = 0; i < sc->num_queues; i++) { in bxe_nic_unload()
4224 fp = &sc->fp[i]; in bxe_nic_unload()
4230 BLOGD(sc, DBG_LOAD, "Starting NIC unload...\n"); in bxe_nic_unload()
4233 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) { in bxe_nic_unload()
4234 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]); in bxe_nic_unload()
4235 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)], in bxe_nic_unload()
4239 if (IS_PF(sc) && sc->recovery_state != BXE_RECOVERY_DONE && in bxe_nic_unload()
4240 (sc->state == BXE_STATE_CLOSED || sc->state == BXE_STATE_ERROR)) { in bxe_nic_unload()
4242 if(CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) { in bxe_nic_unload()
4251 sc->recovery_state = BXE_RECOVERY_DONE; in bxe_nic_unload()
4252 sc->is_leader = 0; in bxe_nic_unload()
4253 bxe_release_leader_lock(sc); in bxe_nic_unload()
4255 BLOGD(sc, DBG_LOAD, "Releasing a leadership...\n"); in bxe_nic_unload()
4257 BLOGE(sc, "Can't unload in closed or error state recover_state 0x%x" in bxe_nic_unload()
4258 " state = 0x%x\n", sc->recovery_state, sc->state); in bxe_nic_unload()
4266 if ((sc->state == BXE_STATE_CLOSED) || in bxe_nic_unload()
4267 (sc->state == BXE_STATE_ERROR)) { in bxe_nic_unload()
4271 sc->state = BXE_STATE_CLOSING_WAITING_HALT; in bxe_nic_unload()
4275 bxe_tx_disable(sc); in bxe_nic_unload()
4277 sc->rx_mode = BXE_RX_MODE_NONE; in bxe_nic_unload()
4280 if (IS_PF(sc) && !sc->grcdump_done) { in bxe_nic_unload()
4282 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE; in bxe_nic_unload()
4284 bxe_drv_pulse(sc); in bxe_nic_unload()
4286 bxe_stats_handle(sc, STATS_EVENT_STOP); in bxe_nic_unload()
4287 bxe_save_statistics(sc); in bxe_nic_unload()
4291 bxe_drain_tx_queues(sc); in bxe_nic_unload()
4296 if (IS_VF(sc)) { in bxe_nic_unload()
4300 if (!sc->grcdump_done) in bxe_nic_unload()
4301 bxe_chip_cleanup(sc, unload_mode, keep_link); in bxe_nic_unload()
4304 bxe_send_unload_req(sc, unload_mode); in bxe_nic_unload()
4313 if (!CHIP_IS_E1x(sc)) { in bxe_nic_unload()
4314 bxe_pf_disable(sc); in bxe_nic_unload()
4318 bxe_int_disable_sync(sc, TRUE); in bxe_nic_unload()
4321 bxe_interrupt_detach(sc); in bxe_nic_unload()
4324 bxe_send_unload_done(sc, FALSE); in bxe_nic_unload()
4331 if (IS_PF(sc)) { in bxe_nic_unload()
4332 bxe_squeeze_objects(sc); in bxe_nic_unload()
4336 sc->sp_state = 0; in bxe_nic_unload()
4338 sc->port.pmf = 0; in bxe_nic_unload()
4340 bxe_free_fp_buffers(sc); in bxe_nic_unload()
4342 if (IS_PF(sc)) { in bxe_nic_unload()
4343 bxe_free_mem(sc); in bxe_nic_unload()
4346 bxe_free_fw_stats_mem(sc); in bxe_nic_unload()
4348 sc->state = BXE_STATE_CLOSED; in bxe_nic_unload()
4354 if (IS_PF(sc) && bxe_chk_parity_attn(sc, &global, FALSE)) { in bxe_nic_unload()
4355 bxe_set_reset_in_progress(sc); in bxe_nic_unload()
4359 bxe_set_reset_global(sc); in bxe_nic_unload()
4367 if (IS_PF(sc) && !bxe_clear_pf_load(sc) && in bxe_nic_unload()
4368 bxe_reset_is_done(sc, SC_PATH(sc))) { in bxe_nic_unload()
4369 bxe_disable_close_the_gate(sc); in bxe_nic_unload()
4372 BLOGD(sc, DBG_LOAD, "Ended NIC unload\n"); in bxe_nic_unload()
4374 bxe_link_report(sc); in bxe_nic_unload()
4386 struct bxe_softc *sc = (struct bxe_softc *)if_getsoftc(ifp); in bxe_ifmedia_update() local
4389 ifm = &sc->ifmedia; in bxe_ifmedia_update()
4405 BLOGD(sc, DBG_LOAD, "Invalid media type (%d)\n", in bxe_ifmedia_update()
4419 struct bxe_softc *sc = if_getsoftc(ifp); in bxe_ifmedia_status() local
4435 BLOGD(sc, DBG_PHY, "in %s : nic still not loaded fully\n", __func__); in bxe_ifmedia_status()
4436 BLOGD(sc, DBG_PHY, "in %s : link_up (1) : %d\n", in bxe_ifmedia_status()
4437 __func__, sc->link_vars.link_up); in bxe_ifmedia_status()
4442 if (sc->link_vars.link_up) { in bxe_ifmedia_status()
4447 BLOGD(sc, DBG_PHY, "in %s : setting IFM_NONE\n", in bxe_ifmedia_status()
4452 ifmr->ifm_active |= sc->media; in bxe_ifmedia_status()
4460 struct bxe_softc *sc = (struct bxe_softc *)context; in bxe_handle_chip_tq() local
4461 long work = atomic_load_acq_long(&sc->chip_tq_flags); in bxe_handle_chip_tq()
4467 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) { in bxe_handle_chip_tq()
4469 BLOGD(sc, DBG_LOAD, "Restarting the interface...\n"); in bxe_handle_chip_tq()
4470 bxe_periodic_stop(sc); in bxe_handle_chip_tq()
4471 BXE_CORE_LOCK(sc); in bxe_handle_chip_tq()
4472 bxe_stop_locked(sc); in bxe_handle_chip_tq()
4473 bxe_init_locked(sc); in bxe_handle_chip_tq()
4474 BXE_CORE_UNLOCK(sc); in bxe_handle_chip_tq()
4494 struct bxe_softc *sc = if_getsoftc(ifp); in bxe_ioctl() local
4506 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFMTU ioctl (mtu=%d)\n", in bxe_ioctl()
4509 if (sc->mtu == ifr->ifr_mtu) { in bxe_ioctl()
4515 BLOGE(sc, "Unsupported MTU size %d (range is %d-%d)\n", in bxe_ioctl()
4521 atomic_store_rel_int((volatile unsigned int *)&sc->mtu, in bxe_ioctl()
4534 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFFLAGS ioctl\n"); in bxe_ioctl()
4536 BXE_CORE_LOCK(sc); in bxe_ioctl()
4541 bxe_set_rx_mode(sc); in bxe_ioctl()
4542 } else if(sc->state != BXE_STATE_DISABLED) { in bxe_ioctl()
4543 bxe_init_locked(sc); in bxe_ioctl()
4547 bxe_periodic_stop(sc); in bxe_ioctl()
4548 bxe_stop_locked(sc); in bxe_ioctl()
4551 BXE_CORE_UNLOCK(sc); in bxe_ioctl()
4558 BLOGD(sc, DBG_IOCTL, "Received SIOCADDMULTI/SIOCDELMULTI ioctl\n"); in bxe_ioctl()
4563 BXE_CORE_LOCK(sc); in bxe_ioctl()
4564 bxe_set_rx_mode(sc); in bxe_ioctl()
4565 BXE_CORE_UNLOCK(sc); in bxe_ioctl()
4574 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFCAP ioctl (mask=0x%08x)\n", in bxe_ioctl()
4580 BLOGD(sc, DBG_IOCTL, "Turning LRO %s\n", in bxe_ioctl()
4588 BLOGD(sc, DBG_IOCTL, "Turning TXCSUM %s\n", in bxe_ioctl()
4605 BLOGD(sc, DBG_IOCTL, "Turning RXCSUM %s\n", in bxe_ioctl()
4622 BLOGD(sc, DBG_IOCTL, "Turning TSO4 %s\n", in bxe_ioctl()
4629 BLOGD(sc, DBG_IOCTL, "Turning TSO6 %s\n", in bxe_ioctl()
4637 BLOGD(sc, DBG_IOCTL, "Turning VLAN_HWTSO %s\n", in bxe_ioctl()
4644 BLOGE(sc, "Changing VLAN_HWCSUM is not supported!\n"); in bxe_ioctl()
4651 BLOGE(sc, "Changing VLAN_MTU is not supported!\n"); in bxe_ioctl()
4658 BLOGE(sc, "Changing VLAN_HWTAGGING is not supported!\n"); in bxe_ioctl()
4665 BLOGE(sc, "Changing VLAN_HWFILTER is not supported!\n"); in bxe_ioctl()
4678 BLOGD(sc, DBG_IOCTL, in bxe_ioctl()
4681 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); in bxe_ioctl()
4685 BLOGD(sc, DBG_IOCTL, "Received Unknown Ioctl (cmd=%lu)\n", in bxe_ioctl()
4691 if (reinit && (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING)) { in bxe_ioctl()
4692 BLOGD(sc, DBG_LOAD | DBG_IOCTL, in bxe_ioctl()
4694 bxe_periodic_stop(sc); in bxe_ioctl()
4695 BXE_CORE_LOCK(sc); in bxe_ioctl()
4696 bxe_stop_locked(sc); in bxe_ioctl()
4697 bxe_init_locked(sc); in bxe_ioctl()
4698 BXE_CORE_UNLOCK(sc); in bxe_ioctl()
4705 bxe_dump_mbuf(struct bxe_softc *sc, in bxe_dump_mbuf() argument
4712 if (!(sc->debug & DBG_MBUF)) { in bxe_dump_mbuf()
4717 BLOGD(sc, DBG_MBUF, "mbuf: null pointer\n"); in bxe_dump_mbuf()
4723 BLOGD(sc, DBG_MBUF, in bxe_dump_mbuf()
4728 BLOGD(sc, DBG_MBUF, in bxe_dump_mbuf()
4750 BLOGD(sc, DBG_MBUF, in bxe_dump_mbuf()
4756 bxe_dump_mbuf_data(sc, "mbuf data", m, TRUE); in bxe_dump_mbuf()
4772 bxe_chktso_window(struct bxe_softc *sc, in bxe_chktso_window() argument
5104 struct bxe_softc *sc; in bxe_tx_encap() local
5112 sc = fp->sc; in bxe_tx_encap()
5160 BLOGE(sc, "Unknown TX mapping error rc=%d\n", error); in bxe_tx_encap()
5161 bxe_dump_mbuf(sc, m0, FALSE); in bxe_tx_encap()
5168 tx_bd_avail = bxe_tx_avail(sc, fp); in bxe_tx_encap()
5192 if (bxe_chktso_window(sc, nsegs, segs, m0) == 0) { in bxe_tx_encap()
5274 BLOGD(sc, DBG_TX, in bxe_tx_encap()
5296 if (IS_VF(sc)) { in bxe_tx_encap()
5334 if (!CHIP_IS_E1x(sc)) { in bxe_tx_encap()
5383 BLOGD(sc, DBG_TX, in bxe_tx_encap()
5391 if (!CHIP_IS_E1x(sc)) { in bxe_tx_encap()
5415 BLOGD(sc, DBG_TX, "last bd %p\n", tx_data_bd); in bxe_tx_encap()
5421 if (__predict_false(sc->debug & DBG_TX)) { in bxe_tx_encap()
5426 BLOGD(sc, DBG_TX, in bxe_tx_encap()
5437 BLOGD(sc, DBG_TX, in bxe_tx_encap()
5452 BLOGD(sc, DBG_TX, in bxe_tx_encap()
5469 BLOGD(sc, DBG_TX, in bxe_tx_encap()
5482 BLOGD(sc, DBG_TX, "doorbell: nbds=%d bd=%u\n", nbds, bd_prod); in bxe_tx_encap()
5504 DOORBELL(sc, fp->index, fp->tx_db.raw); in bxe_tx_encap()
5509 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, in bxe_tx_encap()
5513 bus_space_barrier(sc->bar[BAR2].tag, sc->bar[BAR2].handle, in bxe_tx_encap()
5520 bxe_tx_start_locked(struct bxe_softc *sc, in bxe_tx_start_locked() argument
5570 tx_bd_avail = bxe_tx_avail(sc, fp); in bxe_tx_start_locked()
5575 bxe_txeof(sc, fp); in bxe_tx_start_locked()
5593 struct bxe_softc *sc; in bxe_tx_start() local
5596 sc = if_getsoftc(ifp); in bxe_tx_start()
5599 BLOGW(sc, "Interface not running, ignoring transmit request\n"); in bxe_tx_start()
5603 if (!sc->link_vars.link_up) { in bxe_tx_start()
5604 BLOGW(sc, "Interface link is down, ignoring transmit request\n"); in bxe_tx_start()
5608 fp = &sc->fp[0]; in bxe_tx_start()
5616 bxe_tx_start_locked(sc, ifp, fp); in bxe_tx_start()
5621 bxe_tx_mq_start_locked(struct bxe_softc *sc, in bxe_tx_mq_start_locked() argument
5635 if (sc->state != BXE_STATE_OPEN) { in bxe_tx_mq_start_locked()
5641 BLOGE(sc, "Multiqueue TX and no buf_ring!\n"); in bxe_tx_mq_start_locked()
5653 if (!sc->link_vars.link_up || !(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { in bxe_tx_mq_start_locked()
5667 tx_bd_avail = bxe_tx_avail(sc, fp); in bxe_tx_mq_start_locked()
5670 bxe_txeof(sc, fp); in bxe_tx_mq_start_locked()
5671 tx_bd_avail = bxe_tx_avail(sc, fp); in bxe_tx_mq_start_locked()
5735 struct bxe_softc *sc = fp->sc; in bxe_tx_mq_start_deferred() local
5736 if_t ifp = sc->ifp; in bxe_tx_mq_start_deferred()
5739 bxe_tx_mq_start_locked(sc, ifp, fp, NULL); in bxe_tx_mq_start_deferred()
5748 struct bxe_softc *sc = if_getsoftc(ifp); in bxe_tx_mq_start() local
5757 fp_index = (m->m_pkthdr.flowid % sc->num_queues); in bxe_tx_mq_start()
5759 fp = &sc->fp[fp_index]; in bxe_tx_mq_start()
5761 if (sc->state != BXE_STATE_OPEN) { in bxe_tx_mq_start()
5767 rc = bxe_tx_mq_start_locked(sc, ifp, fp, m); in bxe_tx_mq_start()
5780 struct bxe_softc *sc = if_getsoftc(ifp); in bxe_mq_flush() local
5785 for (i = 0; i < sc->num_queues; i++) { in bxe_mq_flush()
5786 fp = &sc->fp[i]; in bxe_mq_flush()
5789 BLOGD(sc, DBG_LOAD, "Not clearing fp[%02d] buf_ring (state=%d)\n", in bxe_mq_flush()
5795 BLOGD(sc, DBG_LOAD, "Clearing fp[%02d] buf_ring\n", fp->index); in bxe_mq_flush()
5808 bxe_cid_ilt_lines(struct bxe_softc *sc) in bxe_cid_ilt_lines() argument
5810 if (IS_SRIOV(sc)) { in bxe_cid_ilt_lines()
5813 return (L2_ILT_LINES(sc)); in bxe_cid_ilt_lines()
5817 bxe_ilt_set_info(struct bxe_softc *sc) in bxe_ilt_set_info() argument
5820 struct ecore_ilt *ilt = sc->ilt; in bxe_ilt_set_info()
5823 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc)); in bxe_ilt_set_info()
5824 BLOGD(sc, DBG_LOAD, "ilt starts at line %d\n", ilt->start_line); in bxe_ilt_set_info()
5832 line += bxe_cid_ilt_lines(sc); in bxe_ilt_set_info()
5834 if (CNIC_SUPPORT(sc)) { in bxe_ilt_set_info()
5840 BLOGD(sc, DBG_LOAD, in bxe_ilt_set_info()
5849 if (QM_INIT(sc->qm_cid_count)) { in bxe_ilt_set_info()
5857 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4, in bxe_ilt_set_info()
5862 BLOGD(sc, DBG_LOAD, in bxe_ilt_set_info()
5870 if (CNIC_SUPPORT(sc)) { in bxe_ilt_set_info()
5880 BLOGD(sc, DBG_LOAD, in bxe_ilt_set_info()
5896 BLOGD(sc, DBG_LOAD, in bxe_ilt_set_info()
5908 bxe_set_fp_rx_buf_size(struct bxe_softc *sc) in bxe_set_fp_rx_buf_size() argument
5913 rx_buf_size = (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu); in bxe_set_fp_rx_buf_size()
5915 for (i = 0; i < sc->num_queues; i++) { in bxe_set_fp_rx_buf_size()
5917 sc->fp[i].rx_buf_size = rx_buf_size; in bxe_set_fp_rx_buf_size()
5918 sc->fp[i].mbuf_alloc_size = MCLBYTES; in bxe_set_fp_rx_buf_size()
5920 sc->fp[i].rx_buf_size = rx_buf_size; in bxe_set_fp_rx_buf_size()
5921 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE; in bxe_set_fp_rx_buf_size()
5923 sc->fp[i].rx_buf_size = MCLBYTES; in bxe_set_fp_rx_buf_size()
5924 sc->fp[i].mbuf_alloc_size = MCLBYTES; in bxe_set_fp_rx_buf_size()
5926 sc->fp[i].rx_buf_size = MJUMPAGESIZE; in bxe_set_fp_rx_buf_size()
5927 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE; in bxe_set_fp_rx_buf_size()
5929 sc->fp[i].rx_buf_size = MCLBYTES; in bxe_set_fp_rx_buf_size()
5930 sc->fp[i].mbuf_alloc_size = MCLBYTES; in bxe_set_fp_rx_buf_size()
5936 bxe_alloc_ilt_mem(struct bxe_softc *sc) in bxe_alloc_ilt_mem() argument
5940 if ((sc->ilt = in bxe_alloc_ilt_mem()
5951 bxe_alloc_ilt_lines_mem(struct bxe_softc *sc) in bxe_alloc_ilt_lines_mem() argument
5955 if ((sc->ilt->lines = in bxe_alloc_ilt_lines_mem()
5966 bxe_free_ilt_mem(struct bxe_softc *sc) in bxe_free_ilt_mem() argument
5968 if (sc->ilt != NULL) { in bxe_free_ilt_mem()
5969 free(sc->ilt, M_BXE_ILT); in bxe_free_ilt_mem()
5970 sc->ilt = NULL; in bxe_free_ilt_mem()
5975 bxe_free_ilt_lines_mem(struct bxe_softc *sc) in bxe_free_ilt_lines_mem() argument
5977 if (sc->ilt->lines != NULL) { in bxe_free_ilt_lines_mem()
5978 free(sc->ilt->lines, M_BXE_ILT); in bxe_free_ilt_lines_mem()
5979 sc->ilt->lines = NULL; in bxe_free_ilt_lines_mem()
5984 bxe_free_mem(struct bxe_softc *sc) in bxe_free_mem() argument
5988 for (i = 0; i < L2_ILT_LINES(sc); i++) { in bxe_free_mem()
5989 bxe_dma_free(sc, &sc->context[i].vcxt_dma); in bxe_free_mem()
5990 sc->context[i].vcxt = NULL; in bxe_free_mem()
5991 sc->context[i].size = 0; in bxe_free_mem()
5994 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE); in bxe_free_mem()
5996 bxe_free_ilt_lines_mem(sc); in bxe_free_mem()
6001 bxe_alloc_mem(struct bxe_softc *sc) in bxe_alloc_mem() argument
6022 context_size = (sizeof(union cdu_context) * BXE_L2_CID_COUNT(sc)); in bxe_alloc_mem()
6024 sc->context[i].size = min(CDU_ILT_PAGE_SZ, in bxe_alloc_mem()
6027 if (bxe_dma_alloc(sc, sc->context[i].size, in bxe_alloc_mem()
6028 &sc->context[i].vcxt_dma, in bxe_alloc_mem()
6030 bxe_free_mem(sc); in bxe_alloc_mem()
6034 sc->context[i].vcxt = in bxe_alloc_mem()
6035 (union cdu_context *)sc->context[i].vcxt_dma.vaddr; in bxe_alloc_mem()
6037 allocated += sc->context[i].size; in bxe_alloc_mem()
6040 bxe_alloc_ilt_lines_mem(sc); in bxe_alloc_mem()
6042 BLOGD(sc, DBG_LOAD, "ilt=%p start_line=%u lines=%p\n", in bxe_alloc_mem()
6043 sc->ilt, sc->ilt->start_line, sc->ilt->lines); in bxe_alloc_mem()
6046 BLOGD(sc, DBG_LOAD, in bxe_alloc_mem()
6049 sc->ilt->clients[i].page_size, in bxe_alloc_mem()
6050 sc->ilt->clients[i].start, in bxe_alloc_mem()
6051 sc->ilt->clients[i].end, in bxe_alloc_mem()
6052 sc->ilt->clients[i].client_num, in bxe_alloc_mem()
6053 sc->ilt->clients[i].flags); in bxe_alloc_mem()
6056 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) { in bxe_alloc_mem()
6057 BLOGE(sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n"); in bxe_alloc_mem()
6058 bxe_free_mem(sc); in bxe_alloc_mem()
6095 struct bxe_softc *sc; in bxe_free_tpa_pool() local
6098 sc = fp->sc; in bxe_free_tpa_pool()
6104 max_agg_queues = MAX_AGG_QS(sc); in bxe_free_tpa_pool()
6152 bxe_free_fp_buffers(struct bxe_softc *sc) in bxe_free_fp_buffers() argument
6157 for (i = 0; i < sc->num_queues; i++) { in bxe_free_fp_buffers()
6158 fp = &sc->fp[i]; in bxe_free_fp_buffers()
6178 BLOGE(sc, "failed to claim all rx mbufs (%d left)\n", in bxe_free_fp_buffers()
6183 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n", in bxe_free_fp_buffers()
6188 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n", in bxe_free_fp_buffers()
6193 BLOGE(sc, "failed to release tx mbufs (%d left)\n", in bxe_free_fp_buffers()
6409 bxe_alloc_fp_buffers(struct bxe_softc *sc) in bxe_alloc_fp_buffers() argument
6416 for (i = 0; i < sc->num_queues; i++) { in bxe_alloc_fp_buffers()
6417 fp = &sc->fp[i]; in bxe_alloc_fp_buffers()
6424 for (j = 0; j < sc->max_rx_bufs; j++) { in bxe_alloc_fp_buffers()
6427 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n", in bxe_alloc_fp_buffers()
6440 max_agg_queues = MAX_AGG_QS(sc); in bxe_alloc_fp_buffers()
6448 BLOGE(sc, "mbuf alloc fail for fp[%02d] TPA queue %d\n", in bxe_alloc_fp_buffers()
6463 BLOGE(sc, "mbuf alloc fail for fp[%02d] SGE %d\n", in bxe_alloc_fp_buffers()
6490 bxe_free_fw_stats_mem(struct bxe_softc *sc) in bxe_free_fw_stats_mem() argument
6492 bxe_dma_free(sc, &sc->fw_stats_dma); in bxe_free_fw_stats_mem()
6494 sc->fw_stats_num = 0; in bxe_free_fw_stats_mem()
6496 sc->fw_stats_req_size = 0; in bxe_free_fw_stats_mem()
6497 sc->fw_stats_req = NULL; in bxe_free_fw_stats_mem()
6498 sc->fw_stats_req_mapping = 0; in bxe_free_fw_stats_mem()
6500 sc->fw_stats_data_size = 0; in bxe_free_fw_stats_mem()
6501 sc->fw_stats_data = NULL; in bxe_free_fw_stats_mem()
6502 sc->fw_stats_data_mapping = 0; in bxe_free_fw_stats_mem()
6506 bxe_alloc_fw_stats_mem(struct bxe_softc *sc) in bxe_alloc_fw_stats_mem() argument
6512 num_queue_stats = BXE_NUM_ETH_QUEUES(sc); in bxe_alloc_fw_stats_mem()
6518 sc->fw_stats_num = (2 + num_queue_stats); in bxe_alloc_fw_stats_mem()
6527 ((sc->fw_stats_num / STATS_QUERY_CMD_COUNT) + in bxe_alloc_fw_stats_mem()
6528 ((sc->fw_stats_num % STATS_QUERY_CMD_COUNT) ? 1 : 0)); in bxe_alloc_fw_stats_mem()
6530 BLOGD(sc, DBG_LOAD, "stats fw_stats_num %d num_groups %d\n", in bxe_alloc_fw_stats_mem()
6531 sc->fw_stats_num, num_groups); in bxe_alloc_fw_stats_mem()
6533 sc->fw_stats_req_size = in bxe_alloc_fw_stats_mem()
6545 sc->fw_stats_data_size = in bxe_alloc_fw_stats_mem()
6552 if (bxe_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size), in bxe_alloc_fw_stats_mem()
6553 &sc->fw_stats_dma, "fw stats") != 0) { in bxe_alloc_fw_stats_mem()
6554 bxe_free_fw_stats_mem(sc); in bxe_alloc_fw_stats_mem()
6560 sc->fw_stats_req = in bxe_alloc_fw_stats_mem()
6561 (struct bxe_fw_stats_req *)sc->fw_stats_dma.vaddr; in bxe_alloc_fw_stats_mem()
6562 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr; in bxe_alloc_fw_stats_mem()
6564 sc->fw_stats_data = in bxe_alloc_fw_stats_mem()
6565 (struct bxe_fw_stats_data *)((uint8_t *)sc->fw_stats_dma.vaddr + in bxe_alloc_fw_stats_mem()
6566 sc->fw_stats_req_size); in bxe_alloc_fw_stats_mem()
6567 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr + in bxe_alloc_fw_stats_mem()
6568 sc->fw_stats_req_size); in bxe_alloc_fw_stats_mem()
6570 BLOGD(sc, DBG_LOAD, "statistics request base address set to %#jx\n", in bxe_alloc_fw_stats_mem()
6571 (uintmax_t)sc->fw_stats_req_mapping); in bxe_alloc_fw_stats_mem()
6573 BLOGD(sc, DBG_LOAD, "statistics data base address set to %#jx\n", in bxe_alloc_fw_stats_mem()
6574 (uintmax_t)sc->fw_stats_data_mapping); in bxe_alloc_fw_stats_mem()
6603 bxe_set_reset_global(struct bxe_softc *sc) in bxe_set_reset_global() argument
6606 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_set_reset_global()
6607 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_set_reset_global()
6608 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT); in bxe_set_reset_global()
6609 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_set_reset_global()
6614 bxe_clear_reset_global(struct bxe_softc *sc) in bxe_clear_reset_global() argument
6617 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_clear_reset_global()
6618 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_clear_reset_global()
6619 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT)); in bxe_clear_reset_global()
6620 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_clear_reset_global()
6625 bxe_reset_is_global(struct bxe_softc *sc) in bxe_reset_is_global() argument
6627 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_reset_is_global()
6628 BLOGD(sc, DBG_LOAD, "GLOB_REG=0x%08x\n", val); in bxe_reset_is_global()
6634 bxe_set_reset_done(struct bxe_softc *sc) in bxe_set_reset_done() argument
6637 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT : in bxe_set_reset_done()
6640 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_set_reset_done()
6642 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_set_reset_done()
6645 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); in bxe_set_reset_done()
6647 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_set_reset_done()
6652 bxe_set_reset_in_progress(struct bxe_softc *sc) in bxe_set_reset_in_progress() argument
6655 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT : in bxe_set_reset_in_progress()
6658 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_set_reset_in_progress()
6660 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_set_reset_in_progress()
6663 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); in bxe_set_reset_in_progress()
6665 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_set_reset_in_progress()
6670 bxe_reset_is_done(struct bxe_softc *sc, in bxe_reset_is_done() argument
6673 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_reset_is_done()
6683 bxe_get_load_status(struct bxe_softc *sc, in bxe_get_load_status() argument
6690 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_get_load_status()
6692 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val); in bxe_get_load_status()
6696 BLOGD(sc, DBG_LOAD, "Load mask engine %d = 0x%08x\n", engine, val); in bxe_get_load_status()
6704 bxe_set_pf_load(struct bxe_softc *sc) in bxe_set_pf_load() argument
6708 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK : in bxe_set_pf_load()
6710 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT : in bxe_set_pf_load()
6713 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_set_pf_load()
6715 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_set_pf_load()
6716 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val); in bxe_set_pf_load()
6722 val1 |= (1 << SC_ABS_FUNC(sc)); in bxe_set_pf_load()
6730 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); in bxe_set_pf_load()
6732 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_set_pf_load()
6738 bxe_clear_pf_load(struct bxe_softc *sc) in bxe_clear_pf_load() argument
6741 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK : in bxe_clear_pf_load()
6743 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT : in bxe_clear_pf_load()
6746 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_clear_pf_load()
6747 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_clear_pf_load()
6748 BLOGD(sc, DBG_LOAD, "Old GEN_REG_VAL=0x%08x\n", val); in bxe_clear_pf_load()
6754 val1 &= ~(1 << SC_ABS_FUNC(sc)); in bxe_clear_pf_load()
6762 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); in bxe_clear_pf_load()
6763 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); in bxe_clear_pf_load()
6769 bxe_nic_load_request(struct bxe_softc *sc, in bxe_nic_load_request() argument
6773 sc->fw_seq = in bxe_nic_load_request()
6774 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) & in bxe_nic_load_request()
6777 BLOGD(sc, DBG_LOAD, "initial fw_seq 0x%04x\n", sc->fw_seq); in bxe_nic_load_request()
6780 sc->fw_drv_pulse_wr_seq = in bxe_nic_load_request()
6781 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) & in bxe_nic_load_request()
6784 BLOGD(sc, DBG_LOAD, "initial drv_pulse 0x%04x\n", in bxe_nic_load_request()
6785 sc->fw_drv_pulse_wr_seq); in bxe_nic_load_request()
6788 (*load_code) = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ, in bxe_nic_load_request()
6793 BLOGE(sc, "MCP response failure!\n"); in bxe_nic_load_request()
6799 BLOGE(sc, "MCP refused load request\n"); in bxe_nic_load_request()
6812 bxe_nic_load_analyze_req(struct bxe_softc *sc, in bxe_nic_load_analyze_req() argument
6827 loaded_fw = REG_RD(sc, XSEM_REG_PRAM); in bxe_nic_load_analyze_req()
6828 BLOGD(sc, DBG_LOAD, "loaded FW 0x%08x / my FW 0x%08x\n", in bxe_nic_load_analyze_req()
6833 BLOGE(sc, "FW 0x%08x already loaded (mine is 0x%08x)", in bxe_nic_load_analyze_req()
6844 bxe_nic_load_pmf(struct bxe_softc *sc, in bxe_nic_load_pmf() argument
6856 sc->port.pmf = 1; in bxe_nic_load_pmf()
6859 sc->port.pmf = 0; in bxe_nic_load_pmf()
6862 BLOGD(sc, DBG_LOAD, "pmf %d\n", sc->port.pmf); in bxe_nic_load_pmf()
6866 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) { in bxe_nic_load_pmf()
6867 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr); in bxe_nic_load_pmf()
6869 REG_WR(sc, in bxe_nic_load_pmf()
6879 bxe_read_mf_cfg(struct bxe_softc *sc) in bxe_read_mf_cfg() argument
6881 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1); in bxe_read_mf_cfg()
6885 if (BXE_NOMCP(sc)) { in bxe_read_mf_cfg()
6896 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { in bxe_read_mf_cfg()
6897 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc)); in bxe_read_mf_cfg()
6901 sc->devinfo.mf_info.mf_config[vn] = in bxe_read_mf_cfg()
6902 MFCFG_RD(sc, func_mf_config[abs_func].config); in bxe_read_mf_cfg()
6905 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & in bxe_read_mf_cfg()
6907 BLOGD(sc, DBG_LOAD, "mf_cfg function disabled\n"); in bxe_read_mf_cfg()
6908 sc->flags |= BXE_MF_FUNC_DIS; in bxe_read_mf_cfg()
6910 BLOGD(sc, DBG_LOAD, "mf_cfg function enabled\n"); in bxe_read_mf_cfg()
6911 sc->flags &= ~BXE_MF_FUNC_DIS; in bxe_read_mf_cfg()
6916 static int bxe_acquire_alr(struct bxe_softc *sc) in bxe_acquire_alr() argument
6922 REG_WR(sc, GRCBASE_MCP + 0x9c, val); in bxe_acquire_alr()
6923 val = REG_RD(sc, GRCBASE_MCP + 0x9c); in bxe_acquire_alr()
6931 BLOGE(sc, "Cannot acquire MCP access lock register\n"); in bxe_acquire_alr()
6939 static void bxe_release_alr(struct bxe_softc *sc) in bxe_release_alr() argument
6941 REG_WR(sc, GRCBASE_MCP + 0x9c, 0); in bxe_release_alr()
6945 bxe_fan_failure(struct bxe_softc *sc) in bxe_fan_failure() argument
6947 int port = SC_PORT(sc); in bxe_fan_failure()
6952 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config); in bxe_fan_failure()
6956 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config, in bxe_fan_failure()
6960 BLOGW(sc, "Fan Failure has caused the driver to shutdown " in bxe_fan_failure()
6966 bxe_panic(sc, ("Schedule task to handle fan failure\n")); in bxe_fan_failure()
6973 bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state); in bxe_fan_failure()
6974 schedule_delayed_work(&sc->sp_rtnl_task, 0); in bxe_fan_failure()
6980 bxe_link_attn(struct bxe_softc *sc) in bxe_link_attn() argument
6989 bxe_stats_handle(sc, STATS_EVENT_STOP); in bxe_link_attn()
6990 BLOGD(sc, DBG_LOAD, "link_vars phy_flags : %x\n", sc->link_vars.phy_flags); in bxe_link_attn()
6991 elink_link_update(&sc->link_params, &sc->link_vars); in bxe_link_attn()
6993 if (sc->link_vars.link_up) { in bxe_link_attn()
6996 if (!CHIP_IS_E1(sc) && sc->dropless_fc) { in bxe_link_attn()
6999 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) { in bxe_link_attn()
7003 REG_WR(sc, in bxe_link_attn()
7005 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))), in bxe_link_attn()
7009 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) { in bxe_link_attn()
7010 pstats = BXE_SP(sc, port_stats); in bxe_link_attn()
7015 if (sc->state == BXE_STATE_OPEN) { in bxe_link_attn()
7016 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); in bxe_link_attn()
7018 FOR_EACH_ETH_QUEUE(sc, i) { in bxe_link_attn()
7019 fp = &sc->fp[i]; in bxe_link_attn()
7026 if (sc->link_vars.link_up && sc->link_vars.line_speed) { in bxe_link_attn()
7027 cmng_fns = bxe_get_cmng_fns_mode(sc); in bxe_link_attn()
7030 bxe_cmng_fns_init(sc, FALSE, cmng_fns); in bxe_link_attn()
7031 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); in bxe_link_attn()
7034 BLOGD(sc, DBG_LOAD, "single function mode without fairness\n"); in bxe_link_attn()
7038 bxe_link_report_locked(sc); in bxe_link_attn()
7040 if (IS_MF(sc)) { in bxe_link_attn()
7046 bxe_attn_int_asserted(struct bxe_softc *sc, in bxe_attn_int_asserted() argument
7049 int port = SC_PORT(sc); in bxe_attn_int_asserted()
7060 if (sc->attn_state & asserted) { in bxe_attn_int_asserted()
7061 BLOGE(sc, "IGU ERROR attn=0x%08x\n", asserted); in bxe_attn_int_asserted()
7064 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bxe_attn_int_asserted()
7066 aeu_mask = REG_RD(sc, aeu_addr); in bxe_attn_int_asserted()
7068 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly asserted 0x%08x\n", in bxe_attn_int_asserted()
7073 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask); in bxe_attn_int_asserted()
7075 REG_WR(sc, aeu_addr, aeu_mask); in bxe_attn_int_asserted()
7077 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bxe_attn_int_asserted()
7079 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state); in bxe_attn_int_asserted()
7080 sc->attn_state |= asserted; in bxe_attn_int_asserted()
7081 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state); in bxe_attn_int_asserted()
7086 bxe_acquire_phy_lock(sc); in bxe_attn_int_asserted()
7088 nig_mask = REG_RD(sc, nig_int_mask_addr); in bxe_attn_int_asserted()
7092 REG_WR(sc, nig_int_mask_addr, 0); in bxe_attn_int_asserted()
7094 bxe_link_attn(sc); in bxe_attn_int_asserted()
7101 BLOGD(sc, DBG_INTR, "ATTN_SW_TIMER_4_FUNC!\n"); in bxe_attn_int_asserted()
7105 BLOGD(sc, DBG_INTR, "GPIO_2_FUNC!\n"); in bxe_attn_int_asserted()
7109 BLOGD(sc, DBG_INTR, "GPIO_3_FUNC!\n"); in bxe_attn_int_asserted()
7113 BLOGD(sc, DBG_INTR, "GPIO_4_FUNC!\n"); in bxe_attn_int_asserted()
7118 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_1!\n"); in bxe_attn_int_asserted()
7119 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); in bxe_attn_int_asserted()
7122 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_2!\n"); in bxe_attn_int_asserted()
7123 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); in bxe_attn_int_asserted()
7126 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_3!\n"); in bxe_attn_int_asserted()
7127 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); in bxe_attn_int_asserted()
7131 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_4!\n"); in bxe_attn_int_asserted()
7132 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); in bxe_attn_int_asserted()
7135 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_5!\n"); in bxe_attn_int_asserted()
7136 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); in bxe_attn_int_asserted()
7139 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_6!\n"); in bxe_attn_int_asserted()
7140 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); in bxe_attn_int_asserted()
7145 if (sc->devinfo.int_block == INT_BLOCK_HC) { in bxe_attn_int_asserted()
7151 BLOGD(sc, DBG_INTR, "about to mask 0x%08x at %s addr 0x%08x\n", in bxe_attn_int_asserted()
7153 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bxe_attn_int_asserted()
7154 REG_WR(sc, reg_addr, asserted); in bxe_attn_int_asserted()
7162 if (sc->devinfo.int_block != INT_BLOCK_HC) { in bxe_attn_int_asserted()
7166 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS); in bxe_attn_int_asserted()
7171 BLOGE(sc, "Failed to verify IGU ack on time\n"); in bxe_attn_int_asserted()
7177 REG_WR(sc, nig_int_mask_addr, nig_mask); in bxe_attn_int_asserted()
7179 bxe_release_phy_lock(sc); in bxe_attn_int_asserted()
7184 bxe_print_next_block(struct bxe_softc *sc, in bxe_print_next_block() argument
7188 BLOGI(sc, "%s%s", idx ? ", " : "", blk); in bxe_print_next_block()
7192 bxe_check_blocks_with_parity0(struct bxe_softc *sc, in bxe_check_blocks_with_parity0() argument
7206 bxe_print_next_block(sc, par_num++, "BRB"); in bxe_check_blocks_with_parity0()
7210 bxe_print_next_block(sc, par_num++, "PARSER"); in bxe_check_blocks_with_parity0()
7214 bxe_print_next_block(sc, par_num++, "TSDM"); in bxe_check_blocks_with_parity0()
7218 bxe_print_next_block(sc, par_num++, "SEARCHER"); in bxe_check_blocks_with_parity0()
7222 bxe_print_next_block(sc, par_num++, "TCM"); in bxe_check_blocks_with_parity0()
7226 bxe_print_next_block(sc, par_num++, "TSEMI"); in bxe_check_blocks_with_parity0()
7230 bxe_print_next_block(sc, par_num++, "XPB"); in bxe_check_blocks_with_parity0()
7243 bxe_check_blocks_with_parity1(struct bxe_softc *sc, in bxe_check_blocks_with_parity1() argument
7257 bxe_print_next_block(sc, par_num++, "PBF"); in bxe_check_blocks_with_parity1()
7261 bxe_print_next_block(sc, par_num++, "QM"); in bxe_check_blocks_with_parity1()
7265 bxe_print_next_block(sc, par_num++, "TM"); in bxe_check_blocks_with_parity1()
7269 bxe_print_next_block(sc, par_num++, "XSDM"); in bxe_check_blocks_with_parity1()
7273 bxe_print_next_block(sc, par_num++, "XCM"); in bxe_check_blocks_with_parity1()
7277 bxe_print_next_block(sc, par_num++, "XSEMI"); in bxe_check_blocks_with_parity1()
7281 bxe_print_next_block(sc, par_num++, "DOORBELLQ"); in bxe_check_blocks_with_parity1()
7285 bxe_print_next_block(sc, par_num++, "NIG"); in bxe_check_blocks_with_parity1()
7289 bxe_print_next_block(sc, par_num++, "VAUX PCI CORE"); in bxe_check_blocks_with_parity1()
7294 bxe_print_next_block(sc, par_num++, "DEBUG"); in bxe_check_blocks_with_parity1()
7298 bxe_print_next_block(sc, par_num++, "USDM"); in bxe_check_blocks_with_parity1()
7302 bxe_print_next_block(sc, par_num++, "UCM"); in bxe_check_blocks_with_parity1()
7306 bxe_print_next_block(sc, par_num++, "USEMI"); in bxe_check_blocks_with_parity1()
7310 bxe_print_next_block(sc, par_num++, "UPB"); in bxe_check_blocks_with_parity1()
7314 bxe_print_next_block(sc, par_num++, "CSDM"); in bxe_check_blocks_with_parity1()
7318 bxe_print_next_block(sc, par_num++, "CCM"); in bxe_check_blocks_with_parity1()
7331 bxe_check_blocks_with_parity2(struct bxe_softc *sc, in bxe_check_blocks_with_parity2() argument
7345 bxe_print_next_block(sc, par_num++, "CSEMI"); in bxe_check_blocks_with_parity2()
7349 bxe_print_next_block(sc, par_num++, "PXP"); in bxe_check_blocks_with_parity2()
7353 bxe_print_next_block(sc, par_num++, "PXPPCICLOCKCLIENT"); in bxe_check_blocks_with_parity2()
7357 bxe_print_next_block(sc, par_num++, "CFC"); in bxe_check_blocks_with_parity2()
7361 bxe_print_next_block(sc, par_num++, "CDU"); in bxe_check_blocks_with_parity2()
7365 bxe_print_next_block(sc, par_num++, "DMAE"); in bxe_check_blocks_with_parity2()
7369 bxe_print_next_block(sc, par_num++, "IGU"); in bxe_check_blocks_with_parity2()
7373 bxe_print_next_block(sc, par_num++, "MISC"); in bxe_check_blocks_with_parity2()
7386 bxe_check_blocks_with_parity3(struct bxe_softc *sc, in bxe_check_blocks_with_parity3() argument
7401 bxe_print_next_block(sc, par_num++, "MCP ROM"); in bxe_check_blocks_with_parity3()
7406 bxe_print_next_block(sc, par_num++, in bxe_check_blocks_with_parity3()
7412 bxe_print_next_block(sc, par_num++, in bxe_check_blocks_with_parity3()
7418 bxe_print_next_block(sc, par_num++, in bxe_check_blocks_with_parity3()
7433 bxe_check_blocks_with_parity4(struct bxe_softc *sc, in bxe_check_blocks_with_parity4() argument
7447 bxe_print_next_block(sc, par_num++, "PGLUE_B"); in bxe_check_blocks_with_parity4()
7451 bxe_print_next_block(sc, par_num++, "ATC"); in bxe_check_blocks_with_parity4()
7464 bxe_parity_attn(struct bxe_softc *sc, in bxe_parity_attn() argument
7476 BLOGE(sc, "Parity error: HW block parity attention:\n" in bxe_parity_attn()
7485 BLOGI(sc, "Parity errors detected in blocks: "); in bxe_parity_attn()
7488 bxe_check_blocks_with_parity0(sc, sig[0] & in bxe_parity_attn()
7492 bxe_check_blocks_with_parity1(sc, sig[1] & in bxe_parity_attn()
7496 bxe_check_blocks_with_parity2(sc, sig[2] & in bxe_parity_attn()
7500 bxe_check_blocks_with_parity3(sc, sig[3] & in bxe_parity_attn()
7504 bxe_check_blocks_with_parity4(sc, sig[4] & in bxe_parity_attn()
7509 BLOGI(sc, "\n"); in bxe_parity_attn()
7512 BXE_SET_ERROR_BIT(sc, BXE_ERR_GLOBAL); in bxe_parity_attn()
7522 bxe_chk_parity_attn(struct bxe_softc *sc, in bxe_chk_parity_attn() argument
7527 int port = SC_PORT(sc); in bxe_chk_parity_attn()
7529 if(sc->state != BXE_STATE_OPEN) in bxe_chk_parity_attn()
7532 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); in bxe_chk_parity_attn()
7533 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); in bxe_chk_parity_attn()
7534 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); in bxe_chk_parity_attn()
7535 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); in bxe_chk_parity_attn()
7541 attn.sig[3] &= ((REG_RD(sc, (!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 in bxe_chk_parity_attn()
7547 if (!CHIP_IS_E1x(sc)) in bxe_chk_parity_attn()
7548 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); in bxe_chk_parity_attn()
7550 return (bxe_parity_attn(sc, global, print, attn.sig)); in bxe_chk_parity_attn()
7554 bxe_attn_int_deasserted4(struct bxe_softc *sc, in bxe_attn_int_deasserted4() argument
7561 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); in bxe_attn_int_deasserted4()
7562 BLOGE(sc, "PGLUE hw attention 0x%08x\n", val); in bxe_attn_int_deasserted4()
7565 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); in bxe_attn_int_deasserted4()
7567 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); in bxe_attn_int_deasserted4()
7569 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); in bxe_attn_int_deasserted4()
7571 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); in bxe_attn_int_deasserted4()
7573 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); in bxe_attn_int_deasserted4()
7575 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); in bxe_attn_int_deasserted4()
7577 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); in bxe_attn_int_deasserted4()
7579 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); in bxe_attn_int_deasserted4()
7581 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); in bxe_attn_int_deasserted4()
7585 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR); in bxe_attn_int_deasserted4()
7586 BLOGE(sc, "ATC hw attention 0x%08x\n", val); in bxe_attn_int_deasserted4()
7589 BLOGE(sc, "ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); in bxe_attn_int_deasserted4()
7591 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); in bxe_attn_int_deasserted4()
7593 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); in bxe_attn_int_deasserted4()
7595 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); in bxe_attn_int_deasserted4()
7597 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); in bxe_attn_int_deasserted4()
7599 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); in bxe_attn_int_deasserted4()
7604 BLOGE(sc, "FATAL parity attention set4 0x%08x\n", in bxe_attn_int_deasserted4()
7610 BXE_SET_ERROR_BIT(sc, BXE_ERR_MISC); in bxe_attn_int_deasserted4()
7612 &sc->sp_err_timeout_task, hz/10); in bxe_attn_int_deasserted4()
7618 bxe_e1h_disable(struct bxe_softc *sc) in bxe_e1h_disable() argument
7620 int port = SC_PORT(sc); in bxe_e1h_disable()
7622 bxe_tx_disable(sc); in bxe_e1h_disable()
7624 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bxe_e1h_disable()
7628 bxe_e1h_enable(struct bxe_softc *sc) in bxe_e1h_enable() argument
7630 int port = SC_PORT(sc); in bxe_e1h_enable()
7632 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1); in bxe_e1h_enable()
7644 bxe_config_mf_bw(struct bxe_softc *sc) in bxe_config_mf_bw() argument
7646 if (sc->link_vars.link_up) { in bxe_config_mf_bw()
7647 bxe_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX); in bxe_config_mf_bw()
7651 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); in bxe_config_mf_bw()
7655 bxe_set_mf_bw(struct bxe_softc *sc) in bxe_set_mf_bw() argument
7657 bxe_config_mf_bw(sc); in bxe_set_mf_bw()
7658 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0); in bxe_set_mf_bw()
7662 bxe_handle_eee_event(struct bxe_softc *sc) in bxe_handle_eee_event() argument
7664 BLOGD(sc, DBG_INTR, "EEE - LLDP event\n"); in bxe_handle_eee_event()
7665 bxe_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); in bxe_handle_eee_event()
7671 bxe_drv_info_ether_stat(struct bxe_softc *sc) in bxe_drv_info_ether_stat() argument
7674 &sc->sp->drv_info_to_mcp.ether_stat; in bxe_drv_info_ether_stat()
7680 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj, in bxe_drv_info_ether_stat()
7685 ether_stat->mtu_size = sc->mtu; in bxe_drv_info_ether_stat()
7688 if (if_getcapenable(sc->ifp) & (IFCAP_TSO4 | IFCAP_TSO6)) { in bxe_drv_info_ether_stat()
7696 ether_stat->txq_size = sc->tx_ring_size; in bxe_drv_info_ether_stat()
7697 ether_stat->rxq_size = sc->rx_ring_size; in bxe_drv_info_ether_stat()
7701 bxe_handle_drv_info_req(struct bxe_softc *sc) in bxe_handle_drv_info_req() argument
7704 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control); in bxe_handle_drv_info_req()
7708 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0); in bxe_handle_drv_info_req()
7715 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp)); in bxe_handle_drv_info_req()
7719 bxe_drv_info_ether_stat(sc); in bxe_handle_drv_info_req()
7725 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0); in bxe_handle_drv_info_req()
7733 SHMEM2_WR(sc, drv_info_host_addr_lo, in bxe_handle_drv_info_req()
7734 U64_LO(BXE_SP_MAPPING(sc, drv_info_to_mcp))); in bxe_handle_drv_info_req()
7735 SHMEM2_WR(sc, drv_info_host_addr_hi, in bxe_handle_drv_info_req()
7736 U64_HI(BXE_SP_MAPPING(sc, drv_info_to_mcp))); in bxe_handle_drv_info_req()
7738 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0); in bxe_handle_drv_info_req()
7742 bxe_dcc_event(struct bxe_softc *sc, in bxe_dcc_event() argument
7745 BLOGD(sc, DBG_INTR, "dcc_event 0x%08x\n", dcc_event); in bxe_dcc_event()
7753 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) { in bxe_dcc_event()
7754 BLOGD(sc, DBG_INTR, "mf_cfg function disabled\n"); in bxe_dcc_event()
7755 sc->flags |= BXE_MF_FUNC_DIS; in bxe_dcc_event()
7756 bxe_e1h_disable(sc); in bxe_dcc_event()
7758 BLOGD(sc, DBG_INTR, "mf_cfg function enabled\n"); in bxe_dcc_event()
7759 sc->flags &= ~BXE_MF_FUNC_DIS; in bxe_dcc_event()
7760 bxe_e1h_enable(sc); in bxe_dcc_event()
7766 bxe_config_mf_bw(sc); in bxe_dcc_event()
7772 bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0); in bxe_dcc_event()
7774 bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0); in bxe_dcc_event()
7778 bxe_pmf_update(struct bxe_softc *sc) in bxe_pmf_update() argument
7780 int port = SC_PORT(sc); in bxe_pmf_update()
7783 sc->port.pmf = 1; in bxe_pmf_update()
7784 BLOGD(sc, DBG_INTR, "pmf %d\n", sc->port.pmf); in bxe_pmf_update()
7798 val = (0xff0f | (1 << (SC_VN(sc) + 4))); in bxe_pmf_update()
7799 if (sc->devinfo.int_block == INT_BLOCK_HC) { in bxe_pmf_update()
7800 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val); in bxe_pmf_update()
7801 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val); in bxe_pmf_update()
7802 } else if (!CHIP_IS_E1x(sc)) { in bxe_pmf_update()
7803 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val); in bxe_pmf_update()
7804 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val); in bxe_pmf_update()
7807 bxe_stats_handle(sc, STATS_EVENT_PMF); in bxe_pmf_update()
7811 bxe_mc_assert(struct bxe_softc *sc) in bxe_mc_assert() argument
7818 last_idx = REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET); in bxe_mc_assert()
7820 BLOGE(sc, "XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); in bxe_mc_assert()
7825 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i)); in bxe_mc_assert()
7826 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4); in bxe_mc_assert()
7827 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8); in bxe_mc_assert()
7828 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12); in bxe_mc_assert()
7831 BLOGE(sc, "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", in bxe_mc_assert()
7840 last_idx = REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET); in bxe_mc_assert()
7842 BLOGE(sc, "TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); in bxe_mc_assert()
7848 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i)); in bxe_mc_assert()
7849 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4); in bxe_mc_assert()
7850 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8); in bxe_mc_assert()
7851 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12); in bxe_mc_assert()
7854 BLOGE(sc, "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", in bxe_mc_assert()
7863 last_idx = REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET); in bxe_mc_assert()
7865 BLOGE(sc, "CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); in bxe_mc_assert()
7871 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i)); in bxe_mc_assert()
7872 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4); in bxe_mc_assert()
7873 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8); in bxe_mc_assert()
7874 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12); in bxe_mc_assert()
7877 BLOGE(sc, "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", in bxe_mc_assert()
7886 last_idx = REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET); in bxe_mc_assert()
7888 BLOGE(sc, "USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); in bxe_mc_assert()
7894 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i)); in bxe_mc_assert()
7895 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4); in bxe_mc_assert()
7896 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8); in bxe_mc_assert()
7897 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12); in bxe_mc_assert()
7900 BLOGE(sc, "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", in bxe_mc_assert()
7912 bxe_attn_int_deasserted3(struct bxe_softc *sc, in bxe_attn_int_deasserted3() argument
7915 int func = SC_FUNC(sc); in bxe_attn_int_deasserted3()
7920 if (attn & BXE_PMF_LINK_ASSERT(sc)) { in bxe_attn_int_deasserted3()
7922 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bxe_attn_int_deasserted3()
7923 bxe_read_mf_cfg(sc); in bxe_attn_int_deasserted3()
7924 sc->devinfo.mf_info.mf_config[SC_VN(sc)] = in bxe_attn_int_deasserted3()
7925 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); in bxe_attn_int_deasserted3()
7926 val = SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status); in bxe_attn_int_deasserted3()
7929 bxe_dcc_event(sc, (val & DRV_STATUS_DCC_EVENT_MASK)); in bxe_attn_int_deasserted3()
7932 bxe_set_mf_bw(sc); in bxe_attn_int_deasserted3()
7935 bxe_handle_drv_info_req(sc); in bxe_attn_int_deasserted3()
7937 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF)) in bxe_attn_int_deasserted3()
7938 bxe_pmf_update(sc); in bxe_attn_int_deasserted3()
7941 bxe_handle_eee_event(sc); in bxe_attn_int_deasserted3()
7943 if (sc->link_vars.periodic_flags & in bxe_attn_int_deasserted3()
7946 bxe_acquire_phy_lock(sc); in bxe_attn_int_deasserted3()
7947 sc->link_vars.periodic_flags &= in bxe_attn_int_deasserted3()
7949 bxe_release_phy_lock(sc); in bxe_attn_int_deasserted3()
7950 if (IS_MF(sc)) in bxe_attn_int_deasserted3()
7952 bxe_link_report(sc); in bxe_attn_int_deasserted3()
7959 bxe_link_status_update(sc); in bxe_attn_int_deasserted3()
7963 BLOGE(sc, "MC assert!\n"); in bxe_attn_int_deasserted3()
7964 bxe_mc_assert(sc); in bxe_attn_int_deasserted3()
7965 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0); in bxe_attn_int_deasserted3()
7966 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0); in bxe_attn_int_deasserted3()
7967 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0); in bxe_attn_int_deasserted3()
7968 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0); in bxe_attn_int_deasserted3()
7969 bxe_int_disable(sc); in bxe_attn_int_deasserted3()
7970 BXE_SET_ERROR_BIT(sc, BXE_ERR_MC_ASSERT); in bxe_attn_int_deasserted3()
7972 &sc->sp_err_timeout_task, hz/10); in bxe_attn_int_deasserted3()
7976 BLOGE(sc, "MCP assert!\n"); in bxe_attn_int_deasserted3()
7977 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0); in bxe_attn_int_deasserted3()
7978 BXE_SET_ERROR_BIT(sc, BXE_ERR_MCP_ASSERT); in bxe_attn_int_deasserted3()
7980 &sc->sp_err_timeout_task, hz/10); in bxe_attn_int_deasserted3()
7981 bxe_int_disable(sc); /*avoid repetive assert alert */ in bxe_attn_int_deasserted3()
7985 BLOGE(sc, "Unknown HW assert! (attn 0x%08x)\n", attn); in bxe_attn_int_deasserted3()
7990 BLOGE(sc, "LATCHED attention 0x%08x (masked)\n", attn); in bxe_attn_int_deasserted3()
7992 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN); in bxe_attn_int_deasserted3()
7993 BLOGE(sc, "GRC time-out 0x%08x\n", val); in bxe_attn_int_deasserted3()
7996 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN); in bxe_attn_int_deasserted3()
7997 BLOGE(sc, "GRC reserved 0x%08x\n", val); in bxe_attn_int_deasserted3()
7999 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); in bxe_attn_int_deasserted3()
8004 bxe_attn_int_deasserted2(struct bxe_softc *sc, in bxe_attn_int_deasserted2() argument
8007 int port = SC_PORT(sc); in bxe_attn_int_deasserted2()
8014 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR); in bxe_attn_int_deasserted2()
8015 BLOGE(sc, "CFC hw attention 0x%08x\n", val); in bxe_attn_int_deasserted2()
8018 BLOGE(sc, "FATAL error from CFC\n"); in bxe_attn_int_deasserted2()
8024 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0); in bxe_attn_int_deasserted2()
8025 BLOGE(sc, "PXP hw attention-0 0x%08x\n", val); in bxe_attn_int_deasserted2()
8028 BLOGE(sc, "FATAL error from PXP\n"); in bxe_attn_int_deasserted2()
8032 if (!CHIP_IS_E1x(sc)) { in bxe_attn_int_deasserted2()
8033 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1); in bxe_attn_int_deasserted2()
8034 BLOGE(sc, "PXP hw attention-1 0x%08x\n", val); in bxe_attn_int_deasserted2()
8046 if (!CHIP_IS_E1x(sc)) { in bxe_attn_int_deasserted2()
8047 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0); in bxe_attn_int_deasserted2()
8048 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1); in bxe_attn_int_deasserted2()
8049 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1); in bxe_attn_int_deasserted2()
8050 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0); in bxe_attn_int_deasserted2()
8061 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0); in bxe_attn_int_deasserted2()
8064 BLOGE(sc, "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0); in bxe_attn_int_deasserted2()
8071 BLOGE(sc, "PXP2_WR_PGLUE_EOP_ERROR\n"); in bxe_attn_int_deasserted2()
8089 val = REG_RD(sc, reg_offset); in bxe_attn_int_deasserted2()
8091 REG_WR(sc, reg_offset, val); in bxe_attn_int_deasserted2()
8093 BLOGE(sc, "FATAL HW block attention set2 0x%x\n", in bxe_attn_int_deasserted2()
8096 bxe_panic(sc, ("HW block attention set2\n")); in bxe_attn_int_deasserted2()
8099 BXE_SET_ERROR_BIT(sc, BXE_ERR_GLOBAL); in bxe_attn_int_deasserted2()
8101 &sc->sp_err_timeout_task, hz/10); in bxe_attn_int_deasserted2()
8107 bxe_attn_int_deasserted1(struct bxe_softc *sc, in bxe_attn_int_deasserted1() argument
8110 int port = SC_PORT(sc); in bxe_attn_int_deasserted1()
8116 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR); in bxe_attn_int_deasserted1()
8117 BLOGE(sc, "DB hw attention 0x%08x\n", val); in bxe_attn_int_deasserted1()
8120 BLOGE(sc, "FATAL error from DORQ\n"); in bxe_attn_int_deasserted1()
8129 val = REG_RD(sc, reg_offset); in bxe_attn_int_deasserted1()
8131 REG_WR(sc, reg_offset, val); in bxe_attn_int_deasserted1()
8133 BLOGE(sc, "FATAL HW block attention set1 0x%08x\n", in bxe_attn_int_deasserted1()
8136 bxe_panic(sc, ("HW block attention set1\n")); in bxe_attn_int_deasserted1()
8139 BXE_SET_ERROR_BIT(sc, BXE_ERR_MISC); in bxe_attn_int_deasserted1()
8141 &sc->sp_err_timeout_task, hz/10); in bxe_attn_int_deasserted1()
8147 bxe_attn_int_deasserted0(struct bxe_softc *sc, in bxe_attn_int_deasserted0() argument
8150 int port = SC_PORT(sc); in bxe_attn_int_deasserted0()
8158 val = REG_RD(sc, reg_offset); in bxe_attn_int_deasserted0()
8160 REG_WR(sc, reg_offset, val); in bxe_attn_int_deasserted0()
8162 BLOGW(sc, "SPIO5 hw attention\n"); in bxe_attn_int_deasserted0()
8165 elink_hw_reset_phy(&sc->link_params); in bxe_attn_int_deasserted0()
8166 bxe_fan_failure(sc); in bxe_attn_int_deasserted0()
8169 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) { in bxe_attn_int_deasserted0()
8170 bxe_acquire_phy_lock(sc); in bxe_attn_int_deasserted0()
8171 elink_handle_module_detect_int(&sc->link_params); in bxe_attn_int_deasserted0()
8172 bxe_release_phy_lock(sc); in bxe_attn_int_deasserted0()
8176 val = REG_RD(sc, reg_offset); in bxe_attn_int_deasserted0()
8178 REG_WR(sc, reg_offset, val); in bxe_attn_int_deasserted0()
8181 BXE_SET_ERROR_BIT(sc, BXE_ERR_MISC); in bxe_attn_int_deasserted0()
8183 &sc->sp_err_timeout_task, hz/10); in bxe_attn_int_deasserted0()
8185 bxe_panic(sc, ("FATAL HW block attention set0 0x%lx\n", in bxe_attn_int_deasserted0()
8191 bxe_attn_int_deasserted(struct bxe_softc *sc, in bxe_attn_int_deasserted() argument
8196 int port = SC_PORT(sc); in bxe_attn_int_deasserted()
8207 bxe_acquire_alr(sc); in bxe_attn_int_deasserted()
8209 if (bxe_chk_parity_attn(sc, &global, TRUE)) { in bxe_attn_int_deasserted()
8216 bxe_int_disable(sc); in bxe_attn_int_deasserted()
8217 BXE_SET_ERROR_BIT(sc, BXE_ERR_PARITY); in bxe_attn_int_deasserted()
8219 &sc->sp_err_timeout_task, hz/10); in bxe_attn_int_deasserted()
8220 bxe_release_alr(sc); in bxe_attn_int_deasserted()
8224 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); in bxe_attn_int_deasserted()
8225 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); in bxe_attn_int_deasserted()
8226 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); in bxe_attn_int_deasserted()
8227 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); in bxe_attn_int_deasserted()
8228 if (!CHIP_IS_E1x(sc)) { in bxe_attn_int_deasserted()
8229 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); in bxe_attn_int_deasserted()
8234 BLOGD(sc, DBG_INTR, "attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", in bxe_attn_int_deasserted()
8239 group_mask = &sc->attn_group[index]; in bxe_attn_int_deasserted()
8241 BLOGD(sc, DBG_INTR, in bxe_attn_int_deasserted()
8247 bxe_attn_int_deasserted4(sc, attn.sig[4] & group_mask->sig[4]); in bxe_attn_int_deasserted()
8248 bxe_attn_int_deasserted3(sc, attn.sig[3] & group_mask->sig[3]); in bxe_attn_int_deasserted()
8249 bxe_attn_int_deasserted1(sc, attn.sig[1] & group_mask->sig[1]); in bxe_attn_int_deasserted()
8250 bxe_attn_int_deasserted2(sc, attn.sig[2] & group_mask->sig[2]); in bxe_attn_int_deasserted()
8251 bxe_attn_int_deasserted0(sc, attn.sig[0] & group_mask->sig[0]); in bxe_attn_int_deasserted()
8255 bxe_release_alr(sc); in bxe_attn_int_deasserted()
8257 if (sc->devinfo.int_block == INT_BLOCK_HC) { in bxe_attn_int_deasserted()
8265 BLOGD(sc, DBG_INTR, in bxe_attn_int_deasserted()
8267 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bxe_attn_int_deasserted()
8268 REG_WR(sc, reg_addr, val); in bxe_attn_int_deasserted()
8270 if (~sc->attn_state & deasserted) { in bxe_attn_int_deasserted()
8271 BLOGE(sc, "IGU error\n"); in bxe_attn_int_deasserted()
8277 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bxe_attn_int_deasserted()
8279 aeu_mask = REG_RD(sc, reg_addr); in bxe_attn_int_deasserted()
8281 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly deasserted 0x%08x\n", in bxe_attn_int_deasserted()
8284 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask); in bxe_attn_int_deasserted()
8286 REG_WR(sc, reg_addr, aeu_mask); in bxe_attn_int_deasserted()
8287 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bxe_attn_int_deasserted()
8289 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state); in bxe_attn_int_deasserted()
8290 sc->attn_state &= ~deasserted; in bxe_attn_int_deasserted()
8291 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state); in bxe_attn_int_deasserted()
8295 bxe_attn_int(struct bxe_softc *sc) in bxe_attn_int() argument
8298 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits); in bxe_attn_int()
8299 uint32_t attn_ack = le32toh(sc->def_sb->atten_status_block.attn_bits_ack); in bxe_attn_int()
8300 uint32_t attn_state = sc->attn_state; in bxe_attn_int()
8306 BLOGD(sc, DBG_INTR, in bxe_attn_int()
8311 BLOGE(sc, "BAD attention state\n"); in bxe_attn_int()
8316 bxe_attn_int_asserted(sc, asserted); in bxe_attn_int()
8320 bxe_attn_int_deasserted(sc, deasserted); in bxe_attn_int()
8325 bxe_update_dsb_idx(struct bxe_softc *sc) in bxe_update_dsb_idx() argument
8327 struct host_sp_status_block *def_sb = sc->def_sb; in bxe_update_dsb_idx()
8332 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) { in bxe_update_dsb_idx()
8333 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index; in bxe_update_dsb_idx()
8337 if (sc->def_idx != def_sb->sp_sb.running_index) { in bxe_update_dsb_idx()
8338 sc->def_idx = def_sb->sp_sb.running_index; in bxe_update_dsb_idx()
8348 bxe_cid_to_q_obj(struct bxe_softc *sc, in bxe_cid_to_q_obj() argument
8351 BLOGD(sc, DBG_SP, "retrieving fp from cid %d\n", cid); in bxe_cid_to_q_obj()
8352 return (&sc->sp_objs[CID_TO_FP(cid, sc)].q_obj); in bxe_cid_to_q_obj()
8356 bxe_handle_mcast_eqe(struct bxe_softc *sc) in bxe_handle_mcast_eqe() argument
8363 rparam.mcast_obj = &sc->mcast_obj; in bxe_handle_mcast_eqe()
8365 BXE_MCAST_LOCK(sc); in bxe_handle_mcast_eqe()
8368 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw); in bxe_handle_mcast_eqe()
8371 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) { in bxe_handle_mcast_eqe()
8372 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); in bxe_handle_mcast_eqe()
8374 BLOGD(sc, DBG_SP, in bxe_handle_mcast_eqe()
8379 BXE_MCAST_UNLOCK(sc); in bxe_handle_mcast_eqe()
8383 bxe_handle_classification_eqe(struct bxe_softc *sc, in bxe_handle_classification_eqe() argument
8396 BLOGD(sc, DBG_SP, "Got SETUP_MAC completions\n"); in bxe_handle_classification_eqe()
8397 vlan_mac_obj = &sc->sp_objs[cid].mac_obj; in bxe_handle_classification_eqe()
8401 BLOGD(sc, DBG_SP, "Got SETUP_MCAST completions\n"); in bxe_handle_classification_eqe()
8406 bxe_handle_mcast_eqe(sc); in bxe_handle_classification_eqe()
8410 BLOGE(sc, "Unsupported classification command: %d\n", in bxe_handle_classification_eqe()
8415 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags); in bxe_handle_classification_eqe()
8418 BLOGE(sc, "Failed to schedule new commands (%d)\n", rc); in bxe_handle_classification_eqe()
8420 BLOGD(sc, DBG_SP, "Scheduled next pending commands...\n"); in bxe_handle_classification_eqe()
8425 bxe_handle_rx_mode_eqe(struct bxe_softc *sc, in bxe_handle_rx_mode_eqe() argument
8428 bxe_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); in bxe_handle_rx_mode_eqe()
8432 &sc->sp_state)) { in bxe_handle_rx_mode_eqe()
8433 bxe_set_storm_rx_mode(sc); in bxe_handle_rx_mode_eqe()
8438 bxe_update_eq_prod(struct bxe_softc *sc, in bxe_update_eq_prod() argument
8441 storm_memset_eq_prod(sc, prod, SC_FUNC(sc)); in bxe_update_eq_prod()
8446 bxe_eq_int(struct bxe_softc *sc) in bxe_eq_int() argument
8455 struct ecore_func_sp_obj *f_obj = &sc->func_obj; in bxe_eq_int()
8456 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw; in bxe_eq_int()
8458 hw_cons = le16toh(*sc->eq_cons_sb); in bxe_eq_int()
8474 sw_cons = sc->eq_cons; in bxe_eq_int()
8475 sw_prod = sc->eq_prod; in bxe_eq_int()
8477 BLOGD(sc, DBG_SP,"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n", in bxe_eq_int()
8478 hw_cons, sw_cons, atomic_load_acq_long(&sc->eq_spq_left)); in bxe_eq_int()
8484 elem = &sc->eq[EQ_DESC(sw_cons)]; in bxe_eq_int()
8494 BLOGD(sc, DBG_SP, "got statistics completion event %d\n", in bxe_eq_int()
8495 sc->stats_comp++); in bxe_eq_int()
8502 BLOGD(sc, DBG_SP, "got delete ramrod for MULTI[%d]\n", cid); in bxe_eq_int()
8503 q_obj = bxe_cid_to_q_obj(sc, cid); in bxe_eq_int()
8504 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) { in bxe_eq_int()
8510 BLOGD(sc, DBG_SP, "got STOP TRAFFIC\n"); in bxe_eq_int()
8511 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) { in bxe_eq_int()
8518 BLOGD(sc, DBG_SP, "got START TRAFFIC\n"); in bxe_eq_int()
8519 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_START)) { in bxe_eq_int()
8528 BLOGD(sc, DBG_SP, "got FUNC_SWITCH_UPDATE ramrod\n"); in bxe_eq_int()
8529 if (f_obj->complete_cmd(sc, f_obj, in bxe_eq_int()
8535 BLOGD(sc, DBG_SP, in bxe_eq_int()
8541 q_obj = &bxe_fwd_sp_obj(sc, q_obj); in bxe_eq_int()
8542 if (q_obj->complete_cmd(sc, q_obj, in bxe_eq_int()
8549 BLOGD(sc, DBG_SP, "got FUNC_START ramrod\n"); in bxe_eq_int()
8550 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) { in bxe_eq_int()
8556 BLOGD(sc, DBG_SP, "got FUNC_STOP ramrod\n"); in bxe_eq_int()
8557 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) { in bxe_eq_int()
8563 switch (opcode | sc->state) { in bxe_eq_int()
8567 BLOGD(sc, DBG_SP, "got RSS_UPDATE ramrod. CID %d\n", cid); in bxe_eq_int()
8577 BLOGD(sc, DBG_SP, "got (un)set mac ramrod\n"); in bxe_eq_int()
8578 bxe_handle_classification_eqe(sc, elem); in bxe_eq_int()
8584 BLOGD(sc, DBG_SP, "got mcast ramrod\n"); in bxe_eq_int()
8585 bxe_handle_mcast_eqe(sc); in bxe_eq_int()
8591 BLOGD(sc, DBG_SP, "got rx_mode ramrod\n"); in bxe_eq_int()
8592 bxe_handle_rx_mode_eqe(sc, elem); in bxe_eq_int()
8597 BLOGE(sc, "Unknown EQ event %d, sc->state 0x%x\n", in bxe_eq_int()
8598 elem->message.opcode, sc->state); in bxe_eq_int()
8606 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt); in bxe_eq_int()
8608 sc->eq_cons = sw_cons; in bxe_eq_int()
8609 sc->eq_prod = sw_prod; in bxe_eq_int()
8615 bxe_update_eq_prod(sc, sc->eq_prod); in bxe_eq_int()
8622 struct bxe_softc *sc = (struct bxe_softc *)context; in bxe_handle_sp_tq() local
8625 BLOGD(sc, DBG_SP, "---> SP TASK <---\n"); in bxe_handle_sp_tq()
8628 status = bxe_update_dsb_idx(sc); in bxe_handle_sp_tq()
8630 BLOGD(sc, DBG_SP, "dsb status 0x%04x\n", status); in bxe_handle_sp_tq()
8634 BLOGD(sc, DBG_SP, "---> ATTN INTR <---\n"); in bxe_handle_sp_tq()
8635 bxe_attn_int(sc); in bxe_handle_sp_tq()
8642 BLOGD(sc, DBG_SP, "---> EQ INTR <---\n"); in bxe_handle_sp_tq()
8643 bxe_eq_int(sc); in bxe_handle_sp_tq()
8644 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, in bxe_handle_sp_tq()
8645 le16toh(sc->def_idx), IGU_INT_NOP, 1); in bxe_handle_sp_tq()
8651 BLOGE(sc, "Got an unknown SP interrupt! (0x%04x)\n", status); in bxe_handle_sp_tq()
8655 bxe_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID, in bxe_handle_sp_tq()
8656 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1); in bxe_handle_sp_tq()
8673 struct bxe_softc *sc = fp->sc; in bxe_handle_fp_tq() local
8677 BLOGD(sc, DBG_INTR, "---> FP TASK QUEUE (%d) <---\n", fp->index); in bxe_handle_fp_tq()
8686 if (!(if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING)) { in bxe_handle_fp_tq()
8698 /* more_tx = */ bxe_txeof(sc, fp); in bxe_handle_fp_tq()
8703 more_rx = bxe_rxeof(sc, fp); in bxe_handle_fp_tq()
8712 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, in bxe_handle_fp_tq()
8719 struct bxe_softc *sc = fp->sc; in bxe_task_fp() local
8723 BLOGD(sc, DBG_INTR, "---> FP TASK ISR (%d) <---\n", fp->index); in bxe_task_fp()
8732 /* more_tx = */ bxe_txeof(sc, fp); in bxe_task_fp()
8737 more_rx = bxe_rxeof(sc, fp); in bxe_task_fp()
8753 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, in bxe_task_fp()
8767 struct bxe_softc *sc = (struct bxe_softc *)xsc; in bxe_intr_legacy() local
8772 BLOGD(sc, DBG_INTR, "---> BXE INTx <---\n"); in bxe_intr_legacy()
8783 status = bxe_ack_int(sc); in bxe_intr_legacy()
8787 BLOGD(sc, DBG_INTR, "Not our interrupt!\n"); in bxe_intr_legacy()
8791 BLOGD(sc, DBG_INTR, "Interrupt status 0x%04x\n", status); in bxe_intr_legacy()
8793 FOR_EACH_ETH_QUEUE(sc, i) { in bxe_intr_legacy()
8794 fp = &sc->fp[i]; in bxe_intr_legacy()
8795 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc))); in bxe_intr_legacy()
8798 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); in bxe_intr_legacy()
8806 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); in bxe_intr_legacy()
8809 taskqueue_enqueue(sc->sp_tq, &sc->sp_tq_task); in bxe_intr_legacy()
8815 BLOGW(sc, "Unexpected fastpath status (0x%08x)!\n", status); in bxe_intr_legacy()
8823 struct bxe_softc *sc = (struct bxe_softc *)xsc; in bxe_intr_sp() local
8825 BLOGD(sc, (DBG_INTR | DBG_SP), "---> SP INTR <---\n"); in bxe_intr_sp()
8828 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); in bxe_intr_sp()
8831 taskqueue_enqueue(sc->sp_tq, &sc->sp_tq_task); in bxe_intr_sp()
8839 struct bxe_softc *sc = fp->sc; in bxe_intr_fp() local
8841 BLOGD(sc, DBG_INTR, "---> FP INTR %d <---\n", fp->index); in bxe_intr_fp()
8843 BLOGD(sc, DBG_INTR, in bxe_intr_fp()
8848 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); in bxe_intr_fp()
8855 bxe_interrupt_free(struct bxe_softc *sc) in bxe_interrupt_free() argument
8859 switch (sc->interrupt_mode) { in bxe_interrupt_free()
8861 BLOGD(sc, DBG_LOAD, "Releasing legacy INTx vector\n"); in bxe_interrupt_free()
8862 if (sc->intr[0].resource != NULL) { in bxe_interrupt_free()
8863 bus_release_resource(sc->dev, in bxe_interrupt_free()
8865 sc->intr[0].rid, in bxe_interrupt_free()
8866 sc->intr[0].resource); in bxe_interrupt_free()
8870 for (i = 0; i < sc->intr_count; i++) { in bxe_interrupt_free()
8871 BLOGD(sc, DBG_LOAD, "Releasing MSI vector %d\n", i); in bxe_interrupt_free()
8872 if (sc->intr[i].resource && sc->intr[i].rid) { in bxe_interrupt_free()
8873 bus_release_resource(sc->dev, in bxe_interrupt_free()
8875 sc->intr[i].rid, in bxe_interrupt_free()
8876 sc->intr[i].resource); in bxe_interrupt_free()
8879 pci_release_msi(sc->dev); in bxe_interrupt_free()
8882 for (i = 0; i < sc->intr_count; i++) { in bxe_interrupt_free()
8883 BLOGD(sc, DBG_LOAD, "Releasing MSI-X vector %d\n", i); in bxe_interrupt_free()
8884 if (sc->intr[i].resource && sc->intr[i].rid) { in bxe_interrupt_free()
8885 bus_release_resource(sc->dev, in bxe_interrupt_free()
8887 sc->intr[i].rid, in bxe_interrupt_free()
8888 sc->intr[i].resource); in bxe_interrupt_free()
8891 pci_release_msi(sc->dev); in bxe_interrupt_free()
8917 bxe_interrupt_alloc(struct bxe_softc *sc) in bxe_interrupt_alloc() argument
8927 if (sc->interrupt_mode > 0) { in bxe_interrupt_alloc()
8928 if (sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) { in bxe_interrupt_alloc()
8929 msix_count = pci_msix_count(sc->dev); in bxe_interrupt_alloc()
8932 if (sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) { in bxe_interrupt_alloc()
8933 msi_count = pci_msi_count(sc->dev); in bxe_interrupt_alloc()
8936 BLOGD(sc, DBG_LOAD, "%d MSI and %d MSI-X vectors available\n", in bxe_interrupt_alloc()
8941 if (sc->interrupt_mode != INTR_MODE_MSIX) { in bxe_interrupt_alloc()
8945 if (((sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) == 0) || in bxe_interrupt_alloc()
8947 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ in bxe_interrupt_alloc()
8952 num_requested = min((sc->num_queues + 1), msix_count); in bxe_interrupt_alloc()
8954 BLOGD(sc, DBG_LOAD, "Requesting %d MSI-X vectors\n", num_requested); in bxe_interrupt_alloc()
8957 if ((rc = pci_alloc_msix(sc->dev, &num_allocated)) != 0) { in bxe_interrupt_alloc()
8958 BLOGE(sc, "MSI-X alloc failed! (%d)\n", rc); in bxe_interrupt_alloc()
8959 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ in bxe_interrupt_alloc()
8964 BLOGE(sc, "MSI-X allocation less than 2!\n"); in bxe_interrupt_alloc()
8965 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ in bxe_interrupt_alloc()
8966 pci_release_msi(sc->dev); in bxe_interrupt_alloc()
8970 BLOGI(sc, "MSI-X vectors Requested %d and Allocated %d\n", in bxe_interrupt_alloc()
8974 sc->intr_count = num_allocated; in bxe_interrupt_alloc()
8975 sc->num_queues = num_allocated - 1; in bxe_interrupt_alloc()
8981 sc->intr[i].rid = (rid + i); in bxe_interrupt_alloc()
8983 if ((sc->intr[i].resource = in bxe_interrupt_alloc()
8984 bus_alloc_resource_any(sc->dev, in bxe_interrupt_alloc()
8986 &sc->intr[i].rid, in bxe_interrupt_alloc()
8988 BLOGE(sc, "Failed to map MSI-X[%d] (rid=%d)!\n", in bxe_interrupt_alloc()
8992 bus_release_resource(sc->dev, in bxe_interrupt_alloc()
8994 sc->intr[j].rid, in bxe_interrupt_alloc()
8995 sc->intr[j].resource); in bxe_interrupt_alloc()
8998 sc->intr_count = 0; in bxe_interrupt_alloc()
8999 sc->num_queues = 0; in bxe_interrupt_alloc()
9000 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ in bxe_interrupt_alloc()
9001 pci_release_msi(sc->dev); in bxe_interrupt_alloc()
9005 BLOGD(sc, DBG_LOAD, "Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i)); in bxe_interrupt_alloc()
9010 if (sc->interrupt_mode != INTR_MODE_MSI) { in bxe_interrupt_alloc()
9014 if (((sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) == 0) || in bxe_interrupt_alloc()
9016 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ in bxe_interrupt_alloc()
9023 BLOGD(sc, DBG_LOAD, "Requesting %d MSI vectors\n", num_requested); in bxe_interrupt_alloc()
9026 if ((rc = pci_alloc_msi(sc->dev, &num_allocated)) != 0) { in bxe_interrupt_alloc()
9027 BLOGE(sc, "MSI alloc failed (%d)!\n", rc); in bxe_interrupt_alloc()
9028 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ in bxe_interrupt_alloc()
9033 BLOGE(sc, "MSI allocation is not 1!\n"); in bxe_interrupt_alloc()
9034 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ in bxe_interrupt_alloc()
9035 pci_release_msi(sc->dev); in bxe_interrupt_alloc()
9039 BLOGI(sc, "MSI vectors Requested %d and Allocated %d\n", in bxe_interrupt_alloc()
9043 sc->intr_count = num_allocated; in bxe_interrupt_alloc()
9044 sc->num_queues = num_allocated; in bxe_interrupt_alloc()
9048 sc->intr[0].rid = rid; in bxe_interrupt_alloc()
9050 if ((sc->intr[0].resource = in bxe_interrupt_alloc()
9051 bus_alloc_resource_any(sc->dev, in bxe_interrupt_alloc()
9053 &sc->intr[0].rid, in bxe_interrupt_alloc()
9055 BLOGE(sc, "Failed to map MSI[0] (rid=%d)!\n", rid); in bxe_interrupt_alloc()
9056 sc->intr_count = 0; in bxe_interrupt_alloc()
9057 sc->num_queues = 0; in bxe_interrupt_alloc()
9058 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ in bxe_interrupt_alloc()
9059 pci_release_msi(sc->dev); in bxe_interrupt_alloc()
9063 BLOGD(sc, DBG_LOAD, "Mapped MSI[0] (rid=%d)\n", rid); in bxe_interrupt_alloc()
9067 if (sc->interrupt_mode != INTR_MODE_INTX) { in bxe_interrupt_alloc()
9071 BLOGD(sc, DBG_LOAD, "Requesting legacy INTx interrupt\n"); in bxe_interrupt_alloc()
9074 sc->intr_count = 1; in bxe_interrupt_alloc()
9075 sc->num_queues = 1; in bxe_interrupt_alloc()
9079 sc->intr[0].rid = rid; in bxe_interrupt_alloc()
9081 if ((sc->intr[0].resource = in bxe_interrupt_alloc()
9082 bus_alloc_resource_any(sc->dev, in bxe_interrupt_alloc()
9084 &sc->intr[0].rid, in bxe_interrupt_alloc()
9086 BLOGE(sc, "Failed to map INTx (rid=%d)!\n", rid); in bxe_interrupt_alloc()
9087 sc->intr_count = 0; in bxe_interrupt_alloc()
9088 sc->num_queues = 0; in bxe_interrupt_alloc()
9089 sc->interrupt_mode = -1; /* Failed! */ in bxe_interrupt_alloc()
9093 BLOGD(sc, DBG_LOAD, "Mapped INTx (rid=%d)\n", rid); in bxe_interrupt_alloc()
9096 if (sc->interrupt_mode == -1) { in bxe_interrupt_alloc()
9097 BLOGE(sc, "Interrupt Allocation: FAILED!!!\n"); in bxe_interrupt_alloc()
9100 BLOGD(sc, DBG_LOAD, in bxe_interrupt_alloc()
9102 sc->interrupt_mode, sc->num_queues); in bxe_interrupt_alloc()
9110 bxe_interrupt_detach(struct bxe_softc *sc) in bxe_interrupt_detach() argument
9116 for (i = 0; i < sc->intr_count; i++) { in bxe_interrupt_detach()
9117 if (sc->intr[i].resource && sc->intr[i].tag) { in bxe_interrupt_detach()
9118 BLOGD(sc, DBG_LOAD, "Disabling interrupt vector %d\n", i); in bxe_interrupt_detach()
9119 bus_teardown_intr(sc->dev, sc->intr[i].resource, sc->intr[i].tag); in bxe_interrupt_detach()
9123 for (i = 0; i < sc->num_queues; i++) { in bxe_interrupt_detach()
9124 fp = &sc->fp[i]; in bxe_interrupt_detach()
9133 for (i = 0; i < sc->num_queues; i++) { in bxe_interrupt_detach()
9134 fp = &sc->fp[i]; in bxe_interrupt_detach()
9142 if (sc->sp_tq) { in bxe_interrupt_detach()
9143 taskqueue_drain(sc->sp_tq, &sc->sp_tq_task); in bxe_interrupt_detach()
9144 taskqueue_free(sc->sp_tq); in bxe_interrupt_detach()
9145 sc->sp_tq = NULL; in bxe_interrupt_detach()
9159 bxe_interrupt_attach(struct bxe_softc *sc) in bxe_interrupt_attach() argument
9165 snprintf(sc->sp_tq_name, sizeof(sc->sp_tq_name), in bxe_interrupt_attach()
9166 "bxe%d_sp_tq", sc->unit); in bxe_interrupt_attach()
9167 TASK_INIT(&sc->sp_tq_task, 0, bxe_handle_sp_tq, sc); in bxe_interrupt_attach()
9168 sc->sp_tq = taskqueue_create(sc->sp_tq_name, M_NOWAIT, in bxe_interrupt_attach()
9170 &sc->sp_tq); in bxe_interrupt_attach()
9171 taskqueue_start_threads(&sc->sp_tq, 1, PWAIT, /* lower priority */ in bxe_interrupt_attach()
9172 "%s", sc->sp_tq_name); in bxe_interrupt_attach()
9175 for (i = 0; i < sc->num_queues; i++) { in bxe_interrupt_attach()
9176 fp = &sc->fp[i]; in bxe_interrupt_attach()
9178 "bxe%d_fp%d_tq", sc->unit, i); in bxe_interrupt_attach()
9191 if (sc->interrupt_mode == INTR_MODE_MSIX) { in bxe_interrupt_attach()
9192 BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI-X[0] vector\n"); in bxe_interrupt_attach()
9198 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, in bxe_interrupt_attach()
9200 NULL, bxe_intr_sp, sc, in bxe_interrupt_attach()
9201 &sc->intr[0].tag)) != 0) { in bxe_interrupt_attach()
9202 BLOGE(sc, "Failed to allocate MSI-X[0] vector (%d)\n", rc); in bxe_interrupt_attach()
9206 bus_describe_intr(sc->dev, sc->intr[0].resource, in bxe_interrupt_attach()
9207 sc->intr[0].tag, "sp"); in bxe_interrupt_attach()
9212 for (i = 0; i < sc->num_queues; i++) { in bxe_interrupt_attach()
9213 fp = &sc->fp[i]; in bxe_interrupt_attach()
9214 BLOGD(sc, DBG_LOAD, "Enabling MSI-X[%d] vector\n", (i + 1)); in bxe_interrupt_attach()
9221 if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource, in bxe_interrupt_attach()
9224 &sc->intr[i + 1].tag)) != 0) { in bxe_interrupt_attach()
9225 BLOGE(sc, "Failed to allocate MSI-X[%d] vector (%d)\n", in bxe_interrupt_attach()
9230 bus_describe_intr(sc->dev, sc->intr[i + 1].resource, in bxe_interrupt_attach()
9231 sc->intr[i + 1].tag, "fp%02d", i); in bxe_interrupt_attach()
9234 if (sc->num_queues > 1) { in bxe_interrupt_attach()
9235 bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i); in bxe_interrupt_attach()
9240 } else if (sc->interrupt_mode == INTR_MODE_MSI) { in bxe_interrupt_attach()
9241 BLOGD(sc, DBG_LOAD, "Enabling MSI[0] vector\n"); in bxe_interrupt_attach()
9248 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, in bxe_interrupt_attach()
9250 NULL, bxe_intr_legacy, sc, in bxe_interrupt_attach()
9251 &sc->intr[0].tag)) != 0) { in bxe_interrupt_attach()
9252 BLOGE(sc, "Failed to allocate MSI[0] vector (%d)\n", rc); in bxe_interrupt_attach()
9257 BLOGD(sc, DBG_LOAD, "Enabling INTx interrupts\n"); in bxe_interrupt_attach()
9264 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, in bxe_interrupt_attach()
9266 NULL, bxe_intr_legacy, sc, in bxe_interrupt_attach()
9267 &sc->intr[0].tag)) != 0) { in bxe_interrupt_attach()
9268 BLOGE(sc, "Failed to allocate INTx interrupt (%d)\n", rc); in bxe_interrupt_attach()
9278 static int bxe_init_hw_common_chip(struct bxe_softc *sc);
9279 static int bxe_init_hw_common(struct bxe_softc *sc);
9280 static int bxe_init_hw_port(struct bxe_softc *sc);
9281 static int bxe_init_hw_func(struct bxe_softc *sc);
9282 static void bxe_reset_common(struct bxe_softc *sc);
9283 static void bxe_reset_port(struct bxe_softc *sc);
9284 static void bxe_reset_func(struct bxe_softc *sc);
9285 static int bxe_gunzip_init(struct bxe_softc *sc);
9286 static void bxe_gunzip_end(struct bxe_softc *sc);
9287 static int bxe_init_firmware(struct bxe_softc *sc);
9288 static void bxe_release_firmware(struct bxe_softc *sc);
9309 bxe_init_func_obj(struct bxe_softc *sc) in bxe_init_func_obj() argument
9311 sc->dmae_ready = 0; in bxe_init_func_obj()
9313 ecore_init_func_obj(sc, in bxe_init_func_obj()
9314 &sc->func_obj, in bxe_init_func_obj()
9315 BXE_SP(sc, func_rdata), in bxe_init_func_obj()
9316 BXE_SP_MAPPING(sc, func_rdata), in bxe_init_func_obj()
9317 BXE_SP(sc, func_afex_rdata), in bxe_init_func_obj()
9318 BXE_SP_MAPPING(sc, func_afex_rdata), in bxe_init_func_obj()
9323 bxe_init_hw(struct bxe_softc *sc, in bxe_init_hw() argument
9332 func_params.f_obj = &sc->func_obj; in bxe_init_hw()
9341 rc = ecore_func_state_change(sc, &func_params); in bxe_init_hw()
9347 bxe_fill(struct bxe_softc *sc, in bxe_fill() argument
9356 REG_WR(sc, (addr + i), fill); in bxe_fill()
9360 REG_WR8(sc, (addr + i), fill); in bxe_fill()
9367 bxe_wr_fp_sb_data(struct bxe_softc *sc, in bxe_wr_fp_sb_data() argument
9375 REG_WR(sc, in bxe_wr_fp_sb_data()
9384 bxe_zero_fp_sb(struct bxe_softc *sc, in bxe_zero_fp_sb() argument
9392 if (!CHIP_IS_E1x(sc)) { in bxe_zero_fp_sb()
9408 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size); in bxe_zero_fp_sb()
9410 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), in bxe_zero_fp_sb()
9412 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)), in bxe_zero_fp_sb()
9417 bxe_wr_sp_sb_data(struct bxe_softc *sc, in bxe_wr_sp_sb_data() argument
9425 REG_WR(sc, in bxe_wr_sp_sb_data()
9427 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) + in bxe_wr_sp_sb_data()
9434 bxe_zero_sp_sb(struct bxe_softc *sc) in bxe_zero_sp_sb() argument
9443 bxe_wr_sp_sb_data(sc, &sp_sb_data); in bxe_zero_sp_sb()
9445 bxe_fill(sc, in bxe_zero_sp_sb()
9447 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))), in bxe_zero_sp_sb()
9449 bxe_fill(sc, in bxe_zero_sp_sb()
9451 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))), in bxe_zero_sp_sb()
9498 bxe_init_sb(struct bxe_softc *sc, in bxe_init_sb() argument
9512 if (CHIP_INT_MODE_IS_BC(sc)) { in bxe_init_sb()
9518 bxe_zero_fp_sb(sc, fw_sb_id); in bxe_init_sb()
9520 if (!CHIP_IS_E1x(sc)) { in bxe_init_sb()
9523 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc); in bxe_init_sb()
9526 sb_data_e2.common.p_func.vnic_id = SC_VN(sc); in bxe_init_sb()
9538 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc); in bxe_init_sb()
9541 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc); in bxe_init_sb()
9555 BLOGD(sc, DBG_LOAD, "Init FW SB %d\n", fw_sb_id); in bxe_init_sb()
9558 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size); in bxe_init_sb()
9564 if (CHIP_IS_E1x(fp->sc)) { in bxe_fp_qzone_id()
9565 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H); in bxe_fp_qzone_id()
9572 bxe_rx_ustorm_prods_offset(struct bxe_softc *sc, in bxe_rx_ustorm_prods_offset() argument
9577 if (!CHIP_IS_E1x(sc)) { in bxe_rx_ustorm_prods_offset()
9580 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id); in bxe_rx_ustorm_prods_offset()
9587 bxe_init_eth_fp(struct bxe_softc *sc, in bxe_init_eth_fp() argument
9590 struct bxe_fastpath *fp = &sc->fp[idx]; in bxe_init_eth_fp()
9595 fp->sc = sc; in bxe_init_eth_fp()
9598 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc)); in bxe_init_eth_fp()
9599 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc)); in bxe_init_eth_fp()
9601 fp->cl_id = (CHIP_IS_E1x(sc)) ? in bxe_init_eth_fp()
9602 (SC_L_ID(sc) + idx) : in bxe_init_eth_fp()
9608 if (!CHIP_IS_E1x(sc)) { in bxe_init_eth_fp()
9617 fp->ustorm_rx_prods_offset = bxe_rx_ustorm_prods_offset(sc, fp); in bxe_init_eth_fp()
9625 for (cos = 0; cos < sc->max_cos; cos++) { in bxe_init_eth_fp()
9631 if (IS_VF(sc)) { in bxe_init_eth_fp()
9635 bxe_init_sb(sc, fp->sb_dma.paddr, BXE_VF_ID_INVALID, FALSE, in bxe_init_eth_fp()
9644 ecore_init_queue_obj(sc, in bxe_init_eth_fp()
9645 &sc->sp_objs[idx].q_obj, in bxe_init_eth_fp()
9648 sc->max_cos, in bxe_init_eth_fp()
9649 SC_FUNC(sc), in bxe_init_eth_fp()
9650 BXE_SP(sc, q_rdata), in bxe_init_eth_fp()
9651 BXE_SP_MAPPING(sc, q_rdata), in bxe_init_eth_fp()
9655 ecore_init_mac_obj(sc, in bxe_init_eth_fp()
9656 &sc->sp_objs[idx].mac_obj, in bxe_init_eth_fp()
9659 SC_FUNC(sc), in bxe_init_eth_fp()
9660 BXE_SP(sc, mac_rdata), in bxe_init_eth_fp()
9661 BXE_SP_MAPPING(sc, mac_rdata), in bxe_init_eth_fp()
9663 &sc->sp_state, in bxe_init_eth_fp()
9665 &sc->macs_pool); in bxe_init_eth_fp()
9667 BLOGD(sc, DBG_LOAD, "fp[%d]: sb=%p cl_id=%d fw_sb=%d igu_sb=%d\n", in bxe_init_eth_fp()
9672 bxe_update_rx_prod(struct bxe_softc *sc, in bxe_update_rx_prod() argument
9697 REG_WR(sc, in bxe_update_rx_prod()
9704 BLOGD(sc, DBG_RX, in bxe_update_rx_prod()
9710 bxe_init_rx_rings(struct bxe_softc *sc) in bxe_init_rx_rings() argument
9715 for (i = 0; i < sc->num_queues; i++) { in bxe_init_rx_rings()
9716 fp = &sc->fp[i]; in bxe_init_rx_rings()
9725 bxe_update_rx_prod(sc, fp, in bxe_init_rx_rings()
9734 if (CHIP_IS_E1(sc)) { in bxe_init_rx_rings()
9735 REG_WR(sc, in bxe_init_rx_rings()
9737 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc))), in bxe_init_rx_rings()
9739 REG_WR(sc, in bxe_init_rx_rings()
9741 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc)) + 4), in bxe_init_rx_rings()
9762 bxe_init_tx_rings(struct bxe_softc *sc) in bxe_init_tx_rings() argument
9766 for (i = 0; i < sc->num_queues; i++) { in bxe_init_tx_rings()
9767 bxe_init_tx_ring_one(&sc->fp[i]); in bxe_init_tx_rings()
9772 bxe_init_def_sb(struct bxe_softc *sc) in bxe_init_def_sb() argument
9774 struct host_sp_status_block *def_sb = sc->def_sb; in bxe_init_def_sb()
9775 bus_addr_t mapping = sc->def_sb_dma.paddr; in bxe_init_def_sb()
9778 int port = SC_PORT(sc); in bxe_init_def_sb()
9779 int func = SC_FUNC(sc); in bxe_init_def_sb()
9787 if (CHIP_INT_MODE_IS_BC(sc)) { in bxe_init_def_sb()
9791 igu_sp_sb_index = sc->igu_dsb_id; in bxe_init_def_sb()
9799 sc->attn_state = 0; in bxe_init_def_sb()
9811 sc->attn_group[index].sig[sindex] = in bxe_init_def_sb()
9812 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index))); in bxe_init_def_sb()
9815 if (!CHIP_IS_E1x(sc)) { in bxe_init_def_sb()
9821 sc->attn_group[index].sig[4] = in bxe_init_def_sb()
9822 REG_RD(sc, (reg_offset_en5 + (0x4 * index))); in bxe_init_def_sb()
9824 sc->attn_group[index].sig[4] = 0; in bxe_init_def_sb()
9828 if (sc->devinfo.int_block == INT_BLOCK_HC) { in bxe_init_def_sb()
9832 REG_WR(sc, reg_offset, U64_LO(section)); in bxe_init_def_sb()
9833 REG_WR(sc, (reg_offset + 4), U64_HI(section)); in bxe_init_def_sb()
9834 } else if (!CHIP_IS_E1x(sc)) { in bxe_init_def_sb()
9835 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); in bxe_init_def_sb()
9836 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); in bxe_init_def_sb()
9842 bxe_zero_sp_sb(sc); in bxe_init_def_sb()
9851 sp_sb_data.p_func.vnic_id = SC_VN(sc); in bxe_init_def_sb()
9854 bxe_wr_sp_sb_data(sc, &sp_sb_data); in bxe_init_def_sb()
9856 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); in bxe_init_def_sb()
9860 bxe_init_sp_ring(struct bxe_softc *sc) in bxe_init_sp_ring() argument
9862 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING); in bxe_init_sp_ring()
9863 sc->spq_prod_idx = 0; in bxe_init_sp_ring()
9864 sc->dsb_sp_prod = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS]; in bxe_init_sp_ring()
9865 sc->spq_prod_bd = sc->spq; in bxe_init_sp_ring()
9866 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT); in bxe_init_sp_ring()
9870 bxe_init_eq_ring(struct bxe_softc *sc) in bxe_init_eq_ring() argument
9876 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1]; in bxe_init_eq_ring()
9878 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr + in bxe_init_eq_ring()
9881 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr + in bxe_init_eq_ring()
9886 sc->eq_cons = 0; in bxe_init_eq_ring()
9887 sc->eq_prod = NUM_EQ_DESC; in bxe_init_eq_ring()
9888 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS]; in bxe_init_eq_ring()
9890 atomic_store_rel_long(&sc->eq_spq_left, in bxe_init_eq_ring()
9896 bxe_init_internal_common(struct bxe_softc *sc) in bxe_init_internal_common() argument
9905 REG_WR(sc, in bxe_init_internal_common()
9910 if (!CHIP_IS_E1x(sc)) { in bxe_init_internal_common()
9911 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET), in bxe_init_internal_common()
9912 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE : HC_IGU_NBC_MODE); in bxe_init_internal_common()
9917 bxe_init_internal(struct bxe_softc *sc, in bxe_init_internal() argument
9923 bxe_init_internal_common(sc); in bxe_init_internal()
9935 BLOGE(sc, "Unknown load_code (0x%x) from MCP\n", load_code); in bxe_init_internal()
9941 storm_memset_func_cfg(struct bxe_softc *sc, in storm_memset_func_cfg() argument
9951 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)tcfg); in storm_memset_func_cfg()
9955 bxe_func_init(struct bxe_softc *sc, in bxe_func_init() argument
9960 if (CHIP_IS_E1x(sc)) { in bxe_func_init()
9961 storm_memset_func_cfg(sc, &tcfg, p->func_id); in bxe_func_init()
9965 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id); in bxe_func_init()
9966 storm_memset_func_en(sc, p->func_id, 1); in bxe_func_init()
9970 storm_memset_spq_addr(sc, p->spq_map, p->func_id); in bxe_func_init()
9971 REG_WR(sc, in bxe_func_init()
9988 bxe_calc_vn_min(struct bxe_softc *sc, in bxe_calc_vn_min() argument
9996 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { in bxe_calc_vn_min()
9997 vn_cfg = sc->devinfo.mf_info.mf_config[vn]; in bxe_calc_vn_min()
10015 if (BXE_IS_ETS_ENABLED(sc)) { in bxe_calc_vn_min()
10017 BLOGD(sc, DBG_LOAD, "Fairness disabled (ETS)\n"); in bxe_calc_vn_min()
10020 BLOGD(sc, DBG_LOAD, in bxe_calc_vn_min()
10028 bxe_extract_max_cfg(struct bxe_softc *sc, in bxe_extract_max_cfg() argument
10035 BLOGD(sc, DBG_LOAD, "Max BW configured to 0 - using 100 instead\n"); in bxe_extract_max_cfg()
10043 bxe_calc_vn_max(struct bxe_softc *sc, in bxe_calc_vn_max() argument
10048 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn]; in bxe_calc_vn_max()
10054 max_cfg = bxe_extract_max_cfg(sc, vn_cfg); in bxe_calc_vn_max()
10056 if (IS_MF_SI(sc)) { in bxe_calc_vn_max()
10058 vn_max_rate = ((sc->link_vars.line_speed * max_cfg) / 100); in bxe_calc_vn_max()
10065 BLOGD(sc, DBG_LOAD, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); in bxe_calc_vn_max()
10071 bxe_cmng_fns_init(struct bxe_softc *sc, in bxe_cmng_fns_init() argument
10080 input.port_rate = sc->link_vars.line_speed; in bxe_cmng_fns_init()
10085 bxe_read_mf_cfg(sc); in bxe_cmng_fns_init()
10089 bxe_calc_vn_min(sc, &input); in bxe_cmng_fns_init()
10092 if (sc->port.pmf) { in bxe_cmng_fns_init()
10093 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { in bxe_cmng_fns_init()
10094 bxe_calc_vn_max(sc, vn, &input); in bxe_cmng_fns_init()
10101 ecore_init_cmng(&input, &sc->cmng); in bxe_cmng_fns_init()
10106 BLOGD(sc, DBG_LOAD, "rate shaping and fairness have been disabled\n"); in bxe_cmng_fns_init()
10110 bxe_get_cmng_fns_mode(struct bxe_softc *sc) in bxe_get_cmng_fns_mode() argument
10112 if (CHIP_REV_IS_SLOW(sc)) { in bxe_get_cmng_fns_mode()
10116 if (IS_MF(sc)) { in bxe_get_cmng_fns_mode()
10124 storm_memset_cmng(struct bxe_softc *sc, in storm_memset_cmng() argument
10136 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)&cmng->port); in storm_memset_cmng()
10138 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { in storm_memset_cmng()
10139 func = func_by_vn(sc, vn); in storm_memset_cmng()
10144 ecore_storm_memset_struct(sc, addr, size, in storm_memset_cmng()
10150 ecore_storm_memset_struct(sc, addr, size, in storm_memset_cmng()
10156 bxe_pf_init(struct bxe_softc *sc) in bxe_pf_init() argument
10162 if (!CHIP_IS_E1x(sc)) { in bxe_pf_init()
10165 REG_WR(sc, in bxe_pf_init()
10168 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)), in bxe_pf_init()
10171 REG_WR(sc, in bxe_pf_init()
10175 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)), in bxe_pf_init()
10186 flags |= (if_getcapenable(sc->ifp) & IFCAP_LRO) ? FUNC_FLG_TPA : 0; in bxe_pf_init()
10189 func_init.pf_id = SC_FUNC(sc); in bxe_pf_init()
10190 func_init.func_id = SC_FUNC(sc); in bxe_pf_init()
10191 func_init.spq_map = sc->spq_dma.paddr; in bxe_pf_init()
10192 func_init.spq_prod = sc->spq_prod_idx; in bxe_pf_init()
10194 bxe_func_init(sc, &func_init); in bxe_pf_init()
10196 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port)); in bxe_pf_init()
10204 sc->link_vars.line_speed = SPEED_10000; in bxe_pf_init()
10205 bxe_cmng_fns_init(sc, TRUE, bxe_get_cmng_fns_mode(sc)); in bxe_pf_init()
10208 if (sc->port.pmf) { in bxe_pf_init()
10209 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); in bxe_pf_init()
10213 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr); in bxe_pf_init()
10214 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr); in bxe_pf_init()
10215 eq_data.producer = sc->eq_prod; in bxe_pf_init()
10218 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc)); in bxe_pf_init()
10222 bxe_hc_int_enable(struct bxe_softc *sc) in bxe_hc_int_enable() argument
10224 int port = SC_PORT(sc); in bxe_hc_int_enable()
10226 uint32_t val = REG_RD(sc, addr); in bxe_hc_int_enable()
10227 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE; in bxe_hc_int_enable()
10228 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) && in bxe_hc_int_enable()
10229 (sc->intr_count == 1)) ? TRUE : FALSE; in bxe_hc_int_enable()
10230 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE; in bxe_hc_int_enable()
10251 if (!CHIP_IS_E1(sc)) { in bxe_hc_int_enable()
10252 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", in bxe_hc_int_enable()
10255 REG_WR(sc, addr, val); in bxe_hc_int_enable()
10261 if (CHIP_IS_E1(sc)) { in bxe_hc_int_enable()
10262 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF); in bxe_hc_int_enable()
10265 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", in bxe_hc_int_enable()
10268 REG_WR(sc, addr, val); in bxe_hc_int_enable()
10273 if (!CHIP_IS_E1(sc)) { in bxe_hc_int_enable()
10275 if (IS_MF(sc)) { in bxe_hc_int_enable()
10276 val = (0xee0f | (1 << (SC_VN(sc) + 4))); in bxe_hc_int_enable()
10277 if (sc->port.pmf) { in bxe_hc_int_enable()
10285 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val); in bxe_hc_int_enable()
10286 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val); in bxe_hc_int_enable()
10294 bxe_igu_int_enable(struct bxe_softc *sc) in bxe_igu_int_enable() argument
10297 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE; in bxe_igu_int_enable()
10298 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) && in bxe_igu_int_enable()
10299 (sc->intr_count == 1)) ? TRUE : FALSE; in bxe_igu_int_enable()
10300 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE; in bxe_igu_int_enable()
10302 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); in bxe_igu_int_enable()
10326 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bxe_igu_int_enable()
10327 bxe_ack_int(sc); in bxe_igu_int_enable()
10332 BLOGD(sc, DBG_INTR, "write 0x%x to IGU mode %s\n", in bxe_igu_int_enable()
10335 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bxe_igu_int_enable()
10340 if (IS_MF(sc)) { in bxe_igu_int_enable()
10341 val = (0xee0f | (1 << (SC_VN(sc) + 4))); in bxe_igu_int_enable()
10342 if (sc->port.pmf) { in bxe_igu_int_enable()
10350 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val); in bxe_igu_int_enable()
10351 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val); in bxe_igu_int_enable()
10358 bxe_int_enable(struct bxe_softc *sc) in bxe_int_enable() argument
10360 if (sc->devinfo.int_block == INT_BLOCK_HC) { in bxe_int_enable()
10361 bxe_hc_int_enable(sc); in bxe_int_enable()
10363 bxe_igu_int_enable(sc); in bxe_int_enable()
10368 bxe_hc_int_disable(struct bxe_softc *sc) in bxe_hc_int_disable() argument
10370 int port = SC_PORT(sc); in bxe_hc_int_disable()
10372 uint32_t val = REG_RD(sc, addr); in bxe_hc_int_disable()
10379 if (CHIP_IS_E1(sc)) { in bxe_hc_int_disable()
10384 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0); in bxe_hc_int_disable()
10396 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", val, port, addr); in bxe_hc_int_disable()
10401 REG_WR(sc, addr, val); in bxe_hc_int_disable()
10402 if (REG_RD(sc, addr) != val) { in bxe_hc_int_disable()
10403 BLOGE(sc, "proper val not read from HC IGU!\n"); in bxe_hc_int_disable()
10408 bxe_igu_int_disable(struct bxe_softc *sc) in bxe_igu_int_disable() argument
10410 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); in bxe_igu_int_disable()
10416 BLOGD(sc, DBG_INTR, "write %x to IGU\n", val); in bxe_igu_int_disable()
10421 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bxe_igu_int_disable()
10422 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) { in bxe_igu_int_disable()
10423 BLOGE(sc, "proper val not read from IGU!\n"); in bxe_igu_int_disable()
10428 bxe_int_disable(struct bxe_softc *sc) in bxe_int_disable() argument
10430 if (sc->devinfo.int_block == INT_BLOCK_HC) { in bxe_int_disable()
10431 bxe_hc_int_disable(sc); in bxe_int_disable()
10433 bxe_igu_int_disable(sc); in bxe_int_disable()
10438 bxe_nic_init(struct bxe_softc *sc, in bxe_nic_init() argument
10443 for (i = 0; i < sc->num_queues; i++) { in bxe_nic_init()
10444 bxe_init_eth_fp(sc, i); in bxe_nic_init()
10449 bxe_init_rx_rings(sc); in bxe_nic_init()
10450 bxe_init_tx_rings(sc); in bxe_nic_init()
10452 if (IS_VF(sc)) { in bxe_nic_init()
10457 elink_init_mod_abs_int(sc, &sc->link_vars, in bxe_nic_init()
10458 sc->devinfo.chip_id, in bxe_nic_init()
10459 sc->devinfo.shmem_base, in bxe_nic_init()
10460 sc->devinfo.shmem2_base, in bxe_nic_init()
10461 SC_PORT(sc)); in bxe_nic_init()
10463 bxe_init_def_sb(sc); in bxe_nic_init()
10464 bxe_update_dsb_idx(sc); in bxe_nic_init()
10465 bxe_init_sp_ring(sc); in bxe_nic_init()
10466 bxe_init_eq_ring(sc); in bxe_nic_init()
10467 bxe_init_internal(sc, load_code); in bxe_nic_init()
10468 bxe_pf_init(sc); in bxe_nic_init()
10469 bxe_stats_init(sc); in bxe_nic_init()
10474 bxe_int_enable(sc); in bxe_nic_init()
10477 bxe_attn_int_deasserted0(sc, in bxe_nic_init()
10478 REG_RD(sc, in bxe_nic_init()
10480 SC_PORT(sc)*4)) & in bxe_nic_init()
10485 bxe_init_objs(struct bxe_softc *sc) in bxe_init_objs() argument
10489 (sc->flags & BXE_TX_SWITCHING) ? ECORE_OBJ_TYPE_RX_TX : in bxe_init_objs()
10493 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj); in bxe_init_objs()
10496 ecore_init_mcast_obj(sc, in bxe_init_objs()
10497 &sc->mcast_obj, in bxe_init_objs()
10498 sc->fp[0].cl_id, in bxe_init_objs()
10499 sc->fp[0].index, in bxe_init_objs()
10500 SC_FUNC(sc), in bxe_init_objs()
10501 SC_FUNC(sc), in bxe_init_objs()
10502 BXE_SP(sc, mcast_rdata), in bxe_init_objs()
10503 BXE_SP_MAPPING(sc, mcast_rdata), in bxe_init_objs()
10505 &sc->sp_state, in bxe_init_objs()
10509 ecore_init_mac_credit_pool(sc, in bxe_init_objs()
10510 &sc->macs_pool, in bxe_init_objs()
10511 SC_FUNC(sc), in bxe_init_objs()
10512 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) : in bxe_init_objs()
10513 VNICS_PER_PATH(sc)); in bxe_init_objs()
10515 ecore_init_vlan_credit_pool(sc, in bxe_init_objs()
10516 &sc->vlans_pool, in bxe_init_objs()
10517 SC_ABS_FUNC(sc) >> 1, in bxe_init_objs()
10518 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) : in bxe_init_objs()
10519 VNICS_PER_PATH(sc)); in bxe_init_objs()
10522 ecore_init_rss_config_obj(sc, in bxe_init_objs()
10523 &sc->rss_conf_obj, in bxe_init_objs()
10524 sc->fp[0].cl_id, in bxe_init_objs()
10525 sc->fp[0].index, in bxe_init_objs()
10526 SC_FUNC(sc), in bxe_init_objs()
10527 SC_FUNC(sc), in bxe_init_objs()
10528 BXE_SP(sc, rss_rdata), in bxe_init_objs()
10529 BXE_SP_MAPPING(sc, rss_rdata), in bxe_init_objs()
10531 &sc->sp_state, ECORE_OBJ_TYPE_RX); in bxe_init_objs()
10539 bxe_func_start(struct bxe_softc *sc) in bxe_func_start() argument
10547 func_params.f_obj = &sc->func_obj; in bxe_func_start()
10551 start_params->mf_mode = sc->devinfo.mf_info.mf_mode; in bxe_func_start()
10552 start_params->sd_vlan_tag = OVLAN(sc); in bxe_func_start()
10554 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) { in bxe_func_start()
10563 return (ecore_func_state_change(sc, &func_params)); in bxe_func_start()
10567 bxe_set_power_state(struct bxe_softc *sc, in bxe_set_power_state() argument
10573 if (!(sc->devinfo.pcie_cap_flags & BXE_PM_CAPABLE_FLAG)) { in bxe_set_power_state()
10574 BLOGW(sc, "No power capability\n"); in bxe_set_power_state()
10578 pmcsr = pci_read_config(sc->dev, in bxe_set_power_state()
10579 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), in bxe_set_power_state()
10584 pci_write_config(sc->dev, in bxe_set_power_state()
10585 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), in bxe_set_power_state()
10599 if (CHIP_REV_IS_SLOW(sc)) { in bxe_set_power_state()
10606 if (sc->wol) { in bxe_set_power_state()
10610 pci_write_config(sc->dev, in bxe_set_power_state()
10611 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), in bxe_set_power_state()
10621 BLOGE(sc, "Can't support PCI power state = 0x%x pmcsr 0x%x\n", in bxe_set_power_state()
10632 bxe_trylock_hw_lock(struct bxe_softc *sc, in bxe_trylock_hw_lock() argument
10637 int func = SC_FUNC(sc); in bxe_trylock_hw_lock()
10640 BLOGD(sc, DBG_LOAD, "Trying to take a resource lock 0x%x\n", resource); in bxe_trylock_hw_lock()
10644 BLOGD(sc, DBG_LOAD, in bxe_trylock_hw_lock()
10657 REG_WR(sc, hw_lock_control_reg + 4, resource_bit); in bxe_trylock_hw_lock()
10658 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_trylock_hw_lock()
10663 BLOGE(sc, "Failed to get a resource lock 0x%x func %d " in bxe_trylock_hw_lock()
10675 bxe_get_leader_lock_resource(struct bxe_softc *sc) in bxe_get_leader_lock_resource() argument
10677 if (SC_PATH(sc)) { in bxe_get_leader_lock_resource()
10686 bxe_trylock_leader_lock(struct bxe_softc *sc) in bxe_trylock_leader_lock() argument
10688 return (bxe_trylock_hw_lock(sc, bxe_get_leader_lock_resource(sc))); in bxe_trylock_leader_lock()
10692 bxe_release_leader_lock(struct bxe_softc *sc) in bxe_release_leader_lock() argument
10694 return (bxe_release_hw_lock(sc, bxe_get_leader_lock_resource(sc))); in bxe_release_leader_lock()
10699 bxe_set_234_gates(struct bxe_softc *sc, in bxe_set_234_gates() argument
10705 if (!CHIP_IS_E1(sc)) { in bxe_set_234_gates()
10707 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close); in bxe_set_234_gates()
10709 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); in bxe_set_234_gates()
10713 if (CHIP_IS_E1x(sc)) { in bxe_set_234_gates()
10715 val = REG_RD(sc, HC_REG_CONFIG_1); in bxe_set_234_gates()
10716 REG_WR(sc, HC_REG_CONFIG_1, in bxe_set_234_gates()
10720 val = REG_RD(sc, HC_REG_CONFIG_0); in bxe_set_234_gates()
10721 REG_WR(sc, HC_REG_CONFIG_0, in bxe_set_234_gates()
10726 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION); in bxe_set_234_gates()
10728 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, in bxe_set_234_gates()
10734 BLOGD(sc, DBG_LOAD, "%s gates #2, #3 and #4\n", in bxe_set_234_gates()
10742 bxe_er_poll_igu_vq(struct bxe_softc *sc) in bxe_er_poll_igu_vq() argument
10748 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS); in bxe_er_poll_igu_vq()
10758 BLOGE(sc, "Still pending IGU requests bits=0x%08x!\n", pend_bits); in bxe_er_poll_igu_vq()
10768 bxe_clp_reset_prep(struct bxe_softc *sc, in bxe_clp_reset_prep() argument
10772 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb); in bxe_clp_reset_prep()
10774 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); in bxe_clp_reset_prep()
10779 bxe_clp_reset_done(struct bxe_softc *sc, in bxe_clp_reset_done() argument
10783 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb); in bxe_clp_reset_done()
10784 MFCFG_WR(sc, shared_mf_config.clp_mb, in bxe_clp_reset_done()
10790 bxe_reset_mcp_prep(struct bxe_softc *sc, in bxe_reset_mcp_prep() argument
10797 if (!CHIP_IS_E1(sc)) { in bxe_reset_mcp_prep()
10798 bxe_clp_reset_prep(sc, magic_val); in bxe_reset_mcp_prep()
10802 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); in bxe_reset_mcp_prep()
10804 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]); in bxe_reset_mcp_prep()
10808 REG_WR(sc, shmem + validity_offset, 0); in bxe_reset_mcp_prep()
10816 bxe_mcp_wait_one(struct bxe_softc *sc) in bxe_mcp_wait_one() argument
10819 if (CHIP_REV_IS_SLOW(sc)) { in bxe_mcp_wait_one()
10828 bxe_init_shmem(struct bxe_softc *sc) in bxe_init_shmem() argument
10834 sc->devinfo.shmem_base = in bxe_init_shmem()
10835 sc->link_params.shmem_base = in bxe_init_shmem()
10836 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); in bxe_init_shmem()
10838 if (sc->devinfo.shmem_base) { in bxe_init_shmem()
10839 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]); in bxe_init_shmem()
10844 bxe_mcp_wait_one(sc); in bxe_init_shmem()
10848 BLOGE(sc, "BAD MCP validity signature\n"); in bxe_init_shmem()
10854 bxe_reset_mcp_comp(struct bxe_softc *sc, in bxe_reset_mcp_comp() argument
10857 int rc = bxe_init_shmem(sc); in bxe_reset_mcp_comp()
10860 if (!CHIP_IS_E1(sc)) { in bxe_reset_mcp_comp()
10861 bxe_clp_reset_done(sc, magic_val); in bxe_reset_mcp_comp()
10868 bxe_pxp_prep(struct bxe_softc *sc) in bxe_pxp_prep() argument
10870 if (!CHIP_IS_E1(sc)) { in bxe_pxp_prep()
10871 REG_WR(sc, PXP2_REG_RD_START_INIT, 0); in bxe_pxp_prep()
10872 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0); in bxe_pxp_prep()
10887 bxe_process_kill_chip_reset(struct bxe_softc *sc, in bxe_process_kill_chip_reset() argument
10941 if (CHIP_IS_E1(sc)) in bxe_process_kill_chip_reset()
10943 else if (CHIP_IS_E1H(sc)) in bxe_process_kill_chip_reset()
10945 else if (CHIP_IS_E2(sc)) in bxe_process_kill_chip_reset()
10968 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bxe_process_kill_chip_reset()
10971 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bxe_process_kill_chip_reset()
10977 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bxe_process_kill_chip_reset()
10983 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); in bxe_process_kill_chip_reset()
10988 bxe_process_kill(struct bxe_softc *sc, in bxe_process_kill() argument
10998 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT); in bxe_process_kill()
10999 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT); in bxe_process_kill()
11000 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0); in bxe_process_kill()
11001 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1); in bxe_process_kill()
11002 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2); in bxe_process_kill()
11003 if (CHIP_IS_E3(sc)) { in bxe_process_kill()
11004 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32); in bxe_process_kill()
11011 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff))) in bxe_process_kill()
11017 BLOGE(sc, "ERROR: Tetris buffer didn't get empty or there " in bxe_process_kill()
11029 bxe_set_234_gates(sc, TRUE); in bxe_process_kill()
11032 if (!CHIP_IS_E1x(sc) && bxe_er_poll_igu_vq(sc)) { in bxe_process_kill()
11039 REG_WR(sc, MISC_REG_UNPREPARED, 0); in bxe_process_kill()
11054 bxe_reset_mcp_prep(sc, &val); in bxe_process_kill()
11058 bxe_pxp_prep(sc); in bxe_process_kill()
11062 bxe_process_kill_chip_reset(sc, global); in bxe_process_kill()
11066 if (!CHIP_IS_E1(sc)) in bxe_process_kill()
11067 REG_WR(sc, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); in bxe_process_kill()
11071 if (global && bxe_reset_mcp_comp(sc, val)) { in bxe_process_kill()
11078 bxe_set_234_gates(sc, FALSE); in bxe_process_kill()
11089 bxe_leader_reset(struct bxe_softc *sc) in bxe_leader_reset() argument
11092 uint8_t global = bxe_reset_is_global(sc); in bxe_leader_reset()
11099 if (!global && !BXE_NOMCP(sc)) { in bxe_leader_reset()
11100 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ, in bxe_leader_reset()
11103 BLOGE(sc, "MCP response failure, aborting\n"); in bxe_leader_reset()
11110 BLOGE(sc, "MCP unexpected response, aborting\n"); in bxe_leader_reset()
11115 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); in bxe_leader_reset()
11117 BLOGE(sc, "MCP response failure, aborting\n"); in bxe_leader_reset()
11124 if (bxe_process_kill(sc, global)) { in bxe_leader_reset()
11125 BLOGE(sc, "Something bad occurred on engine %d!\n", SC_PATH(sc)); in bxe_leader_reset()
11134 bxe_set_reset_done(sc); in bxe_leader_reset()
11136 bxe_clear_reset_global(sc); in bxe_leader_reset()
11142 if (!global && !BXE_NOMCP(sc)) { in bxe_leader_reset()
11143 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); in bxe_leader_reset()
11144 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0); in bxe_leader_reset()
11149 sc->is_leader = 0; in bxe_leader_reset()
11150 bxe_release_leader_lock(sc); in bxe_leader_reset()
11162 bxe_pf_q_prep_init(struct bxe_softc *sc, in bxe_pf_q_prep_init() argument
11177 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0; in bxe_pf_q_prep_init()
11179 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0; in bxe_pf_q_prep_init()
11189 init_params->max_cos = sc->max_cos; in bxe_pf_q_prep_init()
11191 BLOGD(sc, DBG_LOAD, "fp %d setting queue params max cos to %d\n", in bxe_pf_q_prep_init()
11200 init_params->cxts[cos] = &sc->context[cxt_index].vcxt[cxt_offset].eth; in bxe_pf_q_prep_init()
11206 bxe_get_common_flags(struct bxe_softc *sc, in bxe_get_common_flags() argument
11230 if (sc->flags & BXE_TX_SWITCHING) { in bxe_get_common_flags()
11240 bxe_get_q_flags(struct bxe_softc *sc, in bxe_get_q_flags() argument
11246 if (IS_MF_SD(sc)) { in bxe_get_q_flags()
11250 if (if_getcapenable(sc->ifp) & IFCAP_LRO) { in bxe_get_q_flags()
11263 return (flags | bxe_get_common_flags(sc, fp, TRUE)); in bxe_get_q_flags()
11267 bxe_pf_q_prep_general(struct bxe_softc *sc, in bxe_pf_q_prep_general() argument
11274 gen_init->mtu = sc->mtu; in bxe_pf_q_prep_general()
11279 bxe_pf_rx_q_prep(struct bxe_softc *sc, in bxe_pf_rx_q_prep() argument
11288 pause->sge_th_lo = SGE_TH_LO(sc); in bxe_pf_rx_q_prep()
11289 pause->sge_th_hi = SGE_TH_HI(sc); in bxe_pf_rx_q_prep()
11292 if (sc->dropless_fc && in bxe_pf_rx_q_prep()
11295 BLOGW(sc, "sge ring threshold limit\n"); in bxe_pf_rx_q_prep()
11299 tpa_agg_size = (2 * sc->mtu); in bxe_pf_rx_q_prep()
11300 if (tpa_agg_size < sc->max_aggregation_size) { in bxe_pf_rx_q_prep()
11301 tpa_agg_size = sc->max_aggregation_size; in bxe_pf_rx_q_prep()
11304 max_sge = SGE_PAGE_ALIGN(sc->mtu) >> SGE_PAGE_SHIFT; in bxe_pf_rx_q_prep()
11310 if (!CHIP_IS_E1(sc)) { in bxe_pf_rx_q_prep()
11311 pause->bd_th_lo = BD_TH_LO(sc); in bxe_pf_rx_q_prep()
11312 pause->bd_th_hi = BD_TH_HI(sc); in bxe_pf_rx_q_prep()
11314 pause->rcq_th_lo = RCQ_TH_LO(sc); in bxe_pf_rx_q_prep()
11315 pause->rcq_th_hi = RCQ_TH_HI(sc); in bxe_pf_rx_q_prep()
11318 if (sc->dropless_fc && in bxe_pf_rx_q_prep()
11320 sc->rx_ring_size) { in bxe_pf_rx_q_prep()
11321 BLOGW(sc, "rx bd ring threshold limit\n"); in bxe_pf_rx_q_prep()
11324 if (sc->dropless_fc && in bxe_pf_rx_q_prep()
11327 BLOGW(sc, "rcq ring threshold limit\n"); in bxe_pf_rx_q_prep()
11350 rxq_init->rss_engine_id = SC_FUNC(sc); in bxe_pf_rx_q_prep()
11351 rxq_init->mcast_engine_id = SC_FUNC(sc); in bxe_pf_rx_q_prep()
11358 rxq_init->max_tpa_queues = MAX_AGG_QS(sc); in bxe_pf_rx_q_prep()
11369 if (IS_MF_AFEX(sc)) { in bxe_pf_rx_q_prep()
11371 sc->devinfo.mf_info.afex_def_vlan_tag; in bxe_pf_rx_q_prep()
11377 bxe_pf_tx_q_prep(struct bxe_softc *sc, in bxe_pf_tx_q_prep() argument
11396 txq_init->tss_leading_cl_id = BXE_FP(sc, 0, cl_id); in bxe_pf_tx_q_prep()
11405 bxe_setup_queue(struct bxe_softc *sc, in bxe_setup_queue() argument
11414 BLOGD(sc, DBG_LOAD, "setting up queue %d\n", fp->index); in bxe_setup_queue()
11416 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); in bxe_setup_queue()
11418 q_params.q_obj = &BXE_SP_OBJ(sc, fp).q_obj; in bxe_setup_queue()
11424 bxe_pf_q_prep_init(sc, fp, &q_params.params.init); in bxe_setup_queue()
11430 rc = ecore_queue_state_change(sc, &q_params); in bxe_setup_queue()
11432 BLOGE(sc, "Queue(%d) INIT failed rc = %d\n", fp->index, rc); in bxe_setup_queue()
11436 BLOGD(sc, DBG_LOAD, "init complete\n"); in bxe_setup_queue()
11442 setup_params->flags = bxe_get_q_flags(sc, fp, leading); in bxe_setup_queue()
11445 bxe_pf_q_prep_general(sc, fp, &setup_params->gen_params, in bxe_setup_queue()
11448 bxe_pf_rx_q_prep(sc, fp, in bxe_setup_queue()
11452 bxe_pf_tx_q_prep(sc, fp, in bxe_setup_queue()
11460 rc = ecore_queue_state_change(sc, &q_params); in bxe_setup_queue()
11462 BLOGE(sc, "Queue(%d) SETUP failed (rc = %d)\n", fp->index, rc); in bxe_setup_queue()
11470 bxe_setup_leading(struct bxe_softc *sc) in bxe_setup_leading() argument
11472 return (bxe_setup_queue(sc, &sc->fp[0], TRUE)); in bxe_setup_leading()
11476 bxe_config_rss_pf(struct bxe_softc *sc, in bxe_config_rss_pf() argument
11520 return (ecore_config_rss(sc, ¶ms)); in bxe_config_rss_pf()
11524 bxe_config_rss_eth(struct bxe_softc *sc, in bxe_config_rss_eth() argument
11527 return (bxe_config_rss_pf(sc, &sc->rss_conf_obj, config_hash)); in bxe_config_rss_eth()
11531 bxe_init_rss_pf(struct bxe_softc *sc) in bxe_init_rss_pf() argument
11533 uint8_t num_eth_queues = BXE_NUM_ETH_QUEUES(sc); in bxe_init_rss_pf()
11540 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) { in bxe_init_rss_pf()
11541 sc->rss_conf_obj.ind_table[i] = in bxe_init_rss_pf()
11542 (sc->fp->cl_id + (i % num_eth_queues)); in bxe_init_rss_pf()
11545 if (sc->udp_rss) { in bxe_init_rss_pf()
11546 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1; in bxe_init_rss_pf()
11556 return (bxe_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc))); in bxe_init_rss_pf()
11560 bxe_set_mac_one(struct bxe_softc *sc, in bxe_set_mac_one() argument
11587 rc = ecore_config_vlan_mac(sc, &ramrod_param); in bxe_set_mac_one()
11590 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n"); in bxe_set_mac_one()
11594 BLOGE(sc, "%s MAC failed (%d)\n", (set ? "Set" : "Delete"), rc); in bxe_set_mac_one()
11601 bxe_set_eth_mac(struct bxe_softc *sc, in bxe_set_eth_mac() argument
11606 BLOGD(sc, DBG_LOAD, "Adding Ethernet MAC\n"); in bxe_set_eth_mac()
11611 return (bxe_set_mac_one(sc, sc->link_params.mac_addr, in bxe_set_eth_mac()
11612 &sc->sp_objs->mac_obj, in bxe_set_eth_mac()
11617 bxe_get_cur_phy_idx(struct bxe_softc *sc) in bxe_get_cur_phy_idx() argument
11621 if (sc->link_params.num_phys <= 1) { in bxe_get_cur_phy_idx()
11625 if (sc->link_vars.link_up) { in bxe_get_cur_phy_idx()
11628 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) && in bxe_get_cur_phy_idx()
11629 (sc->link_params.phy[ELINK_EXT_PHY2].supported & in bxe_get_cur_phy_idx()
11633 switch (elink_phy_selection(&sc->link_params)) { in bxe_get_cur_phy_idx()
11650 bxe_get_link_cfg_idx(struct bxe_softc *sc) in bxe_get_link_cfg_idx() argument
11652 uint32_t sel_phy_idx = bxe_get_cur_phy_idx(sc); in bxe_get_link_cfg_idx()
11660 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) { in bxe_get_link_cfg_idx()
11671 bxe_set_requested_fc(struct bxe_softc *sc) in bxe_set_requested_fc() argument
11678 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) { in bxe_set_requested_fc()
11679 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX; in bxe_set_requested_fc()
11681 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH; in bxe_set_requested_fc()
11686 bxe_calc_fc_adv(struct bxe_softc *sc) in bxe_calc_fc_adv() argument
11688 uint8_t cfg_idx = bxe_get_link_cfg_idx(sc); in bxe_calc_fc_adv()
11691 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | in bxe_calc_fc_adv()
11694 switch (sc->link_vars.ieee_fc & in bxe_calc_fc_adv()
11698 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | in bxe_calc_fc_adv()
11703 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; in bxe_calc_fc_adv()
11713 bxe_get_mf_speed(struct bxe_softc *sc) in bxe_get_mf_speed() argument
11715 uint16_t line_speed = sc->link_vars.line_speed; in bxe_get_mf_speed()
11716 if (IS_MF(sc)) { in bxe_get_mf_speed()
11718 bxe_extract_max_cfg(sc, sc->devinfo.mf_info.mf_config[SC_VN(sc)]); in bxe_get_mf_speed()
11721 if (IS_MF_SI(sc)) { in bxe_get_mf_speed()
11736 bxe_fill_report_data(struct bxe_softc *sc, in bxe_fill_report_data() argument
11739 uint16_t line_speed = bxe_get_mf_speed(sc); in bxe_fill_report_data()
11747 if (!sc->link_vars.link_up || (sc->flags & BXE_MF_FUNC_DIS)) { in bxe_fill_report_data()
11752 if (sc->link_vars.duplex == DUPLEX_FULL) { in bxe_fill_report_data()
11757 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) { in bxe_fill_report_data()
11762 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) { in bxe_fill_report_data()
11769 bxe_link_report_locked(struct bxe_softc *sc) in bxe_link_report_locked() argument
11774 if (IS_PF(sc) && !CHIP_IS_E1(sc)) { in bxe_link_report_locked()
11775 bxe_read_mf_cfg(sc); in bxe_link_report_locked()
11779 bxe_fill_report_data(sc, &cur_data); in bxe_link_report_locked()
11782 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) || in bxe_link_report_locked()
11784 &sc->last_reported_link.link_report_flags) && in bxe_link_report_locked()
11790 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %x, last_reported_link = %x\n", in bxe_link_report_locked()
11791 cur_data.link_report_flags, sc->last_reported_link.link_report_flags); in bxe_link_report_locked()
11792 sc->link_cnt++; in bxe_link_report_locked()
11794 ELINK_DEBUG_P1(sc, "link status change count = %x\n", sc->link_cnt); in bxe_link_report_locked()
11796 memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data)); in bxe_link_report_locked()
11800 if_link_state_change(sc->ifp, LINK_STATE_DOWN); in bxe_link_report_locked()
11808 ELINK_DEBUG_P0(sc, "link set to full duplex\n"); in bxe_link_report_locked()
11811 ELINK_DEBUG_P0(sc, "link set to half duplex\n"); in bxe_link_report_locked()
11842 if_link_state_change(sc->ifp, LINK_STATE_UP); in bxe_link_report_locked()
11843 BLOGI(sc, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n", in bxe_link_report_locked()
11849 bxe_link_report(struct bxe_softc *sc) in bxe_link_report() argument
11851 bxe_acquire_phy_lock(sc); in bxe_link_report()
11852 bxe_link_report_locked(sc); in bxe_link_report()
11853 bxe_release_phy_lock(sc); in bxe_link_report()
11857 bxe_link_status_update(struct bxe_softc *sc) in bxe_link_status_update() argument
11859 if (sc->state != BXE_STATE_OPEN) { in bxe_link_status_update()
11863 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) { in bxe_link_status_update()
11864 elink_link_status_update(&sc->link_params, &sc->link_vars); in bxe_link_status_update()
11866 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half | in bxe_link_status_update()
11878 sc->port.advertising[0] = sc->port.supported[0]; in bxe_link_status_update()
11880 sc->link_params.sc = sc; in bxe_link_status_update()
11881 sc->link_params.port = SC_PORT(sc); in bxe_link_status_update()
11882 sc->link_params.req_duplex[0] = DUPLEX_FULL; in bxe_link_status_update()
11883 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE; in bxe_link_status_update()
11884 sc->link_params.req_line_speed[0] = SPEED_10000; in bxe_link_status_update()
11885 sc->link_params.speed_cap_mask[0] = 0x7f0000; in bxe_link_status_update()
11886 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G; in bxe_link_status_update()
11888 if (CHIP_REV_IS_FPGA(sc)) { in bxe_link_status_update()
11889 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC; in bxe_link_status_update()
11890 sc->link_vars.line_speed = ELINK_SPEED_1000; in bxe_link_status_update()
11891 sc->link_vars.link_status = (LINK_STATUS_LINK_UP | in bxe_link_status_update()
11894 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC; in bxe_link_status_update()
11895 sc->link_vars.line_speed = ELINK_SPEED_10000; in bxe_link_status_update()
11896 sc->link_vars.link_status = (LINK_STATUS_LINK_UP | in bxe_link_status_update()
11900 sc->link_vars.link_up = 1; in bxe_link_status_update()
11902 sc->link_vars.duplex = DUPLEX_FULL; in bxe_link_status_update()
11903 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE; in bxe_link_status_update()
11905 if (IS_PF(sc)) { in bxe_link_status_update()
11906 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0); in bxe_link_status_update()
11907 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); in bxe_link_status_update()
11908 bxe_link_report(sc); in bxe_link_status_update()
11912 if (IS_PF(sc)) { in bxe_link_status_update()
11913 if (sc->link_vars.link_up) { in bxe_link_status_update()
11914 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); in bxe_link_status_update()
11916 bxe_stats_handle(sc, STATS_EVENT_STOP); in bxe_link_status_update()
11918 bxe_link_report(sc); in bxe_link_status_update()
11920 bxe_link_report(sc); in bxe_link_status_update()
11921 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); in bxe_link_status_update()
11926 bxe_initial_phy_init(struct bxe_softc *sc, in bxe_initial_phy_init() argument
11929 int rc, cfg_idx = bxe_get_link_cfg_idx(sc); in bxe_initial_phy_init()
11930 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx]; in bxe_initial_phy_init()
11931 struct elink_params *lp = &sc->link_params; in bxe_initial_phy_init()
11933 bxe_set_requested_fc(sc); in bxe_initial_phy_init()
11935 if (CHIP_REV_IS_SLOW(sc)) { in bxe_initial_phy_init()
11936 uint32_t bond = CHIP_BOND_ID(sc); in bxe_initial_phy_init()
11939 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) { in bxe_initial_phy_init()
11942 if (CHIP_IS_E3(sc)) { in bxe_initial_phy_init()
11948 if (CHIP_IS_E3(sc)) { in bxe_initial_phy_init()
11960 sc->link_params.feature_config_flags |= feat; in bxe_initial_phy_init()
11963 bxe_acquire_phy_lock(sc); in bxe_initial_phy_init()
11982 rc = elink_phy_init(&sc->link_params, &sc->link_vars); in bxe_initial_phy_init()
11984 bxe_release_phy_lock(sc); in bxe_initial_phy_init()
11986 bxe_calc_fc_adv(sc); in bxe_initial_phy_init()
11988 if (sc->link_vars.link_up) { in bxe_initial_phy_init()
11989 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); in bxe_initial_phy_init()
11990 bxe_link_report(sc); in bxe_initial_phy_init()
11993 if (!CHIP_REV_IS_SLOW(sc)) { in bxe_initial_phy_init()
11994 bxe_periodic_start(sc); in bxe_initial_phy_init()
11997 sc->link_params.req_line_speed[cfg_idx] = req_line_speed; in bxe_initial_phy_init()
12013 bxe_init_mcast_macs_list(struct bxe_softc *sc, in bxe_init_mcast_macs_list() argument
12016 if_t ifp = sc->ifp; in bxe_init_mcast_macs_list()
12033 BLOGE(sc, "Failed to allocate temp mcast list\n"); in bxe_init_mcast_macs_list()
12041 BLOGD(sc, DBG_LOAD, in bxe_init_mcast_macs_list()
12067 bxe_set_mc_list(struct bxe_softc *sc) in bxe_set_mc_list() argument
12072 rparam.mcast_obj = &sc->mcast_obj; in bxe_set_mc_list()
12074 BXE_MCAST_LOCK(sc); in bxe_set_mc_list()
12077 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); in bxe_set_mc_list()
12079 BLOGE(sc, "Failed to clear multicast configuration: %d\n", rc); in bxe_set_mc_list()
12081 BXE_MCAST_UNLOCK(sc); in bxe_set_mc_list()
12086 rc = bxe_init_mcast_macs_list(sc, &rparam); in bxe_set_mc_list()
12088 BLOGE(sc, "Failed to create mcast MACs list (%d)\n", rc); in bxe_set_mc_list()
12089 BXE_MCAST_UNLOCK(sc); in bxe_set_mc_list()
12094 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_ADD); in bxe_set_mc_list()
12096 BLOGE(sc, "Failed to set new mcast config (%d)\n", rc); in bxe_set_mc_list()
12101 BXE_MCAST_UNLOCK(sc); in bxe_set_mc_list()
12107 struct bxe_softc *sc; member
12116 struct ecore_vlan_mac_obj *mac_obj = &ctx->sc->sp_objs->mac_obj; in bxe_set_addr()
12122 rc = bxe_set_mac_one(ctx->sc, (uint8_t *)LLADDR(sdl), mac_obj, TRUE, in bxe_set_addr()
12127 BLOGD(ctx->sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n"); in bxe_set_addr()
12129 BLOGE(ctx->sc, "Failed to schedule ADD operations (%d)\n", rc); in bxe_set_addr()
12137 bxe_set_uc_list(struct bxe_softc *sc) in bxe_set_uc_list() argument
12139 if_t ifp = sc->ifp; in bxe_set_uc_list()
12140 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj; in bxe_set_uc_list()
12141 struct bxe_set_addr_ctx ctx = { sc, 0, 0 }; in bxe_set_uc_list()
12145 rc = bxe_del_all_macs(sc, mac_obj, ECORE_UC_LIST_MAC, FALSE); in bxe_set_uc_list()
12147 BLOGE(sc, "Failed to schedule delete of all ETH MACs (%d)\n", rc); in bxe_set_uc_list()
12157 return (bxe_set_mac_one(sc, NULL, mac_obj, FALSE /* don't care */, in bxe_set_uc_list()
12162 bxe_set_rx_mode(struct bxe_softc *sc) in bxe_set_rx_mode() argument
12164 if_t ifp = sc->ifp; in bxe_set_rx_mode()
12167 if (sc->state != BXE_STATE_OPEN) { in bxe_set_rx_mode()
12168 BLOGD(sc, DBG_SP, "state is %x, returning\n", sc->state); in bxe_set_rx_mode()
12172 BLOGD(sc, DBG_SP, "if_flags(ifp)=0x%x\n", if_getflags(sc->ifp)); in bxe_set_rx_mode()
12178 CHIP_IS_E1(sc))) { in bxe_set_rx_mode()
12181 if (IS_PF(sc)) { in bxe_set_rx_mode()
12183 if (bxe_set_mc_list(sc) < 0) { in bxe_set_rx_mode()
12186 if (bxe_set_uc_list(sc) < 0) { in bxe_set_rx_mode()
12192 sc->rx_mode = rx_mode; in bxe_set_rx_mode()
12195 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) { in bxe_set_rx_mode()
12196 BLOGD(sc, DBG_LOAD, "Scheduled setting rx_mode with ECORE...\n"); in bxe_set_rx_mode()
12197 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); in bxe_set_rx_mode()
12201 if (IS_PF(sc)) { in bxe_set_rx_mode()
12202 bxe_set_storm_rx_mode(sc); in bxe_set_rx_mode()
12209 bxe_update_drv_flags(struct bxe_softc *sc, in bxe_update_drv_flags() argument
12215 if (SHMEM2_HAS(sc, drv_flags)) { in bxe_update_drv_flags()
12216 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS); in bxe_update_drv_flags()
12217 drv_flags = SHMEM2_RD(sc, drv_flags); in bxe_update_drv_flags()
12225 SHMEM2_WR(sc, drv_flags, drv_flags); in bxe_update_drv_flags()
12226 BLOGD(sc, DBG_LOAD, "drv_flags 0x%08x\n", drv_flags); in bxe_update_drv_flags()
12228 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS); in bxe_update_drv_flags()
12237 struct bxe_softc *sc = (struct bxe_softc *)xsc; in bxe_periodic_callout_func() local
12240 if (!BXE_CORE_TRYLOCK(sc)) { in bxe_periodic_callout_func()
12243 if ((sc->state == BXE_STATE_OPEN) && in bxe_periodic_callout_func()
12244 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) { in bxe_periodic_callout_func()
12246 callout_reset(&sc->periodic_callout, hz, in bxe_periodic_callout_func()
12247 bxe_periodic_callout_func, sc); in bxe_periodic_callout_func()
12253 if ((sc->state != BXE_STATE_OPEN) || in bxe_periodic_callout_func()
12254 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) { in bxe_periodic_callout_func()
12255 BLOGW(sc, "periodic callout exit (state=0x%x)\n", sc->state); in bxe_periodic_callout_func()
12256 BXE_CORE_UNLOCK(sc); in bxe_periodic_callout_func()
12262 FOR_EACH_QUEUE(sc, i) { in bxe_periodic_callout_func()
12263 if (bxe_watchdog(sc, &sc->fp[i]) != 0) { in bxe_periodic_callout_func()
12269 if (!CHIP_REV_IS_SLOW(sc)) { in bxe_periodic_callout_func()
12276 if (sc->port.pmf) { in bxe_periodic_callout_func()
12277 bxe_acquire_phy_lock(sc); in bxe_periodic_callout_func()
12278 elink_period_func(&sc->link_params, &sc->link_vars); in bxe_periodic_callout_func()
12279 bxe_release_phy_lock(sc); in bxe_periodic_callout_func()
12283 if (IS_PF(sc) && !(sc->flags & BXE_NO_PULSE)) { in bxe_periodic_callout_func()
12284 int mb_idx = SC_FW_MB_IDX(sc); in bxe_periodic_callout_func()
12288 ++sc->fw_drv_pulse_wr_seq; in bxe_periodic_callout_func()
12289 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; in bxe_periodic_callout_func()
12291 drv_pulse = sc->fw_drv_pulse_wr_seq; in bxe_periodic_callout_func()
12292 bxe_drv_pulse(sc); in bxe_periodic_callout_func()
12294 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) & in bxe_periodic_callout_func()
12304 BLOGE(sc, "drv_pulse (0x%x) != mcp_pulse (0x%x)\n", in bxe_periodic_callout_func()
12310 bxe_stats_handle(sc, STATS_EVENT_UPDATE); in bxe_periodic_callout_func()
12312 BXE_CORE_UNLOCK(sc); in bxe_periodic_callout_func()
12314 if ((sc->state == BXE_STATE_OPEN) && in bxe_periodic_callout_func()
12315 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) { in bxe_periodic_callout_func()
12317 callout_reset(&sc->periodic_callout, hz, in bxe_periodic_callout_func()
12318 bxe_periodic_callout_func, sc); in bxe_periodic_callout_func()
12323 bxe_periodic_start(struct bxe_softc *sc) in bxe_periodic_start() argument
12325 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO); in bxe_periodic_start()
12326 callout_reset(&sc->periodic_callout, hz, bxe_periodic_callout_func, sc); in bxe_periodic_start()
12330 bxe_periodic_stop(struct bxe_softc *sc) in bxe_periodic_stop() argument
12332 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP); in bxe_periodic_stop()
12333 callout_drain(&sc->periodic_callout); in bxe_periodic_stop()
12337 bxe_parity_recover(struct bxe_softc *sc) in bxe_parity_recover() argument
12343 if ((sc->recovery_state == BXE_RECOVERY_FAILED) && in bxe_parity_recover()
12344 (sc->state == BXE_STATE_ERROR)) { in bxe_parity_recover()
12345 BLOGE(sc, "RECOVERY failed, " in bxe_parity_recover()
12352 BLOGD(sc, DBG_SP, in bxe_parity_recover()
12354 __func__, sc, sc->state, sc->recovery_state, sc->error_status); in bxe_parity_recover()
12356 switch(sc->recovery_state) { in bxe_parity_recover()
12359 bxe_chk_parity_attn(sc, &global, FALSE); in bxe_parity_recover()
12361 if ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) || in bxe_parity_recover()
12362 (sc->error_status & BXE_ERR_MCP_ASSERT) || in bxe_parity_recover()
12363 (sc->error_status & BXE_ERR_GLOBAL)) { in bxe_parity_recover()
12365 BXE_CORE_LOCK(sc); in bxe_parity_recover()
12366 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) { in bxe_parity_recover()
12367 bxe_periodic_stop(sc); in bxe_parity_recover()
12369 bxe_nic_unload(sc, UNLOAD_RECOVERY, false); in bxe_parity_recover()
12370 sc->state = BXE_STATE_ERROR; in bxe_parity_recover()
12371 sc->recovery_state = BXE_RECOVERY_FAILED; in bxe_parity_recover()
12372 BLOGE(sc, " No Recovery tried for error 0x%x" in bxe_parity_recover()
12375 sc->error_status); in bxe_parity_recover()
12376 BXE_CORE_UNLOCK(sc); in bxe_parity_recover()
12382 if (bxe_trylock_leader_lock(sc)) { in bxe_parity_recover()
12384 bxe_set_reset_in_progress(sc); in bxe_parity_recover()
12391 bxe_set_reset_global(sc); in bxe_parity_recover()
12393 sc->is_leader = 1; in bxe_parity_recover()
12398 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) { in bxe_parity_recover()
12399 bxe_periodic_stop(sc); in bxe_parity_recover()
12402 BXE_CORE_LOCK(sc); in bxe_parity_recover()
12403 bxe_nic_unload(sc,UNLOAD_RECOVERY, false); in bxe_parity_recover()
12404 sc->recovery_state = BXE_RECOVERY_WAIT; in bxe_parity_recover()
12405 BXE_CORE_UNLOCK(sc); in bxe_parity_recover()
12416 if (sc->is_leader) { in bxe_parity_recover()
12417 int other_engine = SC_PATH(sc) ? 0 : 1; in bxe_parity_recover()
12419 bxe_get_load_status(sc, other_engine); in bxe_parity_recover()
12421 bxe_get_load_status(sc, SC_PATH(sc)); in bxe_parity_recover()
12422 global = bxe_reset_is_global(sc); in bxe_parity_recover()
12439 &sc->sp_err_timeout_task, hz/10); in bxe_parity_recover()
12448 if (bxe_leader_reset(sc)) { in bxe_parity_recover()
12449 BLOGE(sc, "RECOVERY failed, " in bxe_parity_recover()
12451 sc->recovery_state = BXE_RECOVERY_FAILED; in bxe_parity_recover()
12452 sc->state = BXE_STATE_ERROR; in bxe_parity_recover()
12467 if (!bxe_reset_is_done(sc, SC_PATH(sc))) { in bxe_parity_recover()
12475 if (bxe_trylock_leader_lock(sc)) { in bxe_parity_recover()
12480 sc->is_leader = 1; in bxe_parity_recover()
12485 &sc->sp_err_timeout_task, hz/10); in bxe_parity_recover()
12493 if (bxe_reset_is_global(sc)) { in bxe_parity_recover()
12495 &sc->sp_err_timeout_task, hz/10); in bxe_parity_recover()
12500 sc->eth_stats.recoverable_error; in bxe_parity_recover()
12502 sc->eth_stats.unrecoverable_error; in bxe_parity_recover()
12503 BXE_CORE_LOCK(sc); in bxe_parity_recover()
12504 sc->recovery_state = in bxe_parity_recover()
12506 if (bxe_nic_load(sc, LOAD_NORMAL)) { in bxe_parity_recover()
12508 sc->recovery_state = BXE_RECOVERY_FAILED; in bxe_parity_recover()
12509 sc->state = BXE_STATE_ERROR; in bxe_parity_recover()
12510 BLOGE(sc, "Recovery is NOT successful, " in bxe_parity_recover()
12512 sc->state, sc->recovery_state, sc->error_status); in bxe_parity_recover()
12513 sc->error_status = 0; in bxe_parity_recover()
12515 sc->recovery_state = in bxe_parity_recover()
12518 BLOGI(sc, "Recovery is successful from errors %x," in bxe_parity_recover()
12520 " recovery_state=0x%x \n", sc->error_status, in bxe_parity_recover()
12521 sc->state, sc->recovery_state); in bxe_parity_recover()
12524 sc->error_status = 0; in bxe_parity_recover()
12525 BXE_CORE_UNLOCK(sc); in bxe_parity_recover()
12526 sc->eth_stats.recoverable_error = in bxe_parity_recover()
12528 sc->eth_stats.unrecoverable_error = in bxe_parity_recover()
12540 bxe_handle_error(struct bxe_softc * sc) in bxe_handle_error() argument
12543 if(sc->recovery_state == BXE_RECOVERY_WAIT) { in bxe_handle_error()
12546 if(sc->error_status) { in bxe_handle_error()
12547 if (sc->state == BXE_STATE_OPEN) { in bxe_handle_error()
12548 bxe_int_disable(sc); in bxe_handle_error()
12550 if (sc->link_vars.link_up) { in bxe_handle_error()
12551 if_link_state_change(sc->ifp, LINK_STATE_DOWN); in bxe_handle_error()
12553 sc->recovery_state = BXE_RECOVERY_INIT; in bxe_handle_error()
12554 BLOGI(sc, "bxe%d: Recovery started errors 0x%x recovery state 0x%x\n", in bxe_handle_error()
12555 sc->unit, sc->error_status, sc->recovery_state); in bxe_handle_error()
12556 bxe_parity_recover(sc); in bxe_handle_error()
12564 struct bxe_softc *sc = (struct bxe_softc *)arg; in bxe_sp_err_timeout_task() local
12566 BLOGD(sc, DBG_SP, in bxe_sp_err_timeout_task()
12568 __func__, sc->state, sc->recovery_state, sc->error_status); in bxe_sp_err_timeout_task()
12570 if((sc->recovery_state == BXE_RECOVERY_FAILED) && in bxe_sp_err_timeout_task()
12571 (sc->state == BXE_STATE_ERROR)) { in bxe_sp_err_timeout_task()
12575 if ((sc->error_status) && (sc->trigger_grcdump)) { in bxe_sp_err_timeout_task()
12576 bxe_grc_dump(sc); in bxe_sp_err_timeout_task()
12578 if (sc->recovery_state != BXE_RECOVERY_DONE) { in bxe_sp_err_timeout_task()
12579 bxe_handle_error(sc); in bxe_sp_err_timeout_task()
12580 bxe_parity_recover(sc); in bxe_sp_err_timeout_task()
12581 } else if (sc->error_status) { in bxe_sp_err_timeout_task()
12582 bxe_handle_error(sc); in bxe_sp_err_timeout_task()
12590 bxe_nic_load(struct bxe_softc *sc, in bxe_nic_load() argument
12597 BXE_CORE_LOCK_ASSERT(sc); in bxe_nic_load()
12599 BLOGD(sc, DBG_LOAD, "Starting NIC load...\n"); in bxe_nic_load()
12601 sc->state = BXE_STATE_OPENING_WAITING_LOAD; in bxe_nic_load()
12603 if (IS_PF(sc)) { in bxe_nic_load()
12605 bxe_ilt_set_info(sc); in bxe_nic_load()
12608 sc->last_reported_link_state = LINK_STATE_UNKNOWN; in bxe_nic_load()
12610 bxe_set_fp_rx_buf_size(sc); in bxe_nic_load()
12612 if (bxe_alloc_fp_buffers(sc) != 0) { in bxe_nic_load()
12613 BLOGE(sc, "Failed to allocate fastpath memory\n"); in bxe_nic_load()
12614 sc->state = BXE_STATE_CLOSED; in bxe_nic_load()
12619 if (bxe_alloc_mem(sc) != 0) { in bxe_nic_load()
12620 sc->state = BXE_STATE_CLOSED; in bxe_nic_load()
12625 if (bxe_alloc_fw_stats_mem(sc) != 0) { in bxe_nic_load()
12626 sc->state = BXE_STATE_CLOSED; in bxe_nic_load()
12631 if (IS_PF(sc)) { in bxe_nic_load()
12633 bxe_set_pf_load(sc); in bxe_nic_load()
12636 if (!BXE_NOMCP(sc)) { in bxe_nic_load()
12638 if (bxe_nic_load_request(sc, &load_code) != 0) { in bxe_nic_load()
12639 sc->state = BXE_STATE_CLOSED; in bxe_nic_load()
12645 if (bxe_nic_load_analyze_req(sc, load_code) != 0) { in bxe_nic_load()
12646 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); in bxe_nic_load()
12647 sc->state = BXE_STATE_CLOSED; in bxe_nic_load()
12652 BLOGI(sc, "Device has no MCP!\n"); in bxe_nic_load()
12653 load_code = bxe_nic_load_no_mcp(sc); in bxe_nic_load()
12657 bxe_nic_load_pmf(sc, load_code); in bxe_nic_load()
12660 bxe_init_func_obj(sc); in bxe_nic_load()
12663 if (bxe_init_hw(sc, load_code) != 0) { in bxe_nic_load()
12664 BLOGE(sc, "HW init failed\n"); in bxe_nic_load()
12665 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); in bxe_nic_load()
12666 sc->state = BXE_STATE_CLOSED; in bxe_nic_load()
12673 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE; in bxe_nic_load()
12674 bxe_drv_pulse(sc); in bxe_nic_load()
12675 sc->flags |= BXE_NO_PULSE; in bxe_nic_load()
12678 if (bxe_interrupt_attach(sc) != 0) { in bxe_nic_load()
12679 sc->state = BXE_STATE_CLOSED; in bxe_nic_load()
12684 bxe_nic_init(sc, load_code); in bxe_nic_load()
12687 if (IS_PF(sc)) { in bxe_nic_load()
12688 bxe_init_objs(sc); in bxe_nic_load()
12692 sc->devinfo.mf_info.afex_def_vlan_tag = -1; in bxe_nic_load()
12695 sc->state = BXE_STATE_OPENING_WAITING_PORT; in bxe_nic_load()
12696 rc = bxe_func_start(sc); in bxe_nic_load()
12698 BLOGE(sc, "Function start failed! rc = %d\n", rc); in bxe_nic_load()
12699 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); in bxe_nic_load()
12700 sc->state = BXE_STATE_ERROR; in bxe_nic_load()
12705 if (!BXE_NOMCP(sc)) { in bxe_nic_load()
12706 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); in bxe_nic_load()
12708 BLOGE(sc, "MCP response failure, aborting\n"); in bxe_nic_load()
12709 sc->state = BXE_STATE_ERROR; in bxe_nic_load()
12715 rc = bxe_setup_leading(sc); in bxe_nic_load()
12717 BLOGE(sc, "Setup leading failed! rc = %d\n", rc); in bxe_nic_load()
12718 sc->state = BXE_STATE_ERROR; in bxe_nic_load()
12722 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) { in bxe_nic_load()
12723 rc = bxe_setup_queue(sc, &sc->fp[i], FALSE); in bxe_nic_load()
12725 BLOGE(sc, "Queue(%d) setup failed rc = %d\n", i, rc); in bxe_nic_load()
12726 sc->state = BXE_STATE_ERROR; in bxe_nic_load()
12731 rc = bxe_init_rss_pf(sc); in bxe_nic_load()
12733 BLOGE(sc, "PF RSS init failed\n"); in bxe_nic_load()
12734 sc->state = BXE_STATE_ERROR; in bxe_nic_load()
12741 sc->state = BXE_STATE_OPEN; in bxe_nic_load()
12744 if (IS_PF(sc)) { in bxe_nic_load()
12745 rc = bxe_set_eth_mac(sc, TRUE); in bxe_nic_load()
12748 BLOGE(sc, "Setting Ethernet MAC failed rc = %d\n", rc); in bxe_nic_load()
12749 sc->state = BXE_STATE_ERROR; in bxe_nic_load()
12753 if (sc->port.pmf) { in bxe_nic_load()
12754 rc = bxe_initial_phy_init(sc, /* XXX load_mode */LOAD_OPEN); in bxe_nic_load()
12756 sc->state = BXE_STATE_ERROR; in bxe_nic_load()
12761 sc->link_params.feature_config_flags &= in bxe_nic_load()
12767 bxe_set_rx_mode(sc); in bxe_nic_load()
12777 sc->state = BXE_STATE_DIAG; in bxe_nic_load()
12784 if (sc->port.pmf) { in bxe_nic_load()
12785 bxe_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0); in bxe_nic_load()
12787 bxe_link_status_update(sc); in bxe_nic_load()
12791 bxe_periodic_start(sc); in bxe_nic_load()
12793 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) { in bxe_nic_load()
12795 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]); in bxe_nic_load()
12796 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)], in bxe_nic_load()
12803 if (IS_PF(sc) && !bxe_wait_sp_comp(sc, ~0x0UL)) { in bxe_nic_load()
12804 BLOGE(sc, "Timeout waiting for all SPs to complete!\n"); in bxe_nic_load()
12805 bxe_periodic_stop(sc); in bxe_nic_load()
12806 bxe_nic_unload(sc, UNLOAD_CLOSE, FALSE); in bxe_nic_load()
12811 if_setdrvflags(sc->ifp, IFF_DRV_RUNNING); in bxe_nic_load()
12813 BLOGD(sc, DBG_LOAD, "NIC successfully loaded\n"); in bxe_nic_load()
12819 if (IS_PF(sc)) { in bxe_nic_load()
12820 bxe_int_disable_sync(sc, 1); in bxe_nic_load()
12823 bxe_squeeze_objects(sc); in bxe_nic_load()
12826 bxe_interrupt_detach(sc); in bxe_nic_load()
12830 if (IS_PF(sc) && !BXE_NOMCP(sc)) { in bxe_nic_load()
12831 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); in bxe_nic_load()
12832 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0); in bxe_nic_load()
12835 sc->port.pmf = 0; in bxe_nic_load()
12840 if (IS_PF(sc)) { in bxe_nic_load()
12841 bxe_clear_pf_load(sc); in bxe_nic_load()
12846 bxe_free_fw_stats_mem(sc); in bxe_nic_load()
12847 bxe_free_fp_buffers(sc); in bxe_nic_load()
12848 bxe_free_mem(sc); in bxe_nic_load()
12854 bxe_init_locked(struct bxe_softc *sc) in bxe_init_locked() argument
12856 int other_engine = SC_PATH(sc) ? 0 : 1; in bxe_init_locked()
12861 BXE_CORE_LOCK_ASSERT(sc); in bxe_init_locked()
12864 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) { in bxe_init_locked()
12865 BLOGD(sc, DBG_LOAD, "Init called while driver is running!\n"); in bxe_init_locked()
12869 if((sc->state == BXE_STATE_ERROR) && in bxe_init_locked()
12870 (sc->recovery_state == BXE_RECOVERY_FAILED)) { in bxe_init_locked()
12871 BLOGE(sc, "Initialization not done, " in bxe_init_locked()
12878 bxe_set_power_state(sc, PCI_PM_D0); in bxe_init_locked()
12886 if (IS_PF(sc)) { in bxe_init_locked()
12887 other_load_status = bxe_get_load_status(sc, other_engine); in bxe_init_locked()
12888 load_status = bxe_get_load_status(sc, SC_PATH(sc)); in bxe_init_locked()
12890 if (!bxe_reset_is_done(sc, SC_PATH(sc)) || in bxe_init_locked()
12891 bxe_chk_parity_attn(sc, &global, TRUE)) { in bxe_init_locked()
12899 bxe_set_reset_global(sc); in bxe_init_locked()
12908 bxe_trylock_leader_lock(sc) && !bxe_leader_reset(sc)) { in bxe_init_locked()
12909 BLOGI(sc, "Recovered during init\n"); in bxe_init_locked()
12914 bxe_set_power_state(sc, PCI_PM_D3hot); in bxe_init_locked()
12915 sc->recovery_state = BXE_RECOVERY_FAILED; in bxe_init_locked()
12917 BLOGE(sc, "Recovery flow hasn't properly " in bxe_init_locked()
12928 sc->recovery_state = BXE_RECOVERY_DONE; in bxe_init_locked()
12930 rc = bxe_nic_load(sc, LOAD_OPEN); in bxe_init_locked()
12936 BLOGE(sc, "Initialization failed, " in bxe_init_locked()
12938 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING); in bxe_init_locked()
12945 bxe_stop_locked(struct bxe_softc *sc) in bxe_stop_locked() argument
12947 BXE_CORE_LOCK_ASSERT(sc); in bxe_stop_locked()
12948 return (bxe_nic_unload(sc, UNLOAD_NORMAL, TRUE)); in bxe_stop_locked()
12961 struct bxe_softc *sc = (struct bxe_softc *)xsc; in bxe_init() local
12963 BXE_CORE_LOCK(sc); in bxe_init()
12964 bxe_init_locked(sc); in bxe_init()
12965 BXE_CORE_UNLOCK(sc); in bxe_init()
12969 bxe_init_ifnet(struct bxe_softc *sc) in bxe_init_ifnet() argument
12975 ifmedia_init(&sc->ifmedia, IFM_IMASK, in bxe_init_ifnet()
12980 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_FDX | sc->media), 0, NULL); in bxe_init_ifnet()
12981 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL); in bxe_init_ifnet()
12982 ifmedia_set(&sc->ifmedia, (IFM_ETHER | IFM_AUTO)); in bxe_init_ifnet()
12984 sc->ifmedia.ifm_media = sc->ifmedia.ifm_cur->ifm_media; /* XXX ? */ in bxe_init_ifnet()
12985 BLOGI(sc, "IFMEDIA flags : %x\n", sc->ifmedia.ifm_media); in bxe_init_ifnet()
12990 if_setsoftc(ifp, sc); in bxe_init_ifnet()
12991 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); in bxe_init_ifnet()
12999 if_setmtu(ifp, sc->mtu); in bxe_init_ifnet()
13023 if_setsendqlen(ifp, sc->tx_ring_size); in bxe_init_ifnet()
13027 sc->ifp = ifp; in bxe_init_ifnet()
13030 ether_ifattach(ifp, sc->link_params.mac_addr); in bxe_init_ifnet()
13037 bxe_deallocate_bars(struct bxe_softc *sc) in bxe_deallocate_bars() argument
13042 if (sc->bar[i].resource != NULL) { in bxe_deallocate_bars()
13043 bus_release_resource(sc->dev, in bxe_deallocate_bars()
13045 sc->bar[i].rid, in bxe_deallocate_bars()
13046 sc->bar[i].resource); in bxe_deallocate_bars()
13047 BLOGD(sc, DBG_LOAD, "Released PCI BAR%d [%02x] memory\n", in bxe_deallocate_bars()
13054 bxe_allocate_bars(struct bxe_softc *sc) in bxe_allocate_bars() argument
13059 memset(sc->bar, 0, sizeof(sc->bar)); in bxe_allocate_bars()
13069 sc->bar[i].rid = PCIR_BAR(i); in bxe_allocate_bars()
13076 if ((sc->bar[i].resource = in bxe_allocate_bars()
13077 bus_alloc_resource_any(sc->dev, in bxe_allocate_bars()
13079 &sc->bar[i].rid, in bxe_allocate_bars()
13084 sc->bar[i].tag = rman_get_bustag(sc->bar[i].resource); in bxe_allocate_bars()
13085 sc->bar[i].handle = rman_get_bushandle(sc->bar[i].resource); in bxe_allocate_bars()
13086 sc->bar[i].kva = (vm_offset_t)rman_get_virtual(sc->bar[i].resource); in bxe_allocate_bars()
13088 BLOGI(sc, "PCI BAR%d [%02x] memory allocated: %#jx-%#jx (%jd) -> %#jx\n", in bxe_allocate_bars()
13090 rman_get_start(sc->bar[i].resource), in bxe_allocate_bars()
13091 rman_get_end(sc->bar[i].resource), in bxe_allocate_bars()
13092 rman_get_size(sc->bar[i].resource), in bxe_allocate_bars()
13093 (uintmax_t)sc->bar[i].kva); in bxe_allocate_bars()
13100 bxe_get_function_num(struct bxe_softc *sc) in bxe_get_function_num() argument
13111 val = REG_RD(sc, BAR_ME_REGISTER); in bxe_get_function_num()
13113 sc->pfunc_rel = in bxe_get_function_num()
13115 sc->path_id = in bxe_get_function_num()
13118 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) { in bxe_get_function_num()
13119 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id); in bxe_get_function_num()
13121 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id); in bxe_get_function_num()
13124 BLOGD(sc, DBG_LOAD, in bxe_get_function_num()
13126 sc->pfunc_rel, sc->pfunc_abs, sc->path_id); in bxe_get_function_num()
13130 bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc) in bxe_get_shmem_mf_cfg_base() argument
13137 offset = (SHMEM_RD(sc, func_mb) + in bxe_get_shmem_mf_cfg_base()
13141 if (sc->devinfo.shmem2_base != 0) { in bxe_get_shmem_mf_cfg_base()
13142 shmem2_size = SHMEM2_RD(sc, size); in bxe_get_shmem_mf_cfg_base()
13144 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr); in bxe_get_shmem_mf_cfg_base()
13155 bxe_pcie_capability_read(struct bxe_softc *sc, in bxe_pcie_capability_read() argument
13162 if (pci_find_cap(sc->dev, PCIY_EXPRESS, &pcie_reg) == 0) { in bxe_pcie_capability_read()
13164 BLOGD(sc, DBG_LOAD, "PCIe capability at 0x%04x\n", pcie_reg); in bxe_pcie_capability_read()
13165 return (pci_read_config(sc->dev, (pcie_reg + reg), width)); in bxe_pcie_capability_read()
13169 BLOGE(sc, "PCIe capability NOT FOUND!!!\n"); in bxe_pcie_capability_read()
13175 bxe_is_pcie_pending(struct bxe_softc *sc) in bxe_is_pcie_pending() argument
13177 return (bxe_pcie_capability_read(sc, PCIER_DEVICE_STA, 2) & in bxe_is_pcie_pending()
13187 bxe_probe_pci_caps(struct bxe_softc *sc) in bxe_probe_pci_caps() argument
13193 if (pci_find_cap(sc->dev, PCIY_PMG, ®) == 0) { in bxe_probe_pci_caps()
13195 BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg); in bxe_probe_pci_caps()
13197 sc->devinfo.pcie_cap_flags |= BXE_PM_CAPABLE_FLAG; in bxe_probe_pci_caps()
13198 sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg; in bxe_probe_pci_caps()
13202 link_status = bxe_pcie_capability_read(sc, PCIER_LINK_STA, 2); in bxe_probe_pci_caps()
13205 if (CHIP_IS_E1(sc)) { in bxe_probe_pci_caps()
13207 sc->devinfo.pcie_link_speed = in bxe_probe_pci_caps()
13208 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1; in bxe_probe_pci_caps()
13211 sc->devinfo.pcie_link_width = in bxe_probe_pci_caps()
13213 if (sc->devinfo.pcie_link_speed > 1) { in bxe_probe_pci_caps()
13214 sc->devinfo.pcie_link_width = in bxe_probe_pci_caps()
13218 sc->devinfo.pcie_link_speed = in bxe_probe_pci_caps()
13220 sc->devinfo.pcie_link_width = in bxe_probe_pci_caps()
13224 BLOGD(sc, DBG_LOAD, "PCIe link speed=%d width=%d\n", in bxe_probe_pci_caps()
13225 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width); in bxe_probe_pci_caps()
13227 sc->devinfo.pcie_cap_flags |= BXE_PCIE_CAPABLE_FLAG; in bxe_probe_pci_caps()
13228 sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg; in bxe_probe_pci_caps()
13231 if (pci_find_cap(sc->dev, PCIY_MSI, ®) == 0) { in bxe_probe_pci_caps()
13233 BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg); in bxe_probe_pci_caps()
13235 sc->devinfo.pcie_cap_flags |= BXE_MSI_CAPABLE_FLAG; in bxe_probe_pci_caps()
13236 sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg; in bxe_probe_pci_caps()
13241 if (pci_find_cap(sc->dev, PCIY_MSIX, ®) == 0) { in bxe_probe_pci_caps()
13243 BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg); in bxe_probe_pci_caps()
13245 sc->devinfo.pcie_cap_flags |= BXE_MSIX_CAPABLE_FLAG; in bxe_probe_pci_caps()
13246 sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg; in bxe_probe_pci_caps()
13252 bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc) in bxe_get_shmem_mf_cfg_info_sd() argument
13254 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; in bxe_get_shmem_mf_cfg_info_sd()
13259 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); in bxe_get_shmem_mf_cfg_info_sd()
13265 BLOGE(sc, "Invalid VLAN (%d)\n", mf_info->ext_id); in bxe_get_shmem_mf_cfg_info_sd()
13270 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) == in bxe_get_shmem_mf_cfg_info_sd()
13273 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) == in bxe_get_shmem_mf_cfg_info_sd()
13281 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; in bxe_get_shmem_mf_cfg_info_sd()
13287 bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc) in bxe_get_shmem_ext_proto_support_flags() argument
13292 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg); in bxe_get_shmem_ext_proto_support_flags()
13310 bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc) in bxe_get_shmem_mf_cfg_info_si() argument
13312 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; in bxe_get_shmem_mf_cfg_info_si()
13320 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg); in bxe_get_shmem_mf_cfg_info_si()
13324 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc); in bxe_get_shmem_mf_cfg_info_si()
13327 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; in bxe_get_shmem_mf_cfg_info_si()
13333 bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc) in bxe_get_shmem_mf_cfg_info_niv() argument
13335 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; in bxe_get_shmem_mf_cfg_info_niv()
13342 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); in bxe_get_shmem_mf_cfg_info_niv()
13343 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); in bxe_get_shmem_mf_cfg_info_niv()
13344 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config); in bxe_get_shmem_mf_cfg_info_niv()
13370 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc); in bxe_get_shmem_mf_cfg_info_niv()
13373 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; in bxe_get_shmem_mf_cfg_info_niv()
13379 bxe_check_valid_mf_cfg(struct bxe_softc *sc) in bxe_check_valid_mf_cfg() argument
13381 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; in bxe_check_valid_mf_cfg()
13388 BLOGD(sc, DBG_LOAD, "MF config parameters for function %d\n", in bxe_check_valid_mf_cfg()
13389 SC_PORT(sc)); in bxe_check_valid_mf_cfg()
13390 BLOGD(sc, DBG_LOAD, "\tmf_config=0x%x\n", in bxe_check_valid_mf_cfg()
13391 mf_info->mf_config[SC_VN(sc)]); in bxe_check_valid_mf_cfg()
13392 BLOGD(sc, DBG_LOAD, "\tmulti_vnics_mode=%d\n", in bxe_check_valid_mf_cfg()
13394 BLOGD(sc, DBG_LOAD, "\tvnics_per_port=%d\n", in bxe_check_valid_mf_cfg()
13396 BLOGD(sc, DBG_LOAD, "\tovlan/vifid=%d\n", in bxe_check_valid_mf_cfg()
13398 BLOGD(sc, DBG_LOAD, "\tmin_bw=%d/%d/%d/%d\n", in bxe_check_valid_mf_cfg()
13401 BLOGD(sc, DBG_LOAD, "\tmax_bw=%d/%d/%d/%d\n", in bxe_check_valid_mf_cfg()
13404 BLOGD(sc, DBG_LOAD, "\tmac_addr: %s\n", in bxe_check_valid_mf_cfg()
13405 sc->mac_addr_str); in bxe_check_valid_mf_cfg()
13409 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) { in bxe_check_valid_mf_cfg()
13410 BLOGE(sc, "Enumerated function %d is marked as hidden\n", in bxe_check_valid_mf_cfg()
13411 SC_PORT(sc)); in bxe_check_valid_mf_cfg()
13416 BLOGE(sc, "vnics_per_port=%d multi_vnics_mode=%d\n", in bxe_check_valid_mf_cfg()
13423 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) { in bxe_check_valid_mf_cfg()
13424 BLOGE(sc, "mf_mode=SD vnic_id=%d ovlan=%d\n", in bxe_check_valid_mf_cfg()
13425 SC_VN(sc), OVLAN(sc)); in bxe_check_valid_mf_cfg()
13429 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) { in bxe_check_valid_mf_cfg()
13430 BLOGE(sc, "mf_mode=SD multi_vnics_mode=%d ovlan=%d\n", in bxe_check_valid_mf_cfg()
13431 mf_info->multi_vnics_mode, OVLAN(sc)); in bxe_check_valid_mf_cfg()
13440 FOREACH_ABS_FUNC_IN_PORT(sc, i) { in bxe_check_valid_mf_cfg()
13441 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config); in bxe_check_valid_mf_cfg()
13442 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag); in bxe_check_valid_mf_cfg()
13446 BLOGE(sc, "mf_mode=SD function %d MF config " in bxe_check_valid_mf_cfg()
13454 FOREACH_ABS_FUNC_IN_PORT(sc, i) { in bxe_check_valid_mf_cfg()
13455 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config); in bxe_check_valid_mf_cfg()
13456 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag); in bxe_check_valid_mf_cfg()
13459 mf_cfg2 = MFCFG_RD(sc, func_mf_config[j].config); in bxe_check_valid_mf_cfg()
13460 ovlan2 = MFCFG_RD(sc, func_mf_config[j].e1hov_tag); in bxe_check_valid_mf_cfg()
13466 BLOGE(sc, "mf_mode=SD functions %d and %d " in bxe_check_valid_mf_cfg()
13479 bxe_get_mf_cfg_info(struct bxe_softc *sc) in bxe_get_mf_cfg_info() argument
13481 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; in bxe_get_mf_cfg_info()
13491 if (!CHIP_IS_MF_CAP(sc)) { in bxe_get_mf_cfg_info()
13495 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) { in bxe_get_mf_cfg_info()
13496 BLOGE(sc, "Invalid mf_cfg_base!\n"); in bxe_get_mf_cfg_info()
13502 val = SHMEM_RD(sc, dev_info.shared_feature_config.config); in bxe_get_mf_cfg_info()
13508 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); in bxe_get_mf_cfg_info()
13514 BLOGE(sc, "Invalid config for Switch Independent mode\n"); in bxe_get_mf_cfg_info()
13523 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); in bxe_get_mf_cfg_info()
13529 BLOGE(sc, "Invalid config for Switch Dependent mode\n"); in bxe_get_mf_cfg_info()
13545 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); in bxe_get_mf_cfg_info()
13547 if ((SHMEM2_HAS(sc, afex_driver_support)) && in bxe_get_mf_cfg_info()
13551 BLOGE(sc, "Invalid config for AFEX mode\n"); in bxe_get_mf_cfg_info()
13558 BLOGE(sc, "Unknown MF mode (0x%08x)\n", in bxe_get_mf_cfg_info()
13573 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) { in bxe_get_mf_cfg_info()
13574 uint8_t other_port = !(PORT_ID(sc) & 1); in bxe_get_mf_cfg_info()
13575 uint8_t abs_func_other_port = (SC_PATH(sc) + (2 * other_port)); in bxe_get_mf_cfg_info()
13577 val = MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag); in bxe_get_mf_cfg_info()
13585 if (SC_VN(sc) >= 1) { in bxe_get_mf_cfg_info()
13586 BLOGE(sc, "VNIC ID >= 1 in SF mode\n"); in bxe_get_mf_cfg_info()
13594 mf_info->mf_config[SC_VN(sc)] = in bxe_get_mf_cfg_info()
13595 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); in bxe_get_mf_cfg_info()
13601 bxe_get_shmem_mf_cfg_info_sd(sc); in bxe_get_mf_cfg_info()
13606 bxe_get_shmem_mf_cfg_info_si(sc); in bxe_get_mf_cfg_info()
13611 bxe_get_shmem_mf_cfg_info_niv(sc); in bxe_get_mf_cfg_info()
13616 BLOGE(sc, "Get MF config failed (mf_mode=0x%08x)\n", in bxe_get_mf_cfg_info()
13624 FOREACH_ABS_FUNC_IN_PORT(sc, i) { in bxe_get_mf_cfg_info()
13626 val = MFCFG_RD(sc, func_mf_config[i].config); in bxe_get_mf_cfg_info()
13634 return (bxe_check_valid_mf_cfg(sc)); in bxe_get_mf_cfg_info()
13638 bxe_get_shmem_info(struct bxe_softc *sc) in bxe_get_shmem_info() argument
13643 port = SC_PORT(sc); in bxe_get_shmem_info()
13646 sc->link_params.sc = sc; in bxe_get_shmem_info()
13647 sc->link_params.port = port; in bxe_get_shmem_info()
13650 sc->devinfo.hw_config = in bxe_get_shmem_info()
13651 SHMEM_RD(sc, dev_info.shared_hw_config.config); in bxe_get_shmem_info()
13652 sc->devinfo.hw_config2 = in bxe_get_shmem_info()
13653 SHMEM_RD(sc, dev_info.shared_hw_config.config2); in bxe_get_shmem_info()
13655 sc->link_params.hw_led_mode = in bxe_get_shmem_info()
13656 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >> in bxe_get_shmem_info()
13660 sc->port.config = in bxe_get_shmem_info()
13661 SHMEM_RD(sc, dev_info.port_feature_config[port].config); in bxe_get_shmem_info()
13664 sc->link_params.speed_cap_mask[0] = in bxe_get_shmem_info()
13665 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask); in bxe_get_shmem_info()
13666 sc->link_params.speed_cap_mask[1] = in bxe_get_shmem_info()
13667 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2); in bxe_get_shmem_info()
13670 sc->link_params.lane_config = in bxe_get_shmem_info()
13671 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config); in bxe_get_shmem_info()
13674 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config); in bxe_get_shmem_info()
13675 sc->port.link_config[ELINK_INT_PHY] = val; in bxe_get_shmem_info()
13676 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK); in bxe_get_shmem_info()
13677 sc->port.link_config[ELINK_EXT_PHY1] = in bxe_get_shmem_info()
13678 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2); in bxe_get_shmem_info()
13681 val = SHMEM_RD(sc, dev_info.shared_feature_config.config); in bxe_get_shmem_info()
13683 sc->link_params.feature_config_flags |= in bxe_get_shmem_info()
13686 sc->link_params.feature_config_flags &= in bxe_get_shmem_info()
13691 sc->link_params.multi_phy_config = in bxe_get_shmem_info()
13692 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config); in bxe_get_shmem_info()
13695 sc->port.ext_phy_config = in bxe_get_shmem_info()
13696 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config); in bxe_get_shmem_info()
13699 bxe_get_mf_cfg_info(sc); in bxe_get_shmem_info()
13702 if (IS_MF(sc)) { in bxe_get_shmem_info()
13703 mac_hi = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); in bxe_get_shmem_info()
13704 mac_lo = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower); in bxe_get_shmem_info()
13706 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper); in bxe_get_shmem_info()
13707 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower); in bxe_get_shmem_info()
13711 *sc->mac_addr_str = 0; in bxe_get_shmem_info()
13712 BLOGE(sc, "No Ethernet address programmed!\n"); in bxe_get_shmem_info()
13714 sc->link_params.mac_addr[0] = (uint8_t)(mac_hi >> 8); in bxe_get_shmem_info()
13715 sc->link_params.mac_addr[1] = (uint8_t)(mac_hi); in bxe_get_shmem_info()
13716 sc->link_params.mac_addr[2] = (uint8_t)(mac_lo >> 24); in bxe_get_shmem_info()
13717 sc->link_params.mac_addr[3] = (uint8_t)(mac_lo >> 16); in bxe_get_shmem_info()
13718 sc->link_params.mac_addr[4] = (uint8_t)(mac_lo >> 8); in bxe_get_shmem_info()
13719 sc->link_params.mac_addr[5] = (uint8_t)(mac_lo); in bxe_get_shmem_info()
13720 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str), in bxe_get_shmem_info()
13722 sc->link_params.mac_addr[0], sc->link_params.mac_addr[1], in bxe_get_shmem_info()
13723 sc->link_params.mac_addr[2], sc->link_params.mac_addr[3], in bxe_get_shmem_info()
13724 sc->link_params.mac_addr[4], sc->link_params.mac_addr[5]); in bxe_get_shmem_info()
13725 BLOGD(sc, DBG_LOAD, "Ethernet address: %s\n", sc->mac_addr_str); in bxe_get_shmem_info()
13732 bxe_get_tunable_params(struct bxe_softc *sc) in bxe_get_tunable_params() argument
13739 BLOGW(sc, "invalid interrupt_mode value (%d)\n", bxe_interrupt_mode); in bxe_get_tunable_params()
13744 BLOGW(sc, "invalid queue_count value (%d)\n", bxe_queue_count); in bxe_get_tunable_params()
13752 BLOGW(sc, "invalid max_rx_bufs (%d)\n", bxe_max_rx_bufs); in bxe_get_tunable_params()
13758 BLOGW(sc, "invalid hc_rx_ticks (%d)\n", bxe_hc_rx_ticks); in bxe_get_tunable_params()
13763 BLOGW(sc, "invalid hc_tx_ticks (%d)\n", bxe_hc_tx_ticks); in bxe_get_tunable_params()
13772 BLOGW(sc, "invalid max_aggregation_size (%d)\n", in bxe_get_tunable_params()
13778 BLOGW(sc, "invalid mrrs (%d)\n", bxe_mrrs); in bxe_get_tunable_params()
13783 BLOGW(sc, "invalid autogreeen (%d)\n", bxe_autogreeen); in bxe_get_tunable_params()
13788 BLOGW(sc, "invalid udp_rss (%d)\n", bxe_udp_rss); in bxe_get_tunable_params()
13794 sc->interrupt_mode = bxe_interrupt_mode; in bxe_get_tunable_params()
13795 sc->max_rx_bufs = bxe_max_rx_bufs; in bxe_get_tunable_params()
13796 sc->hc_rx_ticks = bxe_hc_rx_ticks; in bxe_get_tunable_params()
13797 sc->hc_tx_ticks = bxe_hc_tx_ticks; in bxe_get_tunable_params()
13798 sc->max_aggregation_size = bxe_max_aggregation_size; in bxe_get_tunable_params()
13799 sc->mrrs = bxe_mrrs; in bxe_get_tunable_params()
13800 sc->autogreeen = bxe_autogreeen; in bxe_get_tunable_params()
13801 sc->udp_rss = bxe_udp_rss; in bxe_get_tunable_params()
13804 sc->num_queues = 1; in bxe_get_tunable_params()
13806 sc->num_queues = in bxe_get_tunable_params()
13809 if (sc->num_queues > mp_ncpus) { in bxe_get_tunable_params()
13810 sc->num_queues = mp_ncpus; in bxe_get_tunable_params()
13814 BLOGD(sc, DBG_LOAD, in bxe_get_tunable_params()
13827 sc->interrupt_mode, in bxe_get_tunable_params()
13828 sc->num_queues, in bxe_get_tunable_params()
13829 sc->hc_rx_ticks, in bxe_get_tunable_params()
13830 sc->hc_tx_ticks, in bxe_get_tunable_params()
13832 sc->max_aggregation_size, in bxe_get_tunable_params()
13833 sc->mrrs, in bxe_get_tunable_params()
13834 sc->autogreeen, in bxe_get_tunable_params()
13835 sc->udp_rss); in bxe_get_tunable_params()
13839 bxe_media_detect(struct bxe_softc *sc) in bxe_media_detect() argument
13842 uint32_t phy_idx = bxe_get_cur_phy_idx(sc); in bxe_media_detect()
13844 switch (sc->link_params.phy[phy_idx].media_type) { in bxe_media_detect()
13847 BLOGI(sc, "Found 10Gb Fiber media.\n"); in bxe_media_detect()
13848 sc->media = IFM_10G_SR; in bxe_media_detect()
13852 BLOGI(sc, "Found 1Gb Fiber media.\n"); in bxe_media_detect()
13853 sc->media = IFM_1000_SX; in bxe_media_detect()
13858 BLOGI(sc, "Found 10GBase-CX4 media.\n"); in bxe_media_detect()
13859 sc->media = IFM_10G_CX4; in bxe_media_detect()
13863 BLOGI(sc, "Found 10Gb Twinax media.\n"); in bxe_media_detect()
13864 sc->media = IFM_10G_TWINAX; in bxe_media_detect()
13868 if (sc->link_params.speed_cap_mask[0] & in bxe_media_detect()
13870 BLOGI(sc, "Found 10GBase-T media.\n"); in bxe_media_detect()
13871 sc->media = IFM_10G_T; in bxe_media_detect()
13874 BLOGI(sc, "Found 1000Base-T media.\n"); in bxe_media_detect()
13875 sc->media = IFM_1000_T; in bxe_media_detect()
13880 BLOGI(sc, "Media not present.\n"); in bxe_media_detect()
13881 sc->media = 0; in bxe_media_detect()
13886 BLOGI(sc, "Unknown media!\n"); in bxe_media_detect()
13887 sc->media = 0; in bxe_media_detect()
13900 bxe_get_igu_cam_info(struct bxe_softc *sc) in bxe_get_igu_cam_info() argument
13902 int pfid = SC_FUNC(sc); in bxe_get_igu_cam_info()
13907 sc->igu_base_sb = 0xff; in bxe_get_igu_cam_info()
13909 if (CHIP_INT_MODE_IS_BC(sc)) { in bxe_get_igu_cam_info()
13910 int vn = SC_VN(sc); in bxe_get_igu_cam_info()
13911 igu_sb_cnt = sc->igu_sb_cnt; in bxe_get_igu_cam_info()
13912 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) * in bxe_get_igu_cam_info()
13914 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x + in bxe_get_igu_cam_info()
13915 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn)); in bxe_get_igu_cam_info()
13923 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); in bxe_get_igu_cam_info()
13934 sc->igu_dsb_id = igu_sb_id; in bxe_get_igu_cam_info()
13936 if (sc->igu_base_sb == 0xff) { in bxe_get_igu_cam_info()
13937 sc->igu_base_sb = igu_sb_id; in bxe_get_igu_cam_info()
13950 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt); in bxe_get_igu_cam_info()
13953 BLOGE(sc, "CAM configuration error\n"); in bxe_get_igu_cam_info()
13965 bxe_get_device_info(struct bxe_softc *sc) in bxe_get_device_info() argument
13971 sc->devinfo.vendor_id = pci_get_vendor(sc->dev); in bxe_get_device_info()
13972 sc->devinfo.device_id = pci_get_device(sc->dev); in bxe_get_device_info()
13973 sc->devinfo.subvendor_id = pci_get_subvendor(sc->dev); in bxe_get_device_info()
13974 sc->devinfo.subdevice_id = pci_get_subdevice(sc->dev); in bxe_get_device_info()
13977 sc->devinfo.chip_id = in bxe_get_device_info()
13978 sc->link_params.chip_id = in bxe_get_device_info()
13979 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) | in bxe_get_device_info()
13980 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) | in bxe_get_device_info()
13981 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) | in bxe_get_device_info()
13982 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0)); in bxe_get_device_info()
13985 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { in bxe_get_device_info()
13986 if (CHIP_IS_57810(sc)) { in bxe_get_device_info()
13987 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) | in bxe_get_device_info()
13988 (sc->devinfo.chip_id & 0x0000ffff)); in bxe_get_device_info()
13989 } else if (CHIP_IS_57810_MF(sc)) { in bxe_get_device_info()
13990 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) | in bxe_get_device_info()
13991 (sc->devinfo.chip_id & 0x0000ffff)); in bxe_get_device_info()
13993 sc->devinfo.chip_id |= 0x1; in bxe_get_device_info()
13996 BLOGD(sc, DBG_LOAD, in bxe_get_device_info()
13998 sc->devinfo.chip_id, in bxe_get_device_info()
13999 ((sc->devinfo.chip_id >> 16) & 0xffff), in bxe_get_device_info()
14000 ((sc->devinfo.chip_id >> 12) & 0xf), in bxe_get_device_info()
14001 ((sc->devinfo.chip_id >> 4) & 0xff), in bxe_get_device_info()
14002 ((sc->devinfo.chip_id >> 0) & 0xf)); in bxe_get_device_info()
14004 val = (REG_RD(sc, 0x2874) & 0x55); in bxe_get_device_info()
14005 if ((sc->devinfo.chip_id & 0x1) || in bxe_get_device_info()
14006 (CHIP_IS_E1(sc) && val) || in bxe_get_device_info()
14007 (CHIP_IS_E1H(sc) && (val == 0x55))) { in bxe_get_device_info()
14008 sc->flags |= BXE_ONE_PORT_FLAG; in bxe_get_device_info()
14009 BLOGD(sc, DBG_LOAD, "single port device\n"); in bxe_get_device_info()
14013 sc->doorbell_size = (1 << BXE_DB_SHIFT); in bxe_get_device_info()
14016 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1 & E1h*/ in bxe_get_device_info()
14017 if (CHIP_IS_E2E3(sc)) { in bxe_get_device_info()
14023 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR); in bxe_get_device_info()
14027 val = REG_RD(sc, MISC_REG_PORT4MODE_EN); in bxe_get_device_info()
14030 sc->devinfo.chip_port_mode = in bxe_get_device_info()
14033 BLOGD(sc, DBG_LOAD, "Port mode = %s\n", (val) ? "4" : "2"); in bxe_get_device_info()
14037 bxe_get_function_num(sc); in bxe_get_device_info()
14040 sc->devinfo.shmem_base = in bxe_get_device_info()
14041 sc->link_params.shmem_base = in bxe_get_device_info()
14042 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); in bxe_get_device_info()
14043 sc->devinfo.shmem2_base = in bxe_get_device_info()
14044 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 : in bxe_get_device_info()
14047 BLOGD(sc, DBG_LOAD, "shmem_base=0x%08x, shmem2_base=0x%08x\n", in bxe_get_device_info()
14048 sc->devinfo.shmem_base, sc->devinfo.shmem2_base); in bxe_get_device_info()
14050 if (!sc->devinfo.shmem_base) { in bxe_get_device_info()
14052 BLOGI(sc, "MCP not active\n"); in bxe_get_device_info()
14053 sc->flags |= BXE_NO_MCP_FLAG; in bxe_get_device_info()
14058 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]); in bxe_get_device_info()
14061 BLOGE(sc, "Invalid SHMEM validity signature: 0x%08x\n", val); in bxe_get_device_info()
14064 BLOGD(sc, DBG_LOAD, "Valid SHMEM validity signature: 0x%08x\n", val); in bxe_get_device_info()
14067 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev); in bxe_get_device_info()
14068 snprintf(sc->devinfo.bc_ver_str, in bxe_get_device_info()
14069 sizeof(sc->devinfo.bc_ver_str), in bxe_get_device_info()
14071 ((sc->devinfo.bc_ver >> 24) & 0xff), in bxe_get_device_info()
14072 ((sc->devinfo.bc_ver >> 16) & 0xff), in bxe_get_device_info()
14073 ((sc->devinfo.bc_ver >> 8) & 0xff)); in bxe_get_device_info()
14074 BLOGD(sc, DBG_LOAD, "Bootcode version: %s\n", sc->devinfo.bc_ver_str); in bxe_get_device_info()
14077 sc->devinfo.mf_cfg_base = bxe_get_shmem_mf_cfg_base(sc); in bxe_get_device_info()
14078 BLOGD(sc, DBG_LOAD, "mf_cfg_base=0x08%x \n", sc->devinfo.mf_cfg_base); in bxe_get_device_info()
14081 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); in bxe_get_device_info()
14082 if (IS_PF(sc)) { in bxe_get_device_info()
14083 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0); in bxe_get_device_info()
14084 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0); in bxe_get_device_info()
14085 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0); in bxe_get_device_info()
14086 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0); in bxe_get_device_info()
14087 if (CHIP_IS_E1x(sc)) { in bxe_get_device_info()
14088 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0); in bxe_get_device_info()
14089 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0); in bxe_get_device_info()
14090 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0); in bxe_get_device_info()
14091 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0); in bxe_get_device_info()
14099 if (!CHIP_IS_E1x(sc)) { in bxe_get_device_info()
14100 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bxe_get_device_info()
14105 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4); in bxe_get_device_info()
14106 sc->devinfo.flash_size = in bxe_get_device_info()
14108 BLOGD(sc, DBG_LOAD, "nvram flash size: %d\n", sc->devinfo.flash_size); in bxe_get_device_info()
14111 bxe_probe_pci_caps(sc); in bxe_get_device_info()
14113 bxe_set_power_state(sc, PCI_PM_D0); in bxe_get_device_info()
14116 bxe_get_shmem_info(sc); in bxe_get_device_info()
14118 if (sc->devinfo.pcie_msix_cap_reg != 0) { in bxe_get_device_info()
14119 val = pci_read_config(sc->dev, in bxe_get_device_info()
14120 (sc->devinfo.pcie_msix_cap_reg + in bxe_get_device_info()
14123 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE); in bxe_get_device_info()
14125 sc->igu_sb_cnt = 1; in bxe_get_device_info()
14128 sc->igu_base_addr = BAR_IGU_INTMEM; in bxe_get_device_info()
14131 if (CHIP_IS_E1x(sc)) { in bxe_get_device_info()
14132 sc->devinfo.int_block = INT_BLOCK_HC; in bxe_get_device_info()
14133 sc->igu_dsb_id = DEF_SB_IGU_ID; in bxe_get_device_info()
14134 sc->igu_base_sb = 0; in bxe_get_device_info()
14136 sc->devinfo.int_block = INT_BLOCK_IGU; in bxe_get_device_info()
14139 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET); in bxe_get_device_info()
14141 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION); in bxe_get_device_info()
14146 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode\n"); in bxe_get_device_info()
14149 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val); in bxe_get_device_info()
14150 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f); in bxe_get_device_info()
14152 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) { in bxe_get_device_info()
14157 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) { in bxe_get_device_info()
14158 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode failed!!!\n"); in bxe_get_device_info()
14159 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); in bxe_get_device_info()
14165 BLOGD(sc, DBG_LOAD, "IGU Backward Compatible Mode\n"); in bxe_get_device_info()
14166 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP; in bxe_get_device_info()
14168 BLOGD(sc, DBG_LOAD, "IGU Normal Mode\n"); in bxe_get_device_info()
14171 rc = bxe_get_igu_cam_info(sc); in bxe_get_device_info()
14173 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); in bxe_get_device_info()
14185 if (CHIP_IS_E1x(sc)) { in bxe_get_device_info()
14186 sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc)); in bxe_get_device_info()
14193 sc->base_fw_ndsb = sc->igu_base_sb; in bxe_get_device_info()
14196 BLOGD(sc, DBG_LOAD, in bxe_get_device_info()
14198 sc->igu_dsb_id, sc->igu_base_sb, in bxe_get_device_info()
14199 sc->igu_sb_cnt, sc->base_fw_ndsb); in bxe_get_device_info()
14201 elink_phy_probe(&sc->link_params); in bxe_get_device_info()
14207 bxe_link_settings_supported(struct bxe_softc *sc, in bxe_link_settings_supported() argument
14212 uint8_t port = SC_PORT(sc); in bxe_link_settings_supported()
14215 sc->port.supported[0] = 0; in bxe_link_settings_supported()
14216 sc->port.supported[1] = 0; in bxe_link_settings_supported()
14218 switch (sc->link_params.num_phys) { in bxe_link_settings_supported()
14220 sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported; in bxe_link_settings_supported()
14224 sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported; in bxe_link_settings_supported()
14228 if (sc->link_params.multi_phy_config & in bxe_link_settings_supported()
14230 sc->port.supported[1] = in bxe_link_settings_supported()
14231 sc->link_params.phy[ELINK_EXT_PHY1].supported; in bxe_link_settings_supported()
14232 sc->port.supported[0] = in bxe_link_settings_supported()
14233 sc->link_params.phy[ELINK_EXT_PHY2].supported; in bxe_link_settings_supported()
14235 sc->port.supported[0] = in bxe_link_settings_supported()
14236 sc->link_params.phy[ELINK_EXT_PHY1].supported; in bxe_link_settings_supported()
14237 sc->port.supported[1] = in bxe_link_settings_supported()
14238 sc->link_params.phy[ELINK_EXT_PHY2].supported; in bxe_link_settings_supported()
14244 if (!(sc->port.supported[0] || sc->port.supported[1])) { in bxe_link_settings_supported()
14245 BLOGE(sc, "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n", in bxe_link_settings_supported()
14246 SHMEM_RD(sc, in bxe_link_settings_supported()
14248 SHMEM_RD(sc, in bxe_link_settings_supported()
14253 if (CHIP_IS_E3(sc)) in bxe_link_settings_supported()
14254 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR); in bxe_link_settings_supported()
14258 sc->port.phy_addr = in bxe_link_settings_supported()
14259 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); in bxe_link_settings_supported()
14262 sc->port.phy_addr = in bxe_link_settings_supported()
14263 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); in bxe_link_settings_supported()
14266 BLOGE(sc, "Invalid switch config in link_config=0x%08x\n", in bxe_link_settings_supported()
14267 sc->port.link_config[0]); in bxe_link_settings_supported()
14272 BLOGD(sc, DBG_LOAD, "PHY addr 0x%08x\n", sc->port.phy_addr); in bxe_link_settings_supported()
14276 if (!(sc->link_params.speed_cap_mask[idx] & in bxe_link_settings_supported()
14278 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Half; in bxe_link_settings_supported()
14281 if (!(sc->link_params.speed_cap_mask[idx] & in bxe_link_settings_supported()
14283 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Full; in bxe_link_settings_supported()
14286 if (!(sc->link_params.speed_cap_mask[idx] & in bxe_link_settings_supported()
14288 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Half; in bxe_link_settings_supported()
14291 if (!(sc->link_params.speed_cap_mask[idx] & in bxe_link_settings_supported()
14293 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Full; in bxe_link_settings_supported()
14296 if (!(sc->link_params.speed_cap_mask[idx] & in bxe_link_settings_supported()
14298 sc->port.supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full; in bxe_link_settings_supported()
14301 if (!(sc->link_params.speed_cap_mask[idx] & in bxe_link_settings_supported()
14303 sc->port.supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full; in bxe_link_settings_supported()
14306 if (!(sc->link_params.speed_cap_mask[idx] & in bxe_link_settings_supported()
14308 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full; in bxe_link_settings_supported()
14311 if (!(sc->link_params.speed_cap_mask[idx] & in bxe_link_settings_supported()
14313 sc->port.supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full; in bxe_link_settings_supported()
14317 BLOGD(sc, DBG_LOAD, "PHY supported 0=0x%08x 1=0x%08x\n", in bxe_link_settings_supported()
14318 sc->port.supported[0], sc->port.supported[1]); in bxe_link_settings_supported()
14319 ELINK_DEBUG_P2(sc, "PHY supported 0=0x%08x 1=0x%08x\n", in bxe_link_settings_supported()
14320 sc->port.supported[0], sc->port.supported[1]); in bxe_link_settings_supported()
14324 bxe_link_settings_requested(struct bxe_softc *sc) in bxe_link_settings_requested() argument
14330 sc->port.advertising[0] = 0; in bxe_link_settings_requested()
14331 sc->port.advertising[1] = 0; in bxe_link_settings_requested()
14333 switch (sc->link_params.num_phys) { in bxe_link_settings_requested()
14344 sc->link_params.req_duplex[idx] = DUPLEX_FULL; in bxe_link_settings_requested()
14345 link_config = sc->port.link_config[idx]; in bxe_link_settings_requested()
14349 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) { in bxe_link_settings_requested()
14350 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG; in bxe_link_settings_requested()
14351 sc->port.advertising[idx] |= sc->port.supported[idx]; in bxe_link_settings_requested()
14352 if (sc->link_params.phy[ELINK_EXT_PHY1].type == in bxe_link_settings_requested()
14354 sc->port.advertising[idx] |= in bxe_link_settings_requested()
14359 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000; in bxe_link_settings_requested()
14360 sc->port.advertising[idx] |= in bxe_link_settings_requested()
14367 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Full) { in bxe_link_settings_requested()
14368 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10; in bxe_link_settings_requested()
14369 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Full | in bxe_link_settings_requested()
14372 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " in bxe_link_settings_requested()
14374 link_config, sc->link_params.speed_cap_mask[idx]); in bxe_link_settings_requested()
14380 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Half) { in bxe_link_settings_requested()
14381 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10; in bxe_link_settings_requested()
14382 sc->link_params.req_duplex[idx] = DUPLEX_HALF; in bxe_link_settings_requested()
14383 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Half | in bxe_link_settings_requested()
14385 ELINK_DEBUG_P1(sc, "driver requesting DUPLEX_HALF req_duplex = %x!\n", in bxe_link_settings_requested()
14386 sc->link_params.req_duplex[idx]); in bxe_link_settings_requested()
14388 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " in bxe_link_settings_requested()
14390 link_config, sc->link_params.speed_cap_mask[idx]); in bxe_link_settings_requested()
14396 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Full) { in bxe_link_settings_requested()
14397 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100; in bxe_link_settings_requested()
14398 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Full | in bxe_link_settings_requested()
14401 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " in bxe_link_settings_requested()
14403 link_config, sc->link_params.speed_cap_mask[idx]); in bxe_link_settings_requested()
14409 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Half) { in bxe_link_settings_requested()
14410 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100; in bxe_link_settings_requested()
14411 sc->link_params.req_duplex[idx] = DUPLEX_HALF; in bxe_link_settings_requested()
14412 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Half | in bxe_link_settings_requested()
14415 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " in bxe_link_settings_requested()
14417 link_config, sc->link_params.speed_cap_mask[idx]); in bxe_link_settings_requested()
14423 if (sc->port.supported[idx] & ELINK_SUPPORTED_1000baseT_Full) { in bxe_link_settings_requested()
14424 sc->link_params.req_line_speed[idx] = ELINK_SPEED_1000; in bxe_link_settings_requested()
14425 sc->port.advertising[idx] |= (ADVERTISED_1000baseT_Full | in bxe_link_settings_requested()
14428 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " in bxe_link_settings_requested()
14430 link_config, sc->link_params.speed_cap_mask[idx]); in bxe_link_settings_requested()
14436 if (sc->port.supported[idx] & ELINK_SUPPORTED_2500baseX_Full) { in bxe_link_settings_requested()
14437 sc->link_params.req_line_speed[idx] = ELINK_SPEED_2500; in bxe_link_settings_requested()
14438 sc->port.advertising[idx] |= (ADVERTISED_2500baseX_Full | in bxe_link_settings_requested()
14441 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " in bxe_link_settings_requested()
14443 link_config, sc->link_params.speed_cap_mask[idx]); in bxe_link_settings_requested()
14449 if (sc->port.supported[idx] & ELINK_SUPPORTED_10000baseT_Full) { in bxe_link_settings_requested()
14450 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000; in bxe_link_settings_requested()
14451 sc->port.advertising[idx] |= (ADVERTISED_10000baseT_Full | in bxe_link_settings_requested()
14454 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " in bxe_link_settings_requested()
14456 link_config, sc->link_params.speed_cap_mask[idx]); in bxe_link_settings_requested()
14462 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000; in bxe_link_settings_requested()
14466 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " in bxe_link_settings_requested()
14468 link_config, sc->link_params.speed_cap_mask[idx]); in bxe_link_settings_requested()
14469 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG; in bxe_link_settings_requested()
14470 sc->port.advertising[idx] = sc->port.supported[idx]; in bxe_link_settings_requested()
14474 sc->link_params.req_flow_ctrl[idx] = in bxe_link_settings_requested()
14477 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) { in bxe_link_settings_requested()
14478 if (!(sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg)) { in bxe_link_settings_requested()
14479 sc->link_params.req_flow_ctrl[idx] = ELINK_FLOW_CTRL_NONE; in bxe_link_settings_requested()
14481 bxe_set_requested_fc(sc); in bxe_link_settings_requested()
14485 BLOGD(sc, DBG_LOAD, "req_line_speed=%d req_duplex=%d " in bxe_link_settings_requested()
14487 sc->link_params.req_line_speed[idx], in bxe_link_settings_requested()
14488 sc->link_params.req_duplex[idx], in bxe_link_settings_requested()
14489 sc->link_params.req_flow_ctrl[idx], in bxe_link_settings_requested()
14490 sc->port.advertising[idx]); in bxe_link_settings_requested()
14491 ELINK_DEBUG_P3(sc, "req_line_speed=%d req_duplex=%d " in bxe_link_settings_requested()
14493 sc->link_params.req_line_speed[idx], in bxe_link_settings_requested()
14494 sc->link_params.req_duplex[idx], in bxe_link_settings_requested()
14495 sc->port.advertising[idx]); in bxe_link_settings_requested()
14500 bxe_get_phy_info(struct bxe_softc *sc) in bxe_get_phy_info() argument
14502 uint8_t port = SC_PORT(sc); in bxe_get_phy_info()
14503 uint32_t config = sc->port.config; in bxe_get_phy_info()
14508 ELINK_DEBUG_P3(sc, "lane_config=0x%08x speed_cap_mask0=0x%08x " in bxe_get_phy_info()
14510 sc->link_params.lane_config, in bxe_get_phy_info()
14511 sc->link_params.speed_cap_mask[0], in bxe_get_phy_info()
14512 sc->port.link_config[0]); in bxe_get_phy_info()
14515 bxe_link_settings_supported(sc, sc->link_params.switch_cfg); in bxe_get_phy_info()
14516 bxe_link_settings_requested(sc); in bxe_get_phy_info()
14518 if (sc->autogreeen == AUTO_GREEN_FORCE_ON) { in bxe_get_phy_info()
14519 sc->link_params.feature_config_flags |= in bxe_get_phy_info()
14521 } else if (sc->autogreeen == AUTO_GREEN_FORCE_OFF) { in bxe_get_phy_info()
14522 sc->link_params.feature_config_flags &= in bxe_get_phy_info()
14525 sc->link_params.feature_config_flags |= in bxe_get_phy_info()
14531 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) & in bxe_get_phy_info()
14535 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI | in bxe_get_phy_info()
14539 sc->link_params.eee_mode = 0; in bxe_get_phy_info()
14543 bxe_media_detect(sc); in bxe_get_phy_info()
14544 ELINK_DEBUG_P1(sc, "detected media type\n", sc->media); in bxe_get_phy_info()
14548 bxe_get_params(struct bxe_softc *sc) in bxe_get_params() argument
14551 bxe_get_tunable_params(sc); in bxe_get_params()
14554 sc->tx_ring_size = TX_BD_USABLE; in bxe_get_params()
14555 sc->rx_ring_size = RX_BD_USABLE; in bxe_get_params()
14558 sc->wol = 0; in bxe_get_params()
14562 bxe_set_modes_bitmap(struct bxe_softc *sc) in bxe_set_modes_bitmap() argument
14566 if (CHIP_REV_IS_FPGA(sc)) { in bxe_set_modes_bitmap()
14568 } else if (CHIP_REV_IS_EMUL(sc)) { in bxe_set_modes_bitmap()
14574 if (CHIP_IS_MODE_4_PORT(sc)) { in bxe_set_modes_bitmap()
14580 if (CHIP_IS_E2(sc)) { in bxe_set_modes_bitmap()
14582 } else if (CHIP_IS_E3(sc)) { in bxe_set_modes_bitmap()
14584 if (CHIP_REV(sc) == CHIP_REV_Ax) { in bxe_set_modes_bitmap()
14591 if (IS_MF(sc)) { in bxe_set_modes_bitmap()
14593 switch (sc->devinfo.mf_info.mf_mode) { in bxe_set_modes_bitmap()
14614 INIT_MODE_FLAGS(sc) = flags; in bxe_set_modes_bitmap()
14618 bxe_alloc_hsi_mem(struct bxe_softc *sc) in bxe_alloc_hsi_mem() argument
14633 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent tag */ in bxe_alloc_hsi_mem()
14646 &sc->parent_dma_tag); /* returned dma tag */ in bxe_alloc_hsi_mem()
14648 BLOGE(sc, "Failed to alloc parent DMA tag (%d)!\n", rc); in bxe_alloc_hsi_mem()
14656 if (bxe_dma_alloc(sc, sizeof(struct host_sp_status_block), in bxe_alloc_hsi_mem()
14657 &sc->def_sb_dma, "default status block") != 0) { in bxe_alloc_hsi_mem()
14659 bus_dma_tag_destroy(sc->parent_dma_tag); in bxe_alloc_hsi_mem()
14663 sc->def_sb = (struct host_sp_status_block *)sc->def_sb_dma.vaddr; in bxe_alloc_hsi_mem()
14669 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE, in bxe_alloc_hsi_mem()
14670 &sc->eq_dma, "event queue") != 0) { in bxe_alloc_hsi_mem()
14672 bxe_dma_free(sc, &sc->def_sb_dma); in bxe_alloc_hsi_mem()
14673 sc->def_sb = NULL; in bxe_alloc_hsi_mem()
14674 bus_dma_tag_destroy(sc->parent_dma_tag); in bxe_alloc_hsi_mem()
14678 sc->eq = (union event_ring_elem * )sc->eq_dma.vaddr; in bxe_alloc_hsi_mem()
14684 if (bxe_dma_alloc(sc, sizeof(struct bxe_slowpath), in bxe_alloc_hsi_mem()
14685 &sc->sp_dma, "slow path") != 0) { in bxe_alloc_hsi_mem()
14687 bxe_dma_free(sc, &sc->eq_dma); in bxe_alloc_hsi_mem()
14688 sc->eq = NULL; in bxe_alloc_hsi_mem()
14689 bxe_dma_free(sc, &sc->def_sb_dma); in bxe_alloc_hsi_mem()
14690 sc->def_sb = NULL; in bxe_alloc_hsi_mem()
14691 bus_dma_tag_destroy(sc->parent_dma_tag); in bxe_alloc_hsi_mem()
14695 sc->sp = (struct bxe_slowpath *)sc->sp_dma.vaddr; in bxe_alloc_hsi_mem()
14701 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE, in bxe_alloc_hsi_mem()
14702 &sc->spq_dma, "slow path queue") != 0) { in bxe_alloc_hsi_mem()
14704 bxe_dma_free(sc, &sc->sp_dma); in bxe_alloc_hsi_mem()
14705 sc->sp = NULL; in bxe_alloc_hsi_mem()
14706 bxe_dma_free(sc, &sc->eq_dma); in bxe_alloc_hsi_mem()
14707 sc->eq = NULL; in bxe_alloc_hsi_mem()
14708 bxe_dma_free(sc, &sc->def_sb_dma); in bxe_alloc_hsi_mem()
14709 sc->def_sb = NULL; in bxe_alloc_hsi_mem()
14710 bus_dma_tag_destroy(sc->parent_dma_tag); in bxe_alloc_hsi_mem()
14714 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr; in bxe_alloc_hsi_mem()
14720 if (bxe_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma, in bxe_alloc_hsi_mem()
14723 bxe_dma_free(sc, &sc->spq_dma); in bxe_alloc_hsi_mem()
14724 sc->spq = NULL; in bxe_alloc_hsi_mem()
14725 bxe_dma_free(sc, &sc->sp_dma); in bxe_alloc_hsi_mem()
14726 sc->sp = NULL; in bxe_alloc_hsi_mem()
14727 bxe_dma_free(sc, &sc->eq_dma); in bxe_alloc_hsi_mem()
14728 sc->eq = NULL; in bxe_alloc_hsi_mem()
14729 bxe_dma_free(sc, &sc->def_sb_dma); in bxe_alloc_hsi_mem()
14730 sc->def_sb = NULL; in bxe_alloc_hsi_mem()
14731 bus_dma_tag_destroy(sc->parent_dma_tag); in bxe_alloc_hsi_mem()
14735 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr; in bxe_alloc_hsi_mem()
14737 if ((sc->gz_strm = in bxe_alloc_hsi_mem()
14738 malloc(sizeof(*sc->gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) { in bxe_alloc_hsi_mem()
14740 bxe_dma_free(sc, &sc->gz_buf_dma); in bxe_alloc_hsi_mem()
14741 sc->gz_buf = NULL; in bxe_alloc_hsi_mem()
14742 bxe_dma_free(sc, &sc->spq_dma); in bxe_alloc_hsi_mem()
14743 sc->spq = NULL; in bxe_alloc_hsi_mem()
14744 bxe_dma_free(sc, &sc->sp_dma); in bxe_alloc_hsi_mem()
14745 sc->sp = NULL; in bxe_alloc_hsi_mem()
14746 bxe_dma_free(sc, &sc->eq_dma); in bxe_alloc_hsi_mem()
14747 sc->eq = NULL; in bxe_alloc_hsi_mem()
14748 bxe_dma_free(sc, &sc->def_sb_dma); in bxe_alloc_hsi_mem()
14749 sc->def_sb = NULL; in bxe_alloc_hsi_mem()
14750 bus_dma_tag_destroy(sc->parent_dma_tag); in bxe_alloc_hsi_mem()
14759 for (i = 0; i < sc->num_queues; i++) { in bxe_alloc_hsi_mem()
14760 fp = &sc->fp[i]; in bxe_alloc_hsi_mem()
14761 fp->sc = sc; in bxe_alloc_hsi_mem()
14769 if (bxe_dma_alloc(sc, sizeof(union bxe_host_hc_status_block), in bxe_alloc_hsi_mem()
14772 BLOGE(sc, "Failed to alloc %s\n", buf); in bxe_alloc_hsi_mem()
14775 if (CHIP_IS_E2E3(sc)) { in bxe_alloc_hsi_mem()
14789 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * TX_BD_NUM_PAGES), in bxe_alloc_hsi_mem()
14792 BLOGE(sc, "Failed to alloc %s\n", buf); in bxe_alloc_hsi_mem()
14815 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_BD_NUM_PAGES), in bxe_alloc_hsi_mem()
14818 BLOGE(sc, "Failed to alloc %s\n", buf); in bxe_alloc_hsi_mem()
14841 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RCQ_NUM_PAGES), in bxe_alloc_hsi_mem()
14844 BLOGE(sc, "Failed to alloc %s\n", buf); in bxe_alloc_hsi_mem()
14868 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES), in bxe_alloc_hsi_mem()
14871 BLOGE(sc, "Failed to alloc %s\n", buf); in bxe_alloc_hsi_mem()
14894 if (if_getcapenable(sc->ifp) & (IFCAP_TSO4 | IFCAP_TSO6)) { in bxe_alloc_hsi_mem()
14905 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ in bxe_alloc_hsi_mem()
14921 BLOGE(sc, "Failed to create dma tag for " in bxe_alloc_hsi_mem()
14932 BLOGE(sc, "Failed to create dma map for " in bxe_alloc_hsi_mem()
14943 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ in bxe_alloc_hsi_mem()
14959 BLOGE(sc, "Failed to create dma tag for " in bxe_alloc_hsi_mem()
14970 BLOGE(sc, "Failed to create dma map for " in bxe_alloc_hsi_mem()
14981 BLOGE(sc, "Failed to create dma map for " in bxe_alloc_hsi_mem()
14991 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ in bxe_alloc_hsi_mem()
15007 BLOGE(sc, "Failed to create dma tag for " in bxe_alloc_hsi_mem()
15018 BLOGE(sc, "Failed to create dma map for " in bxe_alloc_hsi_mem()
15029 BLOGE(sc, "Failed to create dma map for " in bxe_alloc_hsi_mem()
15039 max_agg_queues = MAX_AGG_QS(sc); in bxe_alloc_hsi_mem()
15046 BLOGE(sc, "Failed to create dma map for " in bxe_alloc_hsi_mem()
15057 BLOGE(sc, "Failed to create dma map for " in bxe_alloc_hsi_mem()
15069 bxe_free_hsi_mem(struct bxe_softc *sc) in bxe_free_hsi_mem() argument
15075 if (sc->parent_dma_tag == NULL) { in bxe_free_hsi_mem()
15079 for (i = 0; i < sc->num_queues; i++) { in bxe_free_hsi_mem()
15080 fp = &sc->fp[i]; in bxe_free_hsi_mem()
15086 bxe_dma_free(sc, &fp->sb_dma); in bxe_free_hsi_mem()
15093 bxe_dma_free(sc, &fp->tx_dma); in bxe_free_hsi_mem()
15100 bxe_dma_free(sc, &fp->rx_dma); in bxe_free_hsi_mem()
15107 bxe_dma_free(sc, &fp->rcq_dma); in bxe_free_hsi_mem()
15114 bxe_dma_free(sc, &fp->rx_sge_dma); in bxe_free_hsi_mem()
15158 max_agg_queues = MAX_AGG_QS(sc); in bxe_free_hsi_mem()
15210 bxe_dma_free(sc, &sc->gz_buf_dma); in bxe_free_hsi_mem()
15211 sc->gz_buf = NULL; in bxe_free_hsi_mem()
15212 free(sc->gz_strm, M_DEVBUF); in bxe_free_hsi_mem()
15213 sc->gz_strm = NULL; in bxe_free_hsi_mem()
15219 bxe_dma_free(sc, &sc->spq_dma); in bxe_free_hsi_mem()
15220 sc->spq = NULL; in bxe_free_hsi_mem()
15226 bxe_dma_free(sc, &sc->sp_dma); in bxe_free_hsi_mem()
15227 sc->sp = NULL; in bxe_free_hsi_mem()
15233 bxe_dma_free(sc, &sc->eq_dma); in bxe_free_hsi_mem()
15234 sc->eq = NULL; in bxe_free_hsi_mem()
15240 bxe_dma_free(sc, &sc->def_sb_dma); in bxe_free_hsi_mem()
15241 sc->def_sb = NULL; in bxe_free_hsi_mem()
15243 bus_dma_tag_destroy(sc->parent_dma_tag); in bxe_free_hsi_mem()
15244 sc->parent_dma_tag = NULL; in bxe_free_hsi_mem()
15255 bxe_prev_interrupted_dmae(struct bxe_softc *sc) in bxe_prev_interrupted_dmae() argument
15259 if (!CHIP_IS_E1x(sc)) { in bxe_prev_interrupted_dmae()
15260 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS); in bxe_prev_interrupted_dmae()
15262 BLOGD(sc, DBG_LOAD, in bxe_prev_interrupted_dmae()
15264 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc)); in bxe_prev_interrupted_dmae()
15270 bxe_prev_mcp_done(struct bxe_softc *sc) in bxe_prev_mcp_done() argument
15272 uint32_t rc = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, in bxe_prev_mcp_done()
15275 BLOGE(sc, "MCP response failure, aborting\n"); in bxe_prev_mcp_done()
15283 bxe_prev_path_get_entry(struct bxe_softc *sc) in bxe_prev_path_get_entry() argument
15288 if ((sc->pcie_bus == tmp->bus) && in bxe_prev_path_get_entry()
15289 (sc->pcie_device == tmp->slot) && in bxe_prev_path_get_entry()
15290 (SC_PATH(sc) == tmp->path)) { in bxe_prev_path_get_entry()
15299 bxe_prev_is_path_marked(struct bxe_softc *sc) in bxe_prev_is_path_marked() argument
15306 tmp = bxe_prev_path_get_entry(sc); in bxe_prev_is_path_marked()
15309 BLOGD(sc, DBG_LOAD, in bxe_prev_is_path_marked()
15311 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); in bxe_prev_is_path_marked()
15314 BLOGD(sc, DBG_LOAD, in bxe_prev_is_path_marked()
15316 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); in bxe_prev_is_path_marked()
15326 bxe_prev_mark_path(struct bxe_softc *sc, in bxe_prev_mark_path() argument
15334 tmp = bxe_prev_path_get_entry(sc); in bxe_prev_mark_path()
15337 BLOGD(sc, DBG_LOAD, in bxe_prev_mark_path()
15339 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); in bxe_prev_mark_path()
15341 BLOGD(sc, DBG_LOAD, in bxe_prev_mark_path()
15343 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); in bxe_prev_mark_path()
15357 BLOGE(sc, "Failed to allocate 'bxe_prev_list_node'\n"); in bxe_prev_mark_path()
15361 tmp->bus = sc->pcie_bus; in bxe_prev_mark_path()
15362 tmp->slot = sc->pcie_device; in bxe_prev_mark_path()
15363 tmp->path = SC_PATH(sc); in bxe_prev_mark_path()
15365 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0; in bxe_prev_mark_path()
15369 BLOGD(sc, DBG_LOAD, in bxe_prev_mark_path()
15371 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); in bxe_prev_mark_path()
15380 bxe_do_flr(struct bxe_softc *sc) in bxe_do_flr() argument
15385 if (CHIP_IS_E1x(sc)) { in bxe_do_flr()
15386 BLOGD(sc, DBG_LOAD, "FLR not supported in E1/E1H\n"); in bxe_do_flr()
15391 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { in bxe_do_flr()
15392 BLOGD(sc, DBG_LOAD, "FLR not supported by BC_VER: 0x%08x\n", in bxe_do_flr()
15393 sc->devinfo.bc_ver); in bxe_do_flr()
15403 if (!bxe_is_pcie_pending(sc)) { in bxe_do_flr()
15408 BLOGE(sc, "PCIE transaction is not cleared, " in bxe_do_flr()
15413 BLOGD(sc, DBG_LOAD, "Initiating FLR\n"); in bxe_do_flr()
15414 bxe_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0); in bxe_do_flr()
15431 bxe_prev_unload_close_mac(struct bxe_softc *sc, in bxe_prev_unload_close_mac() argument
15436 uint8_t port = SC_PORT(sc); in bxe_prev_unload_close_mac()
15445 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2); in bxe_prev_unload_close_mac()
15447 if (!CHIP_IS_E3(sc)) { in bxe_prev_unload_close_mac()
15448 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); in bxe_prev_unload_close_mac()
15451 BLOGD(sc, DBG_LOAD, "Disable BMAC Rx\n"); in bxe_prev_unload_close_mac()
15452 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM in bxe_prev_unload_close_mac()
15454 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL in bxe_prev_unload_close_mac()
15463 wb_data[0] = REG_RD(sc, base_addr + offset); in bxe_prev_unload_close_mac()
15464 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4); in bxe_prev_unload_close_mac()
15469 REG_WR(sc, vals->bmac_addr, wb_data[0]); in bxe_prev_unload_close_mac()
15470 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]); in bxe_prev_unload_close_mac()
15473 BLOGD(sc, DBG_LOAD, "Disable EMAC Rx\n"); in bxe_prev_unload_close_mac()
15474 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4; in bxe_prev_unload_close_mac()
15475 vals->emac_val = REG_RD(sc, vals->emac_addr); in bxe_prev_unload_close_mac()
15476 REG_WR(sc, vals->emac_addr, 0); in bxe_prev_unload_close_mac()
15480 BLOGD(sc, DBG_LOAD, "Disable XMAC Rx\n"); in bxe_prev_unload_close_mac()
15481 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bxe_prev_unload_close_mac()
15482 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI); in bxe_prev_unload_close_mac()
15483 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1)); in bxe_prev_unload_close_mac()
15484 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1)); in bxe_prev_unload_close_mac()
15486 vals->xmac_val = REG_RD(sc, vals->xmac_addr); in bxe_prev_unload_close_mac()
15487 REG_WR(sc, vals->xmac_addr, 0); in bxe_prev_unload_close_mac()
15493 BLOGD(sc, DBG_LOAD, "Disable UMAC Rx\n"); in bxe_prev_unload_close_mac()
15494 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; in bxe_prev_unload_close_mac()
15496 vals->umac_val = REG_RD(sc, vals->umac_addr); in bxe_prev_unload_close_mac()
15497 REG_WR(sc, vals->umac_addr, 0); in bxe_prev_unload_close_mac()
15513 bxe_prev_unload_undi_inc(struct bxe_softc *sc, in bxe_prev_unload_undi_inc() argument
15518 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port)); in bxe_prev_unload_undi_inc()
15524 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg); in bxe_prev_unload_undi_inc()
15526 BLOGD(sc, DBG_LOAD, in bxe_prev_unload_undi_inc()
15532 bxe_prev_unload_common(struct bxe_softc *sc) in bxe_prev_unload_common() argument
15545 BLOGD(sc, DBG_LOAD, "Common unload Flow\n"); in bxe_prev_unload_common()
15549 if (bxe_prev_is_path_marked(sc)) { in bxe_prev_unload_common()
15550 return (bxe_prev_mcp_done(sc)); in bxe_prev_unload_common()
15553 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1); in bxe_prev_unload_common()
15558 bxe_prev_unload_close_mac(sc, &mac_vals); in bxe_prev_unload_common()
15561 elink_set_rx_filter(&sc->link_params, 0); in bxe_prev_unload_common()
15568 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST); in bxe_prev_unload_common()
15570 BLOGD(sc, DBG_LOAD, "UNDI previously loaded\n"); in bxe_prev_unload_common()
15573 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0); in bxe_prev_unload_common()
15575 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0); in bxe_prev_unload_common()
15580 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); in bxe_prev_unload_common()
15584 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); in bxe_prev_unload_common()
15589 BLOGD(sc, DBG_LOAD, "BRB still has 0x%08x\n", tmp_reg); in bxe_prev_unload_common()
15600 bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1); in bxe_prev_unload_common()
15607 BLOGE(sc, "Failed to empty BRB\n"); in bxe_prev_unload_common()
15612 bxe_reset_common(sc); in bxe_prev_unload_common()
15615 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val); in bxe_prev_unload_common()
15618 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val); in bxe_prev_unload_common()
15621 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val); in bxe_prev_unload_common()
15624 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]); in bxe_prev_unload_common()
15625 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); in bxe_prev_unload_common()
15628 rc = bxe_prev_mark_path(sc, prev_undi); in bxe_prev_unload_common()
15630 bxe_prev_mcp_done(sc); in bxe_prev_unload_common()
15634 return (bxe_prev_mcp_done(sc)); in bxe_prev_unload_common()
15638 bxe_prev_unload_uncommon(struct bxe_softc *sc) in bxe_prev_unload_uncommon() argument
15642 BLOGD(sc, DBG_LOAD, "Uncommon unload Flow\n"); in bxe_prev_unload_uncommon()
15645 if (bxe_prev_is_path_marked(sc)) { in bxe_prev_unload_uncommon()
15646 return (bxe_prev_mcp_done(sc)); in bxe_prev_unload_uncommon()
15649 BLOGD(sc, DBG_LOAD, "Path is unmarked\n"); in bxe_prev_unload_uncommon()
15656 rc = bxe_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION); in bxe_prev_unload_uncommon()
15659 BLOGD(sc, DBG_LOAD, "FW version matches our own, attempting FLR\n"); in bxe_prev_unload_uncommon()
15660 rc = bxe_do_flr(sc); in bxe_prev_unload_uncommon()
15665 BLOGD(sc, DBG_LOAD, "FLR successful\n"); in bxe_prev_unload_uncommon()
15669 BLOGD(sc, DBG_LOAD, "Could not FLR\n"); in bxe_prev_unload_uncommon()
15672 rc = bxe_prev_mcp_done(sc); in bxe_prev_unload_uncommon()
15681 bxe_prev_unload(struct bxe_softc *sc) in bxe_prev_unload() argument
15691 bxe_prev_interrupted_dmae(sc); in bxe_prev_unload()
15695 (SC_FUNC(sc) <= 5) ? in bxe_prev_unload()
15696 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) : in bxe_prev_unload()
15697 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8); in bxe_prev_unload()
15699 hw_lock_val = (REG_RD(sc, hw_lock_reg)); in bxe_prev_unload()
15702 BLOGD(sc, DBG_LOAD, "Releasing previously held NVRAM lock\n"); in bxe_prev_unload()
15703 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, in bxe_prev_unload()
15704 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc))); in bxe_prev_unload()
15706 BLOGD(sc, DBG_LOAD, "Releasing previously held HW lock\n"); in bxe_prev_unload()
15707 REG_WR(sc, hw_lock_reg, 0xffffffff); in bxe_prev_unload()
15709 BLOGD(sc, DBG_LOAD, "No need to release HW/NVRAM locks\n"); in bxe_prev_unload()
15712 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) { in bxe_prev_unload()
15713 BLOGD(sc, DBG_LOAD, "Releasing previously held ALR\n"); in bxe_prev_unload()
15714 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0); in bxe_prev_unload()
15719 fw = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); in bxe_prev_unload()
15721 BLOGE(sc, "MCP response failure, aborting\n"); in bxe_prev_unload()
15727 rc = bxe_prev_unload_common(sc); in bxe_prev_unload()
15732 rc = bxe_prev_unload_uncommon(sc); in bxe_prev_unload()
15741 BLOGE(sc, "Failed to unload previous driver!" in bxe_prev_unload()
15750 bxe_dcbx_set_state(struct bxe_softc *sc, in bxe_dcbx_set_state() argument
15754 if (!CHIP_IS_E1x(sc)) { in bxe_dcbx_set_state()
15755 sc->dcb_state = dcb_on; in bxe_dcbx_set_state()
15756 sc->dcbx_enabled = dcbx_enabled; in bxe_dcbx_set_state()
15758 sc->dcb_state = FALSE; in bxe_dcbx_set_state()
15759 sc->dcbx_enabled = BXE_DCBX_ENABLED_INVALID; in bxe_dcbx_set_state()
15761 BLOGD(sc, DBG_LOAD, in bxe_dcbx_set_state()
15772 bxe_set_qm_cid_count(struct bxe_softc *sc) in bxe_set_qm_cid_count() argument
15774 int cid_count = BXE_L2_MAX_CID(sc); in bxe_set_qm_cid_count()
15776 if (IS_SRIOV(sc)) { in bxe_set_qm_cid_count()
15780 if (CNIC_SUPPORT(sc)) { in bxe_set_qm_cid_count()
15788 bxe_init_multi_cos(struct bxe_softc *sc) in bxe_init_multi_cos() argument
15796 if (cos < sc->max_cos) { in bxe_init_multi_cos()
15797 sc->prio_to_cos[pri] = cos; in bxe_init_multi_cos()
15799 BLOGW(sc, "Invalid COS %d for priority %d " in bxe_init_multi_cos()
15801 cos, pri, (sc->max_cos - 1)); in bxe_init_multi_cos()
15802 sc->prio_to_cos[pri] = 0; in bxe_init_multi_cos()
15810 struct bxe_softc *sc; in bxe_sysctl_state() local
15822 sc = (struct bxe_softc *)arg1; in bxe_sysctl_state()
15824 BLOGI(sc, "... dumping driver state ...\n"); in bxe_sysctl_state()
15825 temp = SHMEM2_RD(sc, temperature_in_half_celsius); in bxe_sysctl_state()
15826 BLOGI(sc, "\t Device Temperature = %d Celsius\n", (temp/2)); in bxe_sysctl_state()
15835 struct bxe_softc *sc = (struct bxe_softc *)arg1; in bxe_sysctl_eth_stat() local
15836 uint32_t *eth_stats = (uint32_t *)&sc->eth_stats; in bxe_sysctl_eth_stat()
15842 BLOGE(sc, "bxe_eth_stats index out of range (%d)\n", index); in bxe_sysctl_eth_stat()
15856 BLOGE(sc, "Invalid bxe_eth_stats size (index=%d size=%d)\n", in bxe_sysctl_eth_stat()
15867 struct bxe_softc *sc = (struct bxe_softc *)arg1; in bxe_sysctl_eth_q_stat() local
15875 eth_stats = (uint32_t *)&sc->fp[fp_index].eth_q_stats; in bxe_sysctl_eth_q_stat()
15878 BLOGE(sc, "bxe_eth_q_stats index out of range (%d)\n", index); in bxe_sysctl_eth_q_stat()
15892 BLOGE(sc, "Invalid bxe_eth_q_stats size (index=%d size=%d)\n", in bxe_sysctl_eth_q_stat()
15900 static void bxe_force_link_reset(struct bxe_softc *sc) in bxe_force_link_reset() argument
15903 bxe_acquire_phy_lock(sc); in bxe_force_link_reset()
15904 elink_link_reset(&sc->link_params, &sc->link_vars, 1); in bxe_force_link_reset()
15905 bxe_release_phy_lock(sc); in bxe_force_link_reset()
15911 struct bxe_softc *sc = (struct bxe_softc *)arg1; in bxe_sysctl_pauseparam() local
15912 uint32_t cfg_idx = bxe_get_link_cfg_idx(sc); in bxe_sysctl_pauseparam()
15918 error = sysctl_handle_int(oidp, &sc->bxe_pause_param, 0, req); in bxe_sysctl_pauseparam()
15923 if ((sc->bxe_pause_param < 0) || (sc->bxe_pause_param > 8)) { in bxe_sysctl_pauseparam()
15924 … BLOGW(sc, "invalid pause param (%d) - use integers between 1 & 8\n",sc->bxe_pause_param); in bxe_sysctl_pauseparam()
15925 sc->bxe_pause_param = 8; in bxe_sysctl_pauseparam()
15928 result = (sc->bxe_pause_param << PORT_FEATURE_FLOW_CONTROL_SHIFT); in bxe_sysctl_pauseparam()
15931 if((result & 0x400) && !(sc->port.supported[cfg_idx] & ELINK_SUPPORTED_Autoneg)) { in bxe_sysctl_pauseparam()
15932 BLOGW(sc, "Does not support Autoneg pause_param %d\n", sc->bxe_pause_param); in bxe_sysctl_pauseparam()
15936 if(IS_MF(sc)) in bxe_sysctl_pauseparam()
15938 sc->link_params.req_flow_ctrl[cfg_idx] = ELINK_FLOW_CTRL_AUTO; in bxe_sysctl_pauseparam()
15940 sc->link_params.req_flow_ctrl[cfg_idx] |= ELINK_FLOW_CTRL_RX; in bxe_sysctl_pauseparam()
15943 sc->link_params.req_flow_ctrl[cfg_idx] |= ELINK_FLOW_CTRL_TX; in bxe_sysctl_pauseparam()
15944 if(sc->link_params.req_flow_ctrl[cfg_idx] == ELINK_FLOW_CTRL_AUTO) in bxe_sysctl_pauseparam()
15945 sc->link_params.req_flow_ctrl[cfg_idx] = ELINK_FLOW_CTRL_NONE; in bxe_sysctl_pauseparam()
15948 if (sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG) { in bxe_sysctl_pauseparam()
15949 sc->link_params.req_flow_ctrl[cfg_idx] = in bxe_sysctl_pauseparam()
15952 sc->link_params.req_fc_auto_adv = 0; in bxe_sysctl_pauseparam()
15954 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_RX; in bxe_sysctl_pauseparam()
15957 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_TX; in bxe_sysctl_pauseparam()
15958 if (!sc->link_params.req_fc_auto_adv) in bxe_sysctl_pauseparam()
15959 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_NONE; in bxe_sysctl_pauseparam()
15961 if (IS_PF(sc)) { in bxe_sysctl_pauseparam()
15962 if (sc->link_vars.link_up) { in bxe_sysctl_pauseparam()
15963 bxe_stats_handle(sc, STATS_EVENT_STOP); in bxe_sysctl_pauseparam()
15965 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) { in bxe_sysctl_pauseparam()
15966 bxe_force_link_reset(sc); in bxe_sysctl_pauseparam()
15967 bxe_acquire_phy_lock(sc); in bxe_sysctl_pauseparam()
15969 rc = elink_phy_init(&sc->link_params, &sc->link_vars); in bxe_sysctl_pauseparam()
15971 bxe_release_phy_lock(sc); in bxe_sysctl_pauseparam()
15973 bxe_calc_fc_adv(sc); in bxe_sysctl_pauseparam()
15981 bxe_add_sysctls(struct bxe_softc *sc) in bxe_add_sysctls() argument
15991 ctx = device_get_sysctl_ctx(sc->dev); in bxe_add_sysctls()
15992 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); in bxe_add_sysctls()
15998 snprintf(sc->fw_ver_str, sizeof(sc->fw_ver_str), "%d.%d.%d.%d", in bxe_add_sysctls()
16004 snprintf(sc->mf_mode_str, sizeof(sc->mf_mode_str), "%s", in bxe_add_sysctls()
16005 ((sc->devinfo.mf_info.mf_mode == SINGLE_FUNCTION) ? "Single" : in bxe_add_sysctls()
16006 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD) ? "MF-SD" : in bxe_add_sysctls()
16007 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI) ? "MF-SI" : in bxe_add_sysctls()
16008 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX) ? "MF-AFEX" : in bxe_add_sysctls()
16011 CTLFLAG_RD, &sc->devinfo.mf_info.vnics_per_port, 0, in bxe_add_sysctls()
16014 snprintf(sc->pci_link_str, sizeof(sc->pci_link_str), "%s x%d", in bxe_add_sysctls()
16015 ((sc->devinfo.pcie_link_speed == 1) ? "2.5GT/s" : in bxe_add_sysctls()
16016 (sc->devinfo.pcie_link_speed == 2) ? "5.0GT/s" : in bxe_add_sysctls()
16017 (sc->devinfo.pcie_link_speed == 4) ? "8.0GT/s" : in bxe_add_sysctls()
16019 sc->devinfo.pcie_link_width); in bxe_add_sysctls()
16021 sc->debug = bxe_debug; in bxe_add_sysctls()
16024 CTLFLAG_RD, sc->devinfo.bc_ver_str, 0, in bxe_add_sysctls()
16027 CTLFLAG_RD, sc->fw_ver_str, 0, in bxe_add_sysctls()
16030 CTLFLAG_RD, sc->mf_mode_str, 0, in bxe_add_sysctls()
16033 CTLFLAG_RD, sc->mac_addr_str, 0, in bxe_add_sysctls()
16036 CTLFLAG_RD, sc->pci_link_str, 0, in bxe_add_sysctls()
16039 CTLFLAG_RW, &sc->debug, in bxe_add_sysctls()
16042 sc->trigger_grcdump = 0; in bxe_add_sysctls()
16044 CTLFLAG_RW, &sc->trigger_grcdump, 0, in bxe_add_sysctls()
16048 sc->grcdump_started = 0; in bxe_add_sysctls()
16049 sc->grcdump_done = 0; in bxe_add_sysctls()
16051 CTLFLAG_RD, &sc->grcdump_done, 0, in bxe_add_sysctls()
16054 sc->rx_budget = bxe_rx_budget; in bxe_add_sysctls()
16056 CTLFLAG_RW, &sc->rx_budget, 0, in bxe_add_sysctls()
16060 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, in bxe_add_sysctls()
16066 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_MPSAFE, sc, 0, in bxe_add_sysctls()
16072 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, i, in bxe_add_sysctls()
16081 for (i = 0; i < sc->num_queues; i++) { in bxe_add_sysctls()
16092 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, q_stat, in bxe_add_sysctls()
16099 bxe_alloc_buf_rings(struct bxe_softc *sc) in bxe_alloc_buf_rings() argument
16104 for (i = 0; i < sc->num_queues; i++) { in bxe_alloc_buf_rings()
16106 fp = &sc->fp[i]; in bxe_alloc_buf_rings()
16118 bxe_free_buf_rings(struct bxe_softc *sc) in bxe_free_buf_rings() argument
16123 for (i = 0; i < sc->num_queues; i++) { in bxe_free_buf_rings()
16125 fp = &sc->fp[i]; in bxe_free_buf_rings()
16135 bxe_init_fp_mutexs(struct bxe_softc *sc) in bxe_init_fp_mutexs() argument
16140 for (i = 0; i < sc->num_queues; i++) { in bxe_init_fp_mutexs()
16142 fp = &sc->fp[i]; in bxe_init_fp_mutexs()
16145 "bxe%d_fp%d_tx_lock", sc->unit, i); in bxe_init_fp_mutexs()
16149 "bxe%d_fp%d_rx_lock", sc->unit, i); in bxe_init_fp_mutexs()
16155 bxe_destroy_fp_mutexs(struct bxe_softc *sc) in bxe_destroy_fp_mutexs() argument
16160 for (i = 0; i < sc->num_queues; i++) { in bxe_destroy_fp_mutexs()
16162 fp = &sc->fp[i]; in bxe_destroy_fp_mutexs()
16188 struct bxe_softc *sc; in bxe_attach() local
16190 sc = device_get_softc(dev); in bxe_attach()
16192 BLOGD(sc, DBG_LOAD, "Starting attach...\n"); in bxe_attach()
16194 sc->state = BXE_STATE_CLOSED; in bxe_attach()
16196 sc->dev = dev; in bxe_attach()
16197 sc->unit = device_get_unit(dev); in bxe_attach()
16199 BLOGD(sc, DBG_LOAD, "softc = %p\n", sc); in bxe_attach()
16201 sc->pcie_bus = pci_get_bus(dev); in bxe_attach()
16202 sc->pcie_device = pci_get_slot(dev); in bxe_attach()
16203 sc->pcie_func = pci_get_function(dev); in bxe_attach()
16209 if (bxe_allocate_bars(sc) != 0) { in bxe_attach()
16214 bxe_init_mutexes(sc); in bxe_attach()
16217 callout_init(&sc->periodic_callout, 1); in bxe_attach()
16220 sc->chip_tq_flags = CHIP_TQ_NONE; in bxe_attach()
16221 snprintf(sc->chip_tq_name, sizeof(sc->chip_tq_name), in bxe_attach()
16222 "bxe%d_chip_tq", sc->unit); in bxe_attach()
16223 TASK_INIT(&sc->chip_tq_task, 0, bxe_handle_chip_tq, sc); in bxe_attach()
16224 sc->chip_tq = taskqueue_create(sc->chip_tq_name, M_NOWAIT, in bxe_attach()
16226 &sc->chip_tq); in bxe_attach()
16227 taskqueue_start_threads(&sc->chip_tq, 1, PWAIT, /* lower priority */ in bxe_attach()
16228 "%s", sc->chip_tq_name); in bxe_attach()
16231 &sc->sp_err_timeout_task, 0, bxe_sp_err_timeout_task, sc); in bxe_attach()
16235 if (bxe_get_device_info(sc) != 0) { in bxe_attach()
16236 BLOGE(sc, "getting device info\n"); in bxe_attach()
16237 bxe_deallocate_bars(sc); in bxe_attach()
16243 bxe_get_params(sc); in bxe_attach()
16246 sc->mtu = ETHERMTU; in bxe_attach()
16248 bxe_set_modes_bitmap(sc); in bxe_attach()
16256 bxe_get_phy_info(sc); in bxe_attach()
16259 bxe_init_ifnet(sc); in bxe_attach()
16261 if (bxe_add_cdev(sc) != 0) { in bxe_attach()
16262 if (sc->ifp != NULL) { in bxe_attach()
16263 ether_ifdetach(sc->ifp); in bxe_attach()
16265 ifmedia_removeall(&sc->ifmedia); in bxe_attach()
16266 bxe_release_mutexes(sc); in bxe_attach()
16267 bxe_deallocate_bars(sc); in bxe_attach()
16273 if (bxe_interrupt_alloc(sc) != 0) { in bxe_attach()
16274 bxe_del_cdev(sc); in bxe_attach()
16275 if (sc->ifp != NULL) { in bxe_attach()
16276 ether_ifdetach(sc->ifp); in bxe_attach()
16278 ifmedia_removeall(&sc->ifmedia); in bxe_attach()
16279 bxe_release_mutexes(sc); in bxe_attach()
16280 bxe_deallocate_bars(sc); in bxe_attach()
16285 bxe_init_fp_mutexs(sc); in bxe_attach()
16287 if (bxe_alloc_buf_rings(sc) != 0) { in bxe_attach()
16288 bxe_free_buf_rings(sc); in bxe_attach()
16289 bxe_interrupt_free(sc); in bxe_attach()
16290 bxe_del_cdev(sc); in bxe_attach()
16291 if (sc->ifp != NULL) { in bxe_attach()
16292 ether_ifdetach(sc->ifp); in bxe_attach()
16294 ifmedia_removeall(&sc->ifmedia); in bxe_attach()
16295 bxe_release_mutexes(sc); in bxe_attach()
16296 bxe_deallocate_bars(sc); in bxe_attach()
16302 if (bxe_alloc_ilt_mem(sc) != 0) { in bxe_attach()
16303 bxe_free_buf_rings(sc); in bxe_attach()
16304 bxe_interrupt_free(sc); in bxe_attach()
16305 bxe_del_cdev(sc); in bxe_attach()
16306 if (sc->ifp != NULL) { in bxe_attach()
16307 ether_ifdetach(sc->ifp); in bxe_attach()
16309 ifmedia_removeall(&sc->ifmedia); in bxe_attach()
16310 bxe_release_mutexes(sc); in bxe_attach()
16311 bxe_deallocate_bars(sc); in bxe_attach()
16317 if (bxe_alloc_hsi_mem(sc) != 0) { in bxe_attach()
16318 bxe_free_ilt_mem(sc); in bxe_attach()
16319 bxe_free_buf_rings(sc); in bxe_attach()
16320 bxe_interrupt_free(sc); in bxe_attach()
16321 bxe_del_cdev(sc); in bxe_attach()
16322 if (sc->ifp != NULL) { in bxe_attach()
16323 ether_ifdetach(sc->ifp); in bxe_attach()
16325 ifmedia_removeall(&sc->ifmedia); in bxe_attach()
16326 bxe_release_mutexes(sc); in bxe_attach()
16327 bxe_deallocate_bars(sc); in bxe_attach()
16333 if (IS_PF(sc) && !BXE_NOMCP(sc)) { in bxe_attach()
16335 sc->fw_seq = in bxe_attach()
16336 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) & in bxe_attach()
16338 BLOGD(sc, DBG_LOAD, "prev unload fw_seq 0x%04x\n", sc->fw_seq); in bxe_attach()
16339 bxe_prev_unload(sc); in bxe_attach()
16344 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF); in bxe_attach()
16346 if (SHMEM2_HAS(sc, dcbx_lldp_params_offset) && in bxe_attach()
16347 SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) && in bxe_attach()
16348 SHMEM2_RD(sc, dcbx_lldp_params_offset) && in bxe_attach()
16349 SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) { in bxe_attach()
16350 bxe_dcbx_set_state(sc, TRUE, BXE_DCBX_ENABLED_ON_NEG_ON); in bxe_attach()
16351 bxe_dcbx_init_params(sc); in bxe_attach()
16353 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF); in bxe_attach()
16358 sc->qm_cid_count = bxe_set_qm_cid_count(sc); in bxe_attach()
16359 BLOGD(sc, DBG_LOAD, "qm_cid_count=%d\n", sc->qm_cid_count); in bxe_attach()
16361 sc->max_cos = 1; in bxe_attach()
16362 bxe_init_multi_cos(sc); in bxe_attach()
16364 bxe_add_sysctls(sc); in bxe_attach()
16380 struct bxe_softc *sc; in bxe_detach() local
16383 sc = device_get_softc(dev); in bxe_detach()
16385 BLOGD(sc, DBG_LOAD, "Starting detach...\n"); in bxe_detach()
16387 ifp = sc->ifp; in bxe_detach()
16389 BLOGE(sc, "Cannot detach while VLANs are in use.\n"); in bxe_detach()
16393 bxe_del_cdev(sc); in bxe_detach()
16396 bxe_periodic_stop(sc); in bxe_detach()
16399 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_NONE); in bxe_detach()
16400 if (sc->chip_tq) { in bxe_detach()
16401 taskqueue_drain(sc->chip_tq, &sc->chip_tq_task); in bxe_detach()
16402 taskqueue_free(sc->chip_tq); in bxe_detach()
16403 sc->chip_tq = NULL; in bxe_detach()
16405 &sc->sp_err_timeout_task); in bxe_detach()
16409 if (sc->state != BXE_STATE_CLOSED) { in bxe_detach()
16410 BXE_CORE_LOCK(sc); in bxe_detach()
16411 bxe_nic_unload(sc, UNLOAD_CLOSE, TRUE); in bxe_detach()
16412 sc->state = BXE_STATE_DISABLED; in bxe_detach()
16413 BXE_CORE_UNLOCK(sc); in bxe_detach()
16420 ifmedia_removeall(&sc->ifmedia); in bxe_detach()
16425 bxe_free_hsi_mem(sc); in bxe_detach()
16428 bxe_free_ilt_mem(sc); in bxe_detach()
16430 bxe_free_buf_rings(sc); in bxe_detach()
16433 bxe_interrupt_free(sc); in bxe_detach()
16436 bxe_destroy_fp_mutexs(sc); in bxe_detach()
16437 bxe_release_mutexes(sc); in bxe_detach()
16441 bxe_deallocate_bars(sc); in bxe_detach()
16444 if (sc->ifp != NULL) { in bxe_detach()
16445 if_free(sc->ifp); in bxe_detach()
16464 struct bxe_softc *sc; in bxe_shutdown() local
16466 sc = device_get_softc(dev); in bxe_shutdown()
16468 BLOGD(sc, DBG_LOAD, "Starting shutdown...\n"); in bxe_shutdown()
16471 bxe_periodic_stop(sc); in bxe_shutdown()
16473 if (sc->state != BXE_STATE_CLOSED) { in bxe_shutdown()
16474 BXE_CORE_LOCK(sc); in bxe_shutdown()
16475 bxe_nic_unload(sc, UNLOAD_NORMAL, FALSE); in bxe_shutdown()
16476 BXE_CORE_UNLOCK(sc); in bxe_shutdown()
16483 bxe_igu_ack_sb(struct bxe_softc *sc, in bxe_igu_ack_sb() argument
16490 uint32_t igu_addr = sc->igu_base_addr; in bxe_igu_ack_sb()
16492 bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr); in bxe_igu_ack_sb()
16496 bxe_igu_clear_sb_gen(struct bxe_softc *sc, in bxe_igu_clear_sb_gen() argument
16510 if (CHIP_INT_MODE_IS_BC(sc)) { in bxe_igu_clear_sb_gen()
16523 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n", in bxe_igu_clear_sb_gen()
16525 REG_WR(sc, igu_addr_data, data); in bxe_igu_clear_sb_gen()
16527 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, in bxe_igu_clear_sb_gen()
16531 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n", in bxe_igu_clear_sb_gen()
16533 REG_WR(sc, igu_addr_ctl, ctl); in bxe_igu_clear_sb_gen()
16535 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, in bxe_igu_clear_sb_gen()
16540 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) { in bxe_igu_clear_sb_gen()
16544 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) { in bxe_igu_clear_sb_gen()
16545 BLOGD(sc, DBG_LOAD, in bxe_igu_clear_sb_gen()
16553 bxe_igu_clear_sb(struct bxe_softc *sc, in bxe_igu_clear_sb() argument
16556 bxe_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/); in bxe_igu_clear_sb()
16570 bxe_reset_common(struct bxe_softc *sc) in bxe_reset_common() argument
16575 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f); in bxe_reset_common()
16577 if (CHIP_IS_E3(sc)) { in bxe_reset_common()
16582 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val); in bxe_reset_common()
16586 bxe_common_init_phy(struct bxe_softc *sc) in bxe_common_init_phy() argument
16592 if (SHMEM2_RD(sc, size) > in bxe_common_init_phy()
16594 lfa_host_addr[SC_PORT(sc)])) { in bxe_common_init_phy()
16598 shmem_base[0] = sc->devinfo.shmem_base; in bxe_common_init_phy()
16599 shmem2_base[0] = sc->devinfo.shmem2_base; in bxe_common_init_phy()
16601 if (!CHIP_IS_E1x(sc)) { in bxe_common_init_phy()
16602 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr); in bxe_common_init_phy()
16603 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr); in bxe_common_init_phy()
16606 bxe_acquire_phy_lock(sc); in bxe_common_init_phy()
16607 elink_common_init_phy(sc, shmem_base, shmem2_base, in bxe_common_init_phy()
16608 sc->devinfo.chip_id, 0); in bxe_common_init_phy()
16609 bxe_release_phy_lock(sc); in bxe_common_init_phy()
16613 bxe_pf_disable(struct bxe_softc *sc) in bxe_pf_disable() argument
16615 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); in bxe_pf_disable()
16619 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); in bxe_pf_disable()
16620 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bxe_pf_disable()
16621 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0); in bxe_pf_disable()
16625 bxe_init_pxp(struct bxe_softc *sc) in bxe_init_pxp() argument
16630 devctl = bxe_pcie_capability_read(sc, PCIER_DEVICE_CTL, 2); in bxe_init_pxp()
16632 BLOGD(sc, DBG_LOAD, "read 0x%08x from devctl\n", devctl); in bxe_init_pxp()
16636 if (sc->mrrs == -1) { in bxe_init_pxp()
16639 BLOGD(sc, DBG_LOAD, "forcing read order to %d\n", sc->mrrs); in bxe_init_pxp()
16640 r_order = sc->mrrs; in bxe_init_pxp()
16643 ecore_init_pxp_arb(sc, r_order, w_order); in bxe_init_pxp()
16647 bxe_get_pretend_reg(struct bxe_softc *sc) in bxe_get_pretend_reg() argument
16651 return (base + (SC_ABS_FUNC(sc)) * stride); in bxe_get_pretend_reg()
16661 bxe_pretend_func(struct bxe_softc *sc, in bxe_pretend_func() argument
16666 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX)) { in bxe_pretend_func()
16671 pretend_reg = bxe_get_pretend_reg(sc); in bxe_pretend_func()
16672 REG_WR(sc, pretend_reg, pretend_func_val); in bxe_pretend_func()
16673 REG_RD(sc, pretend_reg); in bxe_pretend_func()
16678 bxe_iov_init_dmae(struct bxe_softc *sc) in bxe_iov_init_dmae() argument
16684 bxe_iov_init_dq(struct bxe_softc *sc) in bxe_iov_init_dq() argument
16691 bxe_lb_pckt(struct bxe_softc *sc) in bxe_lb_pckt() argument
16699 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); in bxe_lb_pckt()
16705 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); in bxe_lb_pckt()
16713 bxe_int_mem_test(struct bxe_softc *sc) in bxe_int_mem_test() argument
16719 if (CHIP_REV_IS_FPGA(sc)) { in bxe_int_mem_test()
16721 } else if (CHIP_REV_IS_EMUL(sc)) { in bxe_int_mem_test()
16728 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0); in bxe_int_mem_test()
16729 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0); in bxe_int_mem_test()
16730 REG_WR(sc, CFC_REG_DEBUG0, 0x1); in bxe_int_mem_test()
16731 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0); in bxe_int_mem_test()
16734 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bxe_int_mem_test()
16737 bxe_lb_pckt(sc); in bxe_int_mem_test()
16743 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); in bxe_int_mem_test()
16744 val = *BXE_SP(sc, wb_data[0]); in bxe_int_mem_test()
16754 BLOGE(sc, "NIG timeout val=0x%x\n", val); in bxe_int_mem_test()
16761 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); in bxe_int_mem_test()
16771 BLOGE(sc, "PRS timeout val=0x%x\n", val); in bxe_int_mem_test()
16776 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bxe_int_mem_test()
16778 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bxe_int_mem_test()
16780 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); in bxe_int_mem_test()
16781 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); in bxe_int_mem_test()
16784 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0); in bxe_int_mem_test()
16785 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0); in bxe_int_mem_test()
16786 REG_WR(sc, CFC_REG_DEBUG0, 0x1); in bxe_int_mem_test()
16787 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0); in bxe_int_mem_test()
16790 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bxe_int_mem_test()
16794 bxe_lb_pckt(sc); in bxe_int_mem_test()
16800 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); in bxe_int_mem_test()
16801 val = *BXE_SP(sc, wb_data[0]); in bxe_int_mem_test()
16811 BLOGE(sc, "NIG timeout val=0x%x\n", val); in bxe_int_mem_test()
16816 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); in bxe_int_mem_test()
16818 BLOGE(sc, "PRS timeout val=0x%x\n", val); in bxe_int_mem_test()
16822 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); in bxe_int_mem_test()
16828 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); in bxe_int_mem_test()
16830 BLOGE(sc, "PRS timeout val=0x%x\n", val); in bxe_int_mem_test()
16835 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO); in bxe_int_mem_test()
16838 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY); in bxe_int_mem_test()
16840 BLOGE(sc, "clear of NIG failed val=0x%x\n", val); in bxe_int_mem_test()
16845 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bxe_int_mem_test()
16847 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bxe_int_mem_test()
16849 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); in bxe_int_mem_test()
16850 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); in bxe_int_mem_test()
16851 if (!CNIC_SUPPORT(sc)) { in bxe_int_mem_test()
16853 REG_WR(sc, PRS_REG_NIC_MODE, 1); in bxe_int_mem_test()
16857 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff); in bxe_int_mem_test()
16858 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1); in bxe_int_mem_test()
16859 REG_WR(sc, CFC_REG_DEBUG0, 0x0); in bxe_int_mem_test()
16860 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1); in bxe_int_mem_test()
16866 bxe_setup_fan_failure_detection(struct bxe_softc *sc) in bxe_setup_fan_failure_detection() argument
16873 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) & in bxe_setup_fan_failure_detection()
16886 is_required |= elink_fan_failure_det_req(sc, in bxe_setup_fan_failure_detection()
16887 sc->devinfo.shmem_base, in bxe_setup_fan_failure_detection()
16888 sc->devinfo.shmem2_base, in bxe_setup_fan_failure_detection()
16893 BLOGD(sc, DBG_LOAD, "fan detection setting: %d\n", is_required); in bxe_setup_fan_failure_detection()
16900 bxe_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); in bxe_setup_fan_failure_detection()
16903 val = REG_RD(sc, MISC_REG_SPIO_INT); in bxe_setup_fan_failure_detection()
16905 REG_WR(sc, MISC_REG_SPIO_INT, val); in bxe_setup_fan_failure_detection()
16908 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN); in bxe_setup_fan_failure_detection()
16910 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val); in bxe_setup_fan_failure_detection()
16914 bxe_enable_blocks_attention(struct bxe_softc *sc) in bxe_enable_blocks_attention() argument
16918 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0); in bxe_enable_blocks_attention()
16919 if (!CHIP_IS_E1x(sc)) { in bxe_enable_blocks_attention()
16920 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40); in bxe_enable_blocks_attention()
16922 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0); in bxe_enable_blocks_attention()
16924 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0); in bxe_enable_blocks_attention()
16925 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0); in bxe_enable_blocks_attention()
16932 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00); in bxe_enable_blocks_attention()
16933 REG_WR(sc, QM_REG_QM_INT_MASK, 0); in bxe_enable_blocks_attention()
16934 REG_WR(sc, TM_REG_TM_INT_MASK, 0); in bxe_enable_blocks_attention()
16935 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0); in bxe_enable_blocks_attention()
16936 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0); in bxe_enable_blocks_attention()
16937 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0); in bxe_enable_blocks_attention()
16940 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0); in bxe_enable_blocks_attention()
16941 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0); in bxe_enable_blocks_attention()
16942 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0); in bxe_enable_blocks_attention()
16945 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); in bxe_enable_blocks_attention()
16946 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0); in bxe_enable_blocks_attention()
16947 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0); in bxe_enable_blocks_attention()
16948 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0); in bxe_enable_blocks_attention()
16955 if (!CHIP_IS_E1x(sc)) { in bxe_enable_blocks_attention()
16959 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val); in bxe_enable_blocks_attention()
16961 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0); in bxe_enable_blocks_attention()
16962 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0); in bxe_enable_blocks_attention()
16963 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0); in bxe_enable_blocks_attention()
16966 if (!CHIP_IS_E1x(sc)) { in bxe_enable_blocks_attention()
16968 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); in bxe_enable_blocks_attention()
16971 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0); in bxe_enable_blocks_attention()
16972 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0); in bxe_enable_blocks_attention()
16974 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ in bxe_enable_blocks_attention()
16983 bxe_init_hw_common(struct bxe_softc *sc) in bxe_init_hw_common() argument
16988 BLOGD(sc, DBG_LOAD, "starting common init for func %d\n", in bxe_init_hw_common()
16989 SC_ABS_FUNC(sc)); in bxe_init_hw_common()
16995 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET); in bxe_init_hw_common()
16997 bxe_reset_common(sc); in bxe_init_hw_common()
16999 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff); in bxe_init_hw_common()
17002 if (CHIP_IS_E3(sc)) { in bxe_init_hw_common()
17007 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val); in bxe_init_hw_common()
17009 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); in bxe_init_hw_common()
17011 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON); in bxe_init_hw_common()
17012 BLOGD(sc, DBG_LOAD, "after misc block init\n"); in bxe_init_hw_common()
17014 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_common()
17021 for (abs_func_id = SC_PATH(sc); in bxe_init_hw_common()
17024 if (abs_func_id == SC_ABS_FUNC(sc)) { in bxe_init_hw_common()
17025 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bxe_init_hw_common()
17029 bxe_pretend_func(sc, abs_func_id); in bxe_init_hw_common()
17032 bxe_pf_disable(sc); in bxe_init_hw_common()
17034 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); in bxe_init_hw_common()
17038 BLOGD(sc, DBG_LOAD, "after pf disable\n"); in bxe_init_hw_common()
17040 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON); in bxe_init_hw_common()
17042 if (CHIP_IS_E1(sc)) { in bxe_init_hw_common()
17047 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0); in bxe_init_hw_common()
17050 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON); in bxe_init_hw_common()
17051 bxe_init_pxp(sc); in bxe_init_hw_common()
17054 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1); in bxe_init_hw_common()
17055 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1); in bxe_init_hw_common()
17056 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1); in bxe_init_hw_common()
17057 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1); in bxe_init_hw_common()
17058 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1); in bxe_init_hw_common()
17060 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0); in bxe_init_hw_common()
17063 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1); in bxe_init_hw_common()
17064 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1); in bxe_init_hw_common()
17065 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1); in bxe_init_hw_common()
17066 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1); in bxe_init_hw_common()
17069 ecore_ilt_init_page_size(sc, INITOP_SET); in bxe_init_hw_common()
17071 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) { in bxe_init_hw_common()
17072 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1); in bxe_init_hw_common()
17079 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE); in bxe_init_hw_common()
17081 BLOGE(sc, "PXP2 CFG failed PXP2_REG_RQ_CFG_DONE val = 0x%x\n", in bxe_init_hw_common()
17085 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE); in bxe_init_hw_common()
17087 BLOGE(sc, "PXP2 RD_INIT failed val = 0x%x\n", val); in bxe_init_hw_common()
17091 BLOGD(sc, DBG_LOAD, "after pxp init\n"); in bxe_init_hw_common()
17098 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_common()
17186 bxe_pretend_func(sc, (SC_PATH(sc) + 6)); in bxe_init_hw_common()
17187 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR); in bxe_init_hw_common()
17188 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); in bxe_init_hw_common()
17190 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN); in bxe_init_hw_common()
17191 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN); in bxe_init_hw_common()
17192 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); in bxe_init_hw_common()
17195 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0); in bxe_init_hw_common()
17196 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0); in bxe_init_hw_common()
17198 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_common()
17199 int factor = CHIP_REV_IS_EMUL(sc) ? 1000 : in bxe_init_hw_common()
17200 (CHIP_REV_IS_FPGA(sc) ? 400 : 0); in bxe_init_hw_common()
17202 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON); in bxe_init_hw_common()
17203 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON); in bxe_init_hw_common()
17208 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE); in bxe_init_hw_common()
17212 BLOGE(sc, "ATC_INIT failed val = 0x%x\n", val); in bxe_init_hw_common()
17217 BLOGD(sc, DBG_LOAD, "after pglue and atc init\n"); in bxe_init_hw_common()
17219 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON); in bxe_init_hw_common()
17221 bxe_iov_init_dmae(sc); in bxe_init_hw_common()
17224 sc->dmae_ready = 1; in bxe_init_hw_common()
17225 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1); in bxe_init_hw_common()
17227 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON); in bxe_init_hw_common()
17229 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON); in bxe_init_hw_common()
17231 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON); in bxe_init_hw_common()
17233 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON); in bxe_init_hw_common()
17235 bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3); in bxe_init_hw_common()
17236 bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3); in bxe_init_hw_common()
17237 bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3); in bxe_init_hw_common()
17238 bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3); in bxe_init_hw_common()
17240 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON); in bxe_init_hw_common()
17243 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET); in bxe_init_hw_common()
17246 REG_WR(sc, QM_REG_SOFT_RESET, 1); in bxe_init_hw_common()
17247 REG_WR(sc, QM_REG_SOFT_RESET, 0); in bxe_init_hw_common()
17249 if (CNIC_SUPPORT(sc)) in bxe_init_hw_common()
17250 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON); in bxe_init_hw_common()
17252 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON); in bxe_init_hw_common()
17253 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT); in bxe_init_hw_common()
17254 if (!CHIP_REV_IS_SLOW(sc)) { in bxe_init_hw_common()
17256 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0); in bxe_init_hw_common()
17259 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); in bxe_init_hw_common()
17261 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); in bxe_init_hw_common()
17262 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf); in bxe_init_hw_common()
17264 if (!CHIP_IS_E1(sc)) { in bxe_init_hw_common()
17265 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan); in bxe_init_hw_common()
17268 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) { in bxe_init_hw_common()
17269 if (IS_MF_AFEX(sc)) { in bxe_init_hw_common()
17274 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE); in bxe_init_hw_common()
17275 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA); in bxe_init_hw_common()
17276 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6); in bxe_init_hw_common()
17277 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926); in bxe_init_hw_common()
17278 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4); in bxe_init_hw_common()
17284 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, in bxe_init_hw_common()
17285 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6); in bxe_init_hw_common()
17289 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON); in bxe_init_hw_common()
17290 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON); in bxe_init_hw_common()
17291 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON); in bxe_init_hw_common()
17292 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON); in bxe_init_hw_common()
17294 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_common()
17296 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bxe_init_hw_common()
17299 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bxe_init_hw_common()
17306 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON); in bxe_init_hw_common()
17307 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON); in bxe_init_hw_common()
17308 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON); in bxe_init_hw_common()
17309 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON); in bxe_init_hw_common()
17312 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bxe_init_hw_common()
17314 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, in bxe_init_hw_common()
17317 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON); in bxe_init_hw_common()
17318 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON); in bxe_init_hw_common()
17319 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON); in bxe_init_hw_common()
17321 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_common()
17322 if (IS_MF_AFEX(sc)) { in bxe_init_hw_common()
17327 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE); in bxe_init_hw_common()
17328 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA); in bxe_init_hw_common()
17329 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6); in bxe_init_hw_common()
17330 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926); in bxe_init_hw_common()
17331 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4); in bxe_init_hw_common()
17333 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, in bxe_init_hw_common()
17334 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6); in bxe_init_hw_common()
17338 REG_WR(sc, SRC_REG_SOFT_RST, 1); in bxe_init_hw_common()
17340 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON); in bxe_init_hw_common()
17342 if (CNIC_SUPPORT(sc)) { in bxe_init_hw_common()
17343 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672); in bxe_init_hw_common()
17344 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); in bxe_init_hw_common()
17345 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b); in bxe_init_hw_common()
17346 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a); in bxe_init_hw_common()
17347 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116); in bxe_init_hw_common()
17348 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b); in bxe_init_hw_common()
17349 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf); in bxe_init_hw_common()
17350 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); in bxe_init_hw_common()
17351 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f); in bxe_init_hw_common()
17352 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7); in bxe_init_hw_common()
17354 REG_WR(sc, SRC_REG_SOFT_RST, 0); in bxe_init_hw_common()
17358 BLOGE(sc, "please adjust the size of cdu_context(%ld)\n", in bxe_init_hw_common()
17362 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON); in bxe_init_hw_common()
17364 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val); in bxe_init_hw_common()
17366 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON); in bxe_init_hw_common()
17368 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF); in bxe_init_hw_common()
17370 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0); in bxe_init_hw_common()
17373 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000); in bxe_init_hw_common()
17374 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON); in bxe_init_hw_common()
17376 if (!CHIP_IS_E1x(sc) && BXE_NOMCP(sc)) { in bxe_init_hw_common()
17377 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36); in bxe_init_hw_common()
17380 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON); in bxe_init_hw_common()
17381 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON); in bxe_init_hw_common()
17384 REG_WR(sc, 0x2814, 0xffffffff); in bxe_init_hw_common()
17385 REG_WR(sc, 0x3820, 0xffffffff); in bxe_init_hw_common()
17387 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_common()
17388 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, in bxe_init_hw_common()
17391 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, in bxe_init_hw_common()
17395 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, in bxe_init_hw_common()
17401 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON); in bxe_init_hw_common()
17403 if (!CHIP_IS_E1(sc)) { in bxe_init_hw_common()
17405 if (!CHIP_IS_E3(sc)) in bxe_init_hw_common()
17406 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc)); in bxe_init_hw_common()
17409 if (CHIP_IS_E1H(sc)) { in bxe_init_hw_common()
17411 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc)); in bxe_init_hw_common()
17414 if (CHIP_REV_IS_SLOW(sc)) { in bxe_init_hw_common()
17419 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10); in bxe_init_hw_common()
17421 BLOGE(sc, "CFC LL_INIT failed val=0x%x\n", val); in bxe_init_hw_common()
17424 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10); in bxe_init_hw_common()
17426 BLOGE(sc, "CFC AC_INIT failed val=0x%x\n", val); in bxe_init_hw_common()
17429 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10); in bxe_init_hw_common()
17431 BLOGE(sc, "CFC CAM_INIT failed val=0x%x\n", val); in bxe_init_hw_common()
17434 REG_WR(sc, CFC_REG_DEBUG0, 0); in bxe_init_hw_common()
17436 if (CHIP_IS_E1(sc)) { in bxe_init_hw_common()
17438 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); in bxe_init_hw_common()
17439 val = *BXE_SP(sc, wb_data[0]); in bxe_init_hw_common()
17442 if ((val == 0) && bxe_int_mem_test(sc)) { in bxe_init_hw_common()
17443 BLOGE(sc, "internal mem self test failed val=0x%x\n", val); in bxe_init_hw_common()
17448 bxe_setup_fan_failure_detection(sc); in bxe_init_hw_common()
17451 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0); in bxe_init_hw_common()
17453 bxe_enable_blocks_attention(sc); in bxe_init_hw_common()
17455 if (!CHIP_REV_IS_SLOW(sc)) { in bxe_init_hw_common()
17456 ecore_enable_blocks_parity(sc); in bxe_init_hw_common()
17459 if (!BXE_NOMCP(sc)) { in bxe_init_hw_common()
17460 if (CHIP_IS_E1x(sc)) { in bxe_init_hw_common()
17461 bxe_common_init_phy(sc); in bxe_init_hw_common()
17474 bxe_init_hw_common_chip(struct bxe_softc *sc) in bxe_init_hw_common_chip() argument
17476 int rc = bxe_init_hw_common(sc); in bxe_init_hw_common_chip()
17479 BLOGE(sc, "bxe_init_hw_common failed rc=%d\n", rc); in bxe_init_hw_common_chip()
17484 if (!BXE_NOMCP(sc)) { in bxe_init_hw_common_chip()
17485 bxe_common_init_phy(sc); in bxe_init_hw_common_chip()
17492 bxe_init_hw_port(struct bxe_softc *sc) in bxe_init_hw_port() argument
17494 int port = SC_PORT(sc); in bxe_init_hw_port()
17499 BLOGD(sc, DBG_LOAD, "starting port init for port %d\n", port); in bxe_init_hw_port()
17501 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bxe_init_hw_port()
17503 ecore_init_block(sc, BLOCK_MISC, init_phase); in bxe_init_hw_port()
17504 ecore_init_block(sc, BLOCK_PXP, init_phase); in bxe_init_hw_port()
17505 ecore_init_block(sc, BLOCK_PXP2, init_phase); in bxe_init_hw_port()
17513 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_port()
17514 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bxe_init_hw_port()
17517 ecore_init_block(sc, BLOCK_ATC, init_phase); in bxe_init_hw_port()
17518 ecore_init_block(sc, BLOCK_DMAE, init_phase); in bxe_init_hw_port()
17519 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase); in bxe_init_hw_port()
17520 ecore_init_block(sc, BLOCK_QM, init_phase); in bxe_init_hw_port()
17522 ecore_init_block(sc, BLOCK_TCM, init_phase); in bxe_init_hw_port()
17523 ecore_init_block(sc, BLOCK_UCM, init_phase); in bxe_init_hw_port()
17524 ecore_init_block(sc, BLOCK_CCM, init_phase); in bxe_init_hw_port()
17525 ecore_init_block(sc, BLOCK_XCM, init_phase); in bxe_init_hw_port()
17528 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET); in bxe_init_hw_port()
17530 if (CNIC_SUPPORT(sc)) { in bxe_init_hw_port()
17531 ecore_init_block(sc, BLOCK_TM, init_phase); in bxe_init_hw_port()
17532 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20); in bxe_init_hw_port()
17533 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); in bxe_init_hw_port()
17536 ecore_init_block(sc, BLOCK_DORQ, init_phase); in bxe_init_hw_port()
17538 ecore_init_block(sc, BLOCK_BRB1, init_phase); in bxe_init_hw_port()
17540 if (CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) { in bxe_init_hw_port()
17541 if (IS_MF(sc)) { in bxe_init_hw_port()
17542 low = (BXE_ONE_PORT(sc) ? 160 : 246); in bxe_init_hw_port()
17543 } else if (sc->mtu > 4096) { in bxe_init_hw_port()
17544 if (BXE_ONE_PORT(sc)) { in bxe_init_hw_port()
17547 val = sc->mtu; in bxe_init_hw_port()
17552 low = (BXE_ONE_PORT(sc) ? 80 : 160); in bxe_init_hw_port()
17555 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); in bxe_init_hw_port()
17556 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); in bxe_init_hw_port()
17559 if (CHIP_IS_MODE_4_PORT(sc)) { in bxe_init_hw_port()
17560 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17565 ecore_init_block(sc, BLOCK_PRS, init_phase); in bxe_init_hw_port()
17566 if (CHIP_IS_E3B0(sc)) { in bxe_init_hw_port()
17567 if (IS_MF_AFEX(sc)) { in bxe_init_hw_port()
17569 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17572 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17575 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17583 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17586 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6)); in bxe_init_hw_port()
17590 ecore_init_block(sc, BLOCK_TSDM, init_phase); in bxe_init_hw_port()
17591 ecore_init_block(sc, BLOCK_CSDM, init_phase); in bxe_init_hw_port()
17592 ecore_init_block(sc, BLOCK_USDM, init_phase); in bxe_init_hw_port()
17593 ecore_init_block(sc, BLOCK_XSDM, init_phase); in bxe_init_hw_port()
17595 ecore_init_block(sc, BLOCK_TSEM, init_phase); in bxe_init_hw_port()
17596 ecore_init_block(sc, BLOCK_USEM, init_phase); in bxe_init_hw_port()
17597 ecore_init_block(sc, BLOCK_CSEM, init_phase); in bxe_init_hw_port()
17598 ecore_init_block(sc, BLOCK_XSEM, init_phase); in bxe_init_hw_port()
17600 ecore_init_block(sc, BLOCK_UPB, init_phase); in bxe_init_hw_port()
17601 ecore_init_block(sc, BLOCK_XPB, init_phase); in bxe_init_hw_port()
17603 ecore_init_block(sc, BLOCK_PBF, init_phase); in bxe_init_hw_port()
17605 if (CHIP_IS_E1x(sc)) { in bxe_init_hw_port()
17607 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bxe_init_hw_port()
17610 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); in bxe_init_hw_port()
17612 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); in bxe_init_hw_port()
17615 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1); in bxe_init_hw_port()
17617 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0); in bxe_init_hw_port()
17620 if (CNIC_SUPPORT(sc)) { in bxe_init_hw_port()
17621 ecore_init_block(sc, BLOCK_SRC, init_phase); in bxe_init_hw_port()
17624 ecore_init_block(sc, BLOCK_CDU, init_phase); in bxe_init_hw_port()
17625 ecore_init_block(sc, BLOCK_CFC, init_phase); in bxe_init_hw_port()
17627 if (CHIP_IS_E1(sc)) { in bxe_init_hw_port()
17628 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); in bxe_init_hw_port()
17629 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bxe_init_hw_port()
17631 ecore_init_block(sc, BLOCK_HC, init_phase); in bxe_init_hw_port()
17633 ecore_init_block(sc, BLOCK_IGU, init_phase); in bxe_init_hw_port()
17635 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase); in bxe_init_hw_port()
17640 val = IS_MF(sc) ? 0xF7 : 0x7; in bxe_init_hw_port()
17642 val |= CHIP_IS_E1(sc) ? 0 : 0x10; in bxe_init_hw_port()
17643 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); in bxe_init_hw_port()
17645 ecore_init_block(sc, BLOCK_NIG, init_phase); in bxe_init_hw_port()
17647 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_port()
17651 if (IS_MF_AFEX(sc)) { in bxe_init_hw_port()
17652 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17656 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17659 IS_MF_SD(sc) ? 7 : 6); in bxe_init_hw_port()
17662 if (CHIP_IS_E3(sc)) { in bxe_init_hw_port()
17663 REG_WR(sc, SC_PORT(sc) ? in bxe_init_hw_port()
17665 NIG_REG_LLH_MF_MODE, IS_MF(sc)); in bxe_init_hw_port()
17668 if (!CHIP_IS_E3(sc)) { in bxe_init_hw_port()
17669 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bxe_init_hw_port()
17672 if (!CHIP_IS_E1(sc)) { in bxe_init_hw_port()
17674 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, in bxe_init_hw_port()
17675 (IS_MF_SD(sc) ? 0x1 : 0x2)); in bxe_init_hw_port()
17677 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_port()
17679 switch (sc->devinfo.mf_info.mf_mode) { in bxe_init_hw_port()
17689 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE : in bxe_init_hw_port()
17692 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0); in bxe_init_hw_port()
17693 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); in bxe_init_hw_port()
17694 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); in bxe_init_hw_port()
17698 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN); in bxe_init_hw_port()
17702 val = REG_RD(sc, reg_addr); in bxe_init_hw_port()
17704 REG_WR(sc, reg_addr, val); in bxe_init_hw_port()
17711 bxe_flr_clnup_reg_poll(struct bxe_softc *sc, in bxe_flr_clnup_reg_poll() argument
17719 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) { in bxe_flr_clnup_reg_poll()
17727 bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc, in bxe_flr_clnup_poll_hw_counter() argument
17732 uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt); in bxe_flr_clnup_poll_hw_counter()
17735 BLOGE(sc, "%s usage count=%d\n", msg, val); in bxe_flr_clnup_poll_hw_counter()
17744 bxe_flr_clnup_poll_count(struct bxe_softc *sc) in bxe_flr_clnup_poll_count() argument
17747 if (CHIP_REV_IS_EMUL(sc)) { in bxe_flr_clnup_poll_count()
17751 if (CHIP_REV_IS_FPGA(sc)) { in bxe_flr_clnup_poll_count()
17759 bxe_poll_hw_usage_counters(struct bxe_softc *sc, in bxe_poll_hw_usage_counters() argument
17763 if (bxe_flr_clnup_poll_hw_counter(sc, in bxe_poll_hw_usage_counters()
17771 if (bxe_flr_clnup_poll_hw_counter(sc, in bxe_poll_hw_usage_counters()
17779 if (bxe_flr_clnup_poll_hw_counter(sc, in bxe_poll_hw_usage_counters()
17780 QM_REG_PF_USG_CNT_0 + 4*SC_FUNC(sc), in bxe_poll_hw_usage_counters()
17787 if (bxe_flr_clnup_poll_hw_counter(sc, in bxe_poll_hw_usage_counters()
17788 TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc), in bxe_poll_hw_usage_counters()
17794 if (bxe_flr_clnup_poll_hw_counter(sc, in bxe_poll_hw_usage_counters()
17795 TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc), in bxe_poll_hw_usage_counters()
17802 if (bxe_flr_clnup_poll_hw_counter(sc, in bxe_poll_hw_usage_counters()
17803 dmae_reg_go_c[INIT_DMAE_C(sc)], in bxe_poll_hw_usage_counters()
17820 bxe_send_final_clnup(struct bxe_softc *sc, in bxe_send_final_clnup() argument
17829 if (REG_RD(sc, comp_addr)) { in bxe_send_final_clnup()
17830 BLOGE(sc, "Cleanup complete was not 0 before sending\n"); in bxe_send_final_clnup()
17839 BLOGD(sc, DBG_LOAD, "sending FW Final cleanup\n"); in bxe_send_final_clnup()
17840 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command); in bxe_send_final_clnup()
17842 if (bxe_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) { in bxe_send_final_clnup()
17843 BLOGE(sc, "FW final cleanup did not succeed\n"); in bxe_send_final_clnup()
17844 BLOGD(sc, DBG_LOAD, "At timeout completion address contained %x\n", in bxe_send_final_clnup()
17845 (REG_RD(sc, comp_addr))); in bxe_send_final_clnup()
17846 bxe_panic(sc, ("FLR cleanup failed\n")); in bxe_send_final_clnup()
17851 REG_WR(sc, comp_addr, 0); in bxe_send_final_clnup()
17857 bxe_pbf_pN_buf_flushed(struct bxe_softc *sc, in bxe_pbf_pN_buf_flushed() argument
17864 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed); in bxe_pbf_pN_buf_flushed()
17865 crd = crd_start = REG_RD(sc, regs->crd); in bxe_pbf_pN_buf_flushed()
17866 init_crd = REG_RD(sc, regs->init_crd); in bxe_pbf_pN_buf_flushed()
17868 BLOGD(sc, DBG_LOAD, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); in bxe_pbf_pN_buf_flushed()
17869 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : s:%x\n", regs->pN, crd); in bxe_pbf_pN_buf_flushed()
17870 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); in bxe_pbf_pN_buf_flushed()
17877 crd = REG_RD(sc, regs->crd); in bxe_pbf_pN_buf_flushed()
17878 crd_freed = REG_RD(sc, regs->crd_freed); in bxe_pbf_pN_buf_flushed()
17880 BLOGD(sc, DBG_LOAD, "PBF tx buffer[%d] timed out\n", regs->pN); in bxe_pbf_pN_buf_flushed()
17881 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : c:%x\n", regs->pN, crd); in bxe_pbf_pN_buf_flushed()
17882 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: c:%x\n", regs->pN, crd_freed); in bxe_pbf_pN_buf_flushed()
17887 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF tx buffer[%d]\n", in bxe_pbf_pN_buf_flushed()
17892 bxe_pbf_pN_cmd_flushed(struct bxe_softc *sc, in bxe_pbf_pN_cmd_flushed() argument
17899 occup = to_free = REG_RD(sc, regs->lines_occup); in bxe_pbf_pN_cmd_flushed()
17900 freed = freed_start = REG_RD(sc, regs->lines_freed); in bxe_pbf_pN_cmd_flushed()
17902 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); in bxe_pbf_pN_cmd_flushed()
17903 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); in bxe_pbf_pN_cmd_flushed()
17909 occup = REG_RD(sc, regs->lines_occup); in bxe_pbf_pN_cmd_flushed()
17910 freed = REG_RD(sc, regs->lines_freed); in bxe_pbf_pN_cmd_flushed()
17912 BLOGD(sc, DBG_LOAD, "PBF cmd queue[%d] timed out\n", regs->pN); in bxe_pbf_pN_cmd_flushed()
17913 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); in bxe_pbf_pN_cmd_flushed()
17914 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); in bxe_pbf_pN_cmd_flushed()
17919 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF cmd queue[%d]\n", in bxe_pbf_pN_cmd_flushed()
17924 bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count) in bxe_tx_hw_flushed() argument
17927 {0, (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17930 (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17933 {1, (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17936 (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17939 {4, (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17942 (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17948 {0, (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17951 (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17954 (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17957 {1, (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17960 (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17963 (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17966 {4, (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17969 (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17972 (CHIP_IS_E3B0(sc)) ? in bxe_tx_hw_flushed()
17981 bxe_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count); in bxe_tx_hw_flushed()
17986 bxe_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count); in bxe_tx_hw_flushed()
17991 bxe_hw_enable_status(struct bxe_softc *sc) in bxe_hw_enable_status() argument
17995 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF); in bxe_hw_enable_status()
17996 BLOGD(sc, DBG_LOAD, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); in bxe_hw_enable_status()
17998 val = REG_RD(sc, PBF_REG_DISABLE_PF); in bxe_hw_enable_status()
17999 BLOGD(sc, DBG_LOAD, "PBF_REG_DISABLE_PF is 0x%x\n", val); in bxe_hw_enable_status()
18001 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN); in bxe_hw_enable_status()
18002 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); in bxe_hw_enable_status()
18004 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN); in bxe_hw_enable_status()
18005 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); in bxe_hw_enable_status()
18007 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK); in bxe_hw_enable_status()
18008 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); in bxe_hw_enable_status()
18010 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); in bxe_hw_enable_status()
18011 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); in bxe_hw_enable_status()
18013 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); in bxe_hw_enable_status()
18014 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); in bxe_hw_enable_status()
18016 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); in bxe_hw_enable_status()
18017 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val); in bxe_hw_enable_status()
18021 bxe_pf_flr_clnup(struct bxe_softc *sc) in bxe_pf_flr_clnup() argument
18023 uint32_t poll_cnt = bxe_flr_clnup_poll_count(sc); in bxe_pf_flr_clnup()
18025 BLOGD(sc, DBG_LOAD, "Cleanup after FLR PF[%d]\n", SC_ABS_FUNC(sc)); in bxe_pf_flr_clnup()
18028 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bxe_pf_flr_clnup()
18031 BLOGD(sc, DBG_LOAD, "Polling usage counters\n"); in bxe_pf_flr_clnup()
18032 if (bxe_poll_hw_usage_counters(sc, poll_cnt)) { in bxe_pf_flr_clnup()
18039 if (bxe_send_final_clnup(sc, (uint8_t)SC_FUNC(sc), poll_cnt)) { in bxe_pf_flr_clnup()
18046 bxe_tx_hw_flushed(sc, poll_cnt); in bxe_pf_flr_clnup()
18052 if (bxe_is_pcie_pending(sc)) { in bxe_pf_flr_clnup()
18053 BLOGE(sc, "PCIE Transactions still pending\n"); in bxe_pf_flr_clnup()
18057 bxe_hw_enable_status(sc); in bxe_pf_flr_clnup()
18063 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bxe_pf_flr_clnup()
18069 bxe_init_hw_func(struct bxe_softc *sc) in bxe_init_hw_func() argument
18071 int port = SC_PORT(sc); in bxe_init_hw_func()
18072 int func = SC_FUNC(sc); in bxe_init_hw_func()
18074 struct ecore_ilt *ilt = sc->ilt; in bxe_init_hw_func()
18080 BLOGD(sc, DBG_LOAD, "starting func init for func %d\n", func); in bxe_init_hw_func()
18083 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_func()
18084 rc = bxe_pf_flr_clnup(sc); in bxe_init_hw_func()
18086 BLOGE(sc, "FLR cleanup failed!\n"); in bxe_init_hw_func()
18094 if (sc->devinfo.int_block == INT_BLOCK_HC) { in bxe_init_hw_func()
18096 val = REG_RD(sc, addr); in bxe_init_hw_func()
18098 REG_WR(sc, addr, val); in bxe_init_hw_func()
18101 ecore_init_block(sc, BLOCK_PXP, init_phase); in bxe_init_hw_func()
18102 ecore_init_block(sc, BLOCK_PXP2, init_phase); in bxe_init_hw_func()
18104 ilt = sc->ilt; in bxe_init_hw_func()
18107 for (i = 0; i < L2_ILT_LINES(sc); i++) { in bxe_init_hw_func()
18108 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt; in bxe_init_hw_func()
18110 sc->context[i].vcxt_dma.paddr; in bxe_init_hw_func()
18111 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size; in bxe_init_hw_func()
18113 ecore_ilt_init_op(sc, INITOP_SET); in bxe_init_hw_func()
18116 REG_WR(sc, PRS_REG_NIC_MODE, 1); in bxe_init_hw_func()
18117 BLOGD(sc, DBG_LOAD, "NIC MODE configured\n"); in bxe_init_hw_func()
18119 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_func()
18125 if (sc->interrupt_mode != INTR_MODE_MSIX) { in bxe_init_hw_func()
18142 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bxe_init_hw_func()
18144 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf); in bxe_init_hw_func()
18147 sc->dmae_ready = 1; in bxe_init_hw_func()
18149 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase); in bxe_init_hw_func()
18151 if (!CHIP_IS_E1x(sc)) in bxe_init_hw_func()
18152 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); in bxe_init_hw_func()
18154 ecore_init_block(sc, BLOCK_ATC, init_phase); in bxe_init_hw_func()
18155 ecore_init_block(sc, BLOCK_DMAE, init_phase); in bxe_init_hw_func()
18156 ecore_init_block(sc, BLOCK_NIG, init_phase); in bxe_init_hw_func()
18157 ecore_init_block(sc, BLOCK_SRC, init_phase); in bxe_init_hw_func()
18158 ecore_init_block(sc, BLOCK_MISC, init_phase); in bxe_init_hw_func()
18159 ecore_init_block(sc, BLOCK_TCM, init_phase); in bxe_init_hw_func()
18160 ecore_init_block(sc, BLOCK_UCM, init_phase); in bxe_init_hw_func()
18161 ecore_init_block(sc, BLOCK_CCM, init_phase); in bxe_init_hw_func()
18162 ecore_init_block(sc, BLOCK_XCM, init_phase); in bxe_init_hw_func()
18163 ecore_init_block(sc, BLOCK_TSEM, init_phase); in bxe_init_hw_func()
18164 ecore_init_block(sc, BLOCK_USEM, init_phase); in bxe_init_hw_func()
18165 ecore_init_block(sc, BLOCK_CSEM, init_phase); in bxe_init_hw_func()
18166 ecore_init_block(sc, BLOCK_XSEM, init_phase); in bxe_init_hw_func()
18168 if (!CHIP_IS_E1x(sc)) in bxe_init_hw_func()
18169 REG_WR(sc, QM_REG_PF_EN, 1); in bxe_init_hw_func()
18171 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_func()
18172 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); in bxe_init_hw_func()
18173 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); in bxe_init_hw_func()
18174 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); in bxe_init_hw_func()
18175 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); in bxe_init_hw_func()
18177 ecore_init_block(sc, BLOCK_QM, init_phase); in bxe_init_hw_func()
18179 ecore_init_block(sc, BLOCK_TM, init_phase); in bxe_init_hw_func()
18180 ecore_init_block(sc, BLOCK_DORQ, init_phase); in bxe_init_hw_func()
18182 bxe_iov_init_dq(sc); in bxe_init_hw_func()
18184 ecore_init_block(sc, BLOCK_BRB1, init_phase); in bxe_init_hw_func()
18185 ecore_init_block(sc, BLOCK_PRS, init_phase); in bxe_init_hw_func()
18186 ecore_init_block(sc, BLOCK_TSDM, init_phase); in bxe_init_hw_func()
18187 ecore_init_block(sc, BLOCK_CSDM, init_phase); in bxe_init_hw_func()
18188 ecore_init_block(sc, BLOCK_USDM, init_phase); in bxe_init_hw_func()
18189 ecore_init_block(sc, BLOCK_XSDM, init_phase); in bxe_init_hw_func()
18190 ecore_init_block(sc, BLOCK_UPB, init_phase); in bxe_init_hw_func()
18191 ecore_init_block(sc, BLOCK_XPB, init_phase); in bxe_init_hw_func()
18192 ecore_init_block(sc, BLOCK_PBF, init_phase); in bxe_init_hw_func()
18193 if (!CHIP_IS_E1x(sc)) in bxe_init_hw_func()
18194 REG_WR(sc, PBF_REG_DISABLE_PF, 0); in bxe_init_hw_func()
18196 ecore_init_block(sc, BLOCK_CDU, init_phase); in bxe_init_hw_func()
18198 ecore_init_block(sc, BLOCK_CFC, init_phase); in bxe_init_hw_func()
18200 if (!CHIP_IS_E1x(sc)) in bxe_init_hw_func()
18201 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1); in bxe_init_hw_func()
18203 if (IS_MF(sc)) { in bxe_init_hw_func()
18204 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1); in bxe_init_hw_func()
18205 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc)); in bxe_init_hw_func()
18208 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase); in bxe_init_hw_func()
18211 if (sc->devinfo.int_block == INT_BLOCK_HC) { in bxe_init_hw_func()
18212 if (CHIP_IS_E1H(sc)) { in bxe_init_hw_func()
18213 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bxe_init_hw_func()
18215 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); in bxe_init_hw_func()
18216 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bxe_init_hw_func()
18218 ecore_init_block(sc, BLOCK_HC, init_phase); in bxe_init_hw_func()
18223 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bxe_init_hw_func()
18225 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_func()
18226 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0); in bxe_init_hw_func()
18227 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0); in bxe_init_hw_func()
18230 ecore_init_block(sc, BLOCK_IGU, init_phase); in bxe_init_hw_func()
18232 if (!CHIP_IS_E1x(sc)) { in bxe_init_hw_func()
18255 num_segs = CHIP_INT_MODE_IS_BC(sc) ? in bxe_init_hw_func()
18257 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) { in bxe_init_hw_func()
18258 prod_offset = (sc->igu_base_sb + sb_idx) * in bxe_init_hw_func()
18264 REG_WR(sc, addr, 0); in bxe_init_hw_func()
18267 bxe_ack_sb(sc, sc->igu_base_sb + sb_idx, in bxe_init_hw_func()
18269 bxe_igu_clear_sb(sc, sc->igu_base_sb + sb_idx); in bxe_init_hw_func()
18273 num_segs = CHIP_INT_MODE_IS_BC(sc) ? in bxe_init_hw_func()
18276 if (CHIP_IS_MODE_4_PORT(sc)) in bxe_init_hw_func()
18277 dsb_idx = SC_FUNC(sc); in bxe_init_hw_func()
18279 dsb_idx = SC_VN(sc); in bxe_init_hw_func()
18281 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ? in bxe_init_hw_func()
18293 REG_WR(sc, addr, 0); in bxe_init_hw_func()
18296 if (CHIP_INT_MODE_IS_BC(sc)) { in bxe_init_hw_func()
18297 bxe_ack_sb(sc, sc->igu_dsb_id, in bxe_init_hw_func()
18299 bxe_ack_sb(sc, sc->igu_dsb_id, in bxe_init_hw_func()
18301 bxe_ack_sb(sc, sc->igu_dsb_id, in bxe_init_hw_func()
18303 bxe_ack_sb(sc, sc->igu_dsb_id, in bxe_init_hw_func()
18305 bxe_ack_sb(sc, sc->igu_dsb_id, in bxe_init_hw_func()
18308 bxe_ack_sb(sc, sc->igu_dsb_id, in bxe_init_hw_func()
18310 bxe_ack_sb(sc, sc->igu_dsb_id, in bxe_init_hw_func()
18313 bxe_igu_clear_sb(sc, sc->igu_dsb_id); in bxe_init_hw_func()
18317 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bxe_init_hw_func()
18318 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bxe_init_hw_func()
18319 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0); in bxe_init_hw_func()
18320 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0); in bxe_init_hw_func()
18321 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0); in bxe_init_hw_func()
18322 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0); in bxe_init_hw_func()
18327 REG_WR(sc, 0x2114, 0xffffffff); in bxe_init_hw_func()
18328 REG_WR(sc, 0x2120, 0xffffffff); in bxe_init_hw_func()
18330 if (CHIP_IS_E1x(sc)) { in bxe_init_hw_func()
18333 SC_PORT(sc) * (main_mem_size * 4); in bxe_init_hw_func()
18337 val = REG_RD(sc, main_mem_prty_clr); in bxe_init_hw_func()
18339 BLOGD(sc, DBG_LOAD, in bxe_init_hw_func()
18348 bxe_read_dmae(sc, i, main_mem_width / 4); in bxe_init_hw_func()
18349 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), in bxe_init_hw_func()
18353 REG_RD(sc, main_mem_prty_clr); in bxe_init_hw_func()
18358 REG_WR8(sc, BAR_USTRORM_INTMEM + in bxe_init_hw_func()
18359 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); in bxe_init_hw_func()
18360 REG_WR8(sc, BAR_TSTRORM_INTMEM + in bxe_init_hw_func()
18361 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); in bxe_init_hw_func()
18362 REG_WR8(sc, BAR_CSTRORM_INTMEM + in bxe_init_hw_func()
18363 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); in bxe_init_hw_func()
18364 REG_WR8(sc, BAR_XSTRORM_INTMEM + in bxe_init_hw_func()
18365 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); in bxe_init_hw_func()
18368 elink_phy_probe(&sc->link_params); in bxe_init_hw_func()
18374 bxe_link_reset(struct bxe_softc *sc) in bxe_link_reset() argument
18376 if (!BXE_NOMCP(sc)) { in bxe_link_reset()
18377 bxe_acquire_phy_lock(sc); in bxe_link_reset()
18378 elink_lfa_reset(&sc->link_params, &sc->link_vars); in bxe_link_reset()
18379 bxe_release_phy_lock(sc); in bxe_link_reset()
18381 if (!CHIP_REV_IS_SLOW(sc)) { in bxe_link_reset()
18382 BLOGW(sc, "Bootcode is missing - cannot reset link\n"); in bxe_link_reset()
18388 bxe_reset_port(struct bxe_softc *sc) in bxe_reset_port() argument
18390 int port = SC_PORT(sc); in bxe_reset_port()
18393 ELINK_DEBUG_P0(sc, "bxe_reset_port called\n"); in bxe_reset_port()
18395 bxe_link_reset(sc); in bxe_reset_port()
18397 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bxe_reset_port()
18400 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); in bxe_reset_port()
18402 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bxe_reset_port()
18406 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); in bxe_reset_port()
18411 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); in bxe_reset_port()
18413 BLOGD(sc, DBG_LOAD, in bxe_reset_port()
18421 bxe_ilt_wr(struct bxe_softc *sc, in bxe_ilt_wr() argument
18428 if (CHIP_IS_E1(sc)) { in bxe_ilt_wr()
18436 REG_WR_DMAE(sc, reg, wb_write, 2); in bxe_ilt_wr()
18440 bxe_clear_func_ilt(struct bxe_softc *sc, in bxe_clear_func_ilt() argument
18445 bxe_ilt_wr(sc, i, 0); in bxe_clear_func_ilt()
18450 bxe_reset_func(struct bxe_softc *sc) in bxe_reset_func() argument
18453 int port = SC_PORT(sc); in bxe_reset_func()
18454 int func = SC_FUNC(sc); in bxe_reset_func()
18458 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); in bxe_reset_func()
18459 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); in bxe_reset_func()
18460 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); in bxe_reset_func()
18461 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); in bxe_reset_func()
18464 FOR_EACH_ETH_QUEUE(sc, i) { in bxe_reset_func()
18465 fp = &sc->fp[i]; in bxe_reset_func()
18466 REG_WR8(sc, BAR_CSTRORM_INTMEM + in bxe_reset_func()
18472 REG_WR8(sc, BAR_CSTRORM_INTMEM + in bxe_reset_func()
18477 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0); in bxe_reset_func()
18481 if (sc->devinfo.int_block == INT_BLOCK_HC) { in bxe_reset_func()
18482 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); in bxe_reset_func()
18483 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bxe_reset_func()
18485 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0); in bxe_reset_func()
18486 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0); in bxe_reset_func()
18489 if (CNIC_LOADED(sc)) { in bxe_reset_func()
18491 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bxe_reset_func()
18498 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4)) in bxe_reset_func()
18504 bxe_clear_func_ilt(sc, func); in bxe_reset_func()
18510 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) { in bxe_reset_func()
18518 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR); in bxe_reset_func()
18522 if (!CHIP_IS_E1x(sc)) { in bxe_reset_func()
18523 bxe_pf_disable(sc); in bxe_reset_func()
18526 sc->dmae_ready = 0; in bxe_reset_func()
18530 bxe_gunzip_init(struct bxe_softc *sc) in bxe_gunzip_init() argument
18536 bxe_gunzip_end(struct bxe_softc *sc) in bxe_gunzip_end() argument
18542 bxe_init_firmware(struct bxe_softc *sc) in bxe_init_firmware() argument
18544 if (CHIP_IS_E1(sc)) { in bxe_init_firmware()
18545 ecore_init_e1_firmware(sc); in bxe_init_firmware()
18546 sc->iro_array = e1_iro_arr; in bxe_init_firmware()
18547 } else if (CHIP_IS_E1H(sc)) { in bxe_init_firmware()
18548 ecore_init_e1h_firmware(sc); in bxe_init_firmware()
18549 sc->iro_array = e1h_iro_arr; in bxe_init_firmware()
18550 } else if (!CHIP_IS_E1x(sc)) { in bxe_init_firmware()
18551 ecore_init_e2_firmware(sc); in bxe_init_firmware()
18552 sc->iro_array = e2_iro_arr; in bxe_init_firmware()
18554 BLOGE(sc, "Unsupported chip revision\n"); in bxe_init_firmware()
18562 bxe_release_firmware(struct bxe_softc *sc) in bxe_release_firmware() argument
18569 ecore_gunzip(struct bxe_softc *sc, in ecore_gunzip() argument
18574 BLOGD(sc, DBG_LOAD, "ECORE_GUNZIP NOT IMPLEMENTED\n"); in ecore_gunzip()
18579 ecore_reg_wr_ind(struct bxe_softc *sc, in ecore_reg_wr_ind() argument
18583 bxe_reg_wr_ind(sc, addr, val); in ecore_reg_wr_ind()
18587 ecore_write_dmae_phys_len(struct bxe_softc *sc, in ecore_write_dmae_phys_len() argument
18592 bxe_write_dmae_phys_len(sc, phys_addr, addr, len); in ecore_write_dmae_phys_len()
18596 ecore_storm_memset_struct(struct bxe_softc *sc, in ecore_storm_memset_struct() argument
18603 REG_WR(sc, addr + (i * 4), data[i]); in ecore_storm_memset_struct()
18626 #define BXE_PATH(sc) (CHIP_IS_E1x(sc) ? 0 : (sc->pcie_func & 1)) argument
18642 bxe_get_preset_regs_len(struct bxe_softc *sc, uint32_t preset) in bxe_get_preset_regs_len() argument
18644 if (CHIP_IS_E1(sc)) in bxe_get_preset_regs_len()
18646 else if (CHIP_IS_E1H(sc)) in bxe_get_preset_regs_len()
18648 else if (CHIP_IS_E2(sc)) in bxe_get_preset_regs_len()
18650 else if (CHIP_IS_E3A0(sc)) in bxe_get_preset_regs_len()
18652 else if (CHIP_IS_E3B0(sc)) in bxe_get_preset_regs_len()
18659 bxe_get_total_regs_len32(struct bxe_softc *sc) in bxe_get_total_regs_len32() argument
18667 regdump_len32 += bxe_get_preset_regs_len(sc, preset_idx); in bxe_get_total_regs_len32()
18674 __bxe_get_page_addr_ar(struct bxe_softc *sc) in __bxe_get_page_addr_ar() argument
18676 if (CHIP_IS_E2(sc)) in __bxe_get_page_addr_ar()
18678 else if (CHIP_IS_E3(sc)) in __bxe_get_page_addr_ar()
18685 __bxe_get_page_reg_num(struct bxe_softc *sc) in __bxe_get_page_reg_num() argument
18687 if (CHIP_IS_E2(sc)) in __bxe_get_page_reg_num()
18689 else if (CHIP_IS_E3(sc)) in __bxe_get_page_reg_num()
18696 __bxe_get_page_write_ar(struct bxe_softc *sc) in __bxe_get_page_write_ar() argument
18698 if (CHIP_IS_E2(sc)) in __bxe_get_page_write_ar()
18700 else if (CHIP_IS_E3(sc)) in __bxe_get_page_write_ar()
18707 __bxe_get_page_write_num(struct bxe_softc *sc) in __bxe_get_page_write_num() argument
18709 if (CHIP_IS_E2(sc)) in __bxe_get_page_write_num()
18711 else if (CHIP_IS_E3(sc)) in __bxe_get_page_write_num()
18718 __bxe_get_page_read_ar(struct bxe_softc *sc) in __bxe_get_page_read_ar() argument
18720 if (CHIP_IS_E2(sc)) in __bxe_get_page_read_ar()
18722 else if (CHIP_IS_E3(sc)) in __bxe_get_page_read_ar()
18729 __bxe_get_page_read_num(struct bxe_softc *sc) in __bxe_get_page_read_num() argument
18731 if (CHIP_IS_E2(sc)) in __bxe_get_page_read_num()
18733 else if (CHIP_IS_E3(sc)) in __bxe_get_page_read_num()
18740 bxe_is_reg_in_chip(struct bxe_softc *sc, const struct reg_addr *reg_info) in bxe_is_reg_in_chip() argument
18742 if (CHIP_IS_E1(sc)) in bxe_is_reg_in_chip()
18744 else if (CHIP_IS_E1H(sc)) in bxe_is_reg_in_chip()
18746 else if (CHIP_IS_E2(sc)) in bxe_is_reg_in_chip()
18748 else if (CHIP_IS_E3A0(sc)) in bxe_is_reg_in_chip()
18750 else if (CHIP_IS_E3B0(sc)) in bxe_is_reg_in_chip()
18757 bxe_is_wreg_in_chip(struct bxe_softc *sc, const struct wreg_addr *wreg_info) in bxe_is_wreg_in_chip() argument
18759 if (CHIP_IS_E1(sc)) in bxe_is_wreg_in_chip()
18761 else if (CHIP_IS_E1H(sc)) in bxe_is_wreg_in_chip()
18763 else if (CHIP_IS_E2(sc)) in bxe_is_wreg_in_chip()
18765 else if (CHIP_IS_E3A0(sc)) in bxe_is_wreg_in_chip()
18767 else if (CHIP_IS_E3B0(sc)) in bxe_is_wreg_in_chip()
18785 bxe_read_pages_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset) in bxe_read_pages_regs() argument
18790 const uint32_t *page_addr = __bxe_get_page_addr_ar(sc); in bxe_read_pages_regs()
18792 int num_pages = __bxe_get_page_reg_num(sc); in bxe_read_pages_regs()
18794 const uint32_t *write_addr = __bxe_get_page_write_ar(sc); in bxe_read_pages_regs()
18796 int write_num = __bxe_get_page_write_num(sc); in bxe_read_pages_regs()
18798 const struct reg_addr *read_addr = __bxe_get_page_read_ar(sc); in bxe_read_pages_regs()
18800 int read_num = __bxe_get_page_read_num(sc); in bxe_read_pages_regs()
18805 REG_WR(sc, write_addr[j], page_addr[i]); in bxe_read_pages_regs()
18812 *p++ = REG_RD(sc, addr); in bxe_read_pages_regs()
18823 bxe_get_preset_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset) in bxe_get_preset_regs() argument
18828 if (CHIP_IS_E1(sc)) in bxe_get_preset_regs()
18830 else if (CHIP_IS_E1H(sc)) in bxe_get_preset_regs()
18832 else if (CHIP_IS_E2(sc)) in bxe_get_preset_regs()
18834 else if (CHIP_IS_E3A0(sc)) in bxe_get_preset_regs()
18836 else if (CHIP_IS_E3B0(sc)) in bxe_get_preset_regs()
18843 if (bxe_is_reg_in_chip(sc, &idle_reg_addrs[i]) && in bxe_get_preset_regs()
18846 *p++ = REG_RD(sc, idle_reg_addrs[i].addr + j*4); in bxe_get_preset_regs()
18852 if (bxe_is_reg_in_chip(sc, ®_addrs[i]) && in bxe_get_preset_regs()
18855 *p++ = REG_RD(sc, reg_addrs[i].addr + j*4); in bxe_get_preset_regs()
18860 if (bxe_is_wreg_in_chip(sc, wreg_addr_p) && in bxe_get_preset_regs()
18863 *p++ = REG_RD(sc, wreg_addr_p->addr + i*4); in bxe_get_preset_regs()
18870 *p++ = REG_RD(sc, addr + j*4); in bxe_get_preset_regs()
18876 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) { in bxe_get_preset_regs()
18878 bxe_read_pages_regs(sc, p, preset); in bxe_get_preset_regs()
18885 bxe_grc_dump(struct bxe_softc *sc) in bxe_grc_dump() argument
18896 struct ecore_ilt *ilt = SC_ILT(sc); in bxe_grc_dump()
18902 if (sc->grcdump_done || sc->grcdump_started) in bxe_grc_dump()
18905 sc->grcdump_started = 1; in bxe_grc_dump()
18906 BLOGI(sc, "Started collecting grcdump\n"); in bxe_grc_dump()
18908 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) + in bxe_grc_dump()
18911 sc->grc_dump = malloc(grc_dump_size, M_DEVBUF, M_NOWAIT); in bxe_grc_dump()
18913 if (sc->grc_dump == NULL) { in bxe_grc_dump()
18914 BLOGW(sc, "Unable to allocate memory for grcdump collection\n"); in bxe_grc_dump()
18926 bxe_pretend_func(sc, 0); in bxe_grc_dump()
18928 ecore_disable_blocks_parity(sc); in bxe_grc_dump()
18931 bxe_pretend_func(sc, 1); in bxe_grc_dump()
18932 ecore_disable_blocks_parity(sc); in bxe_grc_dump()
18935 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); in bxe_grc_dump()
18937 buf = sc->grc_dump; in bxe_grc_dump()
18938 d_hdr = sc->grc_dump; in bxe_grc_dump()
18944 if (CHIP_IS_E1(sc)) { in bxe_grc_dump()
18946 } else if (CHIP_IS_E1H(sc)) { in bxe_grc_dump()
18948 } else if (CHIP_IS_E2(sc)) { in bxe_grc_dump()
18950 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0); in bxe_grc_dump()
18951 } else if (CHIP_IS_E3A0(sc)) { in bxe_grc_dump()
18953 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0); in bxe_grc_dump()
18954 } else if (CHIP_IS_E3B0(sc)) { in bxe_grc_dump()
18956 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0); in bxe_grc_dump()
18968 rval = bxe_get_preset_regs(sc, (uint32_t *)buf, preset_idx); in bxe_grc_dump()
18973 size = bxe_get_preset_regs_len(sc, preset_idx) * (sizeof (uint32_t)); in bxe_grc_dump()
18978 bxe_pretend_func(sc, 0); in bxe_grc_dump()
18979 ecore_clear_blocks_parity(sc); in bxe_grc_dump()
18980 ecore_enable_blocks_parity(sc); in bxe_grc_dump()
18982 bxe_pretend_func(sc, 1); in bxe_grc_dump()
18983 ecore_clear_blocks_parity(sc); in bxe_grc_dump()
18984 ecore_enable_blocks_parity(sc); in bxe_grc_dump()
18987 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); in bxe_grc_dump()
18991 if(sc->state == BXE_STATE_OPEN) { in bxe_grc_dump()
18992 if(sc->fw_stats_req != NULL) { in bxe_grc_dump()
18993 BLOGI(sc, "fw stats start_paddr %#jx end_paddr %#jx vaddr %p size 0x%x\n", in bxe_grc_dump()
18994 (uintmax_t)sc->fw_stats_req_mapping, in bxe_grc_dump()
18995 (uintmax_t)sc->fw_stats_data_mapping, in bxe_grc_dump()
18996 sc->fw_stats_req, (sc->fw_stats_req_size + sc->fw_stats_data_size)); in bxe_grc_dump()
18998 if(sc->def_sb != NULL) { in bxe_grc_dump()
18999 BLOGI(sc, "def_status_block paddr %p vaddr %p size 0x%zx\n", in bxe_grc_dump()
19000 (void *)sc->def_sb_dma.paddr, sc->def_sb, in bxe_grc_dump()
19003 if(sc->eq_dma.vaddr != NULL) { in bxe_grc_dump()
19004 BLOGI(sc, "event_queue paddr %#jx vaddr %p size 0x%x\n", in bxe_grc_dump()
19005 (uintmax_t)sc->eq_dma.paddr, sc->eq_dma.vaddr, BCM_PAGE_SIZE); in bxe_grc_dump()
19007 if(sc->sp_dma.vaddr != NULL) { in bxe_grc_dump()
19008 BLOGI(sc, "slow path paddr %#jx vaddr %p size 0x%zx\n", in bxe_grc_dump()
19009 (uintmax_t)sc->sp_dma.paddr, sc->sp_dma.vaddr, in bxe_grc_dump()
19012 if(sc->spq_dma.vaddr != NULL) { in bxe_grc_dump()
19013 BLOGI(sc, "slow path queue paddr %#jx vaddr %p size 0x%x\n", in bxe_grc_dump()
19014 (uintmax_t)sc->spq_dma.paddr, sc->spq_dma.vaddr, BCM_PAGE_SIZE); in bxe_grc_dump()
19016 if(sc->gz_buf_dma.vaddr != NULL) { in bxe_grc_dump()
19017 BLOGI(sc, "fw_buf paddr %#jx vaddr %p size 0x%x\n", in bxe_grc_dump()
19018 (uintmax_t)sc->gz_buf_dma.paddr, sc->gz_buf_dma.vaddr, in bxe_grc_dump()
19021 for (i = 0; i < sc->num_queues; i++) { in bxe_grc_dump()
19022 fp = &sc->fp[i]; in bxe_grc_dump()
19027 BLOGI(sc, "FP status block fp %d paddr %#jx vaddr %p size 0x%zx\n", i, in bxe_grc_dump()
19030 BLOGI(sc, "TX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i, in bxe_grc_dump()
19033 BLOGI(sc, "RX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i, in bxe_grc_dump()
19036 BLOGI(sc, "RX RCQ CHAIN fp %d paddr %#jx vaddr %p size 0x%zx\n", i, in bxe_grc_dump()
19039 BLOGI(sc, "RX SGE CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i, in bxe_grc_dump()
19048 BLOGI(sc, "ECORE_ILT paddr %#jx vaddr %p size 0x%x\n", in bxe_grc_dump()
19059 reg_val = REG_RD(sc, reg_addr); in bxe_grc_dump()
19060 BLOGI(sc, "DMAE_REG_CMD_MEM i=%d reg_addr 0x%x reg_val 0x%08x\n",i, in bxe_grc_dump()
19065 BLOGI(sc, "Collection of grcdump done\n"); in bxe_grc_dump()
19066 sc->grcdump_done = 1; in bxe_grc_dump()
19071 bxe_add_cdev(struct bxe_softc *sc) in bxe_add_cdev() argument
19073 sc->eeprom = malloc(BXE_EEPROM_MAX_DATA_LEN, M_DEVBUF, M_NOWAIT); in bxe_add_cdev()
19075 if (sc->eeprom == NULL) { in bxe_add_cdev()
19076 BLOGW(sc, "Unable to alloc for eeprom size buffer\n"); in bxe_add_cdev()
19080 sc->ioctl_dev = make_dev(&bxe_cdevsw, in bxe_add_cdev()
19081 if_getdunit(sc->ifp), in bxe_add_cdev()
19086 if_name(sc->ifp)); in bxe_add_cdev()
19088 if (sc->ioctl_dev == NULL) { in bxe_add_cdev()
19089 free(sc->eeprom, M_DEVBUF); in bxe_add_cdev()
19090 sc->eeprom = NULL; in bxe_add_cdev()
19094 sc->ioctl_dev->si_drv1 = sc; in bxe_add_cdev()
19100 bxe_del_cdev(struct bxe_softc *sc) in bxe_del_cdev() argument
19102 if (sc->ioctl_dev != NULL) in bxe_del_cdev()
19103 destroy_dev(sc->ioctl_dev); in bxe_del_cdev()
19105 if (sc->eeprom != NULL) { in bxe_del_cdev()
19106 free(sc->eeprom, M_DEVBUF); in bxe_del_cdev()
19107 sc->eeprom = NULL; in bxe_del_cdev()
19109 sc->ioctl_dev = NULL; in bxe_del_cdev()
19114 static bool bxe_is_nvram_accessible(struct bxe_softc *sc) in bxe_is_nvram_accessible() argument
19117 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0) in bxe_is_nvram_accessible()
19125 bxe_wr_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len) in bxe_wr_eeprom() argument
19129 if(!bxe_is_nvram_accessible(sc)) { in bxe_wr_eeprom()
19130 BLOGW(sc, "Cannot access eeprom when interface is down\n"); in bxe_wr_eeprom()
19133 rval = bxe_nvram_write(sc, offset, (uint8_t *)data, len); in bxe_wr_eeprom()
19140 bxe_rd_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len) in bxe_rd_eeprom() argument
19144 if(!bxe_is_nvram_accessible(sc)) { in bxe_rd_eeprom()
19145 BLOGW(sc, "Cannot access eeprom when interface is down\n"); in bxe_rd_eeprom()
19148 rval = bxe_nvram_read(sc, offset, (uint8_t *)data, len); in bxe_rd_eeprom()
19154 bxe_eeprom_rd_wr(struct bxe_softc *sc, bxe_eeprom_t *eeprom) in bxe_eeprom_rd_wr() argument
19162 rval = copyin(eeprom->eeprom_data, sc->eeprom, in bxe_eeprom_rd_wr()
19168 rval = bxe_wr_eeprom(sc, sc->eeprom, eeprom->eeprom_offset, in bxe_eeprom_rd_wr()
19174 rval = bxe_rd_eeprom(sc, sc->eeprom, eeprom->eeprom_offset, in bxe_eeprom_rd_wr()
19181 rval = copyout(sc->eeprom, eeprom->eeprom_data, in bxe_eeprom_rd_wr()
19191 BLOGW(sc, "ioctl cmd %d failed rval %d\n", eeprom->eeprom_cmd, rval); in bxe_eeprom_rd_wr()
19198 bxe_get_settings(struct bxe_softc *sc, bxe_dev_setting_t *dev_p) in bxe_get_settings() argument
19201 int port = SC_PORT(sc); in bxe_get_settings()
19202 int cfg_idx = bxe_get_link_cfg_idx(sc); in bxe_get_settings()
19204 dev_p->supported = sc->port.supported[cfg_idx] | in bxe_get_settings()
19205 (sc->port.supported[cfg_idx ^ 1] & in bxe_get_settings()
19207 dev_p->advertising = sc->port.advertising[cfg_idx]; in bxe_get_settings()
19208 if(sc->link_params.phy[bxe_get_cur_phy_idx(sc)].media_type == in bxe_get_settings()
19213 if ((sc->state == BXE_STATE_OPEN) && sc->link_vars.link_up && in bxe_get_settings()
19214 !(sc->flags & BXE_MF_FUNC_DIS)) { in bxe_get_settings()
19215 dev_p->duplex = sc->link_vars.duplex; in bxe_get_settings()
19216 if (IS_MF(sc) && !BXE_NOMCP(sc)) in bxe_get_settings()
19217 dev_p->speed = bxe_get_mf_speed(sc); in bxe_get_settings()
19219 dev_p->speed = sc->link_vars.line_speed; in bxe_get_settings()
19225 dev_p->port = bxe_media_detect(sc); in bxe_get_settings()
19227 ext_phy_config = SHMEM_RD(sc, in bxe_get_settings()
19231 dev_p->phy_address = sc->port.phy_addr; in bxe_get_settings()
19240 if(sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG) in bxe_get_settings()
19253 struct bxe_softc *sc; in bxe_eioctl() local
19266 if ((sc = (struct bxe_softc *)dev->si_drv1) == NULL) in bxe_eioctl()
19274 dump->pci_func = sc->pcie_func; in bxe_eioctl()
19276 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) + in bxe_eioctl()
19282 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) + in bxe_eioctl()
19284 if ((!sc->trigger_grcdump) || (dump->grcdump == NULL) || in bxe_eioctl()
19290 if((sc->trigger_grcdump) && (!sc->grcdump_done) && in bxe_eioctl()
19291 (!sc->grcdump_started)) { in bxe_eioctl()
19292 rval = bxe_grc_dump(sc); in bxe_eioctl()
19295 if((!rval) && (sc->grcdump_done) && (sc->grcdump_started) && in bxe_eioctl()
19296 (sc->grc_dump != NULL)) { in bxe_eioctl()
19298 rval = copyout(sc->grc_dump, dump->grcdump, grc_dump_size); in bxe_eioctl()
19299 free(sc->grc_dump, M_DEVBUF); in bxe_eioctl()
19300 sc->grc_dump = NULL; in bxe_eioctl()
19301 sc->grcdump_started = 0; in bxe_eioctl()
19302 sc->grcdump_done = 0; in bxe_eioctl()
19313 sc->devinfo.bc_ver_str); in bxe_eioctl()
19315 "%s", sc->fw_ver_str); in bxe_eioctl()
19316 drv_infop->eeprom_dump_len = sc->devinfo.flash_size; in bxe_eioctl()
19318 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) in bxe_eioctl()
19321 sc->pcie_bus, sc->pcie_device, sc->pcie_func); in bxe_eioctl()
19326 bxe_get_settings(sc, &dev_set); in bxe_eioctl()
19342 if((!sc->grcdump_done) && (!sc->grcdump_started)) { in bxe_eioctl()
19343 bxe_grc_dump(sc); in bxe_eioctl()
19345 if((sc->grcdump_done) && (sc->grcdump_started) && in bxe_eioctl()
19346 (sc->grc_dump != NULL)) { in bxe_eioctl()
19347 rval = copyout(sc->grc_dump, reg_p->reg_buf, grc_dump_size); in bxe_eioctl()
19348 free(sc->grc_dump, M_DEVBUF); in bxe_eioctl()
19349 sc->grc_dump = NULL; in bxe_eioctl()
19350 sc->grcdump_started = 0; in bxe_eioctl()
19351 sc->grcdump_done = 0; in bxe_eioctl()
19360 reg_rdw_p->reg_val = REG_RD(sc, reg_rdw_p->reg_id); in bxe_eioctl()
19364 REG_WR(sc, reg_rdw_p->reg_id, reg_rdw_p->reg_val); in bxe_eioctl()
19372 cfg_rdw_p->cfg_val = pci_read_config(sc->dev, cfg_rdw_p->cfg_id, in bxe_eioctl()
19376 pci_write_config(sc->dev, cfg_rdw_p->cfg_id, cfg_rdw_p->cfg_val, in bxe_eioctl()
19379 BLOGW(sc, "BXE_RDW_PCICFG ioctl wrong cmd passed\n"); in bxe_eioctl()
19385 snprintf(mac_addr_p->mac_addr_str, sizeof(sc->mac_addr_str), "%s", in bxe_eioctl()
19386 sc->mac_addr_str); in bxe_eioctl()
19390 rval = bxe_eeprom_rd_wr(sc, (bxe_eeprom_t *)data); in bxe_eioctl()
19405 struct bxe_softc *sc; in bxe_debugnet_init() local
19407 sc = if_getsoftc(ifp); in bxe_debugnet_init()
19408 BXE_CORE_LOCK(sc); in bxe_debugnet_init()
19409 *nrxr = sc->num_queues; in bxe_debugnet_init()
19411 *clsize = sc->fp[0].mbuf_alloc_size; in bxe_debugnet_init()
19412 BXE_CORE_UNLOCK(sc); in bxe_debugnet_init()
19423 struct bxe_softc *sc; in bxe_debugnet_transmit() local
19426 sc = if_getsoftc(ifp); in bxe_debugnet_transmit()
19428 IFF_DRV_RUNNING || !sc->link_vars.link_up) in bxe_debugnet_transmit()
19431 error = bxe_tx_encap(&sc->fp[0], &m); in bxe_debugnet_transmit()
19440 struct bxe_softc *sc; in bxe_debugnet_poll() local
19443 sc = if_getsoftc(ifp); in bxe_debugnet_poll()
19445 !sc->link_vars.link_up) in bxe_debugnet_poll()
19448 for (i = 0; i < sc->num_queues; i++) in bxe_debugnet_poll()
19449 (void)bxe_rxeof(sc, &sc->fp[i]); in bxe_debugnet_poll()
19450 (void)bxe_txeof(sc, &sc->fp[0]); in bxe_debugnet_poll()