Lines Matching refs:dmae

1500               struct dmae_cmd *dmae,
1508         REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i));
1564                         struct dmae_cmd *dmae,
1568     memset(dmae, 0, sizeof(struct dmae_cmd));
1571     dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type,
1575     dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
1576     dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
1577     dmae->comp_val     = DMAE_COMP_VAL;
1583                          struct dmae_cmd *dmae)
1594     bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
1629     struct dmae_cmd dmae;
1648     bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
1651     dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
1652     dmae.src_addr_hi = 0;
1653     dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
1654     dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
1655     dmae.len         = len32;
1658     if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1669     struct dmae_cmd dmae;
1685     bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
1688     dmae.src_addr_lo = U64_LO(dma_addr);
1689     dmae.src_addr_hi = U64_HI(dma_addr);
1690     dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
1691     dmae.dst_addr_hi = 0;
1692     dmae.len         = len32;
1695     if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
10961      * respond. The write queue in PGLUE would stuck, dmae commands
15458              * use rd/wr since we cannot use dmae. This is safe
17119  *          dmae-operations (writing to pram for example.)
17509      * common phase, we need to enable it here before any dmae access are