Lines Matching refs:REG_RD
1027 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_acquire_hw_lock()
1037 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_acquire_hw_lock()
1073 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_release_hw_lock()
1129 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); in bxe_acquire_nvram_lock()
1165 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); in bxe_release_nvram_lock()
1191 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in bxe_enable_nvram_access()
1203 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); in bxe_disable_nvram_access()
1244 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); in bxe_nvram_read_dword()
1247 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ); in bxe_nvram_read_dword()
1359 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); in bxe_nvram_write_dword()
1641 REG_RD(sc, (src_addr + (i * 4))); in bxe_read_dmae()
1809 return (REG_RD(sc, reg_addr)); in elink_cb_reg_read()
1869 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT); in bxe_set_spio()
1908 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && in bxe_gpio_read()
1909 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); in bxe_gpio_read()
1923 gpio_reg = REG_RD(sc, MISC_REG_GPIO); in bxe_gpio_read()
1936 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && in bxe_gpio_write()
1937 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); in bxe_gpio_write()
1953 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); in bxe_gpio_write()
2004 gpio_reg = REG_RD(sc, MISC_REG_GPIO); in bxe_gpio_mult_write()
2048 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && in bxe_gpio_int_write()
2049 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); in bxe_gpio_int_write()
2065 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT); in bxe_gpio_int_write()
4136 val = REG_RD(sc, addr); in bxe_disable_close_the_gate()
4140 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK); in bxe_disable_close_the_gate()
6607 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_set_reset_global()
6618 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_clear_reset_global()
6627 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_reset_is_global()
6642 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_set_reset_done()
6660 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_set_reset_in_progress()
6673 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_reset_is_done()
6690 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_get_load_status()
6715 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_set_pf_load()
6747 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); in bxe_clear_pf_load()
6827 loaded_fw = REG_RD(sc, XSEM_REG_PRAM); in bxe_nic_load_analyze_req()
6923 val = REG_RD(sc, GRCBASE_MCP + 0x9c); in bxe_acquire_alr()
7066 aeu_mask = REG_RD(sc, aeu_addr); in bxe_attn_int_asserted()
7088 nig_mask = REG_RD(sc, nig_int_mask_addr); in bxe_attn_int_asserted()
7166 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS); in bxe_attn_int_asserted()
7532 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); in bxe_chk_parity_attn()
7533 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); in bxe_chk_parity_attn()
7534 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); in bxe_chk_parity_attn()
7535 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); in bxe_chk_parity_attn()
7541 attn.sig[3] &= ((REG_RD(sc, (!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 in bxe_chk_parity_attn()
7548 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); in bxe_chk_parity_attn()
7561 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); in bxe_attn_int_deasserted4()
7585 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR); in bxe_attn_int_deasserted4()
7825 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i)); in bxe_mc_assert()
7826 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4); in bxe_mc_assert()
7827 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8); in bxe_mc_assert()
7828 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12); in bxe_mc_assert()
7848 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i)); in bxe_mc_assert()
7849 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4); in bxe_mc_assert()
7850 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8); in bxe_mc_assert()
7851 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12); in bxe_mc_assert()
7871 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i)); in bxe_mc_assert()
7872 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4); in bxe_mc_assert()
7873 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8); in bxe_mc_assert()
7874 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12); in bxe_mc_assert()
7894 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i)); in bxe_mc_assert()
7895 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4); in bxe_mc_assert()
7896 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8); in bxe_mc_assert()
7897 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12); in bxe_mc_assert()
7992 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN); in bxe_attn_int_deasserted3()
7996 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN); in bxe_attn_int_deasserted3()
8014 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR); in bxe_attn_int_deasserted2()
8024 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0); in bxe_attn_int_deasserted2()
8033 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1); in bxe_attn_int_deasserted2()
8047 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0); in bxe_attn_int_deasserted2()
8048 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1); in bxe_attn_int_deasserted2()
8049 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1); in bxe_attn_int_deasserted2()
8050 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0); in bxe_attn_int_deasserted2()
8061 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0); in bxe_attn_int_deasserted2()
8089 val = REG_RD(sc, reg_offset); in bxe_attn_int_deasserted2()
8116 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR); in bxe_attn_int_deasserted1()
8129 val = REG_RD(sc, reg_offset); in bxe_attn_int_deasserted1()
8158 val = REG_RD(sc, reg_offset); in bxe_attn_int_deasserted0()
8176 val = REG_RD(sc, reg_offset); in bxe_attn_int_deasserted0()
8224 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); in bxe_attn_int_deasserted()
8225 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); in bxe_attn_int_deasserted()
8226 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); in bxe_attn_int_deasserted()
8227 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); in bxe_attn_int_deasserted()
8229 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); in bxe_attn_int_deasserted()
8279 aeu_mask = REG_RD(sc, reg_addr); in bxe_attn_int_deasserted()
9812 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index))); in bxe_init_def_sb()
9822 REG_RD(sc, (reg_offset_en5 + (0x4 * index))); in bxe_init_def_sb()
10226 uint32_t val = REG_RD(sc, addr); in bxe_hc_int_enable()
10302 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); in bxe_igu_int_enable()
10372 uint32_t val = REG_RD(sc, addr); in bxe_hc_int_disable()
10402 if (REG_RD(sc, addr) != val) { in bxe_hc_int_disable()
10410 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); in bxe_igu_int_disable()
10422 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) { in bxe_igu_int_disable()
10478 REG_RD(sc, in bxe_nic_init()
10658 lock_status = REG_RD(sc, hw_lock_control_reg); in bxe_trylock_hw_lock()
10715 val = REG_RD(sc, HC_REG_CONFIG_1); in bxe_set_234_gates()
10720 val = REG_RD(sc, HC_REG_CONFIG_0); in bxe_set_234_gates()
10726 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION); in bxe_set_234_gates()
10748 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS); in bxe_er_poll_igu_vq()
10802 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); in bxe_reset_mcp_prep()
10836 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); in bxe_init_shmem()
10998 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT); in bxe_process_kill()
10999 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT); in bxe_process_kill()
11000 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0); in bxe_process_kill()
11001 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1); in bxe_process_kill()
11002 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2); in bxe_process_kill()
11004 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32); in bxe_process_kill()
13111 val = REG_RD(sc, BAR_ME_REGISTER); in bxe_get_function_num()
13208 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1; in bxe_probe_pci_caps()
13923 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); in bxe_get_igu_cam_info()
13979 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) | in bxe_get_device_info()
13980 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) | in bxe_get_device_info()
13981 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) | in bxe_get_device_info()
13982 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0)); in bxe_get_device_info()
13985 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { in bxe_get_device_info()
14004 val = (REG_RD(sc, 0x2874) & 0x55); in bxe_get_device_info()
14023 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR); in bxe_get_device_info()
14027 val = REG_RD(sc, MISC_REG_PORT4MODE_EN); in bxe_get_device_info()
14042 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); in bxe_get_device_info()
14044 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 : in bxe_get_device_info()
14105 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4); in bxe_get_device_info()
14141 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION); in bxe_get_device_info()
14152 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) { in bxe_get_device_info()
14157 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) { in bxe_get_device_info()
14254 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR); in bxe_link_settings_supported()
14259 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); in bxe_link_settings_supported()
14263 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); in bxe_link_settings_supported()
15260 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS); in bxe_prev_interrupted_dmae()
15445 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2); in bxe_prev_unload_close_mac()
15448 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); in bxe_prev_unload_close_mac()
15463 wb_data[0] = REG_RD(sc, base_addr + offset); in bxe_prev_unload_close_mac()
15464 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4); in bxe_prev_unload_close_mac()
15475 vals->emac_val = REG_RD(sc, vals->emac_addr); in bxe_prev_unload_close_mac()
15482 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI); in bxe_prev_unload_close_mac()
15486 vals->xmac_val = REG_RD(sc, vals->xmac_addr); in bxe_prev_unload_close_mac()
15496 vals->umac_val = REG_RD(sc, vals->umac_addr); in bxe_prev_unload_close_mac()
15518 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port)); in bxe_prev_unload_undi_inc()
15553 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1); in bxe_prev_unload_common()
15568 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST); in bxe_prev_unload_common()
15575 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0); in bxe_prev_unload_common()
15580 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); in bxe_prev_unload_common()
15584 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); in bxe_prev_unload_common()
15699 hw_lock_val = (REG_RD(sc, hw_lock_reg)); in bxe_prev_unload()
15712 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) { in bxe_prev_unload()
16540 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) { in bxe_igu_clear_sb_gen()
16544 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) { in bxe_igu_clear_sb_gen()
16615 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); in bxe_pf_disable()
16673 REG_RD(sc, pretend_reg); in bxe_pretend_func()
16761 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); in bxe_int_mem_test()
16816 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); in bxe_int_mem_test()
16828 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); in bxe_int_mem_test()
16835 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO); in bxe_int_mem_test()
16838 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY); in bxe_int_mem_test()
16903 val = REG_RD(sc, MISC_REG_SPIO_INT); in bxe_setup_fan_failure_detection()
16908 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN); in bxe_setup_fan_failure_detection()
17079 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE); in bxe_init_hw_common()
17085 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE); in bxe_init_hw_common()
17208 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE); in bxe_init_hw_common()
17451 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0); in bxe_init_hw_common()
17698 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN); in bxe_init_hw_port()
17702 val = REG_RD(sc, reg_addr); in bxe_init_hw_port()
17719 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) { in bxe_flr_clnup_reg_poll()
17829 if (REG_RD(sc, comp_addr)) { in bxe_send_final_clnup()
17845 (REG_RD(sc, comp_addr))); in bxe_send_final_clnup()
17864 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed); in bxe_pbf_pN_buf_flushed()
17865 crd = crd_start = REG_RD(sc, regs->crd); in bxe_pbf_pN_buf_flushed()
17866 init_crd = REG_RD(sc, regs->init_crd); in bxe_pbf_pN_buf_flushed()
17877 crd = REG_RD(sc, regs->crd); in bxe_pbf_pN_buf_flushed()
17878 crd_freed = REG_RD(sc, regs->crd_freed); in bxe_pbf_pN_buf_flushed()
17899 occup = to_free = REG_RD(sc, regs->lines_occup); in bxe_pbf_pN_cmd_flushed()
17900 freed = freed_start = REG_RD(sc, regs->lines_freed); in bxe_pbf_pN_cmd_flushed()
17909 occup = REG_RD(sc, regs->lines_occup); in bxe_pbf_pN_cmd_flushed()
17910 freed = REG_RD(sc, regs->lines_freed); in bxe_pbf_pN_cmd_flushed()
17995 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF); in bxe_hw_enable_status()
17998 val = REG_RD(sc, PBF_REG_DISABLE_PF); in bxe_hw_enable_status()
18001 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN); in bxe_hw_enable_status()
18004 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN); in bxe_hw_enable_status()
18007 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK); in bxe_hw_enable_status()
18010 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); in bxe_hw_enable_status()
18013 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); in bxe_hw_enable_status()
18016 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); in bxe_hw_enable_status()
18096 val = REG_RD(sc, addr); in bxe_init_hw_func()
18337 val = REG_RD(sc, main_mem_prty_clr); in bxe_init_hw_func()
18353 REG_RD(sc, main_mem_prty_clr); in bxe_init_hw_func()
18411 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); in bxe_reset_port()
18498 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4)) in bxe_reset_func()
18812 *p++ = REG_RD(sc, addr); in bxe_read_pages_regs()
18846 *p++ = REG_RD(sc, idle_reg_addrs[i].addr + j*4); in bxe_get_preset_regs()
18855 *p++ = REG_RD(sc, reg_addrs[i].addr + j*4); in bxe_get_preset_regs()
18863 *p++ = REG_RD(sc, wreg_addr_p->addr + i*4); in bxe_get_preset_regs()
18870 *p++ = REG_RD(sc, addr + j*4); in bxe_get_preset_regs()
19059 reg_val = REG_RD(sc, reg_addr); in bxe_grc_dump()
19360 reg_rdw_p->reg_val = REG_RD(sc, reg_rdw_p->reg_id); in bxe_eioctl()