Lines Matching +full:0 +full:x49c
36 #define BWN_IOCTL_PHYCLOCK_ENABLE 0x0004
37 #define BWN_IOCTL_PHYRESET 0x0008
38 #define BWN_IOCTL_MACPHYCLKEN 0x0010 /* MAC PHY Clock Control Enable (rev >= 5) */
39 #define BWN_IOCTL_PLLREFSEL 0x0020 /* PLL Frequency Reference Select (rev >= 5) */
41 #define BWN_IOCTL_PHY_BANDWIDTH 0x00C0
42 #define BWN_IOCTL_PHY_BANDWIDTH_10MHZ 0x0000
43 #define BWN_IOCTL_PHY_BANDWIDTH_20MHZ 0x0040
44 #define BWN_IOCTL_PHY_BANDWIDTH_40MHZ 0x0080
45 #define BWN_IOCTL_SUPPORT_G 0x2000
48 #define BWN_IOST_HAVE_2GHZ 0x0001
49 #define BWN_IOST_HAVE_5GHZ 0x0002
50 #define BWN_IOST_DUALPHY 0x0008
52 #define BWN_PHYTYPE_A 0x00
53 #define BWN_PHYTYPE_B 0x01
54 #define BWN_PHYTYPE_G 0x02
55 #define BWN_PHYTYPE_N 0x04
56 #define BWN_PHYTYPE_LP 0x05
57 #define BWN_PHYTYPE_SSLPN 0x06
58 #define BWN_PHYTYPE_HT 0x07
59 #define BWN_PHYTYPE_LCN 0x08
60 #define BWN_PHYTYPE_LCNXN 0x09
61 #define BWN_PHYTYPE_LCN40 0x0a
62 #define BWN_PHYTYPE_AC 0x0b
64 #define BWN_DMA0_REASON 0x20
65 #define BWN_DMA0_INTR_MASK 0x24
66 #define BWN_DMA1_REASON 0x28
67 #define BWN_DMA1_INTR_MASK 0x2c
68 #define BWN_DMA2_REASON 0x30
69 #define BWN_DMA2_INTR_MASK 0x34
70 #define BWN_DMA3_REASON 0x38
71 #define BWN_DMA3_INTR_MASK 0x3c
72 #define BWN_DMA4_REASON 0x40
73 #define BWN_DMA4_INTR_MASK 0x44
74 #define BWN_DMA5_INTR_MASK 0x4c
76 #define BWN_MACCTL 0x120
77 #define BWN_MACCTL_ON 0x00000001
78 #define BWN_MACCTL_MCODE_RUN 0x00000002
79 #define BWN_MACCTL_MCODE_JMP0 0x00000004
80 #define BWN_MACCTL_SHM_ON 0x00000100
81 #define BWN_MACCTL_IHR_ON 0x00000400
82 #define BWN_MACCTL_GPOUT_MASK 0x0000c000
83 #define BWN_MACCTL_BIGENDIAN 0x00010000
84 #define BWN_MACCTL_STA 0x00020000
85 #define BWN_MACCTL_HOSTAP 0x00040000
86 #define BWN_MACCTL_RADIO_LOCK 0x00080000
87 #define BWN_MACCTL_BEACON_PROMISC 0x00100000
88 #define BWN_MACCTL_PASS_BADPLCP 0x00200000
89 #define BWN_MACCTL_PHY_LOCK 0x00200000 /* PHY-N? */
90 #define BWN_MACCTL_PASS_CTL 0x00400000
91 #define BWN_MACCTL_PASS_BADFCS 0x00800000
92 #define BWN_MACCTL_PROMISC 0x01000000
93 #define BWN_MACCTL_HWPS 0x02000000
94 #define BWN_MACCTL_AWAKE 0x04000000
95 #define BWN_MACCTL_CLOSEDNET 0x08000000
96 #define BWN_MACCTL_TBTT_HOLD 0x10000000
97 #define BWN_MACCTL_DISC_TXSTAT 0x20000000
98 #define BWN_MACCTL_DISC_PMQ 0x40000000
99 #define BWN_MACCTL_GMODE 0x80000000
101 #define BWN_MACCMD 0x124 /* MAC command */
102 #define BWN_MACCMD_BEACON0_VALID 0x00000001
103 #define BWN_MACCMD_BEACON1_VALID 0x00000002
104 #define BWN_MACCMD_DFQ_VALID 0x00000004
105 #define BWN_MACCMD_BGNOISE 0x00000010
106 #define BWN_INTR_REASON 0x128
107 #define BWN_INTR_MASK 0x12c
108 #define BWN_RAM_CONTROL 0x130
109 #define BWN_RAM_DATA 0x134
110 #define BWN_PS_STATUS 0x140
111 #define BWN_MAC_HW_CAP 0x15c /* core rev >= 13 */
112 #define BWN_RF_HWENABLED_HI 0x158
114 #define BWN_SHM_CONTROL 0x160
115 #define BWN_SHM_DATA 0x164
116 #define BWN_SHM_DATA_UNALIGNED 0x166
117 #define BWN_XMITSTAT_0 0x170
118 #define BWN_XMITSTAT_1 0x174
119 #define BWN_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
120 #define BWN_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
121 #define BWN_TSF_CFP_START 0x18c
124 #define BWN_DMA32_BASE0 0x200
125 #define BWN_DMA32_BASE1 0x220
126 #define BWN_DMA32_BASE2 0x240
127 #define BWN_DMA32_BASE3 0x260
128 #define BWN_DMA32_BASE4 0x280
129 #define BWN_DMA32_BASE5 0x2a0
131 #define BWN_DMA64_BASE0 0x200
132 #define BWN_DMA64_BASE1 0x240
133 #define BWN_DMA64_BASE2 0x280
134 #define BWN_DMA64_BASE3 0x2c0
135 #define BWN_DMA64_BASE4 0x300
136 #define BWN_DMA64_BASE5 0x340
139 #define BWN_PIO_BASE0 0x300
140 #define BWN_PIO_BASE1 0x310
141 #define BWN_PIO_BASE2 0x320
142 #define BWN_PIO_BASE3 0x330
143 #define BWN_PIO_BASE4 0x340
144 #define BWN_PIO_BASE5 0x350
145 #define BWN_PIO_BASE6 0x360
146 #define BWN_PIO_BASE7 0x370
148 #define BWN_PIO11_BASE0 0x200
149 #define BWN_PIO11_BASE1 0x240
150 #define BWN_PIO11_BASE2 0x280
151 #define BWN_PIO11_BASE3 0x2c0
152 #define BWN_PIO11_BASE4 0x300
153 #define BWN_PIO11_BASE5 0x340
155 #define BWN_GPIOCTL 0x06c
156 #define BWN_PHYVER 0x3e0
157 #define BWN_PHYVER_ANALOG 0xf000
158 #define BWN_PHYVER_TYPE 0x0f00
159 #define BWN_PHYVER_VERSION 0x00ff
160 #define BWN_PHY_RADIO 0x3e2
161 #define BWN_PHY0 0x3e6
162 #define BWN_CHANNEL 0x3f0
163 #define BWN_CHANNEL_EXT 0x3f4
164 #define BWN_RFCTL 0x3f6
165 #define BWN_RFCTL_ID 0x01
166 #define BWN_RFDATAHI 0x3f8
167 #define BWN_RFDATALO 0x3fa
168 #define BWN_PHYCTL 0x3fc
169 #define BWN_PHYDATA 0x3fe
170 #define BWN_MACFILTER_CONTROL 0x420
171 #define BWN_MACFILTER_DATA 0x422
172 #define BWN_RCMTA_COUNT 0x43c
174 #define BWN_PSM_PHY_HDR 0x492
176 #define BWN_PSM_HDR_MAC_PHY_RESET 0x00000001
177 #define BWN_PSM_HDR_MAC_PHY_CLOCK_EN 0x00000002
178 #define BWN_PSM_HDR_MAC_PHY_FORCE_CLK 0x00000004
180 #define BWN_RF_HWENABLED_LO 0x49a
182 #define BWN_GPIO_CONTROL 0x49c
183 #define BWN_GPIO_MASK 0x49e
184 #define BWN_TSF_CFP_START_LOW 0x604
185 #define BWN_TSF_CFP_START_HIGH 0x606
186 #define BWN_TSF_CFP_PRETBTT 0x612
187 #define BWN_TSF_CLK_FRAC_LOW 0x62e
188 #define BWN_TSF_CLK_FRAC_HIGH 0x630
189 #define BWN_RNG 0x65a
190 #define BWN_IFSCTL 0x688 /* Interframe space control */
191 #define BWN_IFSCTL_USE_EDCF 0x0004
192 #define BWN_POWERUP_DELAY 0x6a8
193 #define BWN_BTCOEX_CTL 0x6b4
194 #define BWN_BTCOEX_TXCTL 0x6b8
196 #define BWN_UCODE 0x0
197 #define BWN_HW 0x3
198 #define BWN_RCMTA 0x4
200 #define BWN_TSSI_MAX 0x7f
201 #define BWN_SHARED 0x1
202 #define BWN_SHARED_UCODE_REV 0x0000
203 #define BWN_SHARED_UCODE_PATCH 0x0002
204 #define BWN_SHARED_UCODE_DATE 0x0004
205 #define BWN_SHARED_UCODE_TIME 0x0006
206 #define BWN_SHARED_COREREV 0x0016
207 #define BWN_SHARED_ACKCTS_PHYCTL 0x0022
208 #define BWN_SHARED_RX_PADOFFSET 0x0034
209 #define BWN_SHARED_UCODESTAT 0x0040
212 #define BWN_SHARED_FWCAPS 0x0042
213 #define BWN_SHARED_SHORT_RETRY_FALLBACK 0x0044
214 #define BWN_SHARED_LONG_RETRY_FALLBACK 0x0046
215 #define BWN_SHARED_BEACON_PHYCTL 0x0054
216 #define BWN_SHARED_KEY_TABLEP 0x0056
217 #define BWN_SHARED_TSSI_CCK 0x0058
218 #define BWN_SHARED_HFLO 0x005e /* low hostflag */
219 #define BWN_SHARED_HFMI 0x0060 /* middle hostflag */
220 #define BWN_SHARED_HFHI 0x0062 /* high hostflag */
221 #define BWN_SHARED_RADIO_ATT 0x0064
222 #define BWN_SHARED_TSSI_OFDM_G 0x0070
223 #define BWN_SHARED_PROBE_RESP_MAXTIME 0x0074
224 #define BWN_SHARED_SPU_WAKEUP 0x0094
225 #define BWN_SHARED_PRETBTT 0x0096
226 #define BWN_SHARED_CHAN 0x00a0
227 #define BWN_SHARED_MACHW_L 0x00c0
228 #define BWN_SHARED_MACHW_H 0x00c2
229 #define BWN_SHARED_AUTOINC 0x0100
230 #define BWN_SHARED_PROBE_RESP_PHYCTL 0x0188
231 #define BWN_SHARED_EDCFQ 0x0240
232 #define BWN_SHARED_KEYIDX_BLOCK 0x05d4
233 #define BWN_SHARED_PSM 0x05f4
236 #define BWN_SHM_SH_NPHY_TXIQW0 0x0700
237 #define BWN_SHM_SH_NPHY_TXIQW1 0x0702
238 #define BWN_SHM_SH_NPHY_TXIQW2 0x0704
239 #define BWN_SHM_SH_NPHY_TXIQW3 0x0706
241 #define BWN_SHM_SH_NPHY_TXPWR_INDX0 0x0708
242 #define BWN_SHM_SH_NPHY_TXPWR_INDX1 0x070E
245 #define BWN_SCRATCH 0x2
246 #define BWN_SCRATCH_CONT_MIN 0x0003
247 #define BWN_SCRATCH_CONT_MAX 0x0004
248 #define BWN_SCRATCH_SHORT_RETRY 0x0006
249 #define BWN_SCRATCH_LONG_RETRY 0x0007
252 #define BWN_INTR_MAC_SUSPENDED 0x00000001
253 #define BWN_INTR_BEACON 0x00000002
254 #define BWN_INTR_TBTT_INDI 0x00000004
255 #define BWN_INTR_ATIM_END 0x00000020
256 #define BWN_INTR_PMQ 0x00000040
257 #define BWN_INTR_MAC_TXERR 0x00000200
258 #define BWN_INTR_PHY_TXERR 0x00000800
259 #define BWN_INTR_DMA 0x00008000
260 #define BWN_INTR_TXFIFO_FLUSH_OK 0x00010000
261 #define BWN_INTR_NOISESAMPLE_OK 0x00040000
262 #define BWN_INTR_UCODE_DEBUG 0x08000000
263 #define BWN_INTR_RFKILL 0x10000000
264 #define BWN_INTR_TX_OK 0x20000000
265 #define BWN_INTR_ALL 0xffffffff
272 #define BWN_HF_UCODE_ANTDIV_HELPER 0x000000000001ull
273 #define BWN_HF_GPHY_SYM_WORKAROUND 0x000000000002ull
274 #define BWN_HF_4DB_CCK_POWERBOOST 0x000000000008ull
275 #define BWN_HF_BT_COEXIST 0x000000000010ull
276 #define BWN_HF_GPHY_DC_CANCELFILTER 0x000000000020ull
277 #define BWN_HF_PAGAINBOOST_OFDM_ON 0x000000000040ull
278 #define BWN_HF_JAPAN_CHAN14_OFF 0x000000000080ull
279 #define BWN_HF_EDCF 0x000000000100ull
280 #define BWN_HF_TSSI_RESET_PSM_WORKAROUN 0x000000000200ull
281 #define BWN_HF_SLOWCLOCK_REQ_OFF 0x000000000400ull
282 #define BWN_HF_ACI_WORKAROUND 0x000000000800ull
283 #define BWN_HF_2060_RADIO_WORKAROUND 0x000000001000ull
284 #define BWN_HF_FORCE_VCO_RECALC 0x000000040000ull
285 #define BWN_HF_PCI_SLOWCLOCK_WORKAROUND 0x000000080000ull
286 #define BWN_HF_4318_TSSI 0x000000200000ull
287 #define BWN_HF_HW_POWERCTL 0x000000800000ull
288 #define BWN_HF_BT_COEXISTALT 0x000001000000ull
289 #define BWN_HF_SKIP_CFP_UPDATE 0x000004000000ull
290 #define BWN_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
291 #define BWN_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */
292 #define BWN_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
293 #define BWN_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) …
294 #define BWN_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
295 #define BWN_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
296 #define BWN_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
297 #define BWN_HF_PR45960W 0x080000000000ULL
299 #define BWN_TX_PHY_ENC_CCK 0x0000
300 #define BWN_TX_PHY_ENC_OFDM 0x0001
301 #define BWN_TX_PHY_SHORTPRMBL 0x0010
302 #define BWN_TX_PHY_ANT 0x03c0
303 #define BWN_TX_PHY_ANT0 0x0000
304 #define BWN_TX_PHY_ANT1 0x0040
305 #define BWN_TX_PHY_ANT01AUTO 0x00c0
306 #define BWN_TX_PHY_ANT2 0x0100
307 #define BWN_TX_PHY_ANT3 0x0200
308 #define BWN_TX_PHY_TXPWR 0xfc00
309 #define BWN_TX_MAC_ACK 0x00000001 /* immediate ACK */
310 #define BWN_TX_MAC_LONGFRAME 0x00000002
311 #define BWN_TX_MAC_SEND_RTSCTS 0x00000004
312 #define BWN_TX_MAC_START_MSDU 0x00000008
313 #define BWN_TX_MAC_HWSEQ 0x00000010
314 #define BWN_TX_MAC_5GHZ 0x00000080
315 #define BWN_TX_MAC_SEND_CTSTOSELF 0x00000800
316 #define BWN_TX_EFT_FB_CCK 0x00
317 #define BWN_TX_EFT_FB_OFDM 0x01
318 #define BWN_TX_EFT_RTS_CCK 0x00
319 #define BWN_TX_EFT_RTS_OFDM 0x04
320 #define BWN_TX_EFT_RTS_FBCCK 0x00
321 #define BWN_TX_EFT_RTS_FBOFDM 0x10
323 #define BWN_PIO_TXCTL 0x00
324 #define BWN_PIO_TXCTL_WRITELO 0x0001
325 #define BWN_PIO_TXCTL_WRITEHI 0x0002
326 #define BWN_PIO_TXCTL_EOF 0x0004
327 #define BWN_PIO_TXCTL_FRAMEREADY 0x0008
328 #define BWN_PIO_TXDATA 0x02
329 #define BWN_PIO_TXQBUFSIZE 0x04
330 #define BWN_PIO_RXCTL 0x00
331 #define BWN_PIO_RXCTL_FRAMEREADY 0x0001
332 #define BWN_PIO_RXCTL_DATAREADY 0x0002
333 #define BWN_PIO_RXDATA 0x02
334 #define BWN_PIO8_TXCTL 0x00
335 #define BWN_PIO8_TXCTL_0_7 0x00000001
336 #define BWN_PIO8_TXCTL_8_15 0x00000002
337 #define BWN_PIO8_TXCTL_16_23 0x00000004
338 #define BWN_PIO8_TXCTL_24_31 0x00000008
339 #define BWN_PIO8_TXCTL_EOF 0x00000010
340 #define BWN_PIO8_TXCTL_FRAMEREADY 0x00000080
341 #define BWN_PIO8_TXDATA 0x04
342 #define BWN_PIO8_RXCTL 0x00
343 #define BWN_PIO8_RXCTL_FRAMEREADY 0x00000001
344 #define BWN_PIO8_RXCTL_DATAREADY 0x00000002
345 #define BWN_PIO8_RXDATA 0x04
347 #define BWN_DMA32_TXCTL 0x00
348 #define BWN_DMA32_TXENABLE 0x00000001
349 #define BWN_DMA32_TXSUSPEND 0x00000002
350 #define BWN_DMA32_TXPARITY_DISABLE 0x00000800
351 #define BWN_DMA32_TXADDREXT_MASK 0x00030000
353 #define BWN_DMA32_TXRING 0x04
354 #define BWN_DMA32_TXINDEX 0x08
355 #define BWN_DMA32_TXSTATUS 0x0c
356 #define BWN_DMA32_TXSTATE 0x0000f000
357 #define BWN_DMA32_TXSTAT_DISABLED 0x00000000
358 #define BWN_DMA32_TXSTAT_IDLEWAIT 0x00002000
359 #define BWN_DMA32_TXSTAT_STOPPED 0x00003000
360 #define BWN_DMA32_RXCTL 0x10
361 #define BWN_DMA32_RXENABLE 0x00000001
363 #define BWN_DMA32_RXDIRECTFIFO 0x00000100
364 #define BWN_DMA32_RXPARITY_DISABLE 0x00000800
365 #define BWN_DMA32_RXADDREXT_MASK 0x00030000
367 #define BWN_DMA32_RXRING 0x14
368 #define BWN_DMA32_RXINDEX 0x18
369 #define BWN_DMA32_RXSTATUS 0x1c
370 #define BWN_DMA32_RXDPTR 0x00000fff
371 #define BWN_DMA32_RXSTATE 0x0000f000
372 #define BWN_DMA32_RXSTAT_DISABLED 0x00000000
373 #define BWN_DMA32_ADDREXT_MASK 0xC0000000
375 #define BWN_DMA64_TXCTL 0x00
376 #define BWN_DMA64_TXENABLE 0x00000001
377 #define BWN_DMA64_TXSUSPEND 0x00000002
378 #define BWN_DMA64_TXPARITY_DISABLE 0x00000800
379 #define BWN_DMA64_TXADDREXT_MASK 0x00030000
381 #define BWN_DMA64_TXINDEX 0x04
382 #define BWN_DMA64_TXRINGLO 0x08
383 #define BWN_DMA64_TXRINGHI 0x0c
384 #define BWN_DMA64_TXSTATUS 0x10
385 #define BWN_DMA64_TXSTAT 0xf0000000
386 #define BWN_DMA64_TXSTAT_DISABLED 0x00000000
387 #define BWN_DMA64_TXSTAT_IDLEWAIT 0x20000000
388 #define BWN_DMA64_TXSTAT_STOPPED 0x30000000
389 #define BWN_DMA64_RXCTL 0x20
390 #define BWN_DMA64_RXENABLE 0x00000001
392 #define BWN_DMA64_RXDIRECTFIFO 0x00000100
393 #define BWN_DMA64_RXPARITY_DISABLE 0x00000800
394 #define BWN_DMA64_RXADDREXT_MASK 0x00030000
396 #define BWN_DMA64_RXINDEX 0x24
397 #define BWN_DMA64_RXRINGLO 0x28
398 #define BWN_DMA64_RXRINGHI 0x2c
399 #define BWN_DMA64_RXSTATUS 0x30
400 #define BWN_DMA64_RXSTATDPTR 0x00001fff
401 #define BWN_DMA64_RXSTAT 0xf0000000
402 #define BWN_DMA64_RXSTAT_DISABLED 0x00000000
403 #define BWN_DMA64_ADDREXT_MASK 0xC000000000000000ULL
414 #define BWN_PHYROUTE_BASE 0x0000
415 #define BWN_PHYROUTE_MASK 0x0c00
416 #define BWN_PHYROUTE_OFDM_GPHY 0x0400
417 #define BWN_PHYROUTE_EXT_GPHY 0x0800
418 #define BWN_PHYROUTE_N_BMODE 0x0C00
425 #define BWN_PHY_VERSION_OFDM BWN_PHY_OFDM(0x00)
426 #define BWN_PHY_BBANDCFG BWN_PHY_OFDM(0x01)
427 #define BWN_PHY_BBANDCFG_RXANT 0x180
429 #define BWN_PHY_PWRDOWN BWN_PHY_OFDM(0x03)
430 #define BWN_PHY_CRSTHRES1_R1 BWN_PHY_OFDM(0x06)
431 #define BWN_PHY_CRSGAIN_CTL BWN_PHY_OFDM(0x10)
432 #define BWN_PHY_MINPWR_LEVEL BWN_PHY_OFDM(0x16)
433 #define BWN_PHY_OFDMSYNCTHRESH0 BWN_PHY_OFDM(0x17)
434 #define BWN_PHY_IDLEAFTERPKTRXTO BWN_PHY_OFDM(0x1a)
435 #define BWN_PHY_LNAHPFCTL BWN_PHY_OFDM(0x1c)
436 #define BWN_PHY_DCOFFSETTRANSIENT BWN_PHY_OFDM(0x1c) /* for LP */
437 #define BWN_PHY_PREAMBLECONFIRMTO BWN_PHY_OFDM(0x1e)
438 #define BWN_PHY_CLIPTHRESH BWN_PHY_OFDM(0x1f)
439 #define BWN_PHY_LPFGAINCTL BWN_PHY_OFDM(0x20)
440 #define BWN_PHY_CLIPCTRTHRESH BWN_PHY_OFDM(0x20) /* for LP */
441 #define BWN_PHY_HIGAINDB BWN_PHY_OFDM(0x23)
442 #define BWN_PHY_LOWGAINDB BWN_PHY_OFDM(0x24)
443 #define BWN_PHY_VERYLOWGAINDB BWN_PHY_OFDM(0x25)
444 #define BWN_PHY_GAINMISMATCH BWN_PHY_OFDM(0x26)
445 #define BWN_PHY_ADIVRELATED BWN_PHY_OFDM(0x27)
446 #define BWN_PHY_GAINDIRECTMISMATCH BWN_PHY_OFDM(0x27) /* for LP */
447 #define BWN_PHY_CRS0 BWN_PHY_OFDM(0x29)
448 #define BWN_PHY_CRS0_EN 0x4000
449 #define BWN_PHY_PWR_THRESH1 BWN_PHY_OFDM(0x29) /* for LP */
450 #define BWN_PHY_ANTDWELL BWN_PHY_OFDM(0x2b)
451 #define BWN_PHY_ANTDWELL_AUTODIV1 0x0100
452 #define BWN_PHY_DSSS_CONFIRM_CNT BWN_PHY_OFDM(0x2f) /* DSSS Confirm Cnt */
453 #define BWN_PHY_PEAK_COUNT BWN_PHY_OFDM(0x30)
454 #define BWN_PHY_GAIN_MISMATCH_LIMIT BWN_PHY_OFDM(0x31)
455 #define BWN_PHY_CRS_ED_THRESH BWN_PHY_OFDM(0x32)
456 #define BWN_PHY_INPUT_PWRDB BWN_PHY_OFDM(0x34)
457 #define BWN_PHY_AFE_ADC_CTL_0 BWN_PHY_OFDM(0x36)
458 #define BWN_PHY_AFE_ADC_CTL_1 BWN_PHY_OFDM(0x37)
459 #define BWN_PHY_AFE_DAC_CTL BWN_PHY_OFDM(0x39)
460 #define BWN_PHY_AFE_CTL BWN_PHY_OFDM(0x3a)
461 #define BWN_PHY_AFE_CTL_OVR BWN_PHY_OFDM(0x3b)
462 #define BWN_PHY_AFE_CTL_OVRVAL BWN_PHY_OFDM(0x3c)
463 #define BWN_PHY_AFE_RSSI_CTL_0 BWN_PHY_OFDM(0x3d)
464 #define BWN_PHY_AFE_RSSI_CTL_1 BWN_PHY_OFDM(0x3e)
465 #define BWN_PHY_LP_PHY_CTL BWN_PHY_OFDM(0x48)
466 #define BWN_PHY_ENCORE BWN_PHY_OFDM(0x49)
467 #define BWN_PHY_ENCORE_EN 0x0200
468 #define BWN_PHY_RESET_CTL BWN_PHY_OFDM(0x4a)
469 #define BWN_PHY_RF_OVERRIDE_0 BWN_PHY_OFDM(0x4c)
470 #define BWN_PHY_RF_OVERRIDE_VAL_0 BWN_PHY_OFDM(0x4d)
471 #define BWN_PHY_TR_LOOKUP_1 BWN_PHY_OFDM(0x4e)
472 #define BWN_PHY_TR_LOOKUP_2 BWN_PHY_OFDM(0x4F)
473 #define BWN_PHY_LMS BWN_PHY_OFDM(0x55)
474 #define BWN_PHY_TABLE_ADDR BWN_PHY_OFDM(0x55) /* for LP */
475 #define BWN_PHY_TABLEDATALO BWN_PHY_OFDM(0x56)
476 #define BWN_PHY_TABLEDATAHI BWN_PHY_OFDM(0x57)
477 #define BWN_PHY_OFDM61 BWN_PHY_OFDM(0x61)
478 #define BWN_PHY_OFDM61_10 0x0010
479 #define BWN_PHY_ADC_COMPENSATION_CTL BWN_PHY_OFDM(0x70)
480 #define BWN_PHY_OTABLECTL BWN_PHY_OFDM(0x72)
482 #define BWN_PHY_OTABLEI BWN_PHY_OFDM(0x73)
483 #define BWN_PHY_OTABLEQ BWN_PHY_OFDM(0x74)
484 #define BWN_PHY_HPWR_TSSICTL BWN_PHY_OFDM(0x78)
485 #define BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR BWN_PHY_OFDM(0x81)
486 #define BWN_PHY_IQ_NUM_SMPLS_ADDR BWN_PHY_OFDM(0x82)
487 #define BWN_PHY_IQ_ACC_HI_ADDR BWN_PHY_OFDM(0x83)
488 #define BWN_PHY_IQ_ACC_LO_ADDR BWN_PHY_OFDM(0x84)
489 #define BWN_PHY_IQ_I_PWR_ACC_HI_ADDR BWN_PHY_OFDM(0x85)
490 #define BWN_PHY_IQ_I_PWR_ACC_LO_ADDR BWN_PHY_OFDM(0x86)
491 #define BWN_PHY_IQ_Q_PWR_ACC_HI_ADDR BWN_PHY_OFDM(0x87)
492 #define BWN_PHY_IQ_Q_PWR_ACC_LO_ADDR BWN_PHY_OFDM(0x88)
493 #define BWN_PHY_ANTWRSETT BWN_PHY_OFDM(0x8c)
494 #define BWN_PHY_ANTWRSETT_ARXDIV 0x2000
495 #define BWN_PHY_OFDM9B BWN_PHY_OFDM(0x9b)
496 #define BWN_PHY_A_PHY_CTL_ADDR BWN_PHY_OFDM(0x9c)
497 #define BWN_PHY_RX_COMP_COEFF_S BWN_PHY_OFDM(0x9e)
498 #define BWN_PHY_N1P1GAIN BWN_PHY_OFDM(0xa0)
499 #define BWN_PHY_SMPL_PLAY_COUNT BWN_PHY_OFDM(0xa0) /* for LP */
500 #define BWN_PHY_P1P2GAIN BWN_PHY_OFDM(0xa1)
501 #define BWN_PHY_SMPL_PLAY_BUFFER_CTL BWN_PHY_OFDM(0xA1) /* for LP */
502 #define BWN_PHY_N1N2GAIN BWN_PHY_OFDM(0xa2)
503 #define BWN_PHY_4WIRECTL BWN_PHY_OFDM(0xa2) /* for LP */
504 #define BWN_PHY_TX_PWR_CTL_CMD BWN_PHY_OFDM(0xa4)
505 #define BWN_PHY_TX_PWR_CTL_CMD_MODE 0xe000
506 #define BWN_PHY_TX_PWR_CTL_CMD_MODE_OFF 0x0000
507 #define BWN_PHY_TX_PWR_CTL_CMD_MODE_SW 0x8000
508 #define BWN_PHY_TX_PWR_CTL_CMD_MODE_HW 0xe000
509 #define BWN_PHY_CCKSHIFTBITS_WA BWN_PHY_OFDM(0xa5)
510 #define BWN_PHY_TX_PWR_CTL_NNUM BWN_PHY_OFDM(0xa5) /* for LP */
511 #define BWN_PHY_CCKSHIFTBITS BWN_PHY_OFDM(0xa7)
512 #define BWN_PHY_DIVSRCHIDX BWN_PHY_OFDM(0xa8)
513 #define BWN_PHY_DIVP1P2GAIN BWN_PHY_OFDM(0xab)
514 #define BWN_PHY_LP_RF_SIGNAL_LUT BWN_PHY_OFDM(0xac)
515 #define BWN_PHY_DIVSRCHGAINBACK BWN_PHY_OFDM(0xad)
516 #define BWN_PHY_RX_RADIO_CTL BWN_PHY_OFDM(0xae)
517 #define BWN_PHY_RF_OVERRIDE_2 BWN_PHY_OFDM(0xb0)
518 #define BWN_PHY_RF_OVERRIDE_2_VAL BWN_PHY_OFDM(0xb1)
519 #define BWN_PHY_PS_CTL_OVERRIDE_VAL0 BWN_PHY_OFDM(0xB2)
520 #define BWN_PHY_PS_CTL_OVERRIDE_VAL1 BWN_PHY_OFDM(0xB3)
521 #define BWN_PHY_PS_CTL_OVERRIDE_VAL2 BWN_PHY_OFDM(0xB4)
522 #define BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL BWN_PHY_OFDM(0xB5)
523 #define BWN_PHY_RX_GAIN_CTL_OVERRIDE_VAL BWN_PHY_OFDM(0xB6)
524 #define BWN_PHY_AFE_DDFS BWN_PHY_OFDM(0xb7)
525 #define BWN_PHY_AFE_DDFS_POINTER_INIT BWN_PHY_OFDM(0xB8)
526 #define BWN_PHY_AFE_DDFS_INCR_INIT BWN_PHY_OFDM(0xB9)
527 #define BWN_PHY_TR_LOOKUP_3 BWN_PHY_OFDM(0xbb)
528 #define BWN_PHY_TR_LOOKUP_4 BWN_PHY_OFDM(0xbc)
529 #define BWN_PHY_GPIO_OUTEN BWN_PHY_OFDM(0xbe)
530 #define BWN_PHY_GPIO_SELECT BWN_PHY_OFDM(0xbf)
531 #define BWN_PHY_CRSTHRES1 BWN_PHY_OFDM(0xc0)
532 #define BWN_PHY_CRSTHRES2 BWN_PHY_OFDM(0xc1)
533 #define BWN_PHY_4C3 BWN_PHY_OFDM(0xC3)
534 #define BWN_PHY_4C4 BWN_PHY_OFDM(0xC4)
535 #define BWN_PHY_4C5 BWN_PHY_OFDM(0xC5)
536 #define BWN_PHY_TR_LOOKUP_5 BWN_PHY_OFDM(0xC7)
537 #define BWN_PHY_TR_LOOKUP_6 BWN_PHY_OFDM(0xC8)
538 #define BWN_PHY_TR_LOOKUP_7 BWN_PHY_OFDM(0xC9)
539 #define BWN_PHY_TR_LOOKUP_8 BWN_PHY_OFDM(0xCA)
540 #define BWN_PHY_RF_PWR_OVERRIDE BWN_PHY_OFDM(0xd3)
544 #define BWN_OFDMTAB_AGC1 BWN_OFDMTAB(0x00, 0)
545 #define BWN_OFDMTAB_GAIN0 BWN_OFDMTAB(0x00, 0)
546 #define BWN_OFDMTAB_GAINX BWN_OFDMTAB(0x01, 0)
547 #define BWN_OFDMTAB_GAIN1 BWN_OFDMTAB(0x01, 4)
548 #define BWN_OFDMTAB_AGC3 BWN_OFDMTAB(0x02, 0)
549 #define BWN_OFDMTAB_GAIN2 BWN_OFDMTAB(0x02, 3)
550 #define BWN_OFDMTAB_LNAHPFGAIN1 BWN_OFDMTAB(0x03, 0)
551 #define BWN_OFDMTAB_WRSSI BWN_OFDMTAB(0x04, 0)
552 #define BWN_OFDMTAB_NOISESCALE BWN_OFDMTAB(0x05, 0)
553 #define BWN_OFDMTAB_AGC2 BWN_OFDMTAB(0x06, 0)
554 #define BWN_OFDMTAB_ROTOR BWN_OFDMTAB(0x08, 0)
555 #define BWN_OFDMTAB_ADVRETARD BWN_OFDMTAB(0x09, 0)
556 #define BWN_OFDMTAB_DAC BWN_OFDMTAB(0x0c, 0)
557 #define BWN_OFDMTAB_DC BWN_OFDMTAB(0x0e, 7)
558 #define BWN_OFDMTAB_PWRDYN2 BWN_OFDMTAB(0x0e, 12)
559 #define BWN_OFDMTAB_UNKNOWN_0F BWN_OFDMTAB(0x0f, 0)
560 #define BWN_OFDMTAB_UNKNOWN_APHY BWN_OFDMTAB(0x0f, 7)
561 #define BWN_OFDMTAB_LPFGAIN BWN_OFDMTAB(0x0f, 12)
562 #define BWN_OFDMTAB_RSSI BWN_OFDMTAB(0x10, 0)
563 #define BWN_OFDMTAB_UNKNOWN_11 BWN_OFDMTAB(0x11, 4)
564 #define BWN_OFDMTAB_AGC1_R1 BWN_OFDMTAB(0x13, 0)
565 #define BWN_OFDMTAB_GAINX_R1 BWN_OFDMTAB(0x14, 0)
566 #define BWN_OFDMTAB_MINSIGSQ BWN_OFDMTAB(0x14, 0)
567 #define BWN_OFDMTAB_AGC3_R1 BWN_OFDMTAB(0x15, 0)
568 #define BWN_OFDMTAB_WRSSI_R1 BWN_OFDMTAB(0x15, 4)
569 #define BWN_OFDMTAB_DACRFPABB BWN_OFDMTAB(0x16, 0)
571 #define BWN_PHY_CCKBBANDCFG BWN_PHY_CCK(0x01)
572 #define BWN_PHY_PGACTL BWN_PHY_CCK(0x15)
573 #define BWN_PHY_PGACTL_LPF 0x1000
574 #define BWN_PHY_PGACTL_LOWBANDW 0x0040
575 #define BWN_PHY_PGACTL_UNKNOWN 0xefa0
576 #define BWN_PHY_TSSI BWN_PHY_CCK(0x29)
577 #define BWN_PHY_LO_LEAKAGE BWN_PHY_CCK(0x2d)
578 #define BWN_PHY_SYNCPEAKCNT BWN_PHY_CCK(0x30)
579 #define BWN_PHY_SYNCCTL BWN_PHY_CCK(0x35)
580 #define BWN_PHY_DACCTL BWN_PHY_CCK(0x60)
582 #define BWN_PHY_CLASSCTL BWN_PHY_EXTG(0x02)
583 #define BWN_PHY_GTABCTL BWN_PHY_EXTG(0x03)
585 #define BWN_PHY_GTABDATA BWN_PHY_EXTG(0x04)
586 #define BWN_PHY_LO_MASK BWN_PHY_EXTG(0x0f)
587 #define BWN_PHY_LO_CTL BWN_PHY_EXTG(0x10)
588 #define BWN_PHY_RFOVER BWN_PHY_EXTG(0x11)
589 #define BWN_PHY_RFOVERVAL BWN_PHY_EXTG(0x12)
590 #define BWN_PHY_RFOVERVAL_EXTLNA 0x8000
591 #define BWN_PHY_RFOVERVAL_LNA 0x7000
593 #define BWN_PHY_RFOVERVAL_PGA 0x0f00
595 #define BWN_PHY_RFOVERVAL_UNK 0x0010
596 #define BWN_PHY_RFOVERVAL_TRSWRX 0x00e0
597 #define BWN_PHY_RFOVERVAL_BW 0x0003
598 #define BWN_PHY_RFOVERVAL_BW_LPF 0x0001
599 #define BWN_PHY_RFOVERVAL_BW_LBW 0x0002
600 #define BWN_PHY_ANALOGOVER BWN_PHY_EXTG(0x14)
601 #define BWN_PHY_ANALOGOVERVAL BWN_PHY_EXTG(0x15)
605 #define BWN_GTAB_ORIGTR BWN_GTAB(0x2e, 0x298)
607 #define BWN_PHY_G_LOCTL 0x0810
608 #define BWN_PHY_RADIO_BITFIELD 0x0401
609 #define BWN_PHY_G_CRS 0x0429
610 #define BWN_PHY_NRSSI_CTRL 0x0803
611 #define BWN_PHY_NRSSI_DATA 0x0804
612 #define BWN_FWCAPS_HWCRYPTO 0x0001
613 #define BWN_FWCAPS_WME 0x0002
614 #define BWN_MACFILTER_SELF 0x0000
615 #define BWN_MACFILTER_BSSID 0x0003
617 #define BWN_SEC_ALGO_NONE 0
618 #define BWN_LED_BEHAVIOUR 0x7f
619 #define BWN_LED_ACTIVELOW 0x80
622 #define BWN_DEBUGINTR_PANIC 0
626 #define BWN_DEBUGINTR_ACK 0xffff
629 #define BWN_FWPANIC_DIE 0
633 #define BWN_CCK_RATE_1MB 0x02
634 #define BWN_CCK_RATE_2MB 0x04
635 #define BWN_CCK_RATE_5MB 0x0b
636 #define BWN_CCK_RATE_11MB 0x16
637 #define BWN_OFDM_RATE_6MB 0x0c
638 #define BWN_OFDM_RATE_9MB 0x12
639 #define BWN_OFDM_RATE_12MB 0x18
640 #define BWN_OFDM_RATE_18MB 0x24
641 #define BWN_OFDM_RATE_24MB 0x30
642 #define BWN_OFDM_RATE_36MB 0x48
643 #define BWN_OFDM_RATE_48MB 0x60
644 #define BWN_OFDM_RATE_54MB 0x6c
646 #define BWN_RX_CHAN_PHYTYPE 0x0007
647 #define BWN_RX_PHYST0_GAINCTL 0x4000
648 #define BWN_RX_PHYST0_PLCPHCF 0x0200
649 #define BWN_RX_PHYST0_PLCPFV 0x0100
650 #define BWN_RX_PHYST0_SHORTPRMBL 0x0080
651 #define BWN_RX_PHYST0_OFDM 0x0001
652 #define BWN_RX_PHYST3_TRSTATE 0x0400
653 #define BWN_RX_MAC_KEYIDX 0x000007e0
655 #define BWN_RX_MAC_DECERR 0x00000010
656 #define BWN_RX_MAC_DEC 0x00000008
657 #define BWN_RX_MAC_PADDING 0x00000004
658 #define BWN_RX_MAC_FCSERR 0x00000001
660 #define BWN_PS_ON (1 << 0)
672 BWN_SPROM1_CC_WORLDWIDE = 0,
687 #define BWN_LED_ACT_LOW 0x80
688 #define BWN_LED_ACT_MASK 0x7f
689 #define BWN_LED_ACT_OFF 0
722 0xfeb93ffd, 0xfec63ffd, 0xfed23ffd, 0xfedf3ffd, 0xfeec3ffe, \
723 0xfef83ffe, 0xff053ffe, 0xff113ffe, 0xff1e3ffe, 0xff2a3fff, \
724 0xff373fff, 0xff443fff, 0xff503fff, 0xff5d3fff, 0xff693fff, \
725 0xff763fff, 0xff824000, 0xff8f4000, 0xff9b4000, 0xffa84000, \
726 0xffb54000, 0xffc14000, 0xffce4000, 0xffda4000, 0xffe74000, \
727 0xfff34000, 0x00004000, 0x000d4000, 0x00194000, 0x00264000, \
728 0x00324000, 0x003f4000, 0x004b4000, 0x00584000, 0x00654000, \
729 0x00714000, 0x007e4000, 0x008a3fff, 0x00973fff, 0x00a33fff, \
730 0x00b03fff, 0x00bc3fff, 0x00c93fff, 0x00d63fff, 0x00e23ffe, \
731 0x00ef3ffe, 0x00fb3ffe, 0x01083ffe, 0x01143ffe, 0x01213ffd, \
732 0x012e3ffd, 0x013a3ffd, 0x01473ffd \
737 0xdb93cb87, 0xd666cf64, 0xd1fdd358, 0xcda6d826, 0xca38dd9f, \
738 0xc729e2b4, 0xc469e88e, 0xc26aee2b, 0xc0def46c, 0xc073fa62, \
739 0xc01d00d5, 0xc0760743, 0xc1560d1e, 0xc2e51369, 0xc4ed18ff, \
740 0xc7ac1ed7, 0xcb2823b2, 0xcefa28d9, 0xd2f62d3f, 0xd7bb3197, \
741 0xdce53568, 0xe1fe3875, 0xe7d13b35, 0xed663d35, 0xf39b3ec4, \
742 0xf98e3fa7, 0x00004000, 0x06723fa7, 0x0c653ec4, 0x129a3d35, \
743 0x182f3b35, 0x1e023875, 0x231b3568, 0x28453197, 0x2d0a2d3f, \
744 0x310628d9, 0x34d823b2, 0x38541ed7, 0x3b1318ff, 0x3d1b1369, \
745 0x3eaa0d1e, 0x3f8a0743, 0x3fe300d5, 0x3f8dfa62, 0x3f22f46c, \
746 0x3d96ee2b, 0x3b97e88e, 0x38d7e2b4, 0x35c8dd9f, 0x325ad826, \
747 0x2e03d358, 0x299acf64, 0x246dcb87, \
752 0x0089, 0x02e9, 0x0409, 0x04e9, 0x05a9, 0x0669, 0x0709, 0x0789, \
753 0x0829, 0x08a9, 0x0929, 0x0989, 0x0a09, 0x0a69, 0x0ac9, 0x0b29, \
754 0x0ba9, 0x0be9, 0x0c49, 0x0ca9, 0x0d09, 0x0d69, 0x0da9, 0x0e09, \
755 0x0e69, 0x0ea9, 0x0f09, 0x0f49, 0x0fa9, 0x0fe9, 0x1029, 0x1089, \
756 0x10c9, 0x1109, 0x1169, 0x11a9, 0x11e9, 0x1229, 0x1289, 0x12c9, \
757 0x1309, 0x1349, 0x1389, 0x13c9, 0x1409, 0x1449, 0x14a9, 0x14e9, \
758 0x1529, 0x1569, 0x15a9, 0x15e9, 0x1629, 0x1669, 0x16a9, 0x16e8, \
759 0x1728, 0x1768, 0x17a8, 0x17e8, 0x1828, 0x1868, 0x18a8, 0x18e8, \
760 0x1928, 0x1968, 0x19a8, 0x19e8, 0x1a28, 0x1a68, 0x1aa8, 0x1ae8, \
761 0x1b28, 0x1b68, 0x1ba8, 0x1be8, 0x1c28, 0x1c68, 0x1ca8, 0x1ce8, \
762 0x1d28, 0x1d68, 0x1dc8, 0x1e08, 0x1e48, 0x1e88, 0x1ec8, 0x1f08, \
763 0x1f48, 0x1f88, 0x1fe8, 0x2028, 0x2068, 0x20a8, 0x2108, 0x2148, \
764 0x2188, 0x21c8, 0x2228, 0x2268, 0x22c8, 0x2308, 0x2348, 0x23a8, \
765 0x23e8, 0x2448, 0x24a8, 0x24e8, 0x2548, 0x25a8, 0x2608, 0x2668, \
766 0x26c8, 0x2728, 0x2787, 0x27e7, 0x2847, 0x28c7, 0x2947, 0x29a7, \
767 0x2a27, 0x2ac7, 0x2b47, 0x2be7, 0x2ca7, 0x2d67, 0x2e47, 0x2f67, \
768 0x3247, 0x3526, 0x3646, 0x3726, 0x3806, 0x38a6, 0x3946, 0x39e6, \
769 0x3a66, 0x3ae6, 0x3b66, 0x3bc6, 0x3c45, 0x3ca5, 0x3d05, 0x3d85, \
770 0x3de5, 0x3e45, 0x3ea5, 0x3ee5, 0x3f45, 0x3fa5, 0x4005, 0x4045, \
771 0x40a5, 0x40e5, 0x4145, 0x4185, 0x41e5, 0x4225, 0x4265, 0x42c5, \
772 0x4305, 0x4345, 0x43a5, 0x43e5, 0x4424, 0x4464, 0x44c4, 0x4504, \
773 0x4544, 0x4584, 0x45c4, 0x4604, 0x4644, 0x46a4, 0x46e4, 0x4724, \
774 0x4764, 0x47a4, 0x47e4, 0x4824, 0x4864, 0x48a4, 0x48e4, 0x4924, \
775 0x4964, 0x49a4, 0x49e4, 0x4a24, 0x4a64, 0x4aa4, 0x4ae4, 0x4b23, \
776 0x4b63, 0x4ba3, 0x4be3, 0x4c23, 0x4c63, 0x4ca3, 0x4ce3, 0x4d23, \
777 0x4d63, 0x4da3, 0x4de3, 0x4e23, 0x4e63, 0x4ea3, 0x4ee3, 0x4f23, \
778 0x4f63, 0x4fc3, 0x5003, 0x5043, 0x5083, 0x50c3, 0x5103, 0x5143, \
779 0x5183, 0x51e2, 0x5222, 0x5262, 0x52a2, 0x52e2, 0x5342, 0x5382, \
780 0x53c2, 0x5402, 0x5462, 0x54a2, 0x5502, 0x5542, 0x55a2, 0x55e2, \
781 0x5642, 0x5682, 0x56e2, 0x5722, 0x5782, 0x57e1, 0x5841, 0x58a1, \
782 0x5901, 0x5961, 0x59c1, 0x5a21, 0x5aa1, 0x5b01, 0x5b81, 0x5be1, \
783 0x5c61, 0x5d01, 0x5d80, 0x5e20, 0x5ee0, 0x5fa0, 0x6080, 0x61c0, \
788 0x013c, 0x01f5, 0x031a, 0x0631, 0x0001, 0x0001, 0x0001, 0x0001, \
793 0x5484, 0x3c40, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, \
798 0x6c77, 0x5162, 0x3b40, 0x3335, 0x2f2d, 0x2a2a, 0x2527, 0x1f21, \
799 0x1a1d, 0x1719, 0x1616, 0x1414, 0x1414, 0x1400, 0x1414, 0x1614, \
800 0x1716, 0x1a19, 0x1f1d, 0x2521, 0x2a27, 0x2f2a, 0x332d, 0x3b35, \
801 0x5140, 0x6c62, 0x0077, \
806 0xd8dd, 0xcbd4, 0xbcc0, 0xb6b7, 0xb2b0, 0xadad, 0xa7a9, 0x9fa1, \
807 0x969b, 0x9195, 0x8f8f, 0x8a8a, 0x8a8a, 0x8a00, 0x8a8a, 0x8f8a, \
808 0x918f, 0x9695, 0x9f9b, 0xa7a1, 0xada9, 0xb2ad, 0xb6b0, 0xbcb7, \
809 0xcbc0, 0xd8d4, 0x00dd, \
814 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, \
815 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa400, 0xa4a4, 0xa4a4, \
816 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, \
817 0xa4a4, 0xa4a4, 0x00a4, \
822 0x00de, 0x00dc, 0x00da, 0x00d8, 0x00d6, 0x00d4, 0x00d2, 0x00cf, \
823 0x00cd, 0x00ca, 0x00c7, 0x00c4, 0x00c1, 0x00be, 0x00be, 0x00be, \
824 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, \
825 0x00be, 0x00be, 0x0000, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, \
826 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, \
827 0x00c1, 0x00c4, 0x00c7, 0x00ca, 0x00cd, 0x00cf, 0x00d2, 0x00d4, \
828 0x00d6, 0x00d8, 0x00da, 0x00dc, 0x00de, \
847 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x10, 0x90, \
848 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, 0x08, 0x88, 0x48, 0xc8, \
849 0x28, 0xa8, 0x68, 0xe8, 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, \
850 0x78, 0xf8, 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, \
851 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, 0x0c, 0x8c, \
852 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, 0x1c, 0x9c, 0x5c, 0xdc, \
853 0x3c, 0xbc, 0x7c, 0xfc, 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, \
854 0x62, 0xe2, 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, \
855 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, 0x1a, 0x9a, \
856 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, 0x06, 0x86, 0x46, 0xc6, \
857 0x26, 0xa6, 0x66, 0xe6, 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, \
858 0x76, 0xf6, 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, \
859 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, 0x01, 0x81, \
860 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, 0x11, 0x91, 0x51, 0xd1, \
861 0x31, 0xb1, 0x71, 0xf1, 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, \
862 0x69, 0xe9, 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, \
863 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, 0x15, 0x95, \
864 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, 0x0d, 0x8d, 0x4d, 0xcd, \
865 0x2d, 0xad, 0x6d, 0xed, 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, \
866 0x7d, 0xfd, 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, \
867 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, 0x0b, 0x8b, \
868 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, 0x1b, 0x9b, 0x5b, 0xdb, \
869 0x3b, 0xbb, 0x7b, 0xfb, 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, \
870 0x67, 0xe7, 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, \
871 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, 0x1f, 0x9f, \
872 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff \
879 #define BWN_TAB_TYPEMASK 0xf0000000
882 #define BWN_TAB_8BIT 0x10000000
883 #define BWN_TAB_16BIT 0x20000000
884 #define BWN_TAB_32BIT 0x30000000
894 #define BWN_LP_SOUTH(radio_reg) BWN_LP_RADIO((radio_reg) | 0x4000)
896 #define BWN_B2062_N_COM1 BWN_LP_NORTH(0x000)
897 #define BWN_B2062_N_COM2 BWN_LP_NORTH(0x002)
898 #define BWN_B2062_N_COM4 BWN_LP_NORTH(0x004)
899 #define BWN_B2062_N_PDNCTL0 BWN_LP_NORTH(0x010)
900 #define BWN_B2062_N_PDNCTL1 BWN_LP_NORTH(0x011)
901 #define BWN_B2062_N_PDNCTL3 BWN_LP_NORTH(0x013)
902 #define BWN_B2062_N_PDNCTL4 BWN_LP_NORTH(0x014)
903 #define BWN_B2062_N_LGENC BWN_LP_NORTH(0x017)
904 #define BWN_B2062_N_LGENATUNE0 BWN_LP_NORTH(0x01E)
905 #define BWN_B2062_N_LGENATUNE2 BWN_LP_NORTH(0x020)
906 #define BWN_B2062_N_LGENATUNE3 BWN_LP_NORTH(0x021)
907 #define BWN_B2062_N_LGENACTL3 BWN_LP_NORTH(0x022)
908 #define BWN_B2062_N_LGENACTL5 BWN_LP_NORTH(0x024)
909 #define BWN_B2062_N_LGENACTL6 BWN_LP_NORTH(0x025)
910 #define BWN_B2062_N_LGENACTL7 BWN_LP_NORTH(0x026)
911 #define BWN_B2062_N_RXA_CTL1 BWN_LP_NORTH(0x028)
912 #define BWN_B2062_N_RXBB_CTL0 BWN_LP_NORTH(0x02F)
913 #define BWN_B2062_N_RXBB_GAIN1 BWN_LP_NORTH(0x033)
914 #define BWN_B2062_N_RXBB_GAIN2 BWN_LP_NORTH(0x034)
915 #define BWN_B2062_N_RXBB_CALIB2 BWN_LP_NORTH(0x03A)
916 #define BWN_B2062_N_TXCTL3 BWN_LP_NORTH(0x048)
917 #define BWN_B2062_N_TXCTL4 BWN_LP_NORTH(0x049)
918 #define BWN_B2062_N_TXCTL5 BWN_LP_NORTH(0x04A)
919 #define BWN_B2062_N_TXCTL6 BWN_LP_NORTH(0x04B)
920 #define BWN_B2062_N_TXCTL_A BWN_LP_NORTH(0x04F)
921 #define BWN_B2062_N_TX_TUNE BWN_LP_NORTH(0x052)
922 #define BWN_B2062_N_TX_PAD BWN_LP_NORTH(0x053)
923 #define BWN_B2062_N_TX_PGA BWN_LP_NORTH(0x054)
924 #define BWN_B2062_N_TSSI_CTL0 BWN_LP_NORTH(0x057)
925 #define BWN_B2062_N_CALIB_TS BWN_LP_NORTH(0x05D)
926 #define BWN_B2062_S_COM4 BWN_LP_SOUTH(0x004)
927 #define BWN_B2062_S_PDS_CTL0 BWN_LP_SOUTH(0x010)
928 #define BWN_B2062_S_BG_CTL1 BWN_LP_SOUTH(0x015)
929 #define BWN_B2062_S_LGENG_CTL0 BWN_LP_SOUTH(0x017)
930 #define BWN_B2062_S_LGENG_CTL1 BWN_LP_SOUTH(0x018)
931 #define BWN_B2062_S_LGENG_CTL8 BWN_LP_SOUTH(0x01F)
932 #define BWN_B2062_S_LGENG_CTL10 BWN_LP_SOUTH(0x021)
933 #define BWN_B2062_S_RFPLLCTL0 BWN_LP_SOUTH(0x034)
934 #define BWN_B2062_S_RFPLLCTL1 BWN_LP_SOUTH(0x035)
935 #define BWN_B2062_S_RFPLLCTL2 BWN_LP_SOUTH(0x036)
936 #define BWN_B2062_S_RFPLLCTL3 BWN_LP_SOUTH(0x037)
937 #define BWN_B2062_S_RFPLLCTL5 BWN_LP_SOUTH(0x039)
938 #define BWN_B2062_S_RFPLLCTL6 BWN_LP_SOUTH(0x03A)
939 #define BWN_B2062_S_RFPLLCTL7 BWN_LP_SOUTH(0x03B)
940 #define BWN_B2062_S_RFPLLCTL8 BWN_LP_SOUTH(0x03C)
941 #define BWN_B2062_S_RFPLLCTL9 BWN_LP_SOUTH(0x03D)
942 #define BWN_B2062_S_RFPLLCTL10 BWN_LP_SOUTH(0x03E)
943 #define BWN_B2062_S_RFPLLCTL11 BWN_LP_SOUTH(0x03F)
944 #define BWN_B2062_S_RFPLLCTL12 BWN_LP_SOUTH(0x040)
945 #define BWN_B2062_S_RFPLLCTL13 BWN_LP_SOUTH(0x041)
946 #define BWN_B2062_S_RFPLLCTL14 BWN_LP_SOUTH(0x042)
947 #define BWN_B2062_S_RFPLLCTL18 BWN_LP_SOUTH(0x046)
948 #define BWN_B2062_S_RFPLLCTL19 BWN_LP_SOUTH(0x047)
949 #define BWN_B2062_S_RFPLLCTL21 BWN_LP_SOUTH(0x049)
950 #define BWN_B2062_S_RFPLLCTL22 BWN_LP_SOUTH(0x04A)
951 #define BWN_B2062_S_RFPLLCTL23 BWN_LP_SOUTH(0x04B)
952 #define BWN_B2062_S_RFPLLCTL24 BWN_LP_SOUTH(0x04C)
953 #define BWN_B2062_S_RFPLLCTL25 BWN_LP_SOUTH(0x04D)
954 #define BWN_B2062_S_RFPLLCTL26 BWN_LP_SOUTH(0x04E)
955 #define BWN_B2062_S_RFPLLCTL27 BWN_LP_SOUTH(0x04F)
956 #define BWN_B2062_S_RFPLLCTL28 BWN_LP_SOUTH(0x050)
957 #define BWN_B2062_S_RFPLLCTL29 BWN_LP_SOUTH(0x051)
958 #define BWN_B2062_S_RFPLLCTL30 BWN_LP_SOUTH(0x052)
959 #define BWN_B2062_S_RFPLLCTL31 BWN_LP_SOUTH(0x053)
960 #define BWN_B2062_S_RFPLLCTL33 BWN_LP_SOUTH(0x055)
961 #define BWN_B2062_S_RFPLLCTL34 BWN_LP_SOUTH(0x056)
962 #define BWN_B2062_S_RXG_CNT8 BWN_LP_SOUTH(0x05F)
963 #define BWN_B2062_S_RXG_CNT16 BWN_LP_SOUTH(0x067)
964 #define BWN_B2063_COM1 BWN_LP_RADIO(0x000)
965 #define BWN_B2063_COM8 BWN_LP_RADIO(0x008)
966 #define BWN_B2063_COM10 BWN_LP_RADIO(0x00A)
967 #define BWN_B2063_COM15 BWN_LP_RADIO(0x00F)
968 #define BWN_B2063_COM16 BWN_LP_RADIO(0x010)
969 #define BWN_B2063_COM17 BWN_LP_RADIO(0x011)
970 #define BWN_B2063_COM18 BWN_LP_RADIO(0x012)
971 #define BWN_B2063_COM19 BWN_LP_RADIO(0x013)
972 #define BWN_B2063_COM20 BWN_LP_RADIO(0x014)
973 #define BWN_B2063_COM21 BWN_LP_RADIO(0x015)
974 #define BWN_B2063_COM22 BWN_LP_RADIO(0x016)
975 #define BWN_B2063_COM23 BWN_LP_RADIO(0x017)
976 #define BWN_B2063_COM24 BWN_LP_RADIO(0x018)
977 #define BWN_B2063_PLL_SP1 BWN_LP_RADIO(0x01A)
978 #define BWN_B2063_PLL_SP2 BWN_LP_RADIO(0x01B)
979 #define BWN_B2063_LOGEN_SP1 BWN_LP_RADIO(0x01C)
980 #define BWN_B2063_LOGEN_SP2 BWN_LP_RADIO(0x01D)
981 #define BWN_B2063_LOGEN_SP4 BWN_LP_RADIO(0x01F)
982 #define BWN_B2063_LOGEN_SP5 BWN_LP_RADIO(0x020)
983 #define BWN_B2063_G_RX_SP1 BWN_LP_RADIO(0x021)
984 #define BWN_B2063_G_RX_SP2 BWN_LP_RADIO(0x022)
985 #define BWN_B2063_G_RX_SP3 BWN_LP_RADIO(0x023)
986 #define BWN_B2063_G_RX_SP7 BWN_LP_RADIO(0x027)
987 #define BWN_B2063_G_RX_SP10 BWN_LP_RADIO(0x02A)
988 #define BWN_B2063_A_RX_SP1 BWN_LP_RADIO(0x02C)
989 #define BWN_B2063_A_RX_SP2 BWN_LP_RADIO(0x02D)
990 #define BWN_B2063_A_RX_SP7 BWN_LP_RADIO(0x032)
991 #define BWN_B2063_RX_BB_SP3 BWN_LP_RADIO(0x035)
992 #define BWN_B2063_RX_BB_SP4 BWN_LP_RADIO(0x036)
993 #define BWN_B2063_RX_BB_SP8 BWN_LP_RADIO(0x03A)
994 #define BWN_B2063_TX_RF_SP3 BWN_LP_RADIO(0x03D)
995 #define BWN_B2063_TX_RF_SP4 BWN_LP_RADIO(0x03E)
996 #define BWN_B2063_TX_RF_SP6 BWN_LP_RADIO(0x040)
997 #define BWN_B2063_TX_RF_SP9 BWN_LP_RADIO(0x043)
998 #define BWN_B2063_PA_SP1 BWN_LP_RADIO(0x04C)
999 #define BWN_B2063_PA_SP2 BWN_LP_RADIO(0x04D)
1000 #define BWN_B2063_PA_SP3 BWN_LP_RADIO(0x04E)
1001 #define BWN_B2063_PA_SP4 BWN_LP_RADIO(0x04F)
1002 #define BWN_B2063_PA_SP7 BWN_LP_RADIO(0x052)
1003 #define BWN_B2063_TX_BB_SP1 BWN_LP_RADIO(0x053)
1004 #define BWN_B2063_TX_BB_SP3 BWN_LP_RADIO(0x055)
1005 #define BWN_B2063_REG_SP1 BWN_LP_RADIO(0x056)
1006 #define BWN_B2063_BANDGAP_CTL1 BWN_LP_RADIO(0x057)
1007 #define BWN_B2063_RC_CALIB_CTL1 BWN_LP_RADIO(0x05A)
1008 #define BWN_B2063_RC_CALIB_CTL2 BWN_LP_RADIO(0x05B)
1009 #define BWN_B2063_RC_CALIB_CTL3 BWN_LP_RADIO(0x05C)
1010 #define BWN_B2063_RC_CALIB_CTL4 BWN_LP_RADIO(0x05D)
1011 #define BWN_B2063_RC_CALIB_CTL5 BWN_LP_RADIO(0x05E)
1012 #define BWN_B2063_RC_CALIB_CTL6 BWN_LP_RADIO(0x05F)
1013 #define BWN_B2063_JTAG_CALNRST BWN_LP_RADIO(0x064)
1014 #define BWN_B2063_JTAG_CP2 BWN_LP_RADIO(0x068)
1015 #define BWN_B2063_JTAG_CP3 BWN_LP_RADIO(0x069)
1016 #define BWN_B2063_JTAG_LF1 BWN_LP_RADIO(0x06C)
1017 #define BWN_B2063_JTAG_LF2 BWN_LP_RADIO(0x06D)
1018 #define BWN_B2063_JTAG_LF3 BWN_LP_RADIO(0x06E)
1019 #define BWN_B2063_JTAG_LF4 BWN_LP_RADIO(0x06F)
1020 #define BWN_B2063_JTAG_SG1 BWN_LP_RADIO(0x070)
1021 #define BWN_B2063_JTAG_SG2 BWN_LP_RADIO(0x071)
1022 #define BWN_B2063_JTAG_SG3 BWN_LP_RADIO(0x072)
1023 #define BWN_B2063_JTAG_SG4 BWN_LP_RADIO(0x073)
1024 #define BWN_B2063_JTAG_VCO1 BWN_LP_RADIO(0x075)
1025 #define BWN_B2063_JTAG_VCO2 BWN_LP_RADIO(0x076)
1026 #define BWN_B2063_JTAG_VCO_CALIB3 BWN_LP_RADIO(0x079)
1027 #define BWN_B2063_JTAG_VCO_CALIB5 BWN_LP_RADIO(0x07B)
1028 #define BWN_B2063_JTAG_VCO_CALIB6 BWN_LP_RADIO(0x07C)
1029 #define BWN_B2063_JTAG_VCO_CALIB7 BWN_LP_RADIO(0x07D)
1030 #define BWN_B2063_JTAG_VCO_CALIB8 BWN_LP_RADIO(0x07E)
1031 #define BWN_B2063_JTAG_XTAL_12 BWN_LP_RADIO(0x081)
1032 #define BWN_B2063_LOGEN_RCCR1 BWN_LP_RADIO(0x0A1)
1033 #define BWN_B2063_LOGEN_VCOBUF1 BWN_LP_RADIO(0x0A2)
1034 #define BWN_B2063_LOGEN_MIXER2 BWN_LP_RADIO(0x0A4)
1035 #define BWN_B2063_LOGEN_BUF2 BWN_LP_RADIO(0x0A6)
1036 #define BWN_B2063_G_RX_MIX3 BWN_LP_RADIO(0x0C4)
1037 #define BWN_B2063_G_RX_MIX4 BWN_LP_RADIO(0x0C5)
1038 #define BWN_B2063_A_RX_1ST2 BWN_LP_RADIO(0x0CF)
1039 #define BWN_B2063_A_RX_1ST3 BWN_LP_RADIO(0x0D0)
1040 #define BWN_B2063_A_RX_2ND1 BWN_LP_RADIO(0x0D3)
1041 #define BWN_B2063_A_RX_2ND4 BWN_LP_RADIO(0x0D6)
1042 #define BWN_B2063_A_RX_2ND7 BWN_LP_RADIO(0x0D9)
1043 #define BWN_B2063_A_RX_PS6 BWN_LP_RADIO(0x0DF)
1044 #define BWN_B2063_A_RX_MIX4 BWN_LP_RADIO(0x0E3)
1045 #define BWN_B2063_A_RX_MIX5 BWN_LP_RADIO(0x0E4)
1046 #define BWN_B2063_A_RX_MIX6 BWN_LP_RADIO(0x0E5)
1047 #define BWN_B2063_RX_TIA_CTL1 BWN_LP_RADIO(0x0EC)
1048 #define BWN_B2063_RX_TIA_CTL3 BWN_LP_RADIO(0x0EE)
1049 #define BWN_B2063_RX_BB_CTL2 BWN_LP_RADIO(0x0F3)
1050 #define BWN_B2063_TX_RF_CTL2 BWN_LP_RADIO(0x100)
1051 #define BWN_B2063_TX_RF_CTL5 BWN_LP_RADIO(0x103)
1052 #define BWN_B2063_PA_CTL1 BWN_LP_RADIO(0x10B)
1053 #define BWN_B2063_PA_CTL11 BWN_LP_RADIO(0x115)
1054 #define BWN_B2063_VREG_CTL1 BWN_LP_RADIO(0x11D)
1058 #define BWN_TXH_PHY1_BW 0x0007 /* Bandwidth */
1059 #define BWN_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
1060 #define BWN_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
1061 #define BWN_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
1062 #define BWN_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
1063 #define BWN_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
1064 #define BWN_TXH_PHY1_BW_40DUP 0x0005 /* 40 MHz duplicate */
1065 #define BWN_TXH_PHY1_MODE 0x0038 /* Mode */
1066 #define BWN_TXH_PHY1_MODE_SISO 0x0000 /* SISO */
1067 #define BWN_TXH_PHY1_MODE_CDD 0x0008 /* CDD */
1068 #define BWN_TXH_PHY1_MODE_STBC 0x0010 /* STBC */
1069 #define BWN_TXH_PHY1_MODE_SDM 0x0018 /* SDM */
1070 #define BWN_TXH_PHY1_CRATE 0x0700 /* Coding rate */
1071 #define BWN_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */
1072 #define BWN_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */
1073 #define BWN_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */
1074 #define BWN_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */
1075 #define BWN_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */
1076 #define BWN_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */
1077 #define BWN_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */
1078 #define BWN_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */
1079 #define BWN_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */
1080 #define BWN_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */
1081 #define BWN_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */
1082 #define BWN_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */