Lines Matching +full:mac +full:-
1 /*-
2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
325 { 1, -66, 15 }, { 2, -66, 15 }, { 3, -66, 15 }, { 4, -66, 15 },
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344 { 192, -62, 25 }, { 196, -62, 25 }, { 200, -62, 25 }, { 204, -62, 25 },
345 { 208, -62, 25 }, { 212, -62, 25 }, { 216, -62, 26 },
348 static const struct bwn_rxcompco bwn_rxcompco_r2 = { 0, -64, 0 };
380 bwn_phy_lp_init_pre(struct bwn_mac *mac) in bwn_phy_lp_init_pre() argument
382 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_lp_init_pre()
383 struct bwn_phy_lp *plp = &phy->phy_lp; in bwn_phy_lp_init_pre()
385 plp->plp_antenna = BWN_ANT_DEFAULT; in bwn_phy_lp_init_pre()
389 bwn_phy_lp_init(struct bwn_mac *mac) in bwn_phy_lp_init() argument
408 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_init()
409 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_init()
411 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_init()
415 /* All LP-PHY devices have a PMU */ in bwn_phy_lp_init()
416 if (sc->sc_pmu == NULL) { in bwn_phy_lp_init()
417 device_printf(sc->sc_dev, "no PMU; cannot configure PAREF " in bwn_phy_lp_init()
422 if ((error = bwn_phy_lp_readsprom(mac))) in bwn_phy_lp_init()
425 bwn_phy_lp_bbinit(mac); in bwn_phy_lp_init()
428 BWN_PHY_SET(mac, BWN_PHY_4WIRECTL, 0x2); in bwn_phy_lp_init()
430 BWN_PHY_MASK(mac, BWN_PHY_4WIRECTL, 0xfffd); in bwn_phy_lp_init()
433 if (mac->mac_phy.rf_ver == 0x2062) { in bwn_phy_lp_init()
434 if ((error = bwn_phy_lp_b2062_init(mac))) in bwn_phy_lp_init()
437 if ((error = bwn_phy_lp_b2063_init(mac))) in bwn_phy_lp_init()
443 tmp = BWN_RF_READ(mac, st->st_rfaddr); in bwn_phy_lp_init()
444 tmp >>= st->st_rfshift; in bwn_phy_lp_init()
445 tmp <<= st->st_physhift; in bwn_phy_lp_init()
446 BWN_PHY_SETMASK(mac, in bwn_phy_lp_init()
447 BWN_PHY_OFDM(0xf2 + st->st_phyoffset), in bwn_phy_lp_init()
448 ~(st->st_mask << st->st_physhift), tmp); in bwn_phy_lp_init()
451 BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xf0), 0x5f80); in bwn_phy_lp_init()
452 BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xf1), 0); in bwn_phy_lp_init()
456 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_init()
457 if ((error = bwn_phy_lp_rxcal_r2(mac))) in bwn_phy_lp_init()
459 } else if (!plp->plp_rccap) { in bwn_phy_lp_init()
460 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_init()
461 if ((error = bwn_phy_lp_rccal_r12(mac))) in bwn_phy_lp_init()
465 bwn_phy_lp_set_rccap(mac); in bwn_phy_lp_init()
467 error = bwn_phy_lp_switch_channel(mac, 7); in bwn_phy_lp_init()
469 device_printf(sc->sc_dev, in bwn_phy_lp_init()
471 bwn_phy_lp_txpctl_init(mac); in bwn_phy_lp_init()
472 bwn_phy_lp_calib(mac); in bwn_phy_lp_init()
477 bwn_phy_lp_read(struct bwn_mac *mac, uint16_t reg) in bwn_phy_lp_read() argument
480 BWN_WRITE_2(mac, BWN_PHYCTL, reg); in bwn_phy_lp_read()
481 return (BWN_READ_2(mac, BWN_PHYDATA)); in bwn_phy_lp_read()
485 bwn_phy_lp_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) in bwn_phy_lp_write() argument
488 BWN_WRITE_2(mac, BWN_PHYCTL, reg); in bwn_phy_lp_write()
489 BWN_WRITE_2(mac, BWN_PHYDATA, value); in bwn_phy_lp_write()
493 bwn_phy_lp_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask, in bwn_phy_lp_maskset() argument
497 BWN_WRITE_2(mac, BWN_PHYCTL, reg); in bwn_phy_lp_maskset()
498 BWN_WRITE_2(mac, BWN_PHYDATA, in bwn_phy_lp_maskset()
499 (BWN_READ_2(mac, BWN_PHYDATA) & mask) | set); in bwn_phy_lp_maskset()
503 bwn_phy_lp_rf_read(struct bwn_mac *mac, uint16_t reg) in bwn_phy_lp_rf_read() argument
507 if (mac->mac_phy.rev < 2 && reg != 0x4001) in bwn_phy_lp_rf_read()
509 if (mac->mac_phy.rev >= 2) in bwn_phy_lp_rf_read()
511 BWN_WRITE_2(mac, BWN_RFCTL, reg); in bwn_phy_lp_rf_read()
512 return BWN_READ_2(mac, BWN_RFDATALO); in bwn_phy_lp_rf_read()
516 bwn_phy_lp_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) in bwn_phy_lp_rf_write() argument
520 BWN_WRITE_2(mac, BWN_RFCTL, reg); in bwn_phy_lp_rf_write()
521 BWN_WRITE_2(mac, BWN_RFDATALO, value); in bwn_phy_lp_rf_write()
525 bwn_phy_lp_rf_onoff(struct bwn_mac *mac, int on) in bwn_phy_lp_rf_onoff() argument
529 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xe0ff); in bwn_phy_lp_rf_onoff()
530 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, in bwn_phy_lp_rf_onoff()
531 (mac->mac_phy.rev >= 2) ? 0xf7f7 : 0xffe7); in bwn_phy_lp_rf_onoff()
535 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_rf_onoff()
536 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x83ff); in bwn_phy_lp_rf_onoff()
537 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x1f00); in bwn_phy_lp_rf_onoff()
538 BWN_PHY_MASK(mac, BWN_PHY_AFE_DDFS, 0x80ff); in bwn_phy_lp_rf_onoff()
539 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xdfff); in bwn_phy_lp_rf_onoff()
540 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x0808); in bwn_phy_lp_rf_onoff()
544 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xe0ff); in bwn_phy_lp_rf_onoff()
545 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x1f00); in bwn_phy_lp_rf_onoff()
546 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfcff); in bwn_phy_lp_rf_onoff()
547 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x0018); in bwn_phy_lp_rf_onoff()
551 bwn_phy_lp_switch_channel(struct bwn_mac *mac, uint32_t chan) in bwn_phy_lp_switch_channel() argument
553 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_lp_switch_channel()
554 struct bwn_phy_lp *plp = &phy->phy_lp; in bwn_phy_lp_switch_channel()
557 if (phy->rf_ver == 0x2063) { in bwn_phy_lp_switch_channel()
558 error = bwn_phy_lp_b2063_switch_channel(mac, chan); in bwn_phy_lp_switch_channel()
562 error = bwn_phy_lp_b2062_switch_channel(mac, chan); in bwn_phy_lp_switch_channel()
565 bwn_phy_lp_set_anafilter(mac, chan); in bwn_phy_lp_switch_channel()
566 bwn_phy_lp_set_gaintbl(mac, ieee80211_ieee2mhz(chan, 0)); in bwn_phy_lp_switch_channel()
569 plp->plp_chan = chan; in bwn_phy_lp_switch_channel()
570 BWN_WRITE_2(mac, BWN_CHANNEL, chan); in bwn_phy_lp_switch_channel()
575 bwn_phy_lp_get_default_chan(struct bwn_mac *mac) in bwn_phy_lp_get_default_chan() argument
577 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_get_default_chan()
578 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_get_default_chan()
580 return (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1 : 36); in bwn_phy_lp_get_default_chan()
584 bwn_phy_lp_set_antenna(struct bwn_mac *mac, int antenna) in bwn_phy_lp_set_antenna() argument
586 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_lp_set_antenna()
587 struct bwn_phy_lp *plp = &phy->phy_lp; in bwn_phy_lp_set_antenna()
589 if (phy->rev >= 2 || antenna > BWN_ANTAUTO1) in bwn_phy_lp_set_antenna()
592 bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_UCODE_ANTDIV_HELPER); in bwn_phy_lp_set_antenna()
593 BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xfffd, antenna & 0x2); in bwn_phy_lp_set_antenna()
594 BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xfffe, antenna & 0x1); in bwn_phy_lp_set_antenna()
595 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_UCODE_ANTDIV_HELPER); in bwn_phy_lp_set_antenna()
596 plp->plp_antenna = antenna; in bwn_phy_lp_set_antenna()
600 bwn_phy_lp_task_60s(struct bwn_mac *mac) in bwn_phy_lp_task_60s() argument
603 bwn_phy_lp_calib(mac); in bwn_phy_lp_task_60s()
607 bwn_phy_lp_readsprom(struct bwn_mac *mac) in bwn_phy_lp_readsprom() argument
609 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_readsprom()
610 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_readsprom()
611 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_readsprom()
625 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_readsprom()
626 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI2G, in bwn_phy_lp_readsprom()
627 &plp->plp_txisoband_m); in bwn_phy_lp_readsprom()
628 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA2G, in bwn_phy_lp_readsprom()
629 &plp->plp_bxarch); in bwn_phy_lp_readsprom()
630 BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO2G, in bwn_phy_lp_readsprom()
631 &plp->plp_rxpwroffset); in bwn_phy_lp_readsprom()
632 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF2G, in bwn_phy_lp_readsprom()
633 &plp->plp_rssivf); in bwn_phy_lp_readsprom()
634 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC2G, in bwn_phy_lp_readsprom()
635 &plp->plp_rssivc); in bwn_phy_lp_readsprom()
636 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV2G, in bwn_phy_lp_readsprom()
637 &plp->plp_rssigs); in bwn_phy_lp_readsprom()
642 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GL, in bwn_phy_lp_readsprom()
643 &plp->plp_txisoband_l); in bwn_phy_lp_readsprom()
644 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5G, in bwn_phy_lp_readsprom()
645 &plp->plp_txisoband_m); in bwn_phy_lp_readsprom()
646 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GH, in bwn_phy_lp_readsprom()
647 &plp->plp_txisoband_h); in bwn_phy_lp_readsprom()
648 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA5G, in bwn_phy_lp_readsprom()
649 &plp->plp_bxarch); in bwn_phy_lp_readsprom()
650 BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO5G, in bwn_phy_lp_readsprom()
651 &plp->plp_rxpwroffset); in bwn_phy_lp_readsprom()
652 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF5G, in bwn_phy_lp_readsprom()
653 &plp->plp_rssivf); in bwn_phy_lp_readsprom()
654 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC5G, in bwn_phy_lp_readsprom()
655 &plp->plp_rssivc); in bwn_phy_lp_readsprom()
656 BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV5G, in bwn_phy_lp_readsprom()
657 &plp->plp_rssigs); in bwn_phy_lp_readsprom()
665 bwn_phy_lp_bbinit(struct bwn_mac *mac) in bwn_phy_lp_bbinit() argument
668 bwn_phy_lp_tblinit(mac); in bwn_phy_lp_bbinit()
669 if (mac->mac_phy.rev >= 2) in bwn_phy_lp_bbinit()
670 bwn_phy_lp_bbinit_r2(mac); in bwn_phy_lp_bbinit()
672 bwn_phy_lp_bbinit_r01(mac); in bwn_phy_lp_bbinit()
676 bwn_phy_lp_txpctl_init(struct bwn_mac *mac) in bwn_phy_lp_txpctl_init() argument
680 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_txpctl_init()
681 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_txpctl_init()
683 bwn_phy_lp_set_txgain(mac, in bwn_phy_lp_txpctl_init()
684 IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? &gain_2ghz : &gain_5ghz); in bwn_phy_lp_txpctl_init()
685 bwn_phy_lp_set_bbmult(mac, 150); in bwn_phy_lp_txpctl_init()
689 bwn_phy_lp_calib(struct bwn_mac *mac) in bwn_phy_lp_calib() argument
691 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_calib()
692 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_calib()
693 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_calib()
699 if (plp->plp_chanfullcal != plp->plp_chan) { in bwn_phy_lp_calib()
700 plp->plp_chanfullcal = plp->plp_chan; in bwn_phy_lp_calib()
704 bwn_mac_suspend(mac); in bwn_phy_lp_calib()
707 BWN_WRITE_2(mac, BWN_BTCOEX_CTL, 0x3); in bwn_phy_lp_calib()
708 BWN_WRITE_2(mac, BWN_BTCOEX_TXCTL, 0xff); in bwn_phy_lp_calib()
710 if (mac->mac_phy.rev >= 2) in bwn_phy_lp_calib()
711 bwn_phy_lp_digflt_save(mac); in bwn_phy_lp_calib()
712 bwn_phy_lp_get_txpctlmode(mac); in bwn_phy_lp_calib()
713 mode = plp->plp_txpctlmode; in bwn_phy_lp_calib()
714 bwn_phy_lp_set_txpctlmode(mac, BWN_PHYLP_TXPCTL_OFF); in bwn_phy_lp_calib()
715 if (mac->mac_phy.rev == 0 && mode != BWN_PHYLP_TXPCTL_OFF) in bwn_phy_lp_calib()
716 bwn_phy_lp_bugfix(mac); in bwn_phy_lp_calib()
717 if (mac->mac_phy.rev >= 2 && fc == 1) { in bwn_phy_lp_calib()
718 bwn_phy_lp_get_txpctlmode(mac); in bwn_phy_lp_calib()
719 omode = plp->plp_txpctlmode; in bwn_phy_lp_calib()
720 oafeovr = BWN_PHY_READ(mac, BWN_PHY_AFE_CTL_OVR) & 0x40; in bwn_phy_lp_calib()
722 ogain = bwn_phy_lp_get_txgain(mac); in bwn_phy_lp_calib()
723 orf = BWN_PHY_READ(mac, BWN_PHY_RF_PWR_OVERRIDE) & 0xff; in bwn_phy_lp_calib()
724 obbmult = bwn_phy_lp_get_bbmult(mac); in bwn_phy_lp_calib()
725 bwn_phy_lp_set_txpctlmode(mac, BWN_PHYLP_TXPCTL_OFF); in bwn_phy_lp_calib()
727 bwn_phy_lp_set_txgain(mac, &ogain); in bwn_phy_lp_calib()
728 bwn_phy_lp_set_bbmult(mac, obbmult); in bwn_phy_lp_calib()
729 bwn_phy_lp_set_txpctlmode(mac, omode); in bwn_phy_lp_calib()
730 BWN_PHY_SETMASK(mac, BWN_PHY_RF_PWR_OVERRIDE, 0xff00, orf); in bwn_phy_lp_calib()
732 bwn_phy_lp_set_txpctlmode(mac, mode); in bwn_phy_lp_calib()
733 if (mac->mac_phy.rev >= 2) in bwn_phy_lp_calib()
734 bwn_phy_lp_digflt_restore(mac); in bwn_phy_lp_calib()
737 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) { in bwn_phy_lp_calib()
739 if (bwn_rxcompco_5354[i].rc_chan == plp->plp_chan) in bwn_phy_lp_calib()
742 } else if (mac->mac_phy.rev >= 2) in bwn_phy_lp_calib()
746 if (bwn_rxcompco_r12[i].rc_chan == plp->plp_chan) in bwn_phy_lp_calib()
753 BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0xff00, rc->rc_c1); in bwn_phy_lp_calib()
754 BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0x00ff, rc->rc_c0 << 8); in bwn_phy_lp_calib()
756 bwn_phy_lp_set_trsw_over(mac, 1 /* TX */, 0 /* RX */); in bwn_phy_lp_calib()
758 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_calib()
759 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x8); in bwn_phy_lp_calib()
760 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfff7, 0); in bwn_phy_lp_calib()
762 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x20); in bwn_phy_lp_calib()
763 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xffdf, 0); in bwn_phy_lp_calib()
766 bwn_phy_lp_set_rxgain(mac, 0x2d5d); in bwn_phy_lp_calib()
767 BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVR, 0xfffe); in bwn_phy_lp_calib()
768 BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVRVAL, 0xfffe); in bwn_phy_lp_calib()
769 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x800); in bwn_phy_lp_calib()
770 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x800); in bwn_phy_lp_calib()
771 bwn_phy_lp_set_deaf(mac, 0); in bwn_phy_lp_calib()
773 (void)bwn_phy_lp_calc_rx_iq_comp(mac, 0xfff0); in bwn_phy_lp_calib()
774 bwn_phy_lp_clear_deaf(mac, 0); in bwn_phy_lp_calib()
775 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xfffc); in bwn_phy_lp_calib()
776 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xfff7); in bwn_phy_lp_calib()
777 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xffdf); in bwn_phy_lp_calib()
780 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xfffe); in bwn_phy_lp_calib()
781 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xffef); in bwn_phy_lp_calib()
782 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xffbf); in bwn_phy_lp_calib()
783 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_calib()
784 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xfeff); in bwn_phy_lp_calib()
785 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_calib()
786 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xfbff); in bwn_phy_lp_calib()
787 BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xe5), 0xfff7); in bwn_phy_lp_calib()
790 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xfdff); in bwn_phy_lp_calib()
793 BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVR, 0xfffe); in bwn_phy_lp_calib()
794 BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVRVAL, 0xf7ff); in bwn_phy_lp_calib()
796 bwn_mac_enable(mac); in bwn_phy_lp_calib()
800 bwn_phy_lp_switch_analog(struct bwn_mac *mac, int on) in bwn_phy_lp_switch_analog() argument
804 BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVR, 0xfff8); in bwn_phy_lp_switch_analog()
808 BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVRVAL, 0x0007); in bwn_phy_lp_switch_analog()
809 BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVR, 0x0007); in bwn_phy_lp_switch_analog()
813 bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan) in bwn_phy_lp_b2063_switch_channel() argument
816 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2063_switch_channel()
832 error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal); in bwn_phy_lp_b2063_switch_channel()
834 device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", in bwn_phy_lp_b2063_switch_channel()
839 BWN_RF_WRITE(mac, BWN_B2063_LOGEN_VCOBUF1, bc->bc_data[0]); in bwn_phy_lp_b2063_switch_channel()
840 BWN_RF_WRITE(mac, BWN_B2063_LOGEN_MIXER2, bc->bc_data[1]); in bwn_phy_lp_b2063_switch_channel()
841 BWN_RF_WRITE(mac, BWN_B2063_LOGEN_BUF2, bc->bc_data[2]); in bwn_phy_lp_b2063_switch_channel()
842 BWN_RF_WRITE(mac, BWN_B2063_LOGEN_RCCR1, bc->bc_data[3]); in bwn_phy_lp_b2063_switch_channel()
843 BWN_RF_WRITE(mac, BWN_B2063_A_RX_1ST3, bc->bc_data[4]); in bwn_phy_lp_b2063_switch_channel()
844 BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND1, bc->bc_data[5]); in bwn_phy_lp_b2063_switch_channel()
845 BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND4, bc->bc_data[6]); in bwn_phy_lp_b2063_switch_channel()
846 BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND7, bc->bc_data[7]); in bwn_phy_lp_b2063_switch_channel()
847 BWN_RF_WRITE(mac, BWN_B2063_A_RX_PS6, bc->bc_data[8]); in bwn_phy_lp_b2063_switch_channel()
848 BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL2, bc->bc_data[9]); in bwn_phy_lp_b2063_switch_channel()
849 BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL5, bc->bc_data[10]); in bwn_phy_lp_b2063_switch_channel()
850 BWN_RF_WRITE(mac, BWN_B2063_PA_CTL11, bc->bc_data[11]); in bwn_phy_lp_b2063_switch_channel()
852 old = BWN_RF_READ(mac, BWN_B2063_COM15); in bwn_phy_lp_b2063_switch_channel()
853 BWN_RF_SET(mac, BWN_B2063_COM15, 0x1e); in bwn_phy_lp_b2063_switch_channel()
855 freqvco = bc->bc_freq << ((bc->bc_freq > 4000) ? 1 : 2); in bwn_phy_lp_b2063_switch_channel()
858 timeout = ((((8 * freqxtal) / (div * 5000000)) + 1) >> 1) - 1; in bwn_phy_lp_b2063_switch_channel()
862 BWN_RF_WRITE(mac, BWN_B2063_JTAG_VCO_CALIB3, 0x2); in bwn_phy_lp_b2063_switch_channel()
863 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_VCO_CALIB6, in bwn_phy_lp_b2063_switch_channel()
865 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_VCO_CALIB7, in bwn_phy_lp_b2063_switch_channel()
867 BWN_RF_WRITE(mac, BWN_B2063_JTAG_VCO_CALIB5, timeoutref); in bwn_phy_lp_b2063_switch_channel()
874 (timeoutref + 1)) - 1; in bwn_phy_lp_b2063_switch_channel()
875 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_VCO_CALIB7, in bwn_phy_lp_b2063_switch_channel()
877 BWN_RF_WRITE(mac, BWN_B2063_JTAG_VCO_CALIB8, count & 0xff); in bwn_phy_lp_b2063_switch_channel()
883 tmp[1] -= freqref; in bwn_phy_lp_b2063_switch_channel()
885 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_SG1, 0xffe0, tmp[0] >> 4); in bwn_phy_lp_b2063_switch_channel()
886 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_SG2, 0xfe0f, tmp[0] << 4); in bwn_phy_lp_b2063_switch_channel()
887 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_SG2, 0xfff0, tmp[0] >> 16); in bwn_phy_lp_b2063_switch_channel()
888 BWN_RF_WRITE(mac, BWN_B2063_JTAG_SG3, (tmp[1] >> 8) & 0xff); in bwn_phy_lp_b2063_switch_channel()
889 BWN_RF_WRITE(mac, BWN_B2063_JTAG_SG4, tmp[1] & 0xff); in bwn_phy_lp_b2063_switch_channel()
891 BWN_RF_WRITE(mac, BWN_B2063_JTAG_LF1, 0xb9); in bwn_phy_lp_b2063_switch_channel()
892 BWN_RF_WRITE(mac, BWN_B2063_JTAG_LF2, 0x88); in bwn_phy_lp_b2063_switch_channel()
893 BWN_RF_WRITE(mac, BWN_B2063_JTAG_LF3, 0x28); in bwn_phy_lp_b2063_switch_channel()
894 BWN_RF_WRITE(mac, BWN_B2063_JTAG_LF4, 0x63); in bwn_phy_lp_b2063_switch_channel()
896 tmp[2] = ((41 * (val[2] - 3000)) /1200) + 27; in bwn_phy_lp_b2063_switch_channel()
901 tmp[4] = ((tmp[3] + tmp[2]) / (tmp[2] << 1)) - 8; in bwn_phy_lp_b2063_switch_channel()
904 tmp[4] = ((tmp[3] + (tmp[2] >> 1)) / tmp[2]) - 8; in bwn_phy_lp_b2063_switch_channel()
906 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_CP2, 0xffc0, tmp[4]); in bwn_phy_lp_b2063_switch_channel()
907 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_CP2, 0xffbf, scale << 6); in bwn_phy_lp_b2063_switch_channel()
914 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_CP3, 0xffe0, tmp[5]); in bwn_phy_lp_b2063_switch_channel()
915 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_CP3, 0xffdf, scale << 5); in bwn_phy_lp_b2063_switch_channel()
917 BWN_RF_SETMASK(mac, BWN_B2063_JTAG_XTAL_12, 0xfffb, 0x4); in bwn_phy_lp_b2063_switch_channel()
919 BWN_RF_SET(mac, BWN_B2063_JTAG_XTAL_12, 0x2); in bwn_phy_lp_b2063_switch_channel()
921 BWN_RF_MASK(mac, BWN_B2063_JTAG_XTAL_12, 0xfd); in bwn_phy_lp_b2063_switch_channel()
924 BWN_RF_SET(mac, BWN_B2063_JTAG_VCO1, 0x2); in bwn_phy_lp_b2063_switch_channel()
926 BWN_RF_MASK(mac, BWN_B2063_JTAG_VCO1, 0xfd); in bwn_phy_lp_b2063_switch_channel()
928 BWN_RF_SET(mac, BWN_B2063_PLL_SP2, 0x3); in bwn_phy_lp_b2063_switch_channel()
930 BWN_RF_MASK(mac, BWN_B2063_PLL_SP2, 0xfffc); in bwn_phy_lp_b2063_switch_channel()
933 BWN_RF_MASK(mac, BWN_B2063_PLL_SP1, ~0x40); in bwn_phy_lp_b2063_switch_channel()
934 tmp16 = BWN_RF_READ(mac, BWN_B2063_JTAG_CALNRST) & 0xf8; in bwn_phy_lp_b2063_switch_channel()
935 BWN_RF_WRITE(mac, BWN_B2063_JTAG_CALNRST, tmp16); in bwn_phy_lp_b2063_switch_channel()
937 BWN_RF_WRITE(mac, BWN_B2063_JTAG_CALNRST, tmp16 | 0x4); in bwn_phy_lp_b2063_switch_channel()
939 BWN_RF_WRITE(mac, BWN_B2063_JTAG_CALNRST, tmp16 | 0x6); in bwn_phy_lp_b2063_switch_channel()
941 BWN_RF_WRITE(mac, BWN_B2063_JTAG_CALNRST, tmp16 | 0x7); in bwn_phy_lp_b2063_switch_channel()
943 BWN_RF_SET(mac, BWN_B2063_PLL_SP1, 0x40); in bwn_phy_lp_b2063_switch_channel()
945 BWN_RF_WRITE(mac, BWN_B2063_COM15, old); in bwn_phy_lp_b2063_switch_channel()
950 bwn_phy_lp_b2062_switch_channel(struct bwn_mac *mac, uint8_t chan) in bwn_phy_lp_b2062_switch_channel() argument
952 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2062_switch_channel()
953 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_b2062_switch_channel()
969 error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal); in bwn_phy_lp_b2062_switch_channel()
971 device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", in bwn_phy_lp_b2062_switch_channel()
976 BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL14, 0x04); in bwn_phy_lp_b2062_switch_channel()
977 BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE0, bc->bc_data[0]); in bwn_phy_lp_b2062_switch_channel()
978 BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE2, bc->bc_data[1]); in bwn_phy_lp_b2062_switch_channel()
979 BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE3, bc->bc_data[2]); in bwn_phy_lp_b2062_switch_channel()
980 BWN_RF_WRITE(mac, BWN_B2062_N_TX_TUNE, bc->bc_data[3]); in bwn_phy_lp_b2062_switch_channel()
981 BWN_RF_WRITE(mac, BWN_B2062_S_LGENG_CTL1, bc->bc_data[4]); in bwn_phy_lp_b2062_switch_channel()
982 BWN_RF_WRITE(mac, BWN_B2062_N_LGENACTL5, bc->bc_data[5]); in bwn_phy_lp_b2062_switch_channel()
983 BWN_RF_WRITE(mac, BWN_B2062_N_LGENACTL6, bc->bc_data[6]); in bwn_phy_lp_b2062_switch_channel()
984 BWN_RF_WRITE(mac, BWN_B2062_N_TX_PGA, bc->bc_data[7]); in bwn_phy_lp_b2062_switch_channel()
985 BWN_RF_WRITE(mac, BWN_B2062_N_TX_PAD, bc->bc_data[8]); in bwn_phy_lp_b2062_switch_channel()
987 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL33, 0xcc); in bwn_phy_lp_b2062_switch_channel()
988 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL34, 0x07); in bwn_phy_lp_b2062_switch_channel()
989 bwn_phy_lp_b2062_reset_pllbias(mac); in bwn_phy_lp_b2062_switch_channel()
991 tmp[1] = plp->plp_div * 1000; in bwn_phy_lp_b2062_switch_channel()
998 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL26, tmp[5]); in bwn_phy_lp_b2062_switch_channel()
1002 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL27, tmp[5]); in bwn_phy_lp_b2062_switch_channel()
1006 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL28, tmp[5]); in bwn_phy_lp_b2062_switch_channel()
1010 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL29, in bwn_phy_lp_b2062_switch_channel()
1012 tmp[7] = BWN_RF_READ(mac, BWN_B2062_S_RFPLLCTL19); in bwn_phy_lp_b2062_switch_channel()
1014 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL23, (tmp[8] >> 8) + 16); in bwn_phy_lp_b2062_switch_channel()
1015 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL24, tmp[8] & 0xff); in bwn_phy_lp_b2062_switch_channel()
1017 bwn_phy_lp_b2062_vco_calib(mac); in bwn_phy_lp_b2062_switch_channel()
1018 if (BWN_RF_READ(mac, BWN_B2062_S_RFPLLCTL3) & 0x10) { in bwn_phy_lp_b2062_switch_channel()
1019 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL33, 0xfc); in bwn_phy_lp_b2062_switch_channel()
1020 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL34, 0); in bwn_phy_lp_b2062_switch_channel()
1021 bwn_phy_lp_b2062_reset_pllbias(mac); in bwn_phy_lp_b2062_switch_channel()
1022 bwn_phy_lp_b2062_vco_calib(mac); in bwn_phy_lp_b2062_switch_channel()
1023 if (BWN_RF_READ(mac, BWN_B2062_S_RFPLLCTL3) & 0x10) { in bwn_phy_lp_b2062_switch_channel()
1024 BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL14, ~0x04); in bwn_phy_lp_b2062_switch_channel()
1028 BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL14, ~0x04); in bwn_phy_lp_b2062_switch_channel()
1033 bwn_phy_lp_set_anafilter(struct bwn_mac *mac, uint8_t channel) in bwn_phy_lp_set_anafilter() argument
1035 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_set_anafilter()
1038 if (mac->mac_phy.rev < 2) { in bwn_phy_lp_set_anafilter()
1039 BWN_PHY_SETMASK(mac, BWN_PHY_LP_PHY_CTL, 0xfcff, tmp << 9); in bwn_phy_lp_set_anafilter()
1040 if ((mac->mac_phy.rev == 1) && (plp->plp_rccap)) in bwn_phy_lp_set_anafilter()
1041 bwn_phy_lp_set_rccap(mac); in bwn_phy_lp_set_anafilter()
1045 BWN_RF_WRITE(mac, BWN_B2063_TX_BB_SP3, 0x3f); in bwn_phy_lp_set_anafilter()
1049 bwn_phy_lp_set_gaintbl(struct bwn_mac *mac, uint32_t freq) in bwn_phy_lp_set_gaintbl() argument
1051 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_set_gaintbl()
1052 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_set_gaintbl()
1053 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_set_gaintbl()
1056 KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); in bwn_phy_lp_set_gaintbl()
1058 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_set_gaintbl()
1059 iso = plp->plp_txisoband_m; in bwn_phy_lp_set_gaintbl()
1061 iso = plp->plp_txisoband_l; in bwn_phy_lp_set_gaintbl()
1063 iso = plp->plp_txisoband_m; in bwn_phy_lp_set_gaintbl()
1065 iso = plp->plp_txisoband_h; in bwn_phy_lp_set_gaintbl()
1067 tmp[0] = ((iso - 26) / 12) << 12; in bwn_phy_lp_set_gaintbl()
1071 bwn_tab_write_multi(mac, BWN_TAB_2(13, 0), 3, tmp); in bwn_phy_lp_set_gaintbl()
1072 bwn_tab_write_multi(mac, BWN_TAB_2(12, 0), 3, tmp); in bwn_phy_lp_set_gaintbl()
1076 bwn_phy_lp_digflt_save(struct bwn_mac *mac) in bwn_phy_lp_digflt_save() argument
1078 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_digflt_save()
1094 plp->plp_digfilt[i] = BWN_PHY_READ(mac, addr[i]); in bwn_phy_lp_digflt_save()
1095 BWN_PHY_WRITE(mac, addr[i], val[i]); in bwn_phy_lp_digflt_save()
1100 bwn_phy_lp_get_txpctlmode(struct bwn_mac *mac) in bwn_phy_lp_get_txpctlmode() argument
1102 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_get_txpctlmode()
1103 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_get_txpctlmode()
1106 ctl = BWN_PHY_READ(mac, BWN_PHY_TX_PWR_CTL_CMD); in bwn_phy_lp_get_txpctlmode()
1109 plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_OFF; in bwn_phy_lp_get_txpctlmode()
1112 plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_ON_SW; in bwn_phy_lp_get_txpctlmode()
1115 plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_ON_HW; in bwn_phy_lp_get_txpctlmode()
1118 plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_UNKNOWN; in bwn_phy_lp_get_txpctlmode()
1119 device_printf(sc->sc_dev, "unknown command mode\n"); in bwn_phy_lp_get_txpctlmode()
1125 bwn_phy_lp_set_txpctlmode(struct bwn_mac *mac, uint8_t mode) in bwn_phy_lp_set_txpctlmode() argument
1127 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_set_txpctlmode()
1131 bwn_phy_lp_get_txpctlmode(mac); in bwn_phy_lp_set_txpctlmode()
1132 old = plp->plp_txpctlmode; in bwn_phy_lp_set_txpctlmode()
1135 plp->plp_txpctlmode = mode; in bwn_phy_lp_set_txpctlmode()
1138 BWN_PHY_SETMASK(mac, BWN_PHY_TX_PWR_CTL_CMD, 0xff80, in bwn_phy_lp_set_txpctlmode()
1139 plp->plp_tssiidx); in bwn_phy_lp_set_txpctlmode()
1140 BWN_PHY_SETMASK(mac, BWN_PHY_TX_PWR_CTL_NNUM, in bwn_phy_lp_set_txpctlmode()
1141 0x8fff, ((uint16_t)plp->plp_tssinpt << 16)); in bwn_phy_lp_set_txpctlmode()
1144 if (mac->mac_phy.rev < 2) in bwn_phy_lp_set_txpctlmode()
1145 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xfeff); in bwn_phy_lp_set_txpctlmode()
1147 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xff7f); in bwn_phy_lp_set_txpctlmode()
1148 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xbfff); in bwn_phy_lp_set_txpctlmode()
1150 BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVR, 0xffbf); in bwn_phy_lp_set_txpctlmode()
1152 plp->plp_txpwridx = -1; in bwn_phy_lp_set_txpctlmode()
1154 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_set_txpctlmode()
1156 BWN_PHY_SET(mac, BWN_PHY_OFDM(0xd0), 0x2); in bwn_phy_lp_set_txpctlmode()
1158 BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xd0), 0xfffd); in bwn_phy_lp_set_txpctlmode()
1162 switch (plp->plp_txpctlmode) { in bwn_phy_lp_set_txpctlmode()
1176 BWN_PHY_SETMASK(mac, BWN_PHY_TX_PWR_CTL_CMD, in bwn_phy_lp_set_txpctlmode()
1181 bwn_phy_lp_bugfix(struct bwn_mac *mac) in bwn_phy_lp_bugfix() argument
1183 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_bugfix()
1184 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_bugfix()
1195 device_printf(sc->sc_dev, "failed to allocate buffer.\n"); in bwn_phy_lp_bugfix()
1199 bwn_phy_lp_get_txpctlmode(mac); in bwn_phy_lp_bugfix()
1200 mode = plp->plp_txpctlmode; in bwn_phy_lp_bugfix()
1201 txpwridx = plp->plp_txpwridx; in bwn_phy_lp_bugfix()
1202 tssinpt = plp->plp_tssinpt; in bwn_phy_lp_bugfix()
1203 tssiidx = plp->plp_tssiidx; in bwn_phy_lp_bugfix()
1205 bwn_tab_read_multi(mac, in bwn_phy_lp_bugfix()
1206 (mac->mac_phy.rev < 2) ? BWN_TAB_4(10, 0x140) : in bwn_phy_lp_bugfix()
1209 bwn_phy_lp_tblinit(mac); in bwn_phy_lp_bugfix()
1210 bwn_phy_lp_bbinit(mac); in bwn_phy_lp_bugfix()
1211 bwn_phy_lp_txpctl_init(mac); in bwn_phy_lp_bugfix()
1212 bwn_phy_lp_rf_onoff(mac, 1); in bwn_phy_lp_bugfix()
1213 bwn_phy_lp_set_txpctlmode(mac, BWN_PHYLP_TXPCTL_OFF); in bwn_phy_lp_bugfix()
1215 bwn_tab_write_multi(mac, in bwn_phy_lp_bugfix()
1216 (mac->mac_phy.rev < 2) ? BWN_TAB_4(10, 0x140) : in bwn_phy_lp_bugfix()
1219 BWN_WRITE_2(mac, BWN_CHANNEL, plp->plp_chan); in bwn_phy_lp_bugfix()
1220 plp->plp_tssinpt = tssinpt; in bwn_phy_lp_bugfix()
1221 plp->plp_tssiidx = tssiidx; in bwn_phy_lp_bugfix()
1222 bwn_phy_lp_set_anafilter(mac, plp->plp_chan); in bwn_phy_lp_bugfix()
1223 if (txpwridx != -1) { in bwn_phy_lp_bugfix()
1225 plp->plp_txpwridx = txpwridx; in bwn_phy_lp_bugfix()
1226 bwn_phy_lp_get_txpctlmode(mac); in bwn_phy_lp_bugfix()
1227 if (plp->plp_txpctlmode != BWN_PHYLP_TXPCTL_OFF) in bwn_phy_lp_bugfix()
1228 bwn_phy_lp_set_txpctlmode(mac, BWN_PHYLP_TXPCTL_ON_SW); in bwn_phy_lp_bugfix()
1229 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_bugfix()
1230 rxcomp = bwn_tab_read(mac, in bwn_phy_lp_bugfix()
1232 txgain = bwn_tab_read(mac, in bwn_phy_lp_bugfix()
1238 bwn_phy_lp_set_txgain(mac, &tg); in bwn_phy_lp_bugfix()
1240 rxcomp = bwn_tab_read(mac, in bwn_phy_lp_bugfix()
1242 txgain = bwn_tab_read(mac, in bwn_phy_lp_bugfix()
1244 BWN_PHY_SETMASK(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL, in bwn_phy_lp_bugfix()
1246 bwn_phy_lp_set_txgain_dac(mac, txgain & 0x7); in bwn_phy_lp_bugfix()
1247 bwn_phy_lp_set_txgain_pa(mac, (txgain >> 24) & 0x7f); in bwn_phy_lp_bugfix()
1249 bwn_phy_lp_set_bbmult(mac, (rxcomp >> 20) & 0xff); in bwn_phy_lp_bugfix()
1254 bwn_tab_write_multi(mac, BWN_TAB_2(0, 80), 2, value); in bwn_phy_lp_bugfix()
1256 coeff = bwn_tab_read(mac, in bwn_phy_lp_bugfix()
1257 (mac->mac_phy.rev >= 2) ? BWN_TAB_4(7, txpwridx + 448) : in bwn_phy_lp_bugfix()
1259 bwn_tab_write(mac, BWN_TAB_2(0, 85), coeff & 0xffff); in bwn_phy_lp_bugfix()
1260 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_bugfix()
1261 rfpwr = bwn_tab_read(mac, in bwn_phy_lp_bugfix()
1263 BWN_PHY_SETMASK(mac, BWN_PHY_RF_PWR_OVERRIDE, 0xff00, in bwn_phy_lp_bugfix()
1266 bwn_phy_lp_set_txgain_override(mac); in bwn_phy_lp_bugfix()
1268 if (plp->plp_rccap) in bwn_phy_lp_bugfix()
1269 bwn_phy_lp_set_rccap(mac); in bwn_phy_lp_bugfix()
1270 bwn_phy_lp_set_antenna(mac, plp->plp_antenna); in bwn_phy_lp_bugfix()
1271 bwn_phy_lp_set_txpctlmode(mac, mode); in bwn_phy_lp_bugfix()
1276 bwn_phy_lp_digflt_restore(struct bwn_mac *mac) in bwn_phy_lp_digflt_restore() argument
1278 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_digflt_restore()
1289 BWN_PHY_WRITE(mac, addr[i], plp->plp_digfilt[i]); in bwn_phy_lp_digflt_restore()
1293 bwn_phy_lp_tblinit(struct bwn_mac *mac) in bwn_phy_lp_tblinit() argument
1295 uint32_t freq = ieee80211_ieee2mhz(bwn_phy_lp_get_default_chan(mac), 0); in bwn_phy_lp_tblinit()
1297 if (mac->mac_phy.rev < 2) { in bwn_phy_lp_tblinit()
1298 bwn_phy_lp_tblinit_r01(mac); in bwn_phy_lp_tblinit()
1299 bwn_phy_lp_tblinit_txgain(mac); in bwn_phy_lp_tblinit()
1300 bwn_phy_lp_set_gaintbl(mac, freq); in bwn_phy_lp_tblinit()
1304 bwn_phy_lp_tblinit_r2(mac); in bwn_phy_lp_tblinit()
1305 bwn_phy_lp_tblinit_txgain(mac); in bwn_phy_lp_tblinit()
1320 bwn_phy_lp_bbinit_r2(struct bwn_mac *mac) in bwn_phy_lp_bbinit_r2() argument
1322 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_bbinit_r2()
1323 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_bbinit_r2()
1324 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_bbinit_r2()
1358 BWN_PHY_WRITE(mac, v1[i].reg, v1[i].value); in bwn_phy_lp_bbinit_r2()
1359 BWN_PHY_SET(mac, BWN_PHY_ADC_COMPENSATION_CTL, 0x10); in bwn_phy_lp_bbinit_r2()
1361 BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, v2[i].set); in bwn_phy_lp_bbinit_r2()
1363 BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x4000); in bwn_phy_lp_bbinit_r2()
1364 BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x2000); in bwn_phy_lp_bbinit_r2()
1365 BWN_PHY_SET(mac, BWN_PHY_OFDM(0x10a), 0x1); in bwn_phy_lp_bbinit_r2()
1366 if (sc->sc_board_info.board_rev >= 0x18) { in bwn_phy_lp_bbinit_r2()
1367 bwn_tab_write(mac, BWN_TAB_4(17, 65), 0xec); in bwn_phy_lp_bbinit_r2()
1368 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x14); in bwn_phy_lp_bbinit_r2()
1370 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x10); in bwn_phy_lp_bbinit_r2()
1372 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0xff00, 0xf4); in bwn_phy_lp_bbinit_r2()
1373 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0x00ff, 0xf100); in bwn_phy_lp_bbinit_r2()
1374 BWN_PHY_WRITE(mac, BWN_PHY_CLIPTHRESH, 0x48); in bwn_phy_lp_bbinit_r2()
1375 BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0xff00, 0x46); in bwn_phy_lp_bbinit_r2()
1376 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xe4), 0xff00, 0x10); in bwn_phy_lp_bbinit_r2()
1377 BWN_PHY_SETMASK(mac, BWN_PHY_PWR_THRESH1, 0xfff0, 0x9); in bwn_phy_lp_bbinit_r2()
1378 BWN_PHY_MASK(mac, BWN_PHY_GAINDIRECTMISMATCH, ~0xf); in bwn_phy_lp_bbinit_r2()
1379 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0x00ff, 0x5500); in bwn_phy_lp_bbinit_r2()
1380 BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0xa0); in bwn_phy_lp_bbinit_r2()
1381 BWN_PHY_SETMASK(mac, BWN_PHY_GAINDIRECTMISMATCH, 0xe0ff, 0x300); in bwn_phy_lp_bbinit_r2()
1382 BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2a00); in bwn_phy_lp_bbinit_r2()
1383 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && in bwn_phy_lp_bbinit_r2()
1384 sc->sc_cid.chip_pkg == 0) { in bwn_phy_lp_bbinit_r2()
1385 BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100); in bwn_phy_lp_bbinit_r2()
1386 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xa); in bwn_phy_lp_bbinit_r2()
1388 BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x1e00); in bwn_phy_lp_bbinit_r2()
1389 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xd); in bwn_phy_lp_bbinit_r2()
1392 BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, v3[i].set); in bwn_phy_lp_bbinit_r2()
1393 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && in bwn_phy_lp_bbinit_r2()
1394 sc->sc_cid.chip_pkg == 0) { in bwn_phy_lp_bbinit_r2()
1395 bwn_tab_write(mac, BWN_TAB_2(0x08, 0x14), 0); in bwn_phy_lp_bbinit_r2()
1396 bwn_tab_write(mac, BWN_TAB_2(0x08, 0x12), 0x40); in bwn_phy_lp_bbinit_r2()
1399 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_bbinit_r2()
1400 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x40); in bwn_phy_lp_bbinit_r2()
1401 BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xf0ff, 0xb00); in bwn_phy_lp_bbinit_r2()
1402 BWN_PHY_SETMASK(mac, BWN_PHY_SYNCPEAKCNT, 0xfff8, 0x6); in bwn_phy_lp_bbinit_r2()
1403 BWN_PHY_SETMASK(mac, BWN_PHY_MINPWR_LEVEL, 0x00ff, 0x9d00); in bwn_phy_lp_bbinit_r2()
1404 BWN_PHY_SETMASK(mac, BWN_PHY_MINPWR_LEVEL, 0xff00, 0xa1); in bwn_phy_lp_bbinit_r2()
1405 BWN_PHY_MASK(mac, BWN_PHY_IDLEAFTERPKTRXTO, 0x00ff); in bwn_phy_lp_bbinit_r2()
1407 BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x40); in bwn_phy_lp_bbinit_r2()
1409 BWN_PHY_SETMASK(mac, BWN_PHY_CRS_ED_THRESH, 0xff00, 0xb3); in bwn_phy_lp_bbinit_r2()
1410 BWN_PHY_SETMASK(mac, BWN_PHY_CRS_ED_THRESH, 0x00ff, 0xad00); in bwn_phy_lp_bbinit_r2()
1411 BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB, 0xff00, plp->plp_rxpwroffset); in bwn_phy_lp_bbinit_r2()
1412 BWN_PHY_SET(mac, BWN_PHY_RESET_CTL, 0x44); in bwn_phy_lp_bbinit_r2()
1413 BWN_PHY_WRITE(mac, BWN_PHY_RESET_CTL, 0x80); in bwn_phy_lp_bbinit_r2()
1414 BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, 0xa954); in bwn_phy_lp_bbinit_r2()
1415 BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_1, in bwn_phy_lp_bbinit_r2()
1416 0x2000 | ((uint16_t)plp->plp_rssigs << 10) | in bwn_phy_lp_bbinit_r2()
1417 ((uint16_t)plp->plp_rssivc << 4) | plp->plp_rssivf); in bwn_phy_lp_bbinit_r2()
1419 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && in bwn_phy_lp_bbinit_r2()
1420 sc->sc_cid.chip_pkg == 0) { in bwn_phy_lp_bbinit_r2()
1421 BWN_PHY_SET(mac, BWN_PHY_AFE_ADC_CTL_0, 0x1c); in bwn_phy_lp_bbinit_r2()
1422 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_CTL, 0x00ff, 0x8800); in bwn_phy_lp_bbinit_r2()
1423 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_1, 0xfc3c, 0x0400); in bwn_phy_lp_bbinit_r2()
1426 bwn_phy_lp_digflt_save(mac); in bwn_phy_lp_bbinit_r2()
1430 bwn_phy_lp_bbinit_r01(struct bwn_mac *mac) in bwn_phy_lp_bbinit_r01() argument
1432 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_bbinit_r01()
1433 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_bbinit_r01()
1434 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_bbinit_r01()
1495 BWN_PHY_MASK(mac, BWN_PHY_AFE_DAC_CTL, 0xf7ff); in bwn_phy_lp_bbinit_r01()
1496 BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL, 0); in bwn_phy_lp_bbinit_r01()
1497 BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL_OVR, 0); in bwn_phy_lp_bbinit_r01()
1498 BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_0, 0); in bwn_phy_lp_bbinit_r01()
1499 BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_2, 0); in bwn_phy_lp_bbinit_r01()
1500 BWN_PHY_SET(mac, BWN_PHY_AFE_DAC_CTL, 0x0004); in bwn_phy_lp_bbinit_r01()
1501 BWN_PHY_SETMASK(mac, BWN_PHY_OFDMSYNCTHRESH0, 0xff00, 0x0078); in bwn_phy_lp_bbinit_r01()
1502 BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0x83ff, 0x5800); in bwn_phy_lp_bbinit_r01()
1503 BWN_PHY_WRITE(mac, BWN_PHY_ADC_COMPENSATION_CTL, 0x0016); in bwn_phy_lp_bbinit_r01()
1504 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_0, 0xfff8, 0x0004); in bwn_phy_lp_bbinit_r01()
1505 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0x00ff, 0x5400); in bwn_phy_lp_bbinit_r01()
1506 BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2400); in bwn_phy_lp_bbinit_r01()
1507 BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100); in bwn_phy_lp_bbinit_r01()
1508 BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0x0006); in bwn_phy_lp_bbinit_r01()
1509 BWN_PHY_MASK(mac, BWN_PHY_RX_RADIO_CTL, 0xfffe); in bwn_phy_lp_bbinit_r01()
1511 BWN_PHY_SETMASK(mac, v1[i].offset, v1[i].mask, v1[i].set); in bwn_phy_lp_bbinit_r01()
1512 BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB, in bwn_phy_lp_bbinit_r01()
1513 0xff00, plp->plp_rxpwroffset); in bwn_phy_lp_bbinit_r01()
1514 if ((sc->sc_board_info.board_flags & BHND_BFL_FEM) && in bwn_phy_lp_bbinit_r01()
1515 ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) || in bwn_phy_lp_bbinit_r01()
1516 (sc->sc_board_info.board_flags & BHND_BFL_PAREF))) { in bwn_phy_lp_bbinit_r01()
1517 error = bhnd_pmu_set_voltage_raw(sc->sc_pmu, in bwn_phy_lp_bbinit_r01()
1520 device_printf(sc->sc_dev, "failed to set PAREF LDO " in bwn_phy_lp_bbinit_r01()
1523 error = bhnd_pmu_enable_regulator(sc->sc_pmu, in bwn_phy_lp_bbinit_r01()
1526 device_printf(sc->sc_dev, "failed to enable PAREF LDO " in bwn_phy_lp_bbinit_r01()
1529 if (mac->mac_phy.rev == 0) in bwn_phy_lp_bbinit_r01()
1530 BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, in bwn_phy_lp_bbinit_r01()
1532 bwn_tab_write(mac, BWN_TAB_2(11, 7), 60); in bwn_phy_lp_bbinit_r01()
1534 error = bhnd_pmu_disable_regulator(sc->sc_pmu, in bwn_phy_lp_bbinit_r01()
1537 device_printf(sc->sc_dev, "failed to disable PAREF LDO " in bwn_phy_lp_bbinit_r01()
1540 BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, 0xffcf, 0x0020); in bwn_phy_lp_bbinit_r01()
1541 bwn_tab_write(mac, BWN_TAB_2(11, 7), 100); in bwn_phy_lp_bbinit_r01()
1543 tmp = plp->plp_rssivf | plp->plp_rssivc << 4 | 0xa000; in bwn_phy_lp_bbinit_r01()
1544 BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, tmp); in bwn_phy_lp_bbinit_r01()
1545 if (sc->sc_board_info.board_flags & BHND_BFL_RSSIINV) in bwn_phy_lp_bbinit_r01()
1546 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x0aaa); in bwn_phy_lp_bbinit_r01()
1548 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x02aa); in bwn_phy_lp_bbinit_r01()
1549 bwn_tab_write(mac, BWN_TAB_2(11, 1), 24); in bwn_phy_lp_bbinit_r01()
1550 BWN_PHY_SETMASK(mac, BWN_PHY_RX_RADIO_CTL, in bwn_phy_lp_bbinit_r01()
1551 0xfff9, (plp->plp_bxarch << 1)); in bwn_phy_lp_bbinit_r01()
1552 if (mac->mac_phy.rev == 1 && in bwn_phy_lp_bbinit_r01()
1553 (sc->sc_board_info.board_flags & BHND_BFL_FEM_BT)) { in bwn_phy_lp_bbinit_r01()
1555 BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, in bwn_phy_lp_bbinit_r01()
1557 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) || in bwn_phy_lp_bbinit_r01()
1558 (sc->sc_board_info.board_type == 0x048a) || in bwn_phy_lp_bbinit_r01()
1559 ((mac->mac_phy.rev == 0) && in bwn_phy_lp_bbinit_r01()
1560 (sc->sc_board_info.board_flags & BHND_BFL_FEM))) { in bwn_phy_lp_bbinit_r01()
1562 BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, in bwn_phy_lp_bbinit_r01()
1564 } else if (mac->mac_phy.rev == 1 || in bwn_phy_lp_bbinit_r01()
1565 (sc->sc_board_info.board_flags & BHND_BFL_FEM)) { in bwn_phy_lp_bbinit_r01()
1567 BWN_PHY_SETMASK(mac, v4[i].offset, v4[i].mask, in bwn_phy_lp_bbinit_r01()
1571 BWN_PHY_SETMASK(mac, v5[i].offset, v5[i].mask, in bwn_phy_lp_bbinit_r01()
1574 if (mac->mac_phy.rev == 1 && in bwn_phy_lp_bbinit_r01()
1575 (sc->sc_board_info.board_flags & BHND_BFL_PAREF)) { in bwn_phy_lp_bbinit_r01()
1576 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_5, BWN_PHY_TR_LOOKUP_1); in bwn_phy_lp_bbinit_r01()
1577 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_6, BWN_PHY_TR_LOOKUP_2); in bwn_phy_lp_bbinit_r01()
1578 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_7, BWN_PHY_TR_LOOKUP_3); in bwn_phy_lp_bbinit_r01()
1579 BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_8, BWN_PHY_TR_LOOKUP_4); in bwn_phy_lp_bbinit_r01()
1581 if ((sc->sc_board_info.board_flags & BHND_BFL_FEM_BT) && in bwn_phy_lp_bbinit_r01()
1582 (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) && in bwn_phy_lp_bbinit_r01()
1583 (sc->sc_cid.chip_pkg == BHND_PKGID_BCM4712SMALL)) { in bwn_phy_lp_bbinit_r01()
1584 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0006); in bwn_phy_lp_bbinit_r01()
1585 BWN_PHY_WRITE(mac, BWN_PHY_GPIO_SELECT, 0x0005); in bwn_phy_lp_bbinit_r01()
1586 BWN_PHY_WRITE(mac, BWN_PHY_GPIO_OUTEN, 0xffff); in bwn_phy_lp_bbinit_r01()
1587 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_PR45960W); in bwn_phy_lp_bbinit_r01()
1589 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_bbinit_r01()
1590 BWN_PHY_SET(mac, BWN_PHY_LP_PHY_CTL, 0x8000); in bwn_phy_lp_bbinit_r01()
1591 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0040); in bwn_phy_lp_bbinit_r01()
1592 BWN_PHY_SETMASK(mac, BWN_PHY_MINPWR_LEVEL, 0x00ff, 0xa400); in bwn_phy_lp_bbinit_r01()
1593 BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xf0ff, 0x0b00); in bwn_phy_lp_bbinit_r01()
1594 BWN_PHY_SETMASK(mac, BWN_PHY_SYNCPEAKCNT, 0xfff8, 0x0007); in bwn_phy_lp_bbinit_r01()
1595 BWN_PHY_SETMASK(mac, BWN_PHY_DSSS_CONFIRM_CNT, 0xfff8, 0x0003); in bwn_phy_lp_bbinit_r01()
1596 BWN_PHY_SETMASK(mac, BWN_PHY_DSSS_CONFIRM_CNT, 0xffc7, 0x0020); in bwn_phy_lp_bbinit_r01()
1597 BWN_PHY_MASK(mac, BWN_PHY_IDLEAFTERPKTRXTO, 0x00ff); in bwn_phy_lp_bbinit_r01()
1599 BWN_PHY_MASK(mac, BWN_PHY_LP_PHY_CTL, 0x7fff); in bwn_phy_lp_bbinit_r01()
1600 BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, 0xffbf); in bwn_phy_lp_bbinit_r01()
1602 if (mac->mac_phy.rev == 1) { in bwn_phy_lp_bbinit_r01()
1603 tmp = BWN_PHY_READ(mac, BWN_PHY_CLIPCTRTHRESH); in bwn_phy_lp_bbinit_r01()
1606 BWN_PHY_WRITE(mac, BWN_PHY_4C3, tmp2); in bwn_phy_lp_bbinit_r01()
1607 tmp = BWN_PHY_READ(mac, BWN_PHY_GAINDIRECTMISMATCH); in bwn_phy_lp_bbinit_r01()
1610 BWN_PHY_WRITE(mac, BWN_PHY_4C4, tmp2); in bwn_phy_lp_bbinit_r01()
1611 tmp = BWN_PHY_READ(mac, BWN_PHY_VERYLOWGAINDB); in bwn_phy_lp_bbinit_r01()
1614 BWN_PHY_WRITE(mac, BWN_PHY_4C5, tmp2); in bwn_phy_lp_bbinit_r01()
1624 bwn_phy_lp_b2062_init(struct bwn_mac *mac) in bwn_phy_lp_b2062_init() argument
1627 (((800000000 * (div) + (freq)) / (2 * (freq)) - 8) & 0xff) in bwn_phy_lp_b2062_init()
1629 ((((100 * (freq) + 16000000 * (div)) / (32000000 * (div))) - 1) & 0xff) in bwn_phy_lp_b2062_init()
1631 ((((2 * (freq) + 1000000 * (div)) / (2000000 * (div))) - 1) & 0xff) in bwn_phy_lp_b2062_init()
1632 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_b2062_init()
1633 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2062_init()
1634 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_b2062_init()
1659 error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &xtalfreq); in bwn_phy_lp_b2062_init()
1661 device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", in bwn_phy_lp_b2062_init()
1666 bwn_phy_lp_b2062_tblinit(mac); in bwn_phy_lp_b2062_init()
1669 BWN_RF_WRITE(mac, v1[i].reg, v1[i].value); in bwn_phy_lp_b2062_init()
1670 if (mac->mac_phy.rev > 0) in bwn_phy_lp_b2062_init()
1671 BWN_RF_WRITE(mac, BWN_B2062_S_BG_CTL1, in bwn_phy_lp_b2062_init()
1672 (BWN_RF_READ(mac, BWN_B2062_N_COM2) >> 1) | 0x80); in bwn_phy_lp_b2062_init()
1673 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_b2062_init()
1674 BWN_RF_SET(mac, BWN_B2062_N_TSSI_CTL0, 0x1); in bwn_phy_lp_b2062_init()
1676 BWN_RF_MASK(mac, BWN_B2062_N_TSSI_CTL0, ~0x1); in bwn_phy_lp_b2062_init()
1679 plp->plp_div = 1; in bwn_phy_lp_b2062_init()
1680 BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL1, 0xfffb); in bwn_phy_lp_b2062_init()
1682 plp->plp_div = 2; in bwn_phy_lp_b2062_init()
1683 BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL1, 0x4); in bwn_phy_lp_b2062_init()
1686 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL7, in bwn_phy_lp_b2062_init()
1687 CALC_CTL7(xtalfreq, plp->plp_div)); in bwn_phy_lp_b2062_init()
1688 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL18, in bwn_phy_lp_b2062_init()
1689 CALC_CTL18(xtalfreq, plp->plp_div)); in bwn_phy_lp_b2062_init()
1690 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL19, in bwn_phy_lp_b2062_init()
1691 CALC_CTL19(xtalfreq, plp->plp_div)); in bwn_phy_lp_b2062_init()
1693 ref = (1000 * plp->plp_div + 2 * xtalfreq) / (2000 * plp->plp_div); in bwn_phy_lp_b2062_init()
1702 f = &freqdata_tab[N(freqdata_tab) - 1]; in bwn_phy_lp_b2062_init()
1703 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL8, in bwn_phy_lp_b2062_init()
1704 ((uint16_t)(f->value[1]) << 4) | f->value[0]); in bwn_phy_lp_b2062_init()
1705 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL9, in bwn_phy_lp_b2062_init()
1706 ((uint16_t)(f->value[3]) << 4) | f->value[2]); in bwn_phy_lp_b2062_init()
1707 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL10, f->value[4]); in bwn_phy_lp_b2062_init()
1708 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL11, f->value[5]); in bwn_phy_lp_b2062_init()
1717 bwn_phy_lp_b2063_init(struct bwn_mac *mac) in bwn_phy_lp_b2063_init() argument
1720 bwn_phy_lp_b2063_tblinit(mac); in bwn_phy_lp_b2063_init()
1721 BWN_RF_WRITE(mac, BWN_B2063_LOGEN_SP5, 0); in bwn_phy_lp_b2063_init()
1722 BWN_RF_SET(mac, BWN_B2063_COM8, 0x38); in bwn_phy_lp_b2063_init()
1723 BWN_RF_WRITE(mac, BWN_B2063_REG_SP1, 0x56); in bwn_phy_lp_b2063_init()
1724 BWN_RF_MASK(mac, BWN_B2063_RX_BB_CTL2, ~0x2); in bwn_phy_lp_b2063_init()
1725 BWN_RF_WRITE(mac, BWN_B2063_PA_SP7, 0); in bwn_phy_lp_b2063_init()
1726 BWN_RF_WRITE(mac, BWN_B2063_TX_RF_SP6, 0x20); in bwn_phy_lp_b2063_init()
1727 BWN_RF_WRITE(mac, BWN_B2063_TX_RF_SP9, 0x40); in bwn_phy_lp_b2063_init()
1728 if (mac->mac_phy.rev == 2) { in bwn_phy_lp_b2063_init()
1729 BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0xa0); in bwn_phy_lp_b2063_init()
1730 BWN_RF_WRITE(mac, BWN_B2063_PA_SP4, 0xa0); in bwn_phy_lp_b2063_init()
1731 BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x18); in bwn_phy_lp_b2063_init()
1733 BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0x20); in bwn_phy_lp_b2063_init()
1734 BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x20); in bwn_phy_lp_b2063_init()
1741 bwn_phy_lp_rxcal_r2(struct bwn_mac *mac) in bwn_phy_lp_rxcal_r2() argument
1743 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_rxcal_r2()
1765 error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal); in bwn_phy_lp_rxcal_r2()
1767 device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", in bwn_phy_lp_rxcal_r2()
1772 tmp = BWN_RF_READ(mac, BWN_B2063_RX_BB_SP8) & 0xff; in bwn_phy_lp_rxcal_r2()
1775 BWN_RF_WRITE(mac, v1[i].reg, v1[i].value); in bwn_phy_lp_rxcal_r2()
1776 BWN_RF_MASK(mac, BWN_B2063_PLL_SP1, 0xf7); in bwn_phy_lp_rxcal_r2()
1778 BWN_RF_WRITE(mac, v1[i].reg, v1[i].value); in bwn_phy_lp_rxcal_r2()
1780 if (BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2) in bwn_phy_lp_rxcal_r2()
1785 if (!(BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2)) in bwn_phy_lp_rxcal_r2()
1786 BWN_RF_WRITE(mac, BWN_B2063_RX_BB_SP8, tmp); in bwn_phy_lp_rxcal_r2()
1788 tmp = BWN_RF_READ(mac, BWN_B2063_TX_BB_SP3) & 0xff; in bwn_phy_lp_rxcal_r2()
1791 BWN_RF_WRITE(mac, v2[i].reg, v2[i].value); in bwn_phy_lp_rxcal_r2()
1793 BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL4, 0xfc); in bwn_phy_lp_rxcal_r2()
1794 BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL5, 0x0); in bwn_phy_lp_rxcal_r2()
1796 BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL4, 0x13); in bwn_phy_lp_rxcal_r2()
1797 BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL5, 0x1); in bwn_phy_lp_rxcal_r2()
1799 BWN_RF_WRITE(mac, BWN_B2063_PA_SP7, 0x7d); in bwn_phy_lp_rxcal_r2()
1801 if (BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2) in bwn_phy_lp_rxcal_r2()
1805 if (!(BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2)) in bwn_phy_lp_rxcal_r2()
1806 BWN_RF_WRITE(mac, BWN_B2063_TX_BB_SP3, tmp); in bwn_phy_lp_rxcal_r2()
1807 BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL1, 0x7e); in bwn_phy_lp_rxcal_r2()
1813 bwn_phy_lp_rccal_r12(struct bwn_mac *mac) in bwn_phy_lp_rccal_r12() argument
1815 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_rccal_r12()
1816 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_rccal_r12()
1830 error = bwn_phy_lp_switch_channel(mac, 7); in bwn_phy_lp_rccal_r12()
1832 device_printf(sc->sc_dev, in bwn_phy_lp_rccal_r12()
1834 txo = (BWN_PHY_READ(mac, BWN_PHY_AFE_CTL_OVR) & 0x40) ? 1 : 0; in bwn_phy_lp_rccal_r12()
1835 bbmult = bwn_phy_lp_get_bbmult(mac); in bwn_phy_lp_rccal_r12()
1837 tx_gains = bwn_phy_lp_get_txgain(mac); in bwn_phy_lp_rccal_r12()
1839 save[0] = BWN_PHY_READ(mac, BWN_PHY_RF_OVERRIDE_0); in bwn_phy_lp_rccal_r12()
1840 save[1] = BWN_PHY_READ(mac, BWN_PHY_RF_OVERRIDE_VAL_0); in bwn_phy_lp_rccal_r12()
1841 save[2] = BWN_PHY_READ(mac, BWN_PHY_AFE_CTL_OVR); in bwn_phy_lp_rccal_r12()
1842 save[3] = BWN_PHY_READ(mac, BWN_PHY_AFE_CTL_OVRVAL); in bwn_phy_lp_rccal_r12()
1843 save[4] = BWN_PHY_READ(mac, BWN_PHY_RF_OVERRIDE_2); in bwn_phy_lp_rccal_r12()
1844 save[5] = BWN_PHY_READ(mac, BWN_PHY_RF_OVERRIDE_2_VAL); in bwn_phy_lp_rccal_r12()
1845 save[6] = BWN_PHY_READ(mac, BWN_PHY_LP_PHY_CTL); in bwn_phy_lp_rccal_r12()
1847 bwn_phy_lp_get_txpctlmode(mac); in bwn_phy_lp_rccal_r12()
1848 txpctlmode = plp->plp_txpctlmode; in bwn_phy_lp_rccal_r12()
1849 bwn_phy_lp_set_txpctlmode(mac, BWN_PHYLP_TXPCTL_OFF); in bwn_phy_lp_rccal_r12()
1852 bwn_phy_lp_set_deaf(mac, 1); in bwn_phy_lp_rccal_r12()
1853 bwn_phy_lp_set_trsw_over(mac, 0, 1); in bwn_phy_lp_rccal_r12()
1854 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfffb); in bwn_phy_lp_rccal_r12()
1855 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x4); in bwn_phy_lp_rccal_r12()
1856 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfff7); in bwn_phy_lp_rccal_r12()
1857 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x8); in bwn_phy_lp_rccal_r12()
1858 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x10); in bwn_phy_lp_rccal_r12()
1859 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x10); in bwn_phy_lp_rccal_r12()
1860 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xffdf); in bwn_phy_lp_rccal_r12()
1861 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x20); in bwn_phy_lp_rccal_r12()
1862 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xffbf); in bwn_phy_lp_rccal_r12()
1863 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x40); in bwn_phy_lp_rccal_r12()
1864 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0x7); in bwn_phy_lp_rccal_r12()
1865 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0x38); in bwn_phy_lp_rccal_r12()
1866 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xff3f); in bwn_phy_lp_rccal_r12()
1867 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0x100); in bwn_phy_lp_rccal_r12()
1868 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfdff); in bwn_phy_lp_rccal_r12()
1869 BWN_PHY_WRITE(mac, BWN_PHY_PS_CTL_OVERRIDE_VAL0, 0); in bwn_phy_lp_rccal_r12()
1870 BWN_PHY_WRITE(mac, BWN_PHY_PS_CTL_OVERRIDE_VAL1, 1); in bwn_phy_lp_rccal_r12()
1871 BWN_PHY_WRITE(mac, BWN_PHY_PS_CTL_OVERRIDE_VAL2, 0x20); in bwn_phy_lp_rccal_r12()
1872 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfbff); in bwn_phy_lp_rccal_r12()
1873 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xf7ff); in bwn_phy_lp_rccal_r12()
1874 BWN_PHY_WRITE(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL, 0); in bwn_phy_lp_rccal_r12()
1875 BWN_PHY_WRITE(mac, BWN_PHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45af); in bwn_phy_lp_rccal_r12()
1876 BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_2, 0x3ff); in bwn_phy_lp_rccal_r12()
1878 loopback = bwn_phy_lp_loopback(mac); in bwn_phy_lp_rccal_r12()
1879 if (loopback == -1) in bwn_phy_lp_rccal_r12()
1881 bwn_phy_lp_set_rxgain_idx(mac, loopback); in bwn_phy_lp_rccal_r12()
1882 BWN_PHY_SETMASK(mac, BWN_PHY_LP_PHY_CTL, 0xffbf, 0x40); in bwn_phy_lp_rccal_r12()
1883 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfff8, 0x1); in bwn_phy_lp_rccal_r12()
1884 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xffc7, 0x8); in bwn_phy_lp_rccal_r12()
1885 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xff3f, 0xc0); in bwn_phy_lp_rccal_r12()
1890 BWN_RF_WRITE(mac, BWN_B2062_N_RXBB_CALIB2, i); in bwn_phy_lp_rccal_r12()
1893 bwn_phy_lp_ddfs_turnon(mac, 1, 1, j, j, 0); in bwn_phy_lp_rccal_r12()
1894 if (!(bwn_phy_lp_rx_iq_est(mac, 1000, 32, &ie))) in bwn_phy_lp_rccal_r12()
1897 ipwr = ((pwrtbl[j - 5] >> 3) + 1) >> 1; in bwn_phy_lp_rccal_r12()
1900 sum += ((ipwr - npwr) * (ipwr - npwr)); in bwn_phy_lp_rccal_r12()
1902 plp->plp_rccap = i; in bwn_phy_lp_rccal_r12()
1907 bwn_phy_lp_ddfs_turnoff(mac); in bwn_phy_lp_rccal_r12()
1910 bwn_phy_lp_clear_deaf(mac, 1); in bwn_phy_lp_rccal_r12()
1911 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xff80); in bwn_phy_lp_rccal_r12()
1912 BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xfc00); in bwn_phy_lp_rccal_r12()
1914 BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_VAL_0, save[1]); in bwn_phy_lp_rccal_r12()
1915 BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_0, save[0]); in bwn_phy_lp_rccal_r12()
1916 BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL_OVRVAL, save[3]); in bwn_phy_lp_rccal_r12()
1917 BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL_OVR, save[2]); in bwn_phy_lp_rccal_r12()
1918 BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_2_VAL, save[5]); in bwn_phy_lp_rccal_r12()
1919 BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_2, save[4]); in bwn_phy_lp_rccal_r12()
1920 BWN_PHY_WRITE(mac, BWN_PHY_LP_PHY_CTL, save[6]); in bwn_phy_lp_rccal_r12()
1922 bwn_phy_lp_set_bbmult(mac, bbmult); in bwn_phy_lp_rccal_r12()
1924 bwn_phy_lp_set_txgain(mac, &tx_gains); in bwn_phy_lp_rccal_r12()
1925 bwn_phy_lp_set_txpctlmode(mac, txpctlmode); in bwn_phy_lp_rccal_r12()
1926 if (plp->plp_rccap) in bwn_phy_lp_rccal_r12()
1927 bwn_phy_lp_set_rccap(mac); in bwn_phy_lp_rccal_r12()
1933 bwn_phy_lp_set_rccap(struct bwn_mac *mac) in bwn_phy_lp_set_rccap() argument
1935 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_set_rccap()
1936 uint8_t rc_cap = (plp->plp_rccap & 0x1f) >> 1; in bwn_phy_lp_set_rccap()
1938 if (mac->mac_phy.rev == 1) in bwn_phy_lp_set_rccap()
1941 BWN_RF_WRITE(mac, BWN_B2062_N_RXBB_CALIB2, in bwn_phy_lp_set_rccap()
1942 MAX(plp->plp_rccap - 4, 0x80)); in bwn_phy_lp_set_rccap()
1943 BWN_RF_WRITE(mac, BWN_B2062_N_TXCTL_A, rc_cap | 0x80); in bwn_phy_lp_set_rccap()
1944 BWN_RF_WRITE(mac, BWN_B2062_S_RXG_CNT16, in bwn_phy_lp_set_rccap()
1945 ((plp->plp_rccap & 0x1f) >> 2) | 0x80); in bwn_phy_lp_set_rccap()
1960 r = (r << 1) - div; in bwn_phy_lp_roundup()
1969 bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *mac) in bwn_phy_lp_b2062_reset_pllbias() argument
1971 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2062_reset_pllbias()
1973 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0xff); in bwn_phy_lp_b2062_reset_pllbias()
1975 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) { in bwn_phy_lp_b2062_reset_pllbias()
1976 BWN_RF_WRITE(mac, BWN_B2062_N_COM1, 4); in bwn_phy_lp_b2062_reset_pllbias()
1977 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 4); in bwn_phy_lp_b2062_reset_pllbias()
1979 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0); in bwn_phy_lp_b2062_reset_pllbias()
1985 bwn_phy_lp_b2062_vco_calib(struct bwn_mac *mac) in bwn_phy_lp_b2062_vco_calib() argument
1988 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL21, 0x42); in bwn_phy_lp_b2062_vco_calib()
1989 BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL21, 0x62); in bwn_phy_lp_b2062_vco_calib()
1994 bwn_phy_lp_b2062_tblinit(struct bwn_mac *mac) in bwn_phy_lp_b2062_tblinit() argument
1998 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2062_tblinit()
1999 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_b2062_tblinit()
2054 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_b2062_tblinit()
2055 if (br->br_flags & FLAG_G) in bwn_phy_lp_b2062_tblinit()
2056 BWN_RF_WRITE(mac, br->br_offset, br->br_valueg); in bwn_phy_lp_b2062_tblinit()
2058 if (br->br_flags & FLAG_A) in bwn_phy_lp_b2062_tblinit()
2059 BWN_RF_WRITE(mac, br->br_offset, br->br_valuea); in bwn_phy_lp_b2062_tblinit()
2067 bwn_phy_lp_b2063_tblinit(struct bwn_mac *mac) in bwn_phy_lp_b2063_tblinit() argument
2071 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_b2063_tblinit()
2072 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_b2063_tblinit()
2122 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_b2063_tblinit()
2123 if (br->br_flags & FLAG_G) in bwn_phy_lp_b2063_tblinit()
2124 BWN_RF_WRITE(mac, br->br_offset, br->br_valueg); in bwn_phy_lp_b2063_tblinit()
2126 if (br->br_flags & FLAG_A) in bwn_phy_lp_b2063_tblinit()
2127 BWN_RF_WRITE(mac, br->br_offset, br->br_valuea); in bwn_phy_lp_b2063_tblinit()
2135 bwn_tab_read_multi(struct bwn_mac *mac, uint32_t typenoffset, in bwn_tab_read_multi() argument
2146 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_read_multi()
2151 *data = BWN_PHY_READ(mac, BWN_PHY_TABLEDATALO) & 0xff; in bwn_tab_read_multi()
2155 *((uint16_t *)data) = BWN_PHY_READ(mac, in bwn_tab_read_multi()
2160 *((uint32_t *)data) = BWN_PHY_READ(mac, in bwn_tab_read_multi()
2163 *((uint32_t *)data) |= BWN_PHY_READ(mac, in bwn_tab_read_multi()
2174 bwn_tab_write_multi(struct bwn_mac *mac, uint32_t typenoffset, in bwn_tab_write_multi() argument
2185 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_write_multi()
2194 BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); in bwn_tab_write_multi()
2201 BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); in bwn_tab_write_multi()
2206 BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATAHI, value >> 16); in bwn_tab_write_multi()
2207 BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); in bwn_tab_write_multi()
2216 bwn_phy_lp_get_txgain(struct bwn_mac *mac) in bwn_phy_lp_get_txgain() argument
2221 tg.tg_dac = (BWN_PHY_READ(mac, BWN_PHY_AFE_DAC_CTL) & 0x380) >> 7; in bwn_phy_lp_get_txgain()
2222 if (mac->mac_phy.rev < 2) { in bwn_phy_lp_get_txgain()
2223 tmp = BWN_PHY_READ(mac, in bwn_phy_lp_get_txgain()
2231 tmp = BWN_PHY_READ(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL); in bwn_phy_lp_get_txgain()
2232 tg.tg_pad = BWN_PHY_READ(mac, BWN_PHY_OFDM(0xfb)) & 0xff; in bwn_phy_lp_get_txgain()
2239 bwn_phy_lp_get_bbmult(struct bwn_mac *mac) in bwn_phy_lp_get_bbmult() argument
2242 return (bwn_tab_read(mac, BWN_TAB_2(0, 87)) & 0xff00) >> 8; in bwn_phy_lp_get_bbmult()
2246 bwn_phy_lp_set_txgain(struct bwn_mac *mac, struct bwn_txgain *tg) in bwn_phy_lp_set_txgain() argument
2250 if (mac->mac_phy.rev < 2) { in bwn_phy_lp_set_txgain()
2251 BWN_PHY_SETMASK(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL, 0xf800, in bwn_phy_lp_set_txgain()
2252 (tg->tg_pad << 7) | (tg->tg_pga << 3) | tg->tg_gm); in bwn_phy_lp_set_txgain()
2253 bwn_phy_lp_set_txgain_dac(mac, tg->tg_dac); in bwn_phy_lp_set_txgain()
2254 bwn_phy_lp_set_txgain_override(mac); in bwn_phy_lp_set_txgain()
2258 pa = bwn_phy_lp_get_pa_gain(mac); in bwn_phy_lp_set_txgain()
2259 BWN_PHY_WRITE(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL, in bwn_phy_lp_set_txgain()
2260 (tg->tg_pga << 8) | tg->tg_gm); in bwn_phy_lp_set_txgain()
2261 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfb), 0x8000, in bwn_phy_lp_set_txgain()
2262 tg->tg_pad | (pa << 6)); in bwn_phy_lp_set_txgain()
2263 BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xfc), (tg->tg_pga << 8) | tg->tg_gm); in bwn_phy_lp_set_txgain()
2264 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfd), 0x8000, in bwn_phy_lp_set_txgain()
2265 tg->tg_pad | (pa << 8)); in bwn_phy_lp_set_txgain()
2266 bwn_phy_lp_set_txgain_dac(mac, tg->tg_dac); in bwn_phy_lp_set_txgain()
2267 bwn_phy_lp_set_txgain_override(mac); in bwn_phy_lp_set_txgain()
2271 bwn_phy_lp_set_bbmult(struct bwn_mac *mac, uint8_t bbmult) in bwn_phy_lp_set_bbmult() argument
2274 bwn_tab_write(mac, BWN_TAB_2(0, 87), (uint16_t)bbmult << 8); in bwn_phy_lp_set_bbmult()
2278 bwn_phy_lp_set_trsw_over(struct bwn_mac *mac, uint8_t tx, uint8_t rx) in bwn_phy_lp_set_trsw_over() argument
2282 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfffc, trsw); in bwn_phy_lp_set_trsw_over()
2283 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x3); in bwn_phy_lp_set_trsw_over()
2287 bwn_phy_lp_set_rxgain(struct bwn_mac *mac, uint32_t gain) in bwn_phy_lp_set_rxgain() argument
2289 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_set_rxgain()
2290 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_set_rxgain()
2293 if (mac->mac_phy.rev < 2) { in bwn_phy_lp_set_rxgain()
2298 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfffe, trsw); in bwn_phy_lp_set_rxgain()
2299 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, in bwn_phy_lp_set_rxgain()
2301 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, in bwn_phy_lp_set_rxgain()
2303 BWN_PHY_WRITE(mac, BWN_PHY_RX_GAIN_CTL_OVERRIDE_VAL, lna); in bwn_phy_lp_set_rxgain()
2310 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfffe, trsw); in bwn_phy_lp_set_rxgain()
2311 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, in bwn_phy_lp_set_rxgain()
2313 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, in bwn_phy_lp_set_rxgain()
2315 BWN_PHY_WRITE(mac, BWN_PHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain); in bwn_phy_lp_set_rxgain()
2316 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS, 0xfff0, high_gain); in bwn_phy_lp_set_rxgain()
2317 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_set_rxgain()
2319 BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, in bwn_phy_lp_set_rxgain()
2321 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xe6), 0xffe7, in bwn_phy_lp_set_rxgain()
2326 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x1); in bwn_phy_lp_set_rxgain()
2327 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x10); in bwn_phy_lp_set_rxgain()
2328 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x40); in bwn_phy_lp_set_rxgain()
2329 if (mac->mac_phy.rev >= 2) { in bwn_phy_lp_set_rxgain()
2330 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x100); in bwn_phy_lp_set_rxgain()
2331 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { in bwn_phy_lp_set_rxgain()
2332 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x400); in bwn_phy_lp_set_rxgain()
2333 BWN_PHY_SET(mac, BWN_PHY_OFDM(0xe5), 0x8); in bwn_phy_lp_set_rxgain()
2337 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x200); in bwn_phy_lp_set_rxgain()
2341 bwn_phy_lp_set_deaf(struct bwn_mac *mac, uint8_t user) in bwn_phy_lp_set_deaf() argument
2343 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_set_deaf()
2346 plp->plp_crsusr_off = 1; in bwn_phy_lp_set_deaf()
2348 plp->plp_crssys_off = 1; in bwn_phy_lp_set_deaf()
2350 BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xff1f, 0x80); in bwn_phy_lp_set_deaf()
2354 bwn_phy_lp_clear_deaf(struct bwn_mac *mac, uint8_t user) in bwn_phy_lp_clear_deaf() argument
2356 struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; in bwn_phy_lp_clear_deaf()
2357 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_clear_deaf()
2358 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_clear_deaf()
2361 plp->plp_crsusr_off = 0; in bwn_phy_lp_clear_deaf()
2363 plp->plp_crssys_off = 0; in bwn_phy_lp_clear_deaf()
2365 if (plp->plp_crsusr_off || plp->plp_crssys_off) in bwn_phy_lp_clear_deaf()
2368 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_clear_deaf()
2369 BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xff1f, 0x60); in bwn_phy_lp_clear_deaf()
2371 BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xff1f, 0x20); in bwn_phy_lp_clear_deaf()
2375 bwn_phy_lp_calc_rx_iq_comp(struct bwn_mac *mac, uint16_t sample) in bwn_phy_lp_calc_rx_iq_comp() argument
2379 _t = _x - 20; \ in bwn_phy_lp_calc_rx_iq_comp()
2381 _v = ((_y << (30 - _x)) + (_z >> (1 + _t))) / (_z >> _t); \ in bwn_phy_lp_calc_rx_iq_comp()
2383 _v = ((_y << (30 - _x)) + (_z << (-1 - _t))) / (_z << -_t); \ in bwn_phy_lp_calc_rx_iq_comp()
2388 _t = _x - 11; \ in bwn_phy_lp_calc_rx_iq_comp()
2390 _v = (_y << (31 - _x)) / (_z >> _t); \ in bwn_phy_lp_calc_rx_iq_comp()
2392 _v = (_y << (31 - _x)) / (_z << -_t); \ in bwn_phy_lp_calc_rx_iq_comp()
2398 v1 = BWN_PHY_READ(mac, BWN_PHY_RX_COMP_COEFF_S); in bwn_phy_lp_calc_rx_iq_comp()
2402 BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0xff00, 0x00c0); in bwn_phy_lp_calc_rx_iq_comp()
2403 BWN_PHY_MASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0x00ff); in bwn_phy_lp_calc_rx_iq_comp()
2405 ret = bwn_phy_lp_rx_iq_est(mac, sample, 32, &ie); in bwn_phy_lp_calc_rx_iq_comp()
2417 tmp[1] = -bwn_sqrt(mac, tmp[1] - (tmp[0] * tmp[0])); in bwn_phy_lp_calc_rx_iq_comp()
2421 BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0xff00, v1); in bwn_phy_lp_calc_rx_iq_comp()
2422 BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0x00ff, v0 << 8); in bwn_phy_lp_calc_rx_iq_comp()
2429 bwn_phy_lp_tblinit_r01(struct bwn_mac *mac) in bwn_phy_lp_tblinit_r01() argument
2596 KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); in bwn_phy_lp_tblinit_r01()
2598 bwn_tab_write_multi(mac, BWN_TAB_1(2, 0), N(bwn_tab_sigsq_tbl), in bwn_phy_lp_tblinit_r01()
2600 bwn_tab_write_multi(mac, BWN_TAB_2(1, 0), N(noisescale), noisescale); in bwn_phy_lp_tblinit_r01()
2601 bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(crsgainnft), crsgainnft); in bwn_phy_lp_tblinit_r01()
2602 bwn_tab_write_multi(mac, BWN_TAB_2(8, 0), N(filterctl), filterctl); in bwn_phy_lp_tblinit_r01()
2603 bwn_tab_write_multi(mac, BWN_TAB_4(9, 0), N(psctl), psctl); in bwn_phy_lp_tblinit_r01()
2604 bwn_tab_write_multi(mac, BWN_TAB_1(6, 0), N(bwn_tab_pllfrac_tbl), in bwn_phy_lp_tblinit_r01()
2606 bwn_tab_write_multi(mac, BWN_TAB_2(0, 0), N(bwn_tabl_iqlocal_tbl), in bwn_phy_lp_tblinit_r01()
2608 if (mac->mac_phy.rev == 0) { in bwn_phy_lp_tblinit_r01()
2609 bwn_tab_write_multi(mac, BWN_TAB_2(13, 0), N(ofdmcckgain_r0), in bwn_phy_lp_tblinit_r01()
2611 bwn_tab_write_multi(mac, BWN_TAB_2(12, 0), N(ofdmcckgain_r0), in bwn_phy_lp_tblinit_r01()
2614 bwn_tab_write_multi(mac, BWN_TAB_2(13, 0), N(ofdmcckgain_r1), in bwn_phy_lp_tblinit_r01()
2616 bwn_tab_write_multi(mac, BWN_TAB_2(12, 0), N(ofdmcckgain_r1), in bwn_phy_lp_tblinit_r01()
2619 bwn_tab_write_multi(mac, BWN_TAB_2(15, 0), N(gaindelta), gaindelta); in bwn_phy_lp_tblinit_r01()
2620 bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(txpwrctl), txpwrctl); in bwn_phy_lp_tblinit_r01()
2624 bwn_phy_lp_tblinit_r2(struct bwn_mac *mac) in bwn_phy_lp_tblinit_r2() argument
2626 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_tblinit_r2()
2811 KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); in bwn_phy_lp_tblinit_r2()
2814 bwn_tab_write(mac, BWN_TAB_4(7, i), 0); in bwn_phy_lp_tblinit_r2()
2816 bwn_tab_write_multi(mac, BWN_TAB_1(2, 0), N(bwn_tab_sigsq_tbl), in bwn_phy_lp_tblinit_r2()
2818 bwn_tab_write_multi(mac, BWN_TAB_2(1, 0), N(noisescale), noisescale); in bwn_phy_lp_tblinit_r2()
2819 bwn_tab_write_multi(mac, BWN_TAB_4(11, 0), N(filterctl), filterctl); in bwn_phy_lp_tblinit_r2()
2820 bwn_tab_write_multi(mac, BWN_TAB_4(12, 0), N(psctl), psctl); in bwn_phy_lp_tblinit_r2()
2821 bwn_tab_write_multi(mac, BWN_TAB_4(13, 0), N(gainidx), gainidx); in bwn_phy_lp_tblinit_r2()
2822 bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(auxgainidx), auxgainidx); in bwn_phy_lp_tblinit_r2()
2823 bwn_tab_write_multi(mac, BWN_TAB_2(15, 0), N(swctl), swctl); in bwn_phy_lp_tblinit_r2()
2824 bwn_tab_write_multi(mac, BWN_TAB_1(16, 0), N(hf), hf); in bwn_phy_lp_tblinit_r2()
2825 bwn_tab_write_multi(mac, BWN_TAB_4(17, 0), N(gainval), gainval); in bwn_phy_lp_tblinit_r2()
2826 bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain), gain); in bwn_phy_lp_tblinit_r2()
2827 bwn_tab_write_multi(mac, BWN_TAB_1(6, 0), N(bwn_tab_pllfrac_tbl), in bwn_phy_lp_tblinit_r2()
2829 bwn_tab_write_multi(mac, BWN_TAB_2(0, 0), N(bwn_tabl_iqlocal_tbl), in bwn_phy_lp_tblinit_r2()
2831 bwn_tab_write_multi(mac, BWN_TAB_4(9, 0), N(papdeps), papdeps); in bwn_phy_lp_tblinit_r2()
2832 bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(papdmult), papdmult); in bwn_phy_lp_tblinit_r2()
2834 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && in bwn_phy_lp_tblinit_r2()
2835 sc->sc_cid.chip_pkg == 0) { in bwn_phy_lp_tblinit_r2()
2836 bwn_tab_write_multi(mac, BWN_TAB_4(13, 0), N(gainidx_a0), in bwn_phy_lp_tblinit_r2()
2838 bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(auxgainidx_a0), in bwn_phy_lp_tblinit_r2()
2840 bwn_tab_write_multi(mac, BWN_TAB_4(17, 0), N(gainval_a0), in bwn_phy_lp_tblinit_r2()
2842 bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain_a0), gain_a0); in bwn_phy_lp_tblinit_r2()
2847 bwn_phy_lp_tblinit_txgain(struct bwn_mac *mac) in bwn_phy_lp_tblinit_txgain() argument
2849 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_tblinit_txgain()
2850 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_tblinit_txgain()
3451 if (mac->mac_phy.rev != 0 && mac->mac_phy.rev != 1) { in bwn_phy_lp_tblinit_txgain()
3452 if (sc->sc_board_info.board_flags & BHND_BFL_NOPA) in bwn_phy_lp_tblinit_txgain()
3453 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r2); in bwn_phy_lp_tblinit_txgain()
3454 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_tblinit_txgain()
3455 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, in bwn_phy_lp_tblinit_txgain()
3458 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, in bwn_phy_lp_tblinit_txgain()
3463 if (mac->mac_phy.rev == 0) { in bwn_phy_lp_tblinit_txgain()
3464 if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) || in bwn_phy_lp_tblinit_txgain()
3465 (sc->sc_board_info.board_flags & BHND_BFL_HGPA)) in bwn_phy_lp_tblinit_txgain()
3466 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r0); in bwn_phy_lp_tblinit_txgain()
3467 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_tblinit_txgain()
3468 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, in bwn_phy_lp_tblinit_txgain()
3471 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, in bwn_phy_lp_tblinit_txgain()
3476 if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) || in bwn_phy_lp_tblinit_txgain()
3477 (sc->sc_board_info.board_flags & BHND_BFL_HGPA)) in bwn_phy_lp_tblinit_txgain()
3478 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r1); in bwn_phy_lp_tblinit_txgain()
3479 else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) in bwn_phy_lp_tblinit_txgain()
3480 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_2ghz_r1); in bwn_phy_lp_tblinit_txgain()
3482 bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_5ghz_r1); in bwn_phy_lp_tblinit_txgain()
3486 bwn_tab_write(struct bwn_mac *mac, uint32_t typeoffset, uint32_t value) in bwn_tab_write() argument
3497 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_write()
3498 BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); in bwn_tab_write()
3503 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_write()
3504 BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); in bwn_tab_write()
3507 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_write()
3508 BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATAHI, value >> 16); in bwn_tab_write()
3509 BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); in bwn_tab_write()
3517 bwn_phy_lp_loopback(struct bwn_mac *mac) in bwn_phy_lp_loopback() argument
3520 int i, index = -1; in bwn_phy_lp_loopback()
3525 bwn_phy_lp_set_trsw_over(mac, 1, 1); in bwn_phy_lp_loopback()
3526 BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVR, 1); in bwn_phy_lp_loopback()
3527 BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVRVAL, 0xfffe); in bwn_phy_lp_loopback()
3528 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x800); in bwn_phy_lp_loopback()
3529 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x800); in bwn_phy_lp_loopback()
3530 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x8); in bwn_phy_lp_loopback()
3531 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x8); in bwn_phy_lp_loopback()
3532 BWN_RF_WRITE(mac, BWN_B2062_N_TXCTL_A, 0x80); in bwn_phy_lp_loopback()
3533 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x80); in bwn_phy_lp_loopback()
3534 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x80); in bwn_phy_lp_loopback()
3536 bwn_phy_lp_set_rxgain_idx(mac, i); in bwn_phy_lp_loopback()
3537 bwn_phy_lp_ddfs_turnon(mac, 1, 1, 5, 5, 0); in bwn_phy_lp_loopback()
3538 if (!(bwn_phy_lp_rx_iq_est(mac, 1000, 32, &ie))) in bwn_phy_lp_loopback()
3546 bwn_phy_lp_ddfs_turnoff(mac); in bwn_phy_lp_loopback()
3551 bwn_phy_lp_set_rxgain_idx(struct bwn_mac *mac, uint16_t idx) in bwn_phy_lp_set_rxgain_idx() argument
3554 bwn_phy_lp_set_rxgain(mac, bwn_tab_read(mac, BWN_TAB_2(12, idx))); in bwn_phy_lp_set_rxgain_idx()
3558 bwn_phy_lp_ddfs_turnon(struct bwn_mac *mac, int i_on, int q_on, in bwn_phy_lp_ddfs_turnon() argument
3562 bwn_phy_lp_ddfs_turnoff(mac); in bwn_phy_lp_ddfs_turnon()
3563 BWN_PHY_MASK(mac, BWN_PHY_AFE_DDFS_POINTER_INIT, 0xff80); in bwn_phy_lp_ddfs_turnon()
3564 BWN_PHY_MASK(mac, BWN_PHY_AFE_DDFS_POINTER_INIT, 0x80ff); in bwn_phy_lp_ddfs_turnon()
3565 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS_INCR_INIT, 0xff80, incr1); in bwn_phy_lp_ddfs_turnon()
3566 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS_INCR_INIT, 0x80ff, incr2 << 8); in bwn_phy_lp_ddfs_turnon()
3567 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS, 0xfff7, i_on << 3); in bwn_phy_lp_ddfs_turnon()
3568 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS, 0xffef, q_on << 4); in bwn_phy_lp_ddfs_turnon()
3569 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS, 0xff9f, scale_idx << 5); in bwn_phy_lp_ddfs_turnon()
3570 BWN_PHY_MASK(mac, BWN_PHY_AFE_DDFS, 0xfffb); in bwn_phy_lp_ddfs_turnon()
3571 BWN_PHY_SET(mac, BWN_PHY_AFE_DDFS, 0x2); in bwn_phy_lp_ddfs_turnon()
3572 BWN_PHY_SET(mac, BWN_PHY_LP_PHY_CTL, 0x20); in bwn_phy_lp_ddfs_turnon()
3576 bwn_phy_lp_rx_iq_est(struct bwn_mac *mac, uint16_t sample, uint8_t time, in bwn_phy_lp_rx_iq_est() argument
3581 BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, 0xfff7); in bwn_phy_lp_rx_iq_est()
3582 BWN_PHY_WRITE(mac, BWN_PHY_IQ_NUM_SMPLS_ADDR, sample); in bwn_phy_lp_rx_iq_est()
3583 BWN_PHY_SETMASK(mac, BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xff00, time); in bwn_phy_lp_rx_iq_est()
3584 BWN_PHY_MASK(mac, BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xfeff); in bwn_phy_lp_rx_iq_est()
3585 BWN_PHY_SET(mac, BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200); in bwn_phy_lp_rx_iq_est()
3588 if (!(BWN_PHY_READ(mac, in bwn_phy_lp_rx_iq_est()
3593 if ((BWN_PHY_READ(mac, BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) { in bwn_phy_lp_rx_iq_est()
3594 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x8); in bwn_phy_lp_rx_iq_est()
3598 ie->ie_iqprod = BWN_PHY_READ(mac, BWN_PHY_IQ_ACC_HI_ADDR); in bwn_phy_lp_rx_iq_est()
3599 ie->ie_iqprod <<= 16; in bwn_phy_lp_rx_iq_est()
3600 ie->ie_iqprod |= BWN_PHY_READ(mac, BWN_PHY_IQ_ACC_LO_ADDR); in bwn_phy_lp_rx_iq_est()
3601 ie->ie_ipwr = BWN_PHY_READ(mac, BWN_PHY_IQ_I_PWR_ACC_HI_ADDR); in bwn_phy_lp_rx_iq_est()
3602 ie->ie_ipwr <<= 16; in bwn_phy_lp_rx_iq_est()
3603 ie->ie_ipwr |= BWN_PHY_READ(mac, BWN_PHY_IQ_I_PWR_ACC_LO_ADDR); in bwn_phy_lp_rx_iq_est()
3604 ie->ie_qpwr = BWN_PHY_READ(mac, BWN_PHY_IQ_Q_PWR_ACC_HI_ADDR); in bwn_phy_lp_rx_iq_est()
3605 ie->ie_qpwr <<= 16; in bwn_phy_lp_rx_iq_est()
3606 ie->ie_qpwr |= BWN_PHY_READ(mac, BWN_PHY_IQ_Q_PWR_ACC_LO_ADDR); in bwn_phy_lp_rx_iq_est()
3608 BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x8); in bwn_phy_lp_rx_iq_est()
3613 bwn_tab_read(struct bwn_mac *mac, uint32_t typeoffset) in bwn_tab_read() argument
3623 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_read()
3624 value = BWN_PHY_READ(mac, BWN_PHY_TABLEDATALO) & 0xff; in bwn_tab_read()
3627 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_read()
3628 value = BWN_PHY_READ(mac, BWN_PHY_TABLEDATALO); in bwn_tab_read()
3631 BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); in bwn_tab_read()
3632 value = BWN_PHY_READ(mac, BWN_PHY_TABLEDATAHI); in bwn_tab_read()
3634 value |= BWN_PHY_READ(mac, BWN_PHY_TABLEDATALO); in bwn_tab_read()
3645 bwn_phy_lp_ddfs_turnoff(struct bwn_mac *mac) in bwn_phy_lp_ddfs_turnoff() argument
3648 BWN_PHY_MASK(mac, BWN_PHY_AFE_DDFS, 0xfffd); in bwn_phy_lp_ddfs_turnoff()
3649 BWN_PHY_MASK(mac, BWN_PHY_LP_PHY_CTL, 0xffdf); in bwn_phy_lp_ddfs_turnoff()
3653 bwn_phy_lp_set_txgain_dac(struct bwn_mac *mac, uint16_t dac) in bwn_phy_lp_set_txgain_dac() argument
3657 ctl = BWN_PHY_READ(mac, BWN_PHY_AFE_DAC_CTL) & 0xc7f; in bwn_phy_lp_set_txgain_dac()
3659 BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DAC_CTL, 0xf000, ctl); in bwn_phy_lp_set_txgain_dac()
3663 bwn_phy_lp_set_txgain_pa(struct bwn_mac *mac, uint16_t gain) in bwn_phy_lp_set_txgain_pa() argument
3666 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfb), 0xe03f, gain << 6); in bwn_phy_lp_set_txgain_pa()
3667 BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfd), 0x80ff, gain << 8); in bwn_phy_lp_set_txgain_pa()
3671 bwn_phy_lp_set_txgain_override(struct bwn_mac *mac) in bwn_phy_lp_set_txgain_override() argument
3674 if (mac->mac_phy.rev < 2) in bwn_phy_lp_set_txgain_override()
3675 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x100); in bwn_phy_lp_set_txgain_override()
3677 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x80); in bwn_phy_lp_set_txgain_override()
3678 BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x4000); in bwn_phy_lp_set_txgain_override()
3680 BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVR, 0x40); in bwn_phy_lp_set_txgain_override()
3684 bwn_phy_lp_get_pa_gain(struct bwn_mac *mac) in bwn_phy_lp_get_pa_gain() argument
3687 return BWN_PHY_READ(mac, BWN_PHY_OFDM(0xfb)) & 0x7f; in bwn_phy_lp_get_pa_gain()
3702 bwn_phy_lp_gaintbl_write_multi(struct bwn_mac *mac, int offset, int count, in bwn_phy_lp_gaintbl_write_multi() argument
3708 bwn_phy_lp_gaintbl_write(mac, i, table[i]); in bwn_phy_lp_gaintbl_write_multi()
3712 bwn_phy_lp_gaintbl_write(struct bwn_mac *mac, int offset, in bwn_phy_lp_gaintbl_write() argument
3716 if (mac->mac_phy.rev >= 2) in bwn_phy_lp_gaintbl_write()
3717 bwn_phy_lp_gaintbl_write_r2(mac, offset, data); in bwn_phy_lp_gaintbl_write()
3719 bwn_phy_lp_gaintbl_write_r01(mac, offset, data); in bwn_phy_lp_gaintbl_write()
3723 bwn_phy_lp_gaintbl_write_r2(struct bwn_mac *mac, int offset, in bwn_phy_lp_gaintbl_write_r2() argument
3726 struct bwn_softc *sc = mac->mac_sc; in bwn_phy_lp_gaintbl_write_r2()
3727 struct ieee80211com *ic = &sc->sc_ic; in bwn_phy_lp_gaintbl_write_r2()
3730 KASSERT(mac->mac_phy.rev >= 2, ("%s:%d: fail", __func__, __LINE__)); in bwn_phy_lp_gaintbl_write_r2()
3733 if (mac->mac_phy.rev >= 3) { in bwn_phy_lp_gaintbl_write_r2()
3734 tmp |= ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ? in bwn_phy_lp_gaintbl_write_r2()
3737 tmp |= ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ? in bwn_phy_lp_gaintbl_write_r2()
3740 bwn_tab_write(mac, BWN_TAB_4(7, 0xc0 + offset), tmp); in bwn_phy_lp_gaintbl_write_r2()
3741 bwn_tab_write(mac, BWN_TAB_4(7, 0x140 + offset), in bwn_phy_lp_gaintbl_write_r2()
3746 bwn_phy_lp_gaintbl_write_r01(struct bwn_mac *mac, int offset, in bwn_phy_lp_gaintbl_write_r01() argument
3750 KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); in bwn_phy_lp_gaintbl_write_r01()
3752 bwn_tab_write(mac, BWN_TAB_4(10, 0xc0 + offset), in bwn_phy_lp_gaintbl_write_r01()
3755 bwn_tab_write(mac, BWN_TAB_4(10, 0x140 + offset), te.te_bbmult << 20); in bwn_phy_lp_gaintbl_write_r01()