Lines Matching +full:0 +full:x6000000

71 	 * * 0x0-0xFFF8 - The function ID
72 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
73 	 * * 0xFFFD - Reserved for user-space HWRM interface
74 	 * * 0xFFFF - HWRM
104 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
109 #define TLV_TYPE_HWRM_REQUEST			UINT32_C(0x1)
111 #define TLV_TYPE_HWRM_RESPONSE		UINT32_C(0x2)
113 #define TLV_TYPE_ROCE_SP_COMMAND		UINT32_C(0x3)
115 #define TLV_TYPE_QUERY_ROCE_CC_GEN1		UINT32_C(0x4)
117 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1		UINT32_C(0x5)
119 #define TLV_TYPE_QUERY_ROCE_CC_GEN2		UINT32_C(0x6)
121 #define TLV_TYPE_MODIFY_ROCE_CC_GEN2		UINT32_C(0x7)
123 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
125 #define TLV_TYPE_ENGINE_CKV_IV		UINT32_C(0x8003)
127 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG		UINT32_C(0x8004)
129 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT	UINT32_C(0x8005)
131 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS	UINT32_C(0x8006)
133 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY  UINT32_C(0x8007)
135 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE	UINT32_C(0x8008)
137 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY	UINT32_C(0x8009)
139 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS	UINT32_C(0x800a)
151 	 * For TLV encapsulated messages this field must be 0x8000.
160 	#define TLV_FLAGS_MORE	UINT32_C(0x1)
162 		#define TLV_FLAGS_MORE_LAST	UINT32_C(0x0)
164 		#define TLV_FLAGS_MORE_NOT_LAST  UINT32_C(0x1)
171 	#define TLV_FLAGS_REQUIRED	UINT32_C(0x2)
173 		#define TLV_FLAGS_REQUIRED_NO	(UINT32_C(0x0) << 1)
175 		#define TLV_FLAGS_REQUIRED_YES   (UINT32_C(0x1) << 1)
186 	 * Global TLV range: `0 - (63k-1)`
220 	 * 0x0 - 0xFFF8 - Used for function ids
221 	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
222 	 * 0xFFFF - HWRM
270 	 * 17185 (0x4321).
274 	#define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
278 	/* Default target_id (0x0) to maintain compatibility with old driver */
279 	#define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
281 	#define HWRM_SHORT_INPUT_TARGET_ID_TOOLS   UINT32_C(0xfffd)
293 	(((x) < 0x80) ? \
294 	((x) == 0x0 ? "HWRM_VER_GET": \
295 	((x) == 0xb ? "HWRM_FUNC_ECHO_RESPONSE": \
296 	((x) == 0xc ? "HWRM_ERROR_RECOVERY_QCFG": \
297 	((x) == 0xd ? "HWRM_FUNC_DRV_IF_CHANGE": \
298 	((x) == 0xe ? "HWRM_FUNC_BUF_UNRGTR": \
299 	((x) == 0xf ? "HWRM_FUNC_VF_CFG": \
300 	((x) == 0x10 ? "HWRM_RESERVED1": \
301 	((x) == 0x11 ? "HWRM_FUNC_RESET": \
302 	((x) == 0x12 ? "HWRM_FUNC_GETFID": \
303 	((x) == 0x13 ? "HWRM_FUNC_VF_ALLOC": \
304 	((x) == 0x14 ? "HWRM_FUNC_VF_FREE": \
305 	((x) == 0x15 ? "HWRM_FUNC_QCAPS": \
306 	((x) == 0x16 ? "HWRM_FUNC_QCFG": \
307 	((x) == 0x17 ? "HWRM_FUNC_CFG": \
308 	((x) == 0x18 ? "HWRM_FUNC_QSTATS": \
309 	((x) == 0x19 ? "HWRM_FUNC_CLR_STATS": \
310 	((x) == 0x1a ? "HWRM_FUNC_DRV_UNRGTR": \
311 	((x) == 0x1b ? "HWRM_FUNC_VF_RESC_FREE": \
312 	((x) == 0x1c ? "HWRM_FUNC_VF_VNIC_IDS_QUERY": \
313 	((x) == 0x1d ? "HWRM_FUNC_DRV_RGTR": \
314 	((x) == 0x1e ? "HWRM_FUNC_DRV_QVER": \
315 	((x) == 0x1f ? "HWRM_FUNC_BUF_RGTR": \
316 	((x) == 0x20 ? "HWRM_PORT_PHY_CFG": \
317 	((x) == 0x21 ? "HWRM_PORT_MAC_CFG": \
318 	((x) == 0x22 ? "HWRM_PORT_TS_QUERY": \
319 	((x) == 0x23 ? "HWRM_PORT_QSTATS": \
320 	((x) == 0x24 ? "HWRM_PORT_LPBK_QSTATS": \
321 	((x) == 0x25 ? "HWRM_PORT_CLR_STATS": \
322 	((x) == 0x26 ? "HWRM_PORT_LPBK_CLR_STATS": \
323 	((x) == 0x27 ? "HWRM_PORT_PHY_QCFG": \
324 	((x) == 0x28 ? "HWRM_PORT_MAC_QCFG": \
325 	((x) == 0x29 ? "HWRM_PORT_MAC_PTP_QCFG": \
326 	((x) == 0x2a ? "HWRM_PORT_PHY_QCAPS": \
327 	((x) == 0x2b ? "HWRM_PORT_PHY_I2C_WRITE": \
328 	((x) == 0x2c ? "HWRM_PORT_PHY_I2C_READ": \
329 	((x) == 0x2d ? "HWRM_PORT_LED_CFG": \
330 	((x) == 0x2e ? "HWRM_PORT_LED_QCFG": \
331 	((x) == 0x2f ? "HWRM_PORT_LED_QCAPS": \
332 	((x) == 0x30 ? "HWRM_QUEUE_QPORTCFG": \
333 	((x) == 0x31 ? "HWRM_QUEUE_QCFG": \
334 	((x) == 0x32 ? "HWRM_QUEUE_CFG": \
335 	((x) == 0x33 ? "HWRM_FUNC_VLAN_CFG": \
336 	((x) == 0x34 ? "HWRM_FUNC_VLAN_QCFG": \
337 	((x) == 0x35 ? "HWRM_QUEUE_PFCENABLE_QCFG": \
338 	((x) == 0x36 ? "HWRM_QUEUE_PFCENABLE_CFG": \
339 	((x) == 0x37 ? "HWRM_QUEUE_PRI2COS_QCFG": \
340 	((x) == 0x38 ? "HWRM_QUEUE_PRI2COS_CFG": \
341 	((x) == 0x39 ? "HWRM_QUEUE_COS2BW_QCFG": \
342 	((x) == 0x3a ? "HWRM_QUEUE_COS2BW_CFG": \
343 	((x) == 0x3b ? "HWRM_QUEUE_DSCP_QCAPS": \
344 	((x) == 0x3c ? "HWRM_QUEUE_DSCP2PRI_QCFG": \
345 	((x) == 0x3d ? "HWRM_QUEUE_DSCP2PRI_CFG": \
346 	((x) == 0x40 ? "HWRM_VNIC_ALLOC": \
347 	((x) == 0x41 ? "HWRM_VNIC_FREE": \
348 	((x) == 0x42 ? "HWRM_VNIC_CFG": \
349 	((x) == 0x43 ? "HWRM_VNIC_QCFG": \
350 	((x) == 0x44 ? "HWRM_VNIC_TPA_CFG": \
351 	((x) == 0x45 ? "HWRM_VNIC_TPA_QCFG": \
352 	((x) == 0x46 ? "HWRM_VNIC_RSS_CFG": \
353 	((x) == 0x47 ? "HWRM_VNIC_RSS_QCFG": \
354 	((x) == 0x48 ? "HWRM_VNIC_PLCMODES_CFG": \
355 	((x) == 0x49 ? "HWRM_VNIC_PLCMODES_QCFG": \
356 	((x) == 0x4a ? "HWRM_VNIC_QCAPS": \
357 	((x) == 0x4b ? "HWRM_VNIC_UPDATE": \
358 	((x) == 0x50 ? "HWRM_RING_ALLOC": \
359 	((x) == 0x51 ? "HWRM_RING_FREE": \
360 	((x) == 0x52 ? "HWRM_RING_CMPL_RING_QAGGINT_PARAMS": \
361 	((x) == 0x53 ? "HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS": \
362 	((x) == 0x54 ? "HWRM_RING_AGGINT_QCAPS": \
363 	((x) == 0x55 ? "HWRM_RING_SCHQ_ALLOC": \
364 	((x) == 0x56 ? "HWRM_RING_SCHQ_CFG": \
365 	((x) == 0x57 ? "HWRM_RING_SCHQ_FREE": \
366 	((x) == 0x5e ? "HWRM_RING_RESET": \
367 	((x) == 0x60 ? "HWRM_RING_GRP_ALLOC": \
368 	((x) == 0x61 ? "HWRM_RING_GRP_FREE": \
369 	((x) == 0x62 ? "HWRM_RING_CFG": \
370 	((x) == 0x63 ? "HWRM_RING_QCFG": \
371 	((x) == 0x64 ? "HWRM_RESERVED5": \
372 	((x) == 0x65 ? "HWRM_RESERVED6": \
373 	((x) == 0x70 ? "HWRM_VNIC_RSS_COS_LB_CTX_ALLOC": \
374 	((x) == 0x71 ? "HWRM_VNIC_RSS_COS_LB_CTX_FREE": \
376 	(((x) < 0x100) ? \
377 	((x) == 0x80 ? "HWRM_QUEUE_MPLS_QCAPS": \
378 	((x) == 0x81 ? "HWRM_QUEUE_MPLSTC2PRI_QCFG": \
379 	((x) == 0x82 ? "HWRM_QUEUE_MPLSTC2PRI_CFG": \
380 	((x) == 0x83 ? "HWRM_QUEUE_VLANPRI_QCAPS": \
381 	((x) == 0x84 ? "HWRM_QUEUE_VLANPRI2PRI_QCFG": \
382 	((x) == 0x85 ? "HWRM_QUEUE_VLANPRI2PRI_CFG": \
383 	((x) == 0x86 ? "HWRM_QUEUE_GLOBAL_CFG": \
384 	((x) == 0x87 ? "HWRM_QUEUE_GLOBAL_QCFG": \
385 	((x) == 0x88 ? "HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG": \
386 	((x) == 0x89 ? "HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG": \
387 	((x) == 0x8a ? "HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG": \
388 	((x) == 0x8b ? "HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG": \
389 	((x) == 0x8c ? "HWRM_QUEUE_QCAPS": \
390 	((x) == 0x8d ? "HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG": \
391 	((x) == 0x8e ? "HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG": \
392 	((x) == 0x8f ? "HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG": \
393 	((x) == 0x90 ? "HWRM_CFA_L2_FILTER_ALLOC": \
394 	((x) == 0x91 ? "HWRM_CFA_L2_FILTER_FREE": \
395 	((x) == 0x92 ? "HWRM_CFA_L2_FILTER_CFG": \
396 	((x) == 0x93 ? "HWRM_CFA_L2_SET_RX_MASK": \
397 	((x) == 0x94 ? "HWRM_CFA_VLAN_ANTISPOOF_CFG": \
398 	((x) == 0x95 ? "HWRM_CFA_TUNNEL_FILTER_ALLOC": \
399 	((x) == 0x96 ? "HWRM_CFA_TUNNEL_FILTER_FREE": \
400 	((x) == 0x97 ? "HWRM_CFA_ENCAP_RECORD_ALLOC": \
401 	((x) == 0x98 ? "HWRM_CFA_ENCAP_RECORD_FREE": \
402 	((x) == 0x99 ? "HWRM_CFA_NTUPLE_FILTER_ALLOC": \
403 	((x) == 0x9a ? "HWRM_CFA_NTUPLE_FILTER_FREE": \
404 	((x) == 0x9b ? "HWRM_CFA_NTUPLE_FILTER_CFG": \
405 	((x) == 0x9c ? "HWRM_CFA_EM_FLOW_ALLOC": \
406 	((x) == 0x9d ? "HWRM_CFA_EM_FLOW_FREE": \
407 	((x) == 0x9e ? "HWRM_CFA_EM_FLOW_CFG": \
408 	((x) == 0xa0 ? "HWRM_TUNNEL_DST_PORT_QUERY": \
409 	((x) == 0xa1 ? "HWRM_TUNNEL_DST_PORT_ALLOC": \
410 	((x) == 0xa2 ? "HWRM_TUNNEL_DST_PORT_FREE": \
411 	((x) == 0xa3 ? "HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG": \
412 	((x) == 0xaf ? "HWRM_STAT_CTX_ENG_QUERY": \
413 	((x) == 0xb0 ? "HWRM_STAT_CTX_ALLOC": \
414 	((x) == 0xb1 ? "HWRM_STAT_CTX_FREE": \
415 	((x) == 0xb2 ? "HWRM_STAT_CTX_QUERY": \
416 	((x) == 0xb3 ? "HWRM_STAT_CTX_CLR_STATS": \
417 	((x) == 0xb4 ? "HWRM_PORT_QSTATS_EXT": \
418 	((x) == 0xb5 ? "HWRM_PORT_PHY_MDIO_WRITE": \
419 	((x) == 0xb6 ? "HWRM_PORT_PHY_MDIO_READ": \
420 	((x) == 0xb7 ? "HWRM_PORT_PHY_MDIO_BUS_ACQUIRE": \
421 	((x) == 0xb8 ? "HWRM_PORT_PHY_MDIO_BUS_RELEASE": \
422 	((x) == 0xb9 ? "HWRM_PORT_QSTATS_EXT_PFC_WD": \
423 	((x) == 0xba ? "HWRM_RESERVED7": \
424 	((x) == 0xbb ? "HWRM_PORT_TX_FIR_CFG": \
425 	((x) == 0xbc ? "HWRM_PORT_TX_FIR_QCFG": \
426 	((x) == 0xbd ? "HWRM_PORT_ECN_QSTATS": \
427 	((x) == 0xbe ? "HWRM_FW_LIVEPATCH_QUERY": \
428 	((x) == 0xbf ? "HWRM_FW_LIVEPATCH": \
429 	((x) == 0xc0 ? "HWRM_FW_RESET": \
430 	((x) == 0xc1 ? "HWRM_FW_QSTATUS": \
431 	((x) == 0xc2 ? "HWRM_FW_HEALTH_CHECK": \
432 	((x) == 0xc3 ? "HWRM_FW_SYNC": \
433 	((x) == 0xc4 ? "HWRM_FW_STATE_QCAPS": \
434 	((x) == 0xc5 ? "HWRM_FW_STATE_QUIESCE": \
435 	((x) == 0xc6 ? "HWRM_FW_STATE_BACKUP": \
436 	((x) == 0xc7 ? "HWRM_FW_STATE_RESTORE": \
437 	((x) == 0xc8 ? "HWRM_FW_SET_TIME": \
438 	((x) == 0xc9 ? "HWRM_FW_GET_TIME": \
439 	((x) == 0xca ? "HWRM_FW_SET_STRUCTURED_DATA": \
440 	((x) == 0xcb ? "HWRM_FW_GET_STRUCTURED_DATA": \
441 	((x) == 0xcc ? "HWRM_FW_IPC_MAILBOX": \
442 	((x) == 0xcd ? "HWRM_FW_ECN_CFG": \
443 	((x) == 0xce ? "HWRM_FW_ECN_QCFG": \
444 	((x) == 0xcf ? "HWRM_FW_SECURE_CFG": \
445 	((x) == 0xd0 ? "HWRM_EXEC_FWD_RESP": \
446 	((x) == 0xd1 ? "HWRM_REJECT_FWD_RESP": \
447 	((x) == 0xd2 ? "HWRM_FWD_RESP": \
448 	((x) == 0xd3 ? "HWRM_FWD_ASYNC_EVENT_CMPL": \
449 	((x) == 0xd4 ? "HWRM_OEM_CMD": \
450 	((x) == 0xd5 ? "HWRM_PORT_PRBS_TEST": \
451 	((x) == 0xd6 ? "HWRM_PORT_SFP_SIDEBAND_CFG": \
452 	((x) == 0xd7 ? "HWRM_PORT_SFP_SIDEBAND_QCFG": \
453 	((x) == 0xd8 ? "HWRM_FW_STATE_UNQUIESCE": \
454 	((x) == 0xd9 ? "HWRM_PORT_DSC_DUMP": \
455 	((x) == 0xda ? "HWRM_PORT_EP_TX_QCFG": \
456 	((x) == 0xdb ? "HWRM_PORT_EP_TX_CFG": \
457 	((x) == 0xdc ? "HWRM_PORT_CFG": \
458 	((x) == 0xdd ? "HWRM_PORT_QCFG": \
459 	((x) == 0xdf ? "HWRM_PORT_MAC_QCAPS": \
460 	((x) == 0xe0 ? "HWRM_TEMP_MONITOR_QUERY": \
461 	((x) == 0xe1 ? "HWRM_REG_POWER_QUERY": \
462 	((x) == 0xe2 ? "HWRM_CORE_FREQUENCY_QUERY": \
463 	((x) == 0xe3 ? "HWRM_REG_POWER_HISTOGRAM": \
464 	((x) == 0xf0 ? "HWRM_WOL_FILTER_ALLOC": \
465 	((x) == 0xf1 ? "HWRM_WOL_FILTER_FREE": \
466 	((x) == 0xf2 ? "HWRM_WOL_FILTER_QCFG": \
467 	((x) == 0xf3 ? "HWRM_WOL_REASON_QCFG": \
468 	((x) == 0xf4 ? "HWRM_CFA_METER_QCAPS": \
469 	((x) == 0xf5 ? "HWRM_CFA_METER_PROFILE_ALLOC": \
470 	((x) == 0xf6 ? "HWRM_CFA_METER_PROFILE_FREE": \
471 	((x) == 0xf7 ? "HWRM_CFA_METER_PROFILE_CFG": \
472 	((x) == 0xf8 ? "HWRM_CFA_METER_INSTANCE_ALLOC": \
473 	((x) == 0xf9 ? "HWRM_CFA_METER_INSTANCE_FREE": \
474 	((x) == 0xfa ? "HWRM_CFA_METER_INSTANCE_CFG": \
475 	((x) == 0xfd ? "HWRM_CFA_VFR_ALLOC": \
476 	((x) == 0xfe ? "HWRM_CFA_VFR_FREE": \
478 	(((x) < 0x180) ? \
479 	((x) == 0x100 ? "HWRM_CFA_VF_PAIR_ALLOC": \
480 	((x) == 0x101 ? "HWRM_CFA_VF_PAIR_FREE": \
481 	((x) == 0x102 ? "HWRM_CFA_VF_PAIR_INFO": \
482 	((x) == 0x103 ? "HWRM_CFA_FLOW_ALLOC": \
483 	((x) == 0x104 ? "HWRM_CFA_FLOW_FREE": \
484 	((x) == 0x105 ? "HWRM_CFA_FLOW_FLUSH": \
485 	((x) == 0x106 ? "HWRM_CFA_FLOW_STATS": \
486 	((x) == 0x107 ? "HWRM_CFA_FLOW_INFO": \
487 	((x) == 0x108 ? "HWRM_CFA_DECAP_FILTER_ALLOC": \
488 	((x) == 0x109 ? "HWRM_CFA_DECAP_FILTER_FREE": \
489 	((x) == 0x10a ? "HWRM_CFA_VLAN_ANTISPOOF_QCFG": \
490 	((x) == 0x10b ? "HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC": \
491 	((x) == 0x10c ? "HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE": \
492 	((x) == 0x10d ? "HWRM_CFA_PAIR_ALLOC": \
493 	((x) == 0x10e ? "HWRM_CFA_PAIR_FREE": \
494 	((x) == 0x10f ? "HWRM_CFA_PAIR_INFO": \
495 	((x) == 0x110 ? "HWRM_FW_IPC_MSG": \
496 	((x) == 0x111 ? "HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO": \
497 	((x) == 0x112 ? "HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE": \
498 	((x) == 0x113 ? "HWRM_CFA_FLOW_AGING_TIMER_RESET": \
499 	((x) == 0x114 ? "HWRM_CFA_FLOW_AGING_CFG": \
500 	((x) == 0x115 ? "HWRM_CFA_FLOW_AGING_QCFG": \
501 	((x) == 0x116 ? "HWRM_CFA_FLOW_AGING_QCAPS": \
502 	((x) == 0x117 ? "HWRM_CFA_CTX_MEM_RGTR": \
503 	((x) == 0x118 ? "HWRM_CFA_CTX_MEM_UNRGTR": \
504 	((x) == 0x119 ? "HWRM_CFA_CTX_MEM_QCTX": \
505 	((x) == 0x11a ? "HWRM_CFA_CTX_MEM_QCAPS": \
506 	((x) == 0x11b ? "HWRM_CFA_COUNTER_QCAPS": \
507 	((x) == 0x11c ? "HWRM_CFA_COUNTER_CFG": \
508 	((x) == 0x11d ? "HWRM_CFA_COUNTER_QCFG": \
509 	((x) == 0x11e ? "HWRM_CFA_COUNTER_QSTATS": \
510 	((x) == 0x11f ? "HWRM_CFA_TCP_FLAG_PROCESS_QCFG": \
511 	((x) == 0x120 ? "HWRM_CFA_EEM_QCAPS": \
512 	((x) == 0x121 ? "HWRM_CFA_EEM_CFG": \
513 	((x) == 0x122 ? "HWRM_CFA_EEM_QCFG": \
514 	((x) == 0x123 ? "HWRM_CFA_EEM_OP": \
515 	((x) == 0x124 ? "HWRM_CFA_ADV_FLOW_MGNT_QCAPS": \
516 	((x) == 0x125 ? "HWRM_CFA_TFLIB": \
517 	((x) == 0x126 ? "HWRM_CFA_LAG_GROUP_MEMBER_RGTR": \
518 	((x) == 0x127 ? "HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR": \
519 	((x) == 0x128 ? "HWRM_CFA_TLS_FILTER_ALLOC": \
520 	((x) == 0x129 ? "HWRM_CFA_TLS_FILTER_FREE": \
521 	((x) == 0x12a ? "HWRM_CFA_RELEASE_AFM_FUNC": \
522 	((x) == 0x12e ? "HWRM_ENGINE_CKV_STATUS": \
523 	((x) == 0x12f ? "HWRM_ENGINE_CKV_CKEK_ADD": \
524 	((x) == 0x130 ? "HWRM_ENGINE_CKV_CKEK_DELETE": \
525 	((x) == 0x131 ? "HWRM_ENGINE_CKV_KEY_ADD": \
526 	((x) == 0x132 ? "HWRM_ENGINE_CKV_KEY_DELETE": \
527 	((x) == 0x133 ? "HWRM_ENGINE_CKV_FLUSH": \
528 	((x) == 0x134 ? "HWRM_ENGINE_CKV_RNG_GET": \
529 	((x) == 0x135 ? "HWRM_ENGINE_CKV_KEY_GEN": \
530 	((x) == 0x136 ? "HWRM_ENGINE_CKV_KEY_LABEL_CFG": \
531 	((x) == 0x137 ? "HWRM_ENGINE_CKV_KEY_LABEL_QCFG": \
532 	((x) == 0x13c ? "HWRM_ENGINE_QG_CONFIG_QUERY": \
533 	((x) == 0x13d ? "HWRM_ENGINE_QG_QUERY": \
534 	((x) == 0x13e ? "HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY": \
535 	((x) == 0x13f ? "HWRM_ENGINE_QG_METER_PROFILE_QUERY": \
536 	((x) == 0x140 ? "HWRM_ENGINE_QG_METER_PROFILE_ALLOC": \
537 	((x) == 0x141 ? "HWRM_ENGINE_QG_METER_PROFILE_FREE": \
538 	((x) == 0x142 ? "HWRM_ENGINE_QG_METER_QUERY": \
539 	((x) == 0x143 ? "HWRM_ENGINE_QG_METER_BIND": \
540 	((x) == 0x144 ? "HWRM_ENGINE_QG_METER_UNBIND": \
541 	((x) == 0x145 ? "HWRM_ENGINE_QG_FUNC_BIND": \
542 	((x) == 0x146 ? "HWRM_ENGINE_SG_CONFIG_QUERY": \
543 	((x) == 0x147 ? "HWRM_ENGINE_SG_QUERY": \
544 	((x) == 0x148 ? "HWRM_ENGINE_SG_METER_QUERY": \
545 	((x) == 0x149 ? "HWRM_ENGINE_SG_METER_CONFIG": \
546 	((x) == 0x14a ? "HWRM_ENGINE_SG_QG_BIND": \
547 	((x) == 0x14b ? "HWRM_ENGINE_QG_SG_UNBIND": \
548 	((x) == 0x154 ? "HWRM_ENGINE_CONFIG_QUERY": \
549 	((x) == 0x155 ? "HWRM_ENGINE_STATS_CONFIG": \
550 	((x) == 0x156 ? "HWRM_ENGINE_STATS_CLEAR": \
551 	((x) == 0x157 ? "HWRM_ENGINE_STATS_QUERY": \
552 	((x) == 0x158 ? "HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR": \
553 	((x) == 0x15e ? "HWRM_ENGINE_RQ_ALLOC": \
554 	((x) == 0x15f ? "HWRM_ENGINE_RQ_FREE": \
555 	((x) == 0x160 ? "HWRM_ENGINE_CQ_ALLOC": \
556 	((x) == 0x161 ? "HWRM_ENGINE_CQ_FREE": \
557 	((x) == 0x162 ? "HWRM_ENGINE_NQ_ALLOC": \
558 	((x) == 0x163 ? "HWRM_ENGINE_NQ_FREE": \
559 	((x) == 0x164 ? "HWRM_ENGINE_ON_DIE_RQE_CREDITS": \
560 	((x) == 0x165 ? "HWRM_ENGINE_FUNC_QCFG": \
562 	(((x) < 0x200) ? \
563 	((x) == 0x190 ? "HWRM_FUNC_RESOURCE_QCAPS": \
564 	((x) == 0x191 ? "HWRM_FUNC_VF_RESOURCE_CFG": \
565 	((x) == 0x192 ? "HWRM_FUNC_BACKING_STORE_QCAPS": \
566 	((x) == 0x193 ? "HWRM_FUNC_BACKING_STORE_CFG": \
567 	((x) == 0x194 ? "HWRM_FUNC_BACKING_STORE_QCFG": \
568 	((x) == 0x195 ? "HWRM_FUNC_VF_BW_CFG": \
569 	((x) == 0x196 ? "HWRM_FUNC_VF_BW_QCFG": \
570 	((x) == 0x197 ? "HWRM_FUNC_HOST_PF_IDS_QUERY": \
571 	((x) == 0x198 ? "HWRM_FUNC_QSTATS_EXT": \
572 	((x) == 0x199 ? "HWRM_STAT_EXT_CTX_QUERY": \
573 	((x) == 0x19a ? "HWRM_FUNC_SPD_CFG": \
574 	((x) == 0x19b ? "HWRM_FUNC_SPD_QCFG": \
575 	((x) == 0x19c ? "HWRM_FUNC_PTP_PIN_QCFG": \
576 	((x) == 0x19d ? "HWRM_FUNC_PTP_PIN_CFG": \
577 	((x) == 0x19e ? "HWRM_FUNC_PTP_CFG": \
578 	((x) == 0x19f ? "HWRM_FUNC_PTP_TS_QUERY": \
579 	((x) == 0x1a0 ? "HWRM_FUNC_PTP_EXT_CFG": \
580 	((x) == 0x1a1 ? "HWRM_FUNC_PTP_EXT_QCFG": \
581 	((x) == 0x1a2 ? "HWRM_FUNC_KEY_CTX_ALLOC": \
582 	((x) == 0x1a3 ? "HWRM_FUNC_BACKING_STORE_CFG_V2": \
583 	((x) == 0x1a4 ? "HWRM_FUNC_BACKING_STORE_QCFG_V2": \
584 	((x) == 0x1a5 ? "HWRM_FUNC_DBR_PACING_CFG": \
585 	((x) == 0x1a6 ? "HWRM_FUNC_DBR_PACING_QCFG": \
586 	((x) == 0x1a7 ? "HWRM_FUNC_DBR_PACING_BROADCAST_EVENT": \
587 	((x) == 0x1a8 ? "HWRM_FUNC_BACKING_STORE_QCAPS_V2": \
588 	((x) == 0x1a9 ? "HWRM_FUNC_DBR_PACING_NQLIST_QUERY": \
589 	((x) == 0x1aa ? "HWRM_FUNC_DBR_RECOVERY_COMPLETED": \
590 	((x) == 0x1ab ? "HWRM_FUNC_SYNCE_CFG": \
591 	((x) == 0x1ac ? "HWRM_FUNC_SYNCE_QCFG": \
592 	((x) == 0x1ad ? "HWRM_FUNC_KEY_CTX_FREE": \
593 	((x) == 0x1ae ? "HWRM_FUNC_LAG_MODE_CFG": \
594 	((x) == 0x1af ? "HWRM_FUNC_LAG_MODE_QCFG": \
595 	((x) == 0x1b0 ? "HWRM_FUNC_LAG_CREATE": \
596 	((x) == 0x1b1 ? "HWRM_FUNC_LAG_UPDATE": \
597 	((x) == 0x1b2 ? "HWRM_FUNC_LAG_FREE": \
598 	((x) == 0x1b3 ? "HWRM_FUNC_LAG_QCFG": \
599 	((x) == 0x1c2 ? "HWRM_FUNC_TIMEDTX_PACING_RATE_ADD": \
600 	((x) == 0x1c3 ? "HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE": \
601 	((x) == 0x1c4 ? "HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY": \
603 	(((x) < 0x280) ? \
604 	((x) == 0x200 ? "HWRM_SELFTEST_QLIST": \
605 	((x) == 0x201 ? "HWRM_SELFTEST_EXEC": \
606 	((x) == 0x202 ? "HWRM_SELFTEST_IRQ": \
607 	((x) == 0x203 ? "HWRM_SELFTEST_RETRIEVE_SERDES_DATA": \
608 	((x) == 0x204 ? "HWRM_PCIE_QSTATS": \
609 	((x) == 0x205 ? "HWRM_MFG_FRU_WRITE_CONTROL": \
610 	((x) == 0x206 ? "HWRM_MFG_TIMERS_QUERY": \
611 	((x) == 0x207 ? "HWRM_MFG_OTP_CFG": \
612 	((x) == 0x208 ? "HWRM_MFG_OTP_QCFG": \
613 	((x) == 0x209 ? "HWRM_MFG_HDMA_TEST": \
614 	((x) == 0x20a ? "HWRM_MFG_FRU_EEPROM_WRITE": \
615 	((x) == 0x20b ? "HWRM_MFG_FRU_EEPROM_READ": \
616 	((x) == 0x20c ? "HWRM_MFG_SOC_IMAGE": \
617 	((x) == 0x20d ? "HWRM_MFG_SOC_QSTATUS": \
618 	((x) == 0x20e ? "HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE": \
619 	((x) == 0x20f ? "HWRM_MFG_PARAM_CRITICAL_DATA_READ": \
620 	((x) == 0x210 ? "HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH": \
621 	((x) == 0x211 ? "HWRM_MFG_PRVSN_EXPORT_CSR": \
622 	((x) == 0x212 ? "HWRM_MFG_PRVSN_IMPORT_CERT": \
623 	((x) == 0x213 ? "HWRM_MFG_PRVSN_GET_STATE": \
624 	((x) == 0x214 ? "HWRM_MFG_GET_NVM_MEASUREMENT": \
625 	((x) == 0x215 ? "HWRM_MFG_PSOC_QSTATUS": \
626 	((x) == 0x216 ? "HWRM_MFG_SELFTEST_QLIST": \
627 	((x) == 0x217 ? "HWRM_MFG_SELFTEST_EXEC": \
628 	((x) == 0x218 ? "HWRM_STAT_GENERIC_QSTATS": \
629 	((x) == 0x219 ? "HWRM_MFG_PRVSN_EXPORT_CERT": \
630 	((x) == 0x21a ? "HWRM_STAT_DB_ERROR_QSTATS": \
631 	((x) == 0x230 ? "HWRM_PORT_POE_CFG": \
632 	((x) == 0x231 ? "HWRM_PORT_POE_QCFG": \
633 	((x) == 0x258 ? "HWRM_UDCC_QCAPS": \
634 	((x) == 0x259 ? "HWRM_UDCC_CFG": \
635 	((x) == 0x25a ? "HWRM_UDCC_QCFG": \
636 	((x) == 0x25b ? "HWRM_UDCC_SESSION_CFG": \
637 	((x) == 0x25c ? "HWRM_UDCC_SESSION_QCFG": \
638 	((x) == 0x25d ? "HWRM_UDCC_SESSION_QUERY": \
639 	((x) == 0x25e ? "HWRM_UDCC_COMP_CFG": \
640 	((x) == 0x25f ? "HWRM_UDCC_COMP_QCFG": \
641 	((x) == 0x260 ? "HWRM_UDCC_COMP_QUERY": \
642 	((x) == 0x261 ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS": \
643 	((x) == 0x262 ? "HWRM_QUEUE_PFCWD_TIMEOUT_CFG": \
644 	((x) == 0x263 ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCFG": \
646 	(((x) < 0x300) ? \
647 	((x) == 0x2bc ? "HWRM_TF": \
648 	((x) == 0x2bd ? "HWRM_TF_VERSION_GET": \
649 	((x) == 0x2c6 ? "HWRM_TF_SESSION_OPEN": \
650 	((x) == 0x2c8 ? "HWRM_TF_SESSION_REGISTER": \
651 	((x) == 0x2c9 ? "HWRM_TF_SESSION_UNREGISTER": \
652 	((x) == 0x2ca ? "HWRM_TF_SESSION_CLOSE": \
653 	((x) == 0x2cb ? "HWRM_TF_SESSION_QCFG": \
654 	((x) == 0x2cc ? "HWRM_TF_SESSION_RESC_QCAPS": \
655 	((x) == 0x2cd ? "HWRM_TF_SESSION_RESC_ALLOC": \
656 	((x) == 0x2ce ? "HWRM_TF_SESSION_RESC_FREE": \
657 	((x) == 0x2cf ? "HWRM_TF_SESSION_RESC_FLUSH": \
658 	((x) == 0x2d0 ? "HWRM_TF_SESSION_RESC_INFO": \
659 	((x) == 0x2d1 ? "HWRM_TF_SESSION_HOTUP_STATE_SET": \
660 	((x) == 0x2d2 ? "HWRM_TF_SESSION_HOTUP_STATE_GET": \
661 	((x) == 0x2da ? "HWRM_TF_TBL_TYPE_GET": \
662 	((x) == 0x2db ? "HWRM_TF_TBL_TYPE_SET": \
663 	((x) == 0x2dc ? "HWRM_TF_TBL_TYPE_BULK_GET": \
664 	((x) == 0x2ea ? "HWRM_TF_EM_INSERT": \
665 	((x) == 0x2eb ? "HWRM_TF_EM_DELETE": \
666 	((x) == 0x2ec ? "HWRM_TF_EM_HASH_INSERT": \
667 	((x) == 0x2ed ? "HWRM_TF_EM_MOVE": \
668 	((x) == 0x2f8 ? "HWRM_TF_TCAM_SET": \
669 	((x) == 0x2f9 ? "HWRM_TF_TCAM_GET": \
670 	((x) == 0x2fa ? "HWRM_TF_TCAM_MOVE": \
671 	((x) == 0x2fb ? "HWRM_TF_TCAM_FREE": \
672 	((x) == 0x2fc ? "HWRM_TF_GLOBAL_CFG_SET": \
673 	((x) == 0x2fd ? "HWRM_TF_GLOBAL_CFG_GET": \
674 	((x) == 0x2fe ? "HWRM_TF_IF_TBL_SET": \
675 	((x) == 0x2ff ? "HWRM_TF_IF_TBL_GET": \
677 	(((x) < 0x380) ? \
678 	((x) == 0x300 ? "HWRM_TF_RESC_USAGE_SET": \
679 	((x) == 0x301 ? "HWRM_TF_RESC_USAGE_QUERY": \
680 	((x) == 0x302 ? "HWRM_TF_TBL_TYPE_ALLOC": \
681 	((x) == 0x303 ? "HWRM_TF_TBL_TYPE_FREE": \
683 	(((x) < 0x400) ? \
684 	((x) == 0x380 ? "HWRM_TFC_TBL_SCOPE_QCAPS": \
685 	((x) == 0x381 ? "HWRM_TFC_TBL_SCOPE_ID_ALLOC": \
686 	((x) == 0x382 ? "HWRM_TFC_TBL_SCOPE_CONFIG": \
687 	((x) == 0x383 ? "HWRM_TFC_TBL_SCOPE_DECONFIG": \
688 	((x) == 0x384 ? "HWRM_TFC_TBL_SCOPE_FID_ADD": \
689 	((x) == 0x385 ? "HWRM_TFC_TBL_SCOPE_FID_REM": \
690 	((x) == 0x386 ? "HWRM_TFC_TBL_SCOPE_POOL_ALLOC": \
691 	((x) == 0x387 ? "HWRM_TFC_TBL_SCOPE_POOL_FREE": \
692 	((x) == 0x388 ? "HWRM_TFC_SESSION_ID_ALLOC": \
693 	((x) == 0x389 ? "HWRM_TFC_SESSION_FID_ADD": \
694 	((x) == 0x38a ? "HWRM_TFC_SESSION_FID_REM": \
695 	((x) == 0x38b ? "HWRM_TFC_IDENT_ALLOC": \
696 	((x) == 0x38c ? "HWRM_TFC_IDENT_FREE": \
697 	((x) == 0x38d ? "HWRM_TFC_IDX_TBL_ALLOC": \
698 	((x) == 0x38e ? "HWRM_TFC_IDX_TBL_ALLOC_SET": \
699 	((x) == 0x38f ? "HWRM_TFC_IDX_TBL_SET": \
700 	((x) == 0x390 ? "HWRM_TFC_IDX_TBL_GET": \
701 	((x) == 0x391 ? "HWRM_TFC_IDX_TBL_FREE": \
702 	((x) == 0x392 ? "HWRM_TFC_GLOBAL_ID_ALLOC": \
703 	((x) == 0x393 ? "HWRM_TFC_TCAM_SET": \
704 	((x) == 0x394 ? "HWRM_TFC_TCAM_GET": \
705 	((x) == 0x395 ? "HWRM_TFC_TCAM_ALLOC": \
706 	((x) == 0x396 ? "HWRM_TFC_TCAM_ALLOC_SET": \
707 	((x) == 0x397 ? "HWRM_TFC_TCAM_FREE": \
708 	((x) == 0x398 ? "HWRM_TFC_IF_TBL_SET": \
709 	((x) == 0x399 ? "HWRM_TFC_IF_TBL_GET": \
710 	((x) == 0x39a ? "HWRM_TFC_TBL_SCOPE_CONFIG_GET": \
711 	((x) == 0x39b ? "HWRM_TFC_RESC_USAGE_QUERY": \
713 	(((x) < 0x480) ? \
714 	((x) == 0x400 ? "HWRM_SV": \
716 	(((x) < 0xff80) ? \
717 	((x) == 0xff0e ? "HWRM_DBG_SERDES_TEST": \
718 	((x) == 0xff0f ? "HWRM_DBG_LOG_BUFFER_FLUSH": \
719 	((x) == 0xff10 ? "HWRM_DBG_READ_DIRECT": \
720 	((x) == 0xff11 ? "HWRM_DBG_READ_INDIRECT": \
721 	((x) == 0xff12 ? "HWRM_DBG_WRITE_DIRECT": \
722 	((x) == 0xff13 ? "HWRM_DBG_WRITE_INDIRECT": \
723 	((x) == 0xff14 ? "HWRM_DBG_DUMP": \
724 	((x) == 0xff15 ? "HWRM_DBG_ERASE_NVM": \
725 	((x) == 0xff16 ? "HWRM_DBG_CFG": \
726 	((x) == 0xff17 ? "HWRM_DBG_COREDUMP_LIST": \
727 	((x) == 0xff18 ? "HWRM_DBG_COREDUMP_INITIATE": \
728 	((x) == 0xff19 ? "HWRM_DBG_COREDUMP_RETRIEVE": \
729 	((x) == 0xff1a ? "HWRM_DBG_FW_CLI": \
730 	((x) == 0xff1b ? "HWRM_DBG_I2C_CMD": \
731 	((x) == 0xff1c ? "HWRM_DBG_RING_INFO_GET": \
732 	((x) == 0xff1d ? "HWRM_DBG_CRASHDUMP_HEADER": \
733 	((x) == 0xff1e ? "HWRM_DBG_CRASHDUMP_ERASE": \
734 	((x) == 0xff1f ? "HWRM_DBG_DRV_TRACE": \
735 	((x) == 0xff20 ? "HWRM_DBG_QCAPS": \
736 	((x) == 0xff21 ? "HWRM_DBG_QCFG": \
737 	((x) == 0xff22 ? "HWRM_DBG_CRASHDUMP_MEDIUM_CFG": \
738 	((x) == 0xff23 ? "HWRM_DBG_USEQ_ALLOC": \
739 	((x) == 0xff24 ? "HWRM_DBG_USEQ_FREE": \
740 	((x) == 0xff25 ? "HWRM_DBG_USEQ_FLUSH": \
741 	((x) == 0xff26 ? "HWRM_DBG_USEQ_QCAPS": \
742 	((x) == 0xff27 ? "HWRM_DBG_USEQ_CW_CFG": \
743 	((x) == 0xff28 ? "HWRM_DBG_USEQ_SCHED_CFG": \
744 	((x) == 0xff29 ? "HWRM_DBG_USEQ_RUN": \
745 	((x) == 0xff2a ? "HWRM_DBG_USEQ_DELIVERY_REQ": \
746 	((x) == 0xff2b ? "HWRM_DBG_USEQ_RESP_HDR": \
747 	((x) == 0xff2c ? "HWRM_DBG_COREDUMP_CAPTURE": \
748 	((x) == 0xff2d ? "HWRM_DBG_PTRACE": \
749 	((x) == 0xff2e ? "HWRM_DBG_SIM_CABLE_STATE": \
752 	((x) == 0xffea ? "HWRM_NVM_GET_VPD_FIELD_INFO": \
753 	((x) == 0xffeb ? "HWRM_NVM_SET_VPD_FIELD_INFO": \
754 	((x) == 0xffec ? "HWRM_NVM_DEFRAG": \
755 	((x) == 0xffed ? "HWRM_NVM_REQ_ARBITRATION": \
756 	((x) == 0xffee ? "HWRM_NVM_FACTORY_DEFAULTS": \
757 	((x) == 0xffef ? "HWRM_NVM_VALIDATE_OPTION": \
758 	((x) == 0xfff0 ? "HWRM_NVM_FLUSH": \
759 	((x) == 0xfff1 ? "HWRM_NVM_GET_VARIABLE": \
760 	((x) == 0xfff2 ? "HWRM_NVM_SET_VARIABLE": \
761 	((x) == 0xfff3 ? "HWRM_NVM_INSTALL_UPDATE": \
762 	((x) == 0xfff4 ? "HWRM_NVM_MODIFY": \
763 	((x) == 0xfff5 ? "HWRM_NVM_VERIFY_UPDATE": \
764 	((x) == 0xfff6 ? "HWRM_NVM_GET_DEV_INFO": \
765 	((x) == 0xfff7 ? "HWRM_NVM_ERASE_DIR_ENTRY": \
766 	((x) == 0xfff8 ? "HWRM_NVM_MOD_DIR_ENTRY": \
767 	((x) == 0xfff9 ? "HWRM_NVM_FIND_DIR_ENTRY": \
768 	((x) == 0xfffa ? "HWRM_NVM_GET_DIR_ENTRIES": \
769 	((x) == 0xfffb ? "HWRM_NVM_GET_DIR_INFO": \
770 	((x) == 0xfffc ? "HWRM_NVM_RAW_DUMP": \
771 	((x) == 0xfffd ? "HWRM_NVM_READ": \
772 	((x) == 0xfffe ? "HWRM_NVM_WRITE": \
773 	((x) == 0xffff ? "HWRM_NVM_RAW_WRITE_BLK": \
806 	#define HWRM_VER_GET				UINT32_C(0x0)
807 	#define HWRM_FUNC_ECHO_RESPONSE		UINT32_C(0xb)
808 	#define HWRM_ERROR_RECOVERY_QCFG		UINT32_C(0xc)
809 	#define HWRM_FUNC_DRV_IF_CHANGE		UINT32_C(0xd)
810 	#define HWRM_FUNC_BUF_UNRGTR			UINT32_C(0xe)
811 	#define HWRM_FUNC_VF_CFG			UINT32_C(0xf)
813 	#define HWRM_RESERVED1				UINT32_C(0x10)
814 	#define HWRM_FUNC_RESET			UINT32_C(0x11)
815 	#define HWRM_FUNC_GETFID			UINT32_C(0x12)
816 	#define HWRM_FUNC_VF_ALLOC			UINT32_C(0x13)
817 	#define HWRM_FUNC_VF_FREE			UINT32_C(0x14)
818 	#define HWRM_FUNC_QCAPS			UINT32_C(0x15)
819 	#define HWRM_FUNC_QCFG				UINT32_C(0x16)
820 	#define HWRM_FUNC_CFG				UINT32_C(0x17)
821 	#define HWRM_FUNC_QSTATS			UINT32_C(0x18)
822 	#define HWRM_FUNC_CLR_STATS			UINT32_C(0x19)
823 	#define HWRM_FUNC_DRV_UNRGTR			UINT32_C(0x1a)
824 	#define HWRM_FUNC_VF_RESC_FREE			UINT32_C(0x1b)
825 	#define HWRM_FUNC_VF_VNIC_IDS_QUERY		UINT32_C(0x1c)
826 	#define HWRM_FUNC_DRV_RGTR			UINT32_C(0x1d)
827 	#define HWRM_FUNC_DRV_QVER			UINT32_C(0x1e)
828 	#define HWRM_FUNC_BUF_RGTR			UINT32_C(0x1f)
829 	#define HWRM_PORT_PHY_CFG			UINT32_C(0x20)
830 	#define HWRM_PORT_MAC_CFG			UINT32_C(0x21)
832 	#define HWRM_PORT_TS_QUERY			UINT32_C(0x22)
833 	#define HWRM_PORT_QSTATS			UINT32_C(0x23)
834 	#define HWRM_PORT_LPBK_QSTATS			UINT32_C(0x24)
836 	#define HWRM_PORT_CLR_STATS			UINT32_C(0x25)
838 	#define HWRM_PORT_LPBK_CLR_STATS		UINT32_C(0x26)
839 	#define HWRM_PORT_PHY_QCFG			UINT32_C(0x27)
840 	#define HWRM_PORT_MAC_QCFG			UINT32_C(0x28)
842 	#define HWRM_PORT_MAC_PTP_QCFG			UINT32_C(0x29)
843 	#define HWRM_PORT_PHY_QCAPS			UINT32_C(0x2a)
844 	#define HWRM_PORT_PHY_I2C_WRITE		UINT32_C(0x2b)
845 	#define HWRM_PORT_PHY_I2C_READ			UINT32_C(0x2c)
846 	#define HWRM_PORT_LED_CFG			UINT32_C(0x2d)
847 	#define HWRM_PORT_LED_QCFG			UINT32_C(0x2e)
848 	#define HWRM_PORT_LED_QCAPS			UINT32_C(0x2f)
849 	#define HWRM_QUEUE_QPORTCFG			UINT32_C(0x30)
850 	#define HWRM_QUEUE_QCFG			UINT32_C(0x31)
851 	#define HWRM_QUEUE_CFG				UINT32_C(0x32)
852 	#define HWRM_FUNC_VLAN_CFG			UINT32_C(0x33)
853 	#define HWRM_FUNC_VLAN_QCFG			UINT32_C(0x34)
854 	#define HWRM_QUEUE_PFCENABLE_QCFG		UINT32_C(0x35)
855 	#define HWRM_QUEUE_PFCENABLE_CFG		UINT32_C(0x36)
856 	#define HWRM_QUEUE_PRI2COS_QCFG		UINT32_C(0x37)
857 	#define HWRM_QUEUE_PRI2COS_CFG			UINT32_C(0x38)
858 	#define HWRM_QUEUE_COS2BW_QCFG			UINT32_C(0x39)
859 	#define HWRM_QUEUE_COS2BW_CFG			UINT32_C(0x3a)
860 	#define HWRM_QUEUE_DSCP_QCAPS			UINT32_C(0x3b)
861 	#define HWRM_QUEUE_DSCP2PRI_QCFG		UINT32_C(0x3c)
862 	#define HWRM_QUEUE_DSCP2PRI_CFG		UINT32_C(0x3d)
863 	#define HWRM_VNIC_ALLOC			UINT32_C(0x40)
864 	#define HWRM_VNIC_FREE				UINT32_C(0x41)
865 	#define HWRM_VNIC_CFG				UINT32_C(0x42)
866 	#define HWRM_VNIC_QCFG				UINT32_C(0x43)
867 	#define HWRM_VNIC_TPA_CFG			UINT32_C(0x44)
869 	#define HWRM_VNIC_TPA_QCFG			UINT32_C(0x45)
870 	#define HWRM_VNIC_RSS_CFG			UINT32_C(0x46)
871 	#define HWRM_VNIC_RSS_QCFG			UINT32_C(0x47)
872 	#define HWRM_VNIC_PLCMODES_CFG			UINT32_C(0x48)
873 	#define HWRM_VNIC_PLCMODES_QCFG		UINT32_C(0x49)
874 	#define HWRM_VNIC_QCAPS			UINT32_C(0x4a)
876 	#define HWRM_VNIC_UPDATE			UINT32_C(0x4b)
877 	#define HWRM_RING_ALLOC			UINT32_C(0x50)
878 	#define HWRM_RING_FREE				UINT32_C(0x51)
879 	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS	UINT32_C(0x52)
880 	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS	UINT32_C(0x53)
881 	#define HWRM_RING_AGGINT_QCAPS			UINT32_C(0x54)
882 	#define HWRM_RING_SCHQ_ALLOC			UINT32_C(0x55)
883 	#define HWRM_RING_SCHQ_CFG			UINT32_C(0x56)
884 	#define HWRM_RING_SCHQ_FREE			UINT32_C(0x57)
885 	#define HWRM_RING_RESET			UINT32_C(0x5e)
886 	#define HWRM_RING_GRP_ALLOC			UINT32_C(0x60)
887 	#define HWRM_RING_GRP_FREE			UINT32_C(0x61)
888 	#define HWRM_RING_CFG				UINT32_C(0x62)
889 	#define HWRM_RING_QCFG				UINT32_C(0x63)
891 	#define HWRM_RESERVED5				UINT32_C(0x64)
893 	#define HWRM_RESERVED6				UINT32_C(0x65)
894 	#define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC		UINT32_C(0x70)
895 	#define HWRM_VNIC_RSS_COS_LB_CTX_FREE		UINT32_C(0x71)
896 	#define HWRM_QUEUE_MPLS_QCAPS			UINT32_C(0x80)
897 	#define HWRM_QUEUE_MPLSTC2PRI_QCFG		UINT32_C(0x81)
898 	#define HWRM_QUEUE_MPLSTC2PRI_CFG		UINT32_C(0x82)
899 	#define HWRM_QUEUE_VLANPRI_QCAPS		UINT32_C(0x83)
900 	#define HWRM_QUEUE_VLANPRI2PRI_QCFG		UINT32_C(0x84)
901 	#define HWRM_QUEUE_VLANPRI2PRI_CFG		UINT32_C(0x85)
902 	#define HWRM_QUEUE_GLOBAL_CFG			UINT32_C(0x86)
903 	#define HWRM_QUEUE_GLOBAL_QCFG			UINT32_C(0x87)
904 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG	UINT32_C(0x88)
905 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG	UINT32_C(0x89)
906 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG	UINT32_C(0x8a)
907 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG	UINT32_C(0x8b)
908 	#define HWRM_QUEUE_QCAPS			UINT32_C(0x8c)
909 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG	UINT32_C(0x8d)
910 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG	UINT32_C(0x8e)
911 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG	UINT32_C(0x8f)
912 	#define HWRM_CFA_L2_FILTER_ALLOC		UINT32_C(0x90)
913 	#define HWRM_CFA_L2_FILTER_FREE		UINT32_C(0x91)
914 	#define HWRM_CFA_L2_FILTER_CFG			UINT32_C(0x92)
915 	#define HWRM_CFA_L2_SET_RX_MASK		UINT32_C(0x93)
916 	#define HWRM_CFA_VLAN_ANTISPOOF_CFG		UINT32_C(0x94)
917 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC		UINT32_C(0x95)
918 	#define HWRM_CFA_TUNNEL_FILTER_FREE		UINT32_C(0x96)
920 	#define HWRM_CFA_ENCAP_RECORD_ALLOC		UINT32_C(0x97)
922 	#define HWRM_CFA_ENCAP_RECORD_FREE		UINT32_C(0x98)
923 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC		UINT32_C(0x99)
924 	#define HWRM_CFA_NTUPLE_FILTER_FREE		UINT32_C(0x9a)
925 	#define HWRM_CFA_NTUPLE_FILTER_CFG		UINT32_C(0x9b)
927 	#define HWRM_CFA_EM_FLOW_ALLOC			UINT32_C(0x9c)
929 	#define HWRM_CFA_EM_FLOW_FREE			UINT32_C(0x9d)
931 	#define HWRM_CFA_EM_FLOW_CFG			UINT32_C(0x9e)
932 	#define HWRM_TUNNEL_DST_PORT_QUERY		UINT32_C(0xa0)
933 	#define HWRM_TUNNEL_DST_PORT_ALLOC		UINT32_C(0xa1)
934 	#define HWRM_TUNNEL_DST_PORT_FREE		UINT32_C(0xa2)
935 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG	UINT32_C(0xa3)
936 	#define HWRM_STAT_CTX_ENG_QUERY		UINT32_C(0xaf)
937 	#define HWRM_STAT_CTX_ALLOC			UINT32_C(0xb0)
938 	#define HWRM_STAT_CTX_FREE			UINT32_C(0xb1)
939 	#define HWRM_STAT_CTX_QUERY			UINT32_C(0xb2)
940 	#define HWRM_STAT_CTX_CLR_STATS		UINT32_C(0xb3)
941 	#define HWRM_PORT_QSTATS_EXT			UINT32_C(0xb4)
942 	#define HWRM_PORT_PHY_MDIO_WRITE		UINT32_C(0xb5)
943 	#define HWRM_PORT_PHY_MDIO_READ		UINT32_C(0xb6)
944 	#define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE		UINT32_C(0xb7)
945 	#define HWRM_PORT_PHY_MDIO_BUS_RELEASE		UINT32_C(0xb8)
946 	#define HWRM_PORT_QSTATS_EXT_PFC_WD		UINT32_C(0xb9)
948 	#define HWRM_RESERVED7				UINT32_C(0xba)
949 	#define HWRM_PORT_TX_FIR_CFG			UINT32_C(0xbb)
950 	#define HWRM_PORT_TX_FIR_QCFG			UINT32_C(0xbc)
951 	#define HWRM_PORT_ECN_QSTATS			UINT32_C(0xbd)
952 	#define HWRM_FW_LIVEPATCH_QUERY		UINT32_C(0xbe)
953 	#define HWRM_FW_LIVEPATCH			UINT32_C(0xbf)
954 	#define HWRM_FW_RESET				UINT32_C(0xc0)
955 	#define HWRM_FW_QSTATUS			UINT32_C(0xc1)
956 	#define HWRM_FW_HEALTH_CHECK			UINT32_C(0xc2)
957 	#define HWRM_FW_SYNC				UINT32_C(0xc3)
958 	#define HWRM_FW_STATE_QCAPS			UINT32_C(0xc4)
959 	#define HWRM_FW_STATE_QUIESCE			UINT32_C(0xc5)
960 	#define HWRM_FW_STATE_BACKUP			UINT32_C(0xc6)
961 	#define HWRM_FW_STATE_RESTORE			UINT32_C(0xc7)
963 	#define HWRM_FW_SET_TIME			UINT32_C(0xc8)
965 	#define HWRM_FW_GET_TIME			UINT32_C(0xc9)
967 	#define HWRM_FW_SET_STRUCTURED_DATA		UINT32_C(0xca)
969 	#define HWRM_FW_GET_STRUCTURED_DATA		UINT32_C(0xcb)
971 	#define HWRM_FW_IPC_MAILBOX			UINT32_C(0xcc)
972 	#define HWRM_FW_ECN_CFG			UINT32_C(0xcd)
973 	#define HWRM_FW_ECN_QCFG			UINT32_C(0xce)
974 	#define HWRM_FW_SECURE_CFG			UINT32_C(0xcf)
975 	#define HWRM_EXEC_FWD_RESP			UINT32_C(0xd0)
976 	#define HWRM_REJECT_FWD_RESP			UINT32_C(0xd1)
977 	#define HWRM_FWD_RESP				UINT32_C(0xd2)
978 	#define HWRM_FWD_ASYNC_EVENT_CMPL		UINT32_C(0xd3)
979 	#define HWRM_OEM_CMD				UINT32_C(0xd4)
981 	#define HWRM_PORT_PRBS_TEST			UINT32_C(0xd5)
982 	#define HWRM_PORT_SFP_SIDEBAND_CFG		UINT32_C(0xd6)
983 	#define HWRM_PORT_SFP_SIDEBAND_QCFG		UINT32_C(0xd7)
984 	#define HWRM_FW_STATE_UNQUIESCE		UINT32_C(0xd8)
986 	#define HWRM_PORT_DSC_DUMP			UINT32_C(0xd9)
987 	#define HWRM_PORT_EP_TX_QCFG			UINT32_C(0xda)
988 	#define HWRM_PORT_EP_TX_CFG			UINT32_C(0xdb)
989 	#define HWRM_PORT_CFG				UINT32_C(0xdc)
990 	#define HWRM_PORT_QCFG				UINT32_C(0xdd)
992 	#define HWRM_PORT_MAC_QCAPS			UINT32_C(0xdf)
993 	#define HWRM_TEMP_MONITOR_QUERY		UINT32_C(0xe0)
994 	#define HWRM_REG_POWER_QUERY			UINT32_C(0xe1)
995 	#define HWRM_CORE_FREQUENCY_QUERY		UINT32_C(0xe2)
996 	#define HWRM_REG_POWER_HISTOGRAM		UINT32_C(0xe3)
997 	#define HWRM_WOL_FILTER_ALLOC			UINT32_C(0xf0)
998 	#define HWRM_WOL_FILTER_FREE			UINT32_C(0xf1)
999 	#define HWRM_WOL_FILTER_QCFG			UINT32_C(0xf2)
1000 	#define HWRM_WOL_REASON_QCFG			UINT32_C(0xf3)
1002 	#define HWRM_CFA_METER_QCAPS			UINT32_C(0xf4)
1004 	#define HWRM_CFA_METER_PROFILE_ALLOC		UINT32_C(0xf5)
1006 	#define HWRM_CFA_METER_PROFILE_FREE		UINT32_C(0xf6)
1008 	#define HWRM_CFA_METER_PROFILE_CFG		UINT32_C(0xf7)
1010 	#define HWRM_CFA_METER_INSTANCE_ALLOC		UINT32_C(0xf8)
1012 	#define HWRM_CFA_METER_INSTANCE_FREE		UINT32_C(0xf9)
1014 	#define HWRM_CFA_METER_INSTANCE_CFG		UINT32_C(0xfa)
1016 	#define HWRM_CFA_VFR_ALLOC			UINT32_C(0xfd)
1018 	#define HWRM_CFA_VFR_FREE			UINT32_C(0xfe)
1020 	#define HWRM_CFA_VF_PAIR_ALLOC			UINT32_C(0x100)
1022 	#define HWRM_CFA_VF_PAIR_FREE			UINT32_C(0x101)
1024 	#define HWRM_CFA_VF_PAIR_INFO			UINT32_C(0x102)
1026 	#define HWRM_CFA_FLOW_ALLOC			UINT32_C(0x103)
1028 	#define HWRM_CFA_FLOW_FREE			UINT32_C(0x104)
1030 	#define HWRM_CFA_FLOW_FLUSH			UINT32_C(0x105)
1031 	#define HWRM_CFA_FLOW_STATS			UINT32_C(0x106)
1032 	#define HWRM_CFA_FLOW_INFO			UINT32_C(0x107)
1034 	#define HWRM_CFA_DECAP_FILTER_ALLOC		UINT32_C(0x108)
1036 	#define HWRM_CFA_DECAP_FILTER_FREE		UINT32_C(0x109)
1037 	#define HWRM_CFA_VLAN_ANTISPOOF_QCFG		UINT32_C(0x10a)
1038 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC	UINT32_C(0x10b)
1039 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE	UINT32_C(0x10c)
1041 	#define HWRM_CFA_PAIR_ALLOC			UINT32_C(0x10d)
1043 	#define HWRM_CFA_PAIR_FREE			UINT32_C(0x10e)
1045 	#define HWRM_CFA_PAIR_INFO			UINT32_C(0x10f)
1047 	#define HWRM_FW_IPC_MSG			UINT32_C(0x110)
1048 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO	UINT32_C(0x111)
1049 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE	UINT32_C(0x112)
1051 	#define HWRM_CFA_FLOW_AGING_TIMER_RESET	UINT32_C(0x113)
1053 	#define HWRM_CFA_FLOW_AGING_CFG		UINT32_C(0x114)
1055 	#define HWRM_CFA_FLOW_AGING_QCFG		UINT32_C(0x115)
1057 	#define HWRM_CFA_FLOW_AGING_QCAPS		UINT32_C(0x116)
1059 	#define HWRM_CFA_CTX_MEM_RGTR			UINT32_C(0x117)
1061 	#define HWRM_CFA_CTX_MEM_UNRGTR		UINT32_C(0x118)
1063 	#define HWRM_CFA_CTX_MEM_QCTX			UINT32_C(0x119)
1065 	#define HWRM_CFA_CTX_MEM_QCAPS			UINT32_C(0x11a)
1067 	#define HWRM_CFA_COUNTER_QCAPS			UINT32_C(0x11b)
1069 	#define HWRM_CFA_COUNTER_CFG			UINT32_C(0x11c)
1071 	#define HWRM_CFA_COUNTER_QCFG			UINT32_C(0x11d)
1073 	#define HWRM_CFA_COUNTER_QSTATS		UINT32_C(0x11e)
1075 	#define HWRM_CFA_TCP_FLAG_PROCESS_QCFG		UINT32_C(0x11f)
1077 	#define HWRM_CFA_EEM_QCAPS			UINT32_C(0x120)
1079 	#define HWRM_CFA_EEM_CFG			UINT32_C(0x121)
1081 	#define HWRM_CFA_EEM_QCFG			UINT32_C(0x122)
1083 	#define HWRM_CFA_EEM_OP			UINT32_C(0x123)
1085 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS		UINT32_C(0x124)
1087 	#define HWRM_CFA_TFLIB				UINT32_C(0x125)
1089 	#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR		UINT32_C(0x126)
1091 	#define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR	UINT32_C(0x127)
1093 	#define HWRM_CFA_TLS_FILTER_ALLOC		UINT32_C(0x128)
1095 	#define HWRM_CFA_TLS_FILTER_FREE		UINT32_C(0x129)
1097 	#define HWRM_CFA_RELEASE_AFM_FUNC		UINT32_C(0x12a)
1102 	#define HWRM_ENGINE_CKV_STATUS			UINT32_C(0x12e)
1104 	#define HWRM_ENGINE_CKV_CKEK_ADD		UINT32_C(0x12f)
1106 	#define HWRM_ENGINE_CKV_CKEK_DELETE		UINT32_C(0x130)
1108 	#define HWRM_ENGINE_CKV_KEY_ADD		UINT32_C(0x131)
1110 	#define HWRM_ENGINE_CKV_KEY_DELETE		UINT32_C(0x132)
1112 	#define HWRM_ENGINE_CKV_FLUSH			UINT32_C(0x133)
1114 	#define HWRM_ENGINE_CKV_RNG_GET		UINT32_C(0x134)
1116 	#define HWRM_ENGINE_CKV_KEY_GEN		UINT32_C(0x135)
1118 	#define HWRM_ENGINE_CKV_KEY_LABEL_CFG		UINT32_C(0x136)
1120 	#define HWRM_ENGINE_CKV_KEY_LABEL_QCFG		UINT32_C(0x137)
1122 	#define HWRM_ENGINE_QG_CONFIG_QUERY		UINT32_C(0x13c)
1124 	#define HWRM_ENGINE_QG_QUERY			UINT32_C(0x13d)
1126 	#define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
1128 	#define HWRM_ENGINE_QG_METER_PROFILE_QUERY	UINT32_C(0x13f)
1130 	#define HWRM_ENGINE_QG_METER_PROFILE_ALLOC	UINT32_C(0x140)
1132 	#define HWRM_ENGINE_QG_METER_PROFILE_FREE	UINT32_C(0x141)
1134 	#define HWRM_ENGINE_QG_METER_QUERY		UINT32_C(0x142)
1136 	#define HWRM_ENGINE_QG_METER_BIND		UINT32_C(0x143)
1138 	#define HWRM_ENGINE_QG_METER_UNBIND		UINT32_C(0x144)
1140 	#define HWRM_ENGINE_QG_FUNC_BIND		UINT32_C(0x145)
1142 	#define HWRM_ENGINE_SG_CONFIG_QUERY		UINT32_C(0x146)
1144 	#define HWRM_ENGINE_SG_QUERY			UINT32_C(0x147)
1146 	#define HWRM_ENGINE_SG_METER_QUERY		UINT32_C(0x148)
1148 	#define HWRM_ENGINE_SG_METER_CONFIG		UINT32_C(0x149)
1150 	#define HWRM_ENGINE_SG_QG_BIND			UINT32_C(0x14a)
1152 	#define HWRM_ENGINE_QG_SG_UNBIND		UINT32_C(0x14b)
1154 	#define HWRM_ENGINE_CONFIG_QUERY		UINT32_C(0x154)
1156 	#define HWRM_ENGINE_STATS_CONFIG		UINT32_C(0x155)
1158 	#define HWRM_ENGINE_STATS_CLEAR		UINT32_C(0x156)
1160 	#define HWRM_ENGINE_STATS_QUERY		UINT32_C(0x157)
1165 	#define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR  UINT32_C(0x158)
1167 	#define HWRM_ENGINE_RQ_ALLOC			UINT32_C(0x15e)
1169 	#define HWRM_ENGINE_RQ_FREE			UINT32_C(0x15f)
1171 	#define HWRM_ENGINE_CQ_ALLOC			UINT32_C(0x160)
1173 	#define HWRM_ENGINE_CQ_FREE			UINT32_C(0x161)
1175 	#define HWRM_ENGINE_NQ_ALLOC			UINT32_C(0x162)
1177 	#define HWRM_ENGINE_NQ_FREE			UINT32_C(0x163)
1179 	#define HWRM_ENGINE_ON_DIE_RQE_CREDITS		UINT32_C(0x164)
1181 	#define HWRM_ENGINE_FUNC_QCFG			UINT32_C(0x165)
1183 	#define HWRM_FUNC_RESOURCE_QCAPS		UINT32_C(0x190)
1185 	#define HWRM_FUNC_VF_RESOURCE_CFG		UINT32_C(0x191)
1187 	#define HWRM_FUNC_BACKING_STORE_QCAPS		UINT32_C(0x192)
1189 	#define HWRM_FUNC_BACKING_STORE_CFG		UINT32_C(0x193)
1191 	#define HWRM_FUNC_BACKING_STORE_QCFG		UINT32_C(0x194)
1193 	#define HWRM_FUNC_VF_BW_CFG			UINT32_C(0x195)
1195 	#define HWRM_FUNC_VF_BW_QCFG			UINT32_C(0x196)
1197 	#define HWRM_FUNC_HOST_PF_IDS_QUERY		UINT32_C(0x197)
1199 	#define HWRM_FUNC_QSTATS_EXT			UINT32_C(0x198)
1201 	#define HWRM_STAT_EXT_CTX_QUERY		UINT32_C(0x199)
1203 	#define HWRM_FUNC_SPD_CFG			UINT32_C(0x19a)
1205 	#define HWRM_FUNC_SPD_QCFG			UINT32_C(0x19b)
1207 	#define HWRM_FUNC_PTP_PIN_QCFG			UINT32_C(0x19c)
1209 	#define HWRM_FUNC_PTP_PIN_CFG			UINT32_C(0x19d)
1211 	#define HWRM_FUNC_PTP_CFG			UINT32_C(0x19e)
1213 	#define HWRM_FUNC_PTP_TS_QUERY			UINT32_C(0x19f)
1215 	#define HWRM_FUNC_PTP_EXT_CFG			UINT32_C(0x1a0)
1217 	#define HWRM_FUNC_PTP_EXT_QCFG			UINT32_C(0x1a1)
1219 	#define HWRM_FUNC_KEY_CTX_ALLOC		UINT32_C(0x1a2)
1221 	#define HWRM_FUNC_BACKING_STORE_CFG_V2		UINT32_C(0x1a3)
1223 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2	UINT32_C(0x1a4)
1225 	#define HWRM_FUNC_DBR_PACING_CFG		UINT32_C(0x1a5)
1227 	#define HWRM_FUNC_DBR_PACING_QCFG		UINT32_C(0x1a6)
1232 	#define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT	UINT32_C(0x1a7)
1234 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2	UINT32_C(0x1a8)
1236 	#define HWRM_FUNC_DBR_PACING_NQLIST_QUERY	UINT32_C(0x1a9)
1241 	#define HWRM_FUNC_DBR_RECOVERY_COMPLETED	UINT32_C(0x1aa)
1243 	#define HWRM_FUNC_SYNCE_CFG			UINT32_C(0x1ab)
1245 	#define HWRM_FUNC_SYNCE_QCFG			UINT32_C(0x1ac)
1247 	#define HWRM_FUNC_KEY_CTX_FREE			UINT32_C(0x1ad)
1249 	#define HWRM_FUNC_LAG_MODE_CFG			UINT32_C(0x1ae)
1251 	#define HWRM_FUNC_LAG_MODE_QCFG		UINT32_C(0x1af)
1253 	#define HWRM_FUNC_LAG_CREATE			UINT32_C(0x1b0)
1255 	#define HWRM_FUNC_LAG_UPDATE			UINT32_C(0x1b1)
1257 	#define HWRM_FUNC_LAG_FREE			UINT32_C(0x1b2)
1259 	#define HWRM_FUNC_LAG_QCFG			UINT32_C(0x1b3)
1261 	#define HWRM_FUNC_TIMEDTX_PACING_RATE_ADD	UINT32_C(0x1c2)
1266 	#define HWRM_FUNC_TIMEDTX_PACING_RATE_DELETE	UINT32_C(0x1c3)
1271 	#define HWRM_FUNC_TIMEDTX_PACING_RATE_QUERY	UINT32_C(0x1c4)
1273 	#define HWRM_SELFTEST_QLIST			UINT32_C(0x200)
1275 	#define HWRM_SELFTEST_EXEC			UINT32_C(0x201)
1277 	#define HWRM_SELFTEST_IRQ			UINT32_C(0x202)
1279 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA	UINT32_C(0x203)
1281 	#define HWRM_PCIE_QSTATS			UINT32_C(0x204)
1283 	#define HWRM_MFG_FRU_WRITE_CONTROL		UINT32_C(0x205)
1285 	#define HWRM_MFG_TIMERS_QUERY			UINT32_C(0x206)
1287 	#define HWRM_MFG_OTP_CFG			UINT32_C(0x207)
1289 	#define HWRM_MFG_OTP_QCFG			UINT32_C(0x208)
1294 	#define HWRM_MFG_HDMA_TEST			UINT32_C(0x209)
1296 	#define HWRM_MFG_FRU_EEPROM_WRITE		UINT32_C(0x20a)
1298 	#define HWRM_MFG_FRU_EEPROM_READ		UINT32_C(0x20b)
1300 	#define HWRM_MFG_SOC_IMAGE			UINT32_C(0x20c)
1302 	#define HWRM_MFG_SOC_QSTATUS			UINT32_C(0x20d)
1304 	#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE	UINT32_C(0x20e)
1306 	#define HWRM_MFG_PARAM_CRITICAL_DATA_READ	UINT32_C(0x20f)
1308 	#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH	UINT32_C(0x210)
1313 	#define HWRM_MFG_PRVSN_EXPORT_CSR		UINT32_C(0x211)
1318 	#define HWRM_MFG_PRVSN_IMPORT_CERT		UINT32_C(0x212)
1323 	#define HWRM_MFG_PRVSN_GET_STATE		UINT32_C(0x213)
1328 	#define HWRM_MFG_GET_NVM_MEASUREMENT		UINT32_C(0x214)
1330 	#define HWRM_MFG_PSOC_QSTATUS			UINT32_C(0x215)
1335 	#define HWRM_MFG_SELFTEST_QLIST		UINT32_C(0x216)
1340 	#define HWRM_MFG_SELFTEST_EXEC			UINT32_C(0x217)
1342 	#define HWRM_STAT_GENERIC_QSTATS		UINT32_C(0x218)
1347 	#define HWRM_MFG_PRVSN_EXPORT_CERT		UINT32_C(0x219)
1349 	#define HWRM_STAT_DB_ERROR_QSTATS		UINT32_C(0x21a)
1354 	#define HWRM_PORT_POE_CFG			UINT32_C(0x230)
1359 	#define HWRM_PORT_POE_QCFG			UINT32_C(0x231)
1364 	#define HWRM_UDCC_QCAPS			UINT32_C(0x258)
1366 	#define HWRM_UDCC_CFG				UINT32_C(0x259)
1371 	#define HWRM_UDCC_QCFG				UINT32_C(0x25a)
1373 	#define HWRM_UDCC_SESSION_CFG			UINT32_C(0x25b)
1375 	#define HWRM_UDCC_SESSION_QCFG			UINT32_C(0x25c)
1377 	#define HWRM_UDCC_SESSION_QUERY		UINT32_C(0x25d)
1379 	#define HWRM_UDCC_COMP_CFG			UINT32_C(0x25e)
1381 	#define HWRM_UDCC_COMP_QCFG			UINT32_C(0x25f)
1383 	#define HWRM_UDCC_COMP_QUERY			UINT32_C(0x260)
1388 	#define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS		UINT32_C(0x261)
1390 	#define HWRM_QUEUE_PFCWD_TIMEOUT_CFG		UINT32_C(0x262)
1395 	#define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG		UINT32_C(0x263)
1397 	#define HWRM_TF				UINT32_C(0x2bc)
1399 	#define HWRM_TF_VERSION_GET			UINT32_C(0x2bd)
1401 	#define HWRM_TF_SESSION_OPEN			UINT32_C(0x2c6)
1403 	#define HWRM_TF_SESSION_REGISTER		UINT32_C(0x2c8)
1405 	#define HWRM_TF_SESSION_UNREGISTER		UINT32_C(0x2c9)
1407 	#define HWRM_TF_SESSION_CLOSE			UINT32_C(0x2ca)
1409 	#define HWRM_TF_SESSION_QCFG			UINT32_C(0x2cb)
1411 	#define HWRM_TF_SESSION_RESC_QCAPS		UINT32_C(0x2cc)
1413 	#define HWRM_TF_SESSION_RESC_ALLOC		UINT32_C(0x2cd)
1415 	#define HWRM_TF_SESSION_RESC_FREE		UINT32_C(0x2ce)
1417 	#define HWRM_TF_SESSION_RESC_FLUSH		UINT32_C(0x2cf)
1419 	#define HWRM_TF_SESSION_RESC_INFO		UINT32_C(0x2d0)
1421 	#define HWRM_TF_SESSION_HOTUP_STATE_SET	UINT32_C(0x2d1)
1423 	#define HWRM_TF_SESSION_HOTUP_STATE_GET	UINT32_C(0x2d2)
1425 	#define HWRM_TF_TBL_TYPE_GET			UINT32_C(0x2da)
1427 	#define HWRM_TF_TBL_TYPE_SET			UINT32_C(0x2db)
1429 	#define HWRM_TF_TBL_TYPE_BULK_GET		UINT32_C(0x2dc)
1431 	#define HWRM_TF_EM_INSERT			UINT32_C(0x2ea)
1433 	#define HWRM_TF_EM_DELETE			UINT32_C(0x2eb)
1435 	#define HWRM_TF_EM_HASH_INSERT			UINT32_C(0x2ec)
1437 	#define HWRM_TF_EM_MOVE			UINT32_C(0x2ed)
1439 	#define HWRM_TF_TCAM_SET			UINT32_C(0x2f8)
1441 	#define HWRM_TF_TCAM_GET			UINT32_C(0x2f9)
1443 	#define HWRM_TF_TCAM_MOVE			UINT32_C(0x2fa)
1445 	#define HWRM_TF_TCAM_FREE			UINT32_C(0x2fb)
1447 	#define HWRM_TF_GLOBAL_CFG_SET			UINT32_C(0x2fc)
1449 	#define HWRM_TF_GLOBAL_CFG_GET			UINT32_C(0x2fd)
1451 	#define HWRM_TF_IF_TBL_SET			UINT32_C(0x2fe)
1453 	#define HWRM_TF_IF_TBL_GET			UINT32_C(0x2ff)
1455 	#define HWRM_TF_RESC_USAGE_SET			UINT32_C(0x300)
1457 	#define HWRM_TF_RESC_USAGE_QUERY		UINT32_C(0x301)
1459 	#define HWRM_TF_TBL_TYPE_ALLOC			UINT32_C(0x302)
1461 	#define HWRM_TF_TBL_TYPE_FREE			UINT32_C(0x303)
1463 	#define HWRM_TFC_TBL_SCOPE_QCAPS		UINT32_C(0x380)
1465 	#define HWRM_TFC_TBL_SCOPE_ID_ALLOC		UINT32_C(0x381)
1467 	#define HWRM_TFC_TBL_SCOPE_CONFIG		UINT32_C(0x382)
1469 	#define HWRM_TFC_TBL_SCOPE_DECONFIG		UINT32_C(0x383)
1471 	#define HWRM_TFC_TBL_SCOPE_FID_ADD		UINT32_C(0x384)
1473 	#define HWRM_TFC_TBL_SCOPE_FID_REM		UINT32_C(0x385)
1475 	#define HWRM_TFC_TBL_SCOPE_POOL_ALLOC		UINT32_C(0x386)
1477 	#define HWRM_TFC_TBL_SCOPE_POOL_FREE		UINT32_C(0x387)
1479 	#define HWRM_TFC_SESSION_ID_ALLOC		UINT32_C(0x388)
1481 	#define HWRM_TFC_SESSION_FID_ADD		UINT32_C(0x389)
1483 	#define HWRM_TFC_SESSION_FID_REM		UINT32_C(0x38a)
1485 	#define HWRM_TFC_IDENT_ALLOC			UINT32_C(0x38b)
1487 	#define HWRM_TFC_IDENT_FREE			UINT32_C(0x38c)
1489 	#define HWRM_TFC_IDX_TBL_ALLOC			UINT32_C(0x38d)
1491 	#define HWRM_TFC_IDX_TBL_ALLOC_SET		UINT32_C(0x38e)
1493 	#define HWRM_TFC_IDX_TBL_SET			UINT32_C(0x38f)
1495 	#define HWRM_TFC_IDX_TBL_GET			UINT32_C(0x390)
1497 	#define HWRM_TFC_IDX_TBL_FREE			UINT32_C(0x391)
1499 	#define HWRM_TFC_GLOBAL_ID_ALLOC		UINT32_C(0x392)
1501 	#define HWRM_TFC_TCAM_SET			UINT32_C(0x393)
1503 	#define HWRM_TFC_TCAM_GET			UINT32_C(0x394)
1505 	#define HWRM_TFC_TCAM_ALLOC			UINT32_C(0x395)
1507 	#define HWRM_TFC_TCAM_ALLOC_SET		UINT32_C(0x396)
1509 	#define HWRM_TFC_TCAM_FREE			UINT32_C(0x397)
1511 	#define HWRM_TFC_IF_TBL_SET			UINT32_C(0x398)
1513 	#define HWRM_TFC_IF_TBL_GET			UINT32_C(0x399)
1515 	#define HWRM_TFC_TBL_SCOPE_CONFIG_GET		UINT32_C(0x39a)
1517 	#define HWRM_TFC_RESC_USAGE_QUERY		UINT32_C(0x39b)
1519 	#define HWRM_SV				UINT32_C(0x400)
1521 	#define HWRM_DBG_SERDES_TEST			UINT32_C(0xff0e)
1523 	#define HWRM_DBG_LOG_BUFFER_FLUSH		UINT32_C(0xff0f)
1525 	#define HWRM_DBG_READ_DIRECT			UINT32_C(0xff10)
1527 	#define HWRM_DBG_READ_INDIRECT			UINT32_C(0xff11)
1529 	#define HWRM_DBG_WRITE_DIRECT			UINT32_C(0xff12)
1531 	#define HWRM_DBG_WRITE_INDIRECT		UINT32_C(0xff13)
1532 	#define HWRM_DBG_DUMP				UINT32_C(0xff14)
1534 	#define HWRM_DBG_ERASE_NVM			UINT32_C(0xff15)
1536 	#define HWRM_DBG_CFG				UINT32_C(0xff16)
1538 	#define HWRM_DBG_COREDUMP_LIST			UINT32_C(0xff17)
1540 	#define HWRM_DBG_COREDUMP_INITIATE		UINT32_C(0xff18)
1542 	#define HWRM_DBG_COREDUMP_RETRIEVE		UINT32_C(0xff19)
1544 	#define HWRM_DBG_FW_CLI			UINT32_C(0xff1a)
1546 	#define HWRM_DBG_I2C_CMD			UINT32_C(0xff1b)
1548 	#define HWRM_DBG_RING_INFO_GET			UINT32_C(0xff1c)
1550 	#define HWRM_DBG_CRASHDUMP_HEADER		UINT32_C(0xff1d)
1552 	#define HWRM_DBG_CRASHDUMP_ERASE		UINT32_C(0xff1e)
1554 	#define HWRM_DBG_DRV_TRACE			UINT32_C(0xff1f)
1556 	#define HWRM_DBG_QCAPS				UINT32_C(0xff20)
1558 	#define HWRM_DBG_QCFG				UINT32_C(0xff21)
1560 	#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG		UINT32_C(0xff22)
1562 	#define HWRM_DBG_USEQ_ALLOC			UINT32_C(0xff23)
1564 	#define HWRM_DBG_USEQ_FREE			UINT32_C(0xff24)
1566 	#define HWRM_DBG_USEQ_FLUSH			UINT32_C(0xff25)
1568 	#define HWRM_DBG_USEQ_QCAPS			UINT32_C(0xff26)
1570 	#define HWRM_DBG_USEQ_CW_CFG			UINT32_C(0xff27)
1572 	#define HWRM_DBG_USEQ_SCHED_CFG		UINT32_C(0xff28)
1574 	#define HWRM_DBG_USEQ_RUN			UINT32_C(0xff29)
1576 	#define HWRM_DBG_USEQ_DELIVERY_REQ		UINT32_C(0xff2a)
1578 	#define HWRM_DBG_USEQ_RESP_HDR			UINT32_C(0xff2b)
1584 	#define HWRM_DBG_COREDUMP_CAPTURE		UINT32_C(0xff2c)
1585 	#define HWRM_DBG_PTRACE			UINT32_C(0xff2d)
1590 	#define HWRM_DBG_SIM_CABLE_STATE		UINT32_C(0xff2e)
1591 	#define HWRM_NVM_GET_VPD_FIELD_INFO		UINT32_C(0xffea)
1592 	#define HWRM_NVM_SET_VPD_FIELD_INFO		UINT32_C(0xffeb)
1593 	#define HWRM_NVM_DEFRAG			UINT32_C(0xffec)
1594 	#define HWRM_NVM_REQ_ARBITRATION		UINT32_C(0xffed)
1596 	#define HWRM_NVM_FACTORY_DEFAULTS		UINT32_C(0xffee)
1597 	#define HWRM_NVM_VALIDATE_OPTION		UINT32_C(0xffef)
1598 	#define HWRM_NVM_FLUSH				UINT32_C(0xfff0)
1599 	#define HWRM_NVM_GET_VARIABLE			UINT32_C(0xfff1)
1600 	#define HWRM_NVM_SET_VARIABLE			UINT32_C(0xfff2)
1601 	#define HWRM_NVM_INSTALL_UPDATE		UINT32_C(0xfff3)
1602 	#define HWRM_NVM_MODIFY			UINT32_C(0xfff4)
1603 	#define HWRM_NVM_VERIFY_UPDATE			UINT32_C(0xfff5)
1604 	#define HWRM_NVM_GET_DEV_INFO			UINT32_C(0xfff6)
1605 	#define HWRM_NVM_ERASE_DIR_ENTRY		UINT32_C(0xfff7)
1606 	#define HWRM_NVM_MOD_DIR_ENTRY			UINT32_C(0xfff8)
1607 	#define HWRM_NVM_FIND_DIR_ENTRY		UINT32_C(0xfff9)
1608 	#define HWRM_NVM_GET_DIR_ENTRIES		UINT32_C(0xfffa)
1609 	#define HWRM_NVM_GET_DIR_INFO			UINT32_C(0xfffb)
1610 	#define HWRM_NVM_RAW_DUMP			UINT32_C(0xfffc)
1611 	#define HWRM_NVM_READ				UINT32_C(0xfffd)
1612 	#define HWRM_NVM_WRITE				UINT32_C(0xfffe)
1613 	#define HWRM_NVM_RAW_WRITE_BLK			UINT32_C(0xffff)
1624 	#define HWRM_ERR_CODE_SUCCESS			UINT32_C(0x0)
1626 	#define HWRM_ERR_CODE_FAIL			UINT32_C(0x1)
1631 	#define HWRM_ERR_CODE_INVALID_PARAMS		UINT32_C(0x2)
1638 	#define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED	UINT32_C(0x3)
1644 	#define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR	UINT32_C(0x4)
1649 	#define HWRM_ERR_CODE_INVALID_FLAGS		UINT32_C(0x5)
1654 	#define HWRM_ERR_CODE_INVALID_ENABLES		UINT32_C(0x6)
1659 	#define HWRM_ERR_CODE_UNSUPPORTED_TLV		UINT32_C(0x7)
1664 	#define HWRM_ERR_CODE_NO_BUFFER			UINT32_C(0x8)
1669 	#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR	UINT32_C(0x9)
1674 	#define HWRM_ERR_CODE_HOT_RESET_PROGRESS	UINT32_C(0xa)
1679 	#define HWRM_ERR_CODE_HOT_RESET_FAIL		UINT32_C(0xb)
1685 	#define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
1691 	#define HWRM_ERR_CODE_KEY_HASH_COLLISION	UINT32_C(0xd)
1697 	#define HWRM_ERR_CODE_KEY_ALREADY_EXISTS	UINT32_C(0xe)
1702 	#define HWRM_ERR_CODE_HWRM_ERROR		UINT32_C(0xf)
1707 	#define HWRM_ERR_CODE_BUSY			UINT32_C(0x10)
1712 	#define HWRM_ERR_CODE_RESOURCE_LOCKED		UINT32_C(0x11)
1719 	#define HWRM_ERR_CODE_PF_UNAVAILABLE		UINT32_C(0x12)
1724 	#define HWRM_ERR_CODE_ENTITY_NOT_PRESENT	UINT32_C(0x13)
1732 	#define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE	UINT32_C(0x8000)
1734 	#define HWRM_ERR_CODE_UNKNOWN_ERR		UINT32_C(0xfffe)
1736 	#define HWRM_ERR_CODE_CMD_NOT_SUPPORTED		UINT32_C(0xffff)
1742 	(((x) < 0x80) ? \
1743 	((x) == 0x0 ? "SUCCESS": \
1744 	((x) == 0x1 ? "FAIL": \
1745 	((x) == 0x2 ? "INVALID_PARAMS": \
1746 	((x) == 0x3 ? "RESOURCE_ACCESS_DENIED": \
1747 	((x) == 0x4 ? "RESOURCE_ALLOC_ERROR": \
1748 	((x) == 0x5 ? "INVALID_FLAGS": \
1749 	((x) == 0x6 ? "INVALID_ENABLES": \
1750 	((x) == 0x7 ? "UNSUPPORTED_TLV": \
1751 	((x) == 0x8 ? "NO_BUFFER": \
1752 	((x) == 0x9 ? "UNSUPPORTED_OPTION_ERR": \
1753 	((x) == 0xa ? "HOT_RESET_PROGRESS": \
1754 	((x) == 0xb ? "HOT_RESET_FAIL": \
1755 	((x) == 0xc ? "NO_FLOW_COUNTER_DURING_ALLOC": \
1756 	((x) == 0xd ? "KEY_HASH_COLLISION": \
1757 	((x) == 0xe ? "KEY_ALREADY_EXISTS": \
1758 	((x) == 0xf ? "HWRM_ERROR": \
1759 	((x) == 0x10 ? "BUSY": \
1760 	((x) == 0x11 ? "RESOURCE_LOCKED": \
1761 	((x) == 0x12 ? "PF_UNAVAILABLE": \
1762 	((x) == 0x13 ? "ENTITY_NOT_PRESENT": \
1764 	(((x) < 0x8080) ? \
1765 	((x) == 0x8000 ? "TLV_ENCAPSULATED_RESPONSE": \
1768 	((x) == 0xfffe ? "UNKNOWN_ERR": \
1769 	((x) == 0xffff ? "CMD_NOT_SUPPORTED": \
1830 #define HW_HASH_INDEX_SIZE 0x80
1835 #define HWRM_TARGET_ID_BONO 0xFFF8
1837 #define HWRM_TARGET_ID_KONG 0xFFF9
1839 #define HWRM_TARGET_ID_APE 0xFFFA
1846 #define HWRM_TARGET_ID_TOOLS 0xFFFD
1877 	 * * 0x0-0xFFF8 - The function ID
1878 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
1879 	 * * 0xFFFD - Reserved for user-space HWRM interface
1880 	 * * 0xFFFF - HWRM
2045 	 * If set to 0, then secure firmware update behavior is
2048 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED		UINT32_C(0x1)
2051 	 * If set to 0, then firmware based DCBX agent capability
2054 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED		UINT32_C(0x2)
2057 	 * If set to 0, then HWRM short command format is not supported.
2059 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED			UINT32_C(0x4)
2062 	 * If set to 0, then HWRM short command format is not required.
2064 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED			UINT32_C(0x8)
2067 	 * If set to 0, then the KONG host mailbox channel is not supported.
2068 	 * By default, this flag should be 0 for older version of core
2071 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED		UINT32_C(0x10)
2074 	 * to the legacy 16bit flow handle. If set to 0, then the 64bit flow
2075 	 * handle is not supported. By default, this flag should be 0 for
2078 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED		UINT32_C(0x20)
2082 	 * l2 traffic. If set to 0, then filter types not supported. By
2083 	 * default, this flag should be 0 for older version of core firmware.
2085 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED	UINT32_C(0x40)
2088 	 * model. If set to 0, firmware can't supported virtio vSwitch
2090 	 * By default, this flag should be 0 for older version of core
2093 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED	UINT32_C(0x80)
2096 	 * If set to 0, firmware is not capable to support trusted VF.
2097 	 * By default, this flag should be 0 for older version of core
2100 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED			UINT32_C(0x100)
2103 	 * If set to 0, firmware is not capable to support flow aging.
2104 	 * By default, this flag should be 0 for older version of core
2107 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED			UINT32_C(0x200)
2111 	 * If set to 0, firmware is not capable to support advanced flow
2112 	 * counters. By default, this flag should be 0 for older version of
2115 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED		UINT32_C(0x400)
2119 	 * If set to 0, firmware is not capable to support the use of the
2121 	 * By default, this flag should be 0 for older version of core
2124 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED			UINT32_C(0x800)
2128 	 * If set to 0, then the firmware doesn't support the advance CFA
2130 	 * By default, this flag should be 0 for older version of core
2133 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED		UINT32_C(0x1000)
2137 	 * If set to 0, then the firmware doesn't support TFLIB features.
2138 	 * By default, this flag should be 0 for older version of core
2141 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED			UINT32_C(0x2000)
2144 	 * If set to 0, then the firmware doesn't support TruFlow features.
2145 	 * By default, this flag should be 0 for older version of
2148 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED			UINT32_C(0x4000)
2151 	 * If set to 0, then firmware doesn't support secure boot.
2153 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE			UINT32_C(0x8000)
2157 	 * If set to 0, then firmware does not support the secure solution
2160 	#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_SOC_CAPABLE			UINT32_C(0x10000)
2219 	#define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC	UINT32_C(0x0)
2221 	#define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA	UINT32_C(0x1)
2223 	#define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
2256 	 * If set to 0, device is ready to accept all HWRM commands.
2258 	#define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY		UINT32_C(0x1)
2261 	 * If set to 0, external version not present.
2263 	#define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL		UINT32_C(0x2)
2271 	 * If this flag and dev_not_rdy flag are set to 0, device is ready
2274 	#define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE	UINT32_C(0x4)
2447 	#define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
2452 	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK  UINT32_C(0xf)
2453 	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT   0
2455 		#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION  UINT32_C(0x0)
2457 		#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM	UINT32_C(0x1)
2461 	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2462 	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2468 	#define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2469 	#define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
2472 	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
2473 	#define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
2492 	#define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
2497 	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK  UINT32_C(0xf)
2498 	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT   0
2500 		#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION  UINT32_C(0x0)
2502 		#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM	UINT32_C(0x1)
2508 	#define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU	UINT32_C(0x10)
2511 	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2512 	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2518 	#define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2519 	#define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
2522 	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
2523 	#define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
2545 	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
2550 	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK  UINT32_C(0xf)
2551 	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT   0
2553 		#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION  UINT32_C(0x0)
2555 		#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM	UINT32_C(0x1)
2559 	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2560 	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2566 	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2567 	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0
2570 	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
2571 	#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
2581 	 * can read. Bit 0 of the field will clear bits 15:0 of the first word
2599 	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
2606 	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK	UINT32_C(0xf)
2607 	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT	0
2612 	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU	UINT32_C(0x10)
2615 	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2616 	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2622 	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2623 	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
2626 	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
2627 	#define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
2646 	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
2653 	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK	UINT32_C(0xf)
2654 	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT	0
2659 	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU	UINT32_C(0x10)
2662 	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2663 	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2669 	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2670 	#define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
2694 	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
2699 	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK  UINT32_C(0xf)
2700 	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT   0
2702 		#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION  UINT32_C(0x0)
2704 		#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM	UINT32_C(0x1)
2708 	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2709 	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2712 	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2713 	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0
2716 	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
2717 	#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
2727 	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT UINT32_C(0x6)
2732 	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2733 	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2739 	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2740 	#define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
2757 	#define CE_BDS_ADD_DATA_MSG_OPCODE_MASK		UINT32_C(0xf)
2758 	#define CE_BDS_ADD_DATA_MSG_OPCODE_SFT		0
2764 		#define CE_BDS_ADD_DATA_MSG_OPCODE_ADD		UINT32_C(0x1)
2770 	#define CE_BDS_ADD_DATA_MSG_KID_MASK		UINT32_C(0xfffff0)
2776 	#define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK		UINT32_C(0xf000000)
2779 	#define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128	UINT32_C(0x1000000)
2781 	#define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256	UINT32_C(0x2000000)
2788 	#define CE_BDS_ADD_DATA_MSG_VERSION_MASK		UINT32_C(0xf0000000)
2791 		#define CE_BDS_ADD_DATA_MSG__TLS1_2			(UINT32_C(0x0) << 28)
2793 		#define CE_BDS_ADD_DATA_MSG__TLS1_3			(UINT32_C(0x1) << 28)
2797 	#define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f)
2798 	#define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT  0
2800 		#define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX  UINT32_C(0x11)
2802 		#define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX  UINT32_C(0x12)
2865 	#define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK	UINT32_C(0xf)
2866 	#define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT	0
2876 		#define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE	UINT32_C(0x2)
2882 	#define CE_BDS_DELETE_DATA_MSG_KID_MASK	UINT32_C(0xfffff0)
2885 	#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_MASK   UINT32_C(0x1f000000)
2888 		#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_TX	(UINT32_C(0x11) << 24)
2890 		#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_RX	(UINT32_C(0x12) << 24)
2892 		#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_TX  (UINT32_C(0x14) << 24)
2894 		#define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX  (UINT32_C(0x15) << 24)
2906 	#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK	UINT32_C(0xf)
2907 	#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT	0
2912 		#define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC	UINT32_C(0x3)
2918 	#define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK	UINT32_C(0xfffff0)
2924 	#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS	UINT32_C(0x1000000)
2929 		#define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK   (UINT32_C(0x0) << 24)
2956 	#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK	UINT32_C(0xf)
2957 	#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT	0
2962 		#define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC	UINT32_C(0x3)
2968 	#define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK	UINT32_C(0xfffff0)
2974 	#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS	UINT32_C(0x1000000)
2979 		#define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK  (UINT32_C(0x1) << 24)
3015 	#define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR	UINT32_C(0x1)
3027 	#define CRYPTO_PRESYNC_BD_CMD_FLAGS_FULL_REPLAY_RETRAN	UINT32_C(0x2)
3032 	 * Header of the active TLS record. This field is set to 0 during
3043 	 * be re-transmitted. This field is initialized to 0 during Mid-path BD
3054 	 * that need to be re-transmitted. This field is initialized to 0 during
3067 	 * initialized to 0 when presync BD is detected by taking the value from
3076 	 * Initial Vector (IV). The field is initialized to 0 during Mid-path BD
3094 	#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_MASK	UINT32_C(0xf)
3095 	#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_SFT	0
3101 		#define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD		UINT32_C(0x1)
3107 	#define CE_BDS_QUIC_ADD_DATA_MSG_KID_MASK		UINT32_C(0xfffff0)
3110 	#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_MASK	UINT32_C(0xf000000)
3113 		#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_128  (UINT32_C(0x1) << 24)
3115 		#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_256  (UINT32_C(0x2) << 24)
3117 		#define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20	(UINT32_C(0x3) << 24)
3120 	#define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_MASK	UINT32_C(0xf0000000)
3123 		#define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_2		(UINT32_C(0x0) << 28)
3125 		#define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_3		(UINT32_C(0x1) << 28)
3127 		#define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2		(UINT32_C(0x2) << 28)
3129 		#define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2_ROCE	(UINT32_C(0x3) << 28)
3131 		#define CE_BDS_QUIC_ADD_DATA_MSG__QUIC		(UINT32_C(0x4) << 28)
3135 	#define CE_BDS_QUIC_ADD_DATA_MSG_KEY_PHASE	UINT32_C(0x1)
3137 	#define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_MASK UINT32_C(0x3e)
3140 	#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_MASK   UINT32_C(0x7c0)
3143 		#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_TX  (UINT32_C(0x14) << 6)
3145 		#define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX  (UINT32_C(0x15) << 6)
3178 	#define BD_BASE_TYPE_MASK		UINT32_C(0x3f)
3179 	#define BD_BASE_TYPE_SFT		0
3184 		#define BD_BASE_TYPE_TX_BD_SHORT	UINT32_C(0x0)
3189 		#define BD_BASE_TYPE_TX_BD_EMPTY	UINT32_C(0x1)
3194 		#define BD_BASE_TYPE_RX_PROD_PKT	UINT32_C(0x4)
3199 		#define BD_BASE_TYPE_RX_PROD_BFR	UINT32_C(0x5)
3204 		#define BD_BASE_TYPE_RX_PROD_AGG	UINT32_C(0x6)
3209 		#define BD_BASE_TYPE_TX_BD_MP_CMD	UINT32_C(0x8)
3214 		#define BD_BASE_TYPE_TX_BD_PRESYNC_CMD  UINT32_C(0x9)
3220 		#define BD_BASE_TYPE_TX_BD_TIMEDTX	UINT32_C(0xa)
3225 		#define BD_BASE_TYPE_TX_BD_LONG	UINT32_C(0x10)
3231 		#define BD_BASE_TYPE_TX_BD_LONG_INLINE  UINT32_C(0x11)
3246 	#define TX_BD_SHORT_TYPE_MASK		UINT32_C(0x3f)
3247 	#define TX_BD_SHORT_TYPE_SFT		0
3252 		#define TX_BD_SHORT_TYPE_TX_BD_SHORT	UINT32_C(0x0)
3259 	#define TX_BD_SHORT_FLAGS_MASK	UINT32_C(0xffc0)
3266 	#define TX_BD_SHORT_FLAGS_PACKET_END	UINT32_C(0x40)
3272 	 * is set to 0, then the packet will be completed normally.
3276 	#define TX_BD_SHORT_FLAGS_NO_CMPL	UINT32_C(0x80)
3283 	 * BD in the packet. A value of 0 indicates
3288 	#define TX_BD_SHORT_FLAGS_BD_CNT_MASK	UINT32_C(0x1f00)
3298 	#define TX_BD_SHORT_FLAGS_LHINT_MASK	UINT32_C(0x6000)
3301 		#define TX_BD_SHORT_FLAGS_LHINT_LT512	(UINT32_C(0x0) << 13)
3303 		#define TX_BD_SHORT_FLAGS_LHINT_LT1K	(UINT32_C(0x1) << 13)
3305 		#define TX_BD_SHORT_FLAGS_LHINT_LT2K	(UINT32_C(0x2) << 13)
3307 		#define TX_BD_SHORT_FLAGS_LHINT_GTE2K	(UINT32_C(0x3) << 13)
3315 	 * is set to 0, then the Consumer Index is only updated as soon
3320 	#define TX_BD_SHORT_FLAGS_COAL_NOW	UINT32_C(0x8000)
3359 	#define TX_BD_LONG_TYPE_MASK		UINT32_C(0x3f)
3360 	#define TX_BD_LONG_TYPE_SFT		0
3365 		#define TX_BD_LONG_TYPE_TX_BD_LONG	UINT32_C(0x10)
3372 	#define TX_BD_LONG_FLAGS_MASK	UINT32_C(0xffc0)
3379 	#define TX_BD_LONG_FLAGS_PACKET_END	UINT32_C(0x40)
3385 	 * is set to 0, then the packet will be completed normally.
3389 	#define TX_BD_LONG_FLAGS_NO_CMPL	UINT32_C(0x80)
3396 	 * BD in the packet. A value of 0 indicates
3401 	#define TX_BD_LONG_FLAGS_BD_CNT_MASK	UINT32_C(0x1f00)
3411 	#define TX_BD_LONG_FLAGS_LHINT_MASK	UINT32_C(0x6000)
3414 		#define TX_BD_LONG_FLAGS_LHINT_LT512	(UINT32_C(0x0) << 13)
3416 		#define TX_BD_LONG_FLAGS_LHINT_LT1K	(UINT32_C(0x1) << 13)
3418 		#define TX_BD_LONG_FLAGS_LHINT_LT2K	(UINT32_C(0x2) << 13)
3420 		#define TX_BD_LONG_FLAGS_LHINT_GTE2K	(UINT32_C(0x3) << 13)
3428 	 * is set to 0, then the Consumer Index is only updated as soon
3433 	#define TX_BD_LONG_FLAGS_COAL_NOW	UINT32_C(0x8000)
3481 	#define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM	UINT32_C(0x1)
3490 	#define TX_BD_LONG_LFLAGS_IP_CHKSUM	UINT32_C(0x2)
3502 	#define TX_BD_LONG_LFLAGS_NOCRC		UINT32_C(0x4)
3521 	#define TX_BD_LONG_LFLAGS_STAMP		UINT32_C(0x8)
3538 	#define TX_BD_LONG_LFLAGS_T_IP_CHKSUM	UINT32_C(0x10)
3550 	#define TX_BD_LONG_LFLAGS_LSO		UINT32_C(0x20)
3554 	 * 0xffff.
3558 	 * 0x7fff.
3560 	#define TX_BD_LONG_LFLAGS_IPID_FMT	UINT32_C(0x40)
3572 	#define TX_BD_LONG_LFLAGS_T_IPID		UINT32_C(0x80)
3577 	#define TX_BD_LONG_LFLAGS_ROCE_CRC	UINT32_C(0x100)
3582 	#define TX_BD_LONG_LFLAGS_FCOE_CRC	UINT32_C(0x200)
3585 	 * to 0, then TWE provides the timestamp.
3592 	#define TX_BD_LONG_LFLAGS_BD_TS_EN	UINT32_C(0x400)
3597 	#define TX_BD_LONG_LFLAGS_DEBUG_TRACE	UINT32_C(0x800)
3608 	#define TX_BD_LONG_LFLAGS_STAMP_1STEP	UINT32_C(0x1000)
3615 	 * If outer UDP checksum is 0, then do not update it.
3619 	#define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM	UINT32_C(0x2000)
3628 	#define TX_BD_LONG_LFLAGS_OT_IPID		UINT32_C(0x4000)
3638 	#define TX_BD_LONG_LFLAGS_CRYPTO_EN	UINT32_C(0x8000)
3649 	#define TX_BD_LONG_HDR_SIZE_MASK	UINT32_C(0x1ff)
3650 	#define TX_BD_LONG_HDR_SIZE_SFT	0
3661 	#define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
3671 	#define TX_BD_LONG_MSS_MASK	UINT32_C(0x7fff)
3672 	#define TX_BD_LONG_MSS_SFT		0
3683 	#define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
3690 	#define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
3691 	#define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
3705 	#define TX_BD_LONG_CFA_META_VLAN_VID_MASK	UINT32_C(0xfff)
3706 	#define TX_BD_LONG_CFA_META_VLAN_VID_SFT	0
3708 	#define TX_BD_LONG_CFA_META_VLAN_DE		UINT32_C(0x1000)
3710 	#define TX_BD_LONG_CFA_META_VLAN_PRI_MASK	UINT32_C(0xe000)
3713 	#define TX_BD_LONG_CFA_META_VLAN_TPID_MASK	UINT32_C(0x70000)
3715 	/* 0x88a8 */
3716 		#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8	(UINT32_C(0x0) << 16)
3717 	/* 0x8100 */
3718 		#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100	(UINT32_C(0x1) << 16)
3719 	/* 0x9100 */
3720 		#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100	(UINT32_C(0x2) << 16)
3721 	/* 0x9200 */
3722 		#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200	(UINT32_C(0x3) << 16)
3723 	/* 0x9300 */
3724 		#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300	(UINT32_C(0x4) << 16)
3726 		#define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG	(UINT32_C(0x5) << 16)
3729 	#define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK   UINT32_C(0xff80000)
3737 	#define TX_BD_LONG_CFA_META_KEY_MASK		UINT32_C(0xf0000000)
3740 		#define TX_BD_LONG_CFA_META_KEY_NONE		(UINT32_C(0x0) << 28)
3742 	 * - meta[17:16] - TPID select value (0 = 0x8100).
3744 	 * - meta[11:0] - VID value.
3746 		#define TX_BD_LONG_CFA_META_KEY_VLAN_TAG	(UINT32_C(0x1) << 28)
3750 	 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
3752 	 * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if
3755 		#define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER  (UINT32_C(0x2) << 28)
3771 	#define TX_BD_LONG_INLINE_TYPE_MASK		UINT32_C(0x3f)
3772 	#define TX_BD_LONG_INLINE_TYPE_SFT		0
3777 		#define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE  UINT32_C(0x11)
3783 	#define TX_BD_LONG_INLINE_FLAGS_MASK		UINT32_C(0xffc0)
3790 	#define TX_BD_LONG_INLINE_FLAGS_PACKET_END	UINT32_C(0x40)
3794 	 * If this bit is set to 0, then the packet will be completed
3799 	#define TX_BD_LONG_INLINE_FLAGS_NO_CMPL	UINT32_C(0x80)
3805 	#define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK	UINT32_C(0x1f00)
3808 	#define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK	UINT32_C(0x6000)
3816 	 * is set to 0, then the Consumer Index is only updated as soon
3821 	#define TX_BD_LONG_INLINE_FLAGS_COAL_NOW	UINT32_C(0x8000)
3861 	#define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM	UINT32_C(0x1)
3868 	#define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM	UINT32_C(0x2)
3878 	#define TX_BD_LONG_INLINE_LFLAGS_NOCRC		UINT32_C(0x4)
3884 	#define TX_BD_LONG_INLINE_LFLAGS_STAMP		UINT32_C(0x8)
3891 	#define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM	UINT32_C(0x10)
3893 	 * This bit must be 0 for BDs of this type. LSO is not supported with
3896 	#define TX_BD_LONG_INLINE_LFLAGS_LSO		UINT32_C(0x20)
3898 	#define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT	UINT32_C(0x40)
3900 	#define TX_BD_LONG_INLINE_LFLAGS_T_IPID		UINT32_C(0x80)
3905 	#define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC	UINT32_C(0x100)
3910 	#define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC	UINT32_C(0x200)
3913 	 * to 0, then TWE provides the timestamp.
3920 	#define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN	UINT32_C(0x400)
3925 	#define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE	UINT32_C(0x800)
3931 	#define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP	UINT32_C(0x1000)
3938 	 * is 0, then do not update it. If outer UDP checksum is non zero, then
3941 	#define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM	UINT32_C(0x2000)
3950 	#define TX_BD_LONG_INLINE_LFLAGS_OT_IPID		UINT32_C(0x4000)
3960 	#define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN	UINT32_C(0x8000)
3963 	#define TX_BD_LONG_INLINE_UNUSED		UINT32_C(0x1)
3974 	#define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
3977 	#define TX_BD_LONG_INLINE_UNUSED_MASK	UINT32_C(0x7fff)
3978 	#define TX_BD_LONG_INLINE_UNUSED_SFT	0
3989 	#define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
3996 	#define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
3997 	#define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
4011 	#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK	UINT32_C(0xfff)
4012 	#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT	0
4014 	#define TX_BD_LONG_INLINE_CFA_META_VLAN_DE		UINT32_C(0x1000)
4016 	#define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK	UINT32_C(0xe000)
4019 	#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK	UINT32_C(0x70000)
4021 	/* 0x88a8 */
4022 		#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8	(UINT32_C(0x0) << 16)
4023 	/* 0x8100 */
4024 		#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100	(UINT32_C(0x1) << 16)
4025 	/* 0x9100 */
4026 		#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100	(UINT32_C(0x2) << 16)
4027 	/* 0x9200 */
4028 		#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200	(UINT32_C(0x3) << 16)
4029 	/* 0x9300 */
4030 		#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300	(UINT32_C(0x4) << 16)
4032 		#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG	(UINT32_C(0x5) << 16)
4034 	#define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK   UINT32_C(0xff80000)
4042 	#define TX_BD_LONG_INLINE_CFA_META_KEY_MASK		UINT32_C(0xf0000000)
4045 		#define TX_BD_LONG_INLINE_CFA_META_KEY_NONE		(UINT32_C(0x0) << 28)
4047 	 * - meta[17:16] - TPID select value (0 = 0x8100).
4049 	 * - meta[11:0] - VID value.
4051 		#define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG	(UINT32_C(0x1) << 28)
4055 	 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
4057 	 * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if
4060 		#define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER  (UINT32_C(0x2) << 28)
4069 	#define TX_BD_EMPTY_TYPE_MASK	UINT32_C(0x3f)
4070 	#define TX_BD_EMPTY_TYPE_SFT	0
4075 		#define TX_BD_EMPTY_TYPE_TX_BD_EMPTY  UINT32_C(0x1)
4089 	#define TX_BD_MP_CMD_TYPE_MASK	UINT32_C(0x3f)
4090 	#define TX_BD_MP_CMD_TYPE_SFT	0
4095 		#define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD  UINT32_C(0x8)
4097 	#define TX_BD_MP_CMD_FLAGS_MASK	UINT32_C(0xffc0)
4100 	#define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
4107 	#define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
4134 	#define TX_BD_PRESYNC_CMD_TYPE_MASK		UINT32_C(0x3f)
4135 	#define TX_BD_PRESYNC_CMD_TYPE_SFT		0
4140 		#define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD  UINT32_C(0x9)
4142 	#define TX_BD_PRESYNC_CMD_FLAGS_MASK		UINT32_C(0xffc0)
4145 	#define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK	UINT32_C(0xc0)
4152 	#define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK	UINT32_C(0x1f00)
4180 	#define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
4181 	#define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
4196 	#define TX_BD_TIMEDTX_TYPE_MASK	UINT32_C(0x3f)
4197 	#define TX_BD_TIMEDTX_TYPE_SFT		0
4203 		#define TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX	UINT32_C(0xa)
4206 	#define TX_BD_TIMEDTX_FLAGS_MASK	UINT32_C(0xffc0)
4212 	#define TX_BD_TIMEDTX_FLAGS_KIND_MASK	UINT32_C(0x1c0)
4222 		#define TX_BD_TIMEDTX_FLAGS_KIND_ASAP	(UINT32_C(0x0) << 6)
4231 		#define TX_BD_TIMEDTX_FLAGS_KIND_SO_TXTIME   (UINT32_C(0x1) << 6)
4239 		#define TX_BD_TIMEDTX_FLAGS_KIND_PACE	(UINT32_C(0x2) << 6)
4264 	#define TX_BD_TIMEDTX_RATE_VAL_MASK UINT32_C(0x1ffffff)
4265 	#define TX_BD_TIMEDTX_RATE_VAL_SFT 0
4280 	#define RX_PROD_PKT_BD_TYPE_MASK	UINT32_C(0x3f)
4281 	#define RX_PROD_PKT_BD_TYPE_SFT	0
4286 		#define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT	UINT32_C(0x4)
4288 	#define RX_PROD_PKT_BD_FLAGS_MASK	UINT32_C(0xffc0)
4300 	#define RX_PROD_PKT_BD_FLAGS_SOP_PAD	UINT32_C(0x40)
4310 	#define RX_PROD_PKT_BD_FLAGS_EOP_PAD	UINT32_C(0x80)
4325 	#define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
4359 	#define RX_PROD_BFR_BD_TYPE_MASK	UINT32_C(0x3f)
4360 	#define RX_PROD_BFR_BD_TYPE_SFT	0
4365 		#define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR  UINT32_C(0x5)
4367 	#define RX_PROD_BFR_BD_FLAGS_MASK	UINT32_C(0xffc0)
4397 	#define RX_PROD_AGG_BD_TYPE_MASK	UINT32_C(0x3f)
4398 	#define RX_PROD_AGG_BD_TYPE_SFT	0
4403 		#define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG	UINT32_C(0x6)
4405 	#define RX_PROD_AGG_BD_FLAGS_MASK	UINT32_C(0xffc0)
4416 	#define RX_PROD_AGG_BD_FLAGS_EOP_PAD	UINT32_C(0x40)
4457 	#define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK		UINT32_C(0x3f)
4458 	#define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT		0
4460 		#define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT	UINT32_C(0x1e)
4463 	#define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK		UINT32_C(0x3c0)
4466 		#define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK		(UINT32_C(0x0) << 6)
4468 		#define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR	(UINT32_C(0x1) << 6)
4473 		#define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR		(UINT32_C(0x2) << 6)
4478 		#define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR	(UINT32_C(0x3) << 6)
4486 		#define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR		(UINT32_C(0x4) << 6)
4491 		#define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR	(UINT32_C(0x5) << 6)
4498 		#define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL		(UINT32_C(0x6) << 6)
4503 		#define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL  (UINT32_C(0x7) << 6)
4505 	#define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK		UINT32_C(0xc00)
4508 	#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK		UINT32_C(0xff000)
4514 		#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ		(UINT32_C(0x0) << 12)
4519 		#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE		(UINT32_C(0x1) << 12)
4525 		#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR		(UINT32_C(0x2) << 12)
4531 		#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT	(UINT32_C(0x3) << 12)
4533 		#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE	(UINT32_C(0x4) << 12)
4538 		#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE	(UINT32_C(0x5) << 12)
4540 		#define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT	(UINT32_C(0x6) << 12)
4545 	 * between 0 and 128. A value of zero indicates that there is no DMA
4548 	#define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK	UINT32_C(0xff00000)
4554 	#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK	UINT32_C(0xf0000000)
4557 		#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA	(UINT32_C(0x2) << 28)
4559 		#define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA	(UINT32_C(0x3) << 28)
4570 	 * write 1. The odd passes will write 0.
4572 	#define CFA_CMPLS_CMP_DATA_MSG_V		UINT32_C(0x1)
4573 	#define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
4579 	#define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
4583 	#define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK	UINT32_C(0xf)
4584 	#define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT	0
4585 	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK  UINT32_C(0xf0)
4588 		#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION  (UINT32_C(0x0) << 4)
4590 		#define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM	(UINT32_C(0x1) << 4)
4594 	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
4595 	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
4602 	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
4603 	#define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
4648 	#define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK	UINT32_C(0x3f)
4649 	#define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT	0
4651 		#define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT  UINT32_C(0x1e)
4653 	#define CE_CMPLS_CMP_DATA_MSG_UNUSED0_MASK	UINT32_C(0xc0)
4659 	#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK	UINT32_C(0xf00)
4662 		#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED	(UINT32_C(0x0) << 8)
4664 		#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR	(UINT32_C(0x1) << 8)
4666 		#define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC	(UINT32_C(0x2) << 8)
4672 	#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK	UINT32_C(0xf000)
4675 		#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_TCE	(UINT32_C(0x0) << 12)
4677 		#define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE	(UINT32_C(0x1) << 12)
4681 	#define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK	UINT32_C(0xf)
4682 	#define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT	0
4684 		#define CE_CMPLS_CMP_DATA_MSG_STATUS_OK	UINT32_C(0x0)
4686 		#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR   UINT32_C(0x1)
4688 		#define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR  UINT32_C(0x2)
4690 		#define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR  UINT32_C(0x3)
4692 		#define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR   UINT32_C(0x4)
4697 		#define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR   UINT32_C(0x5)
4699 	#define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK	UINT32_C(0xfff0)
4710 	 * write 1. The odd passes will write 0.
4712 	#define CE_CMPLS_CMP_DATA_MSG_V	UINT32_C(0x1)
4713 	#define CE_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xfffffffe)
4720 	#define CE_CMPLS_CMP_DATA_MSG_KID_MASK	UINT32_C(0xfffff)
4721 	#define CE_CMPLS_CMP_DATA_MSG_KID_SFT	0
4722 	#define CE_CMPLS_CMP_DATA_MSG_UNUSED3_MASK UINT32_C(0xfff00000)
4737 	#define CMPL_BASE_TYPE_MASK		UINT32_C(0x3f)
4738 	#define CMPL_BASE_TYPE_SFT		0
4743 		#define CMPL_BASE_TYPE_TX_L2		UINT32_C(0x0)
4748 		#define CMPL_BASE_TYPE_NO_OP		UINT32_C(0x1)
4753 		#define CMPL_BASE_TYPE_TX_L2_COAL	UINT32_C(0x2)
4758 		#define CMPL_BASE_TYPE_TX_L2_PKT_TS	UINT32_C(0x4)
4765 		#define CMPL_BASE_TYPE_RX_TPA_START_V2   UINT32_C(0xd)
4772 		#define CMPL_BASE_TYPE_RX_L2_V2	UINT32_C(0xf)
4778 		#define CMPL_BASE_TYPE_RX_L2_COMPRESS	UINT32_C(0x10)
4783 		#define CMPL_BASE_TYPE_RX_L2		UINT32_C(0x11)
4789 		#define CMPL_BASE_TYPE_RX_AGG		UINT32_C(0x12)
4795 		#define CMPL_BASE_TYPE_RX_TPA_START	UINT32_C(0x13)
4801 		#define CMPL_BASE_TYPE_RX_TPA_END	UINT32_C(0x15)
4808 		#define CMPL_BASE_TYPE_RX_TPA_AGG	UINT32_C(0x16)
4813 		#define CMPL_BASE_TYPE_RX_L2_V3	UINT32_C(0x17)
4819 		#define CMPL_BASE_TYPE_RX_TPA_START_V3   UINT32_C(0x19)
4825 		#define CMPL_BASE_TYPE_STAT_EJECT	UINT32_C(0x1a)
4833 		#define CMPL_BASE_TYPE_VEE_FLUSH	UINT32_C(0x1c)
4838 		#define CMPL_BASE_TYPE_MID_PATH_SHORT	UINT32_C(0x1e)
4843 		#define CMPL_BASE_TYPE_MID_PATH_LONG	UINT32_C(0x1f)
4848 		#define CMPL_BASE_TYPE_HWRM_DONE	UINT32_C(0x20)
4850 		#define CMPL_BASE_TYPE_HWRM_FWD_REQ	UINT32_C(0x22)
4852 		#define CMPL_BASE_TYPE_HWRM_FWD_RESP	UINT32_C(0x24)
4854 		#define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
4856 		#define CMPL_BASE_TYPE_CQ_NOTIFICATION   UINT32_C(0x30)
4858 		#define CMPL_BASE_TYPE_SRQ_EVENT	UINT32_C(0x32)
4860 		#define CMPL_BASE_TYPE_DBQ_EVENT	UINT32_C(0x34)
4862 		#define CMPL_BASE_TYPE_QP_EVENT	UINT32_C(0x38)
4864 		#define CMPL_BASE_TYPE_FUNC_EVENT	UINT32_C(0x3a)
4873 	 * will write 1. The odd passes will write 0.
4876 	#define CMPL_BASE_V	UINT32_C(0x1)
4877 	#define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
4894 	#define TX_CMPL_TYPE_MASK	UINT32_C(0x3f)
4895 	#define TX_CMPL_TYPE_SFT	0
4900 		#define TX_CMPL_TYPE_TX_L2	UINT32_C(0x0)
4902 	#define TX_CMPL_FLAGS_MASK	UINT32_C(0xffc0)
4909 	#define TX_CMPL_FLAGS_ERROR	UINT32_C(0x40)
4913 	 * by the driver. When this bit is '0', it indicates that the
4917 	#define TX_CMPL_FLAGS_PUSH	UINT32_C(0x80)
4931 	 * will write 1. The odd passes will write 0.
4933 	#define TX_CMPL_V				UINT32_C(0x1)
4934 	#define TX_CMPL_ERRORS_MASK			UINT32_C(0xfffe)
4940 	#define TX_CMPL_ERRORS_BUFFER_ERROR_MASK		UINT32_C(0xe)
4943 		#define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR	(UINT32_C(0x0) << 1)
4948 		#define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT	(UINT32_C(0x2) << 1)
4954 	#define TX_CMPL_ERRORS_ZERO_LENGTH_PKT		UINT32_C(0x10)
4960 	#define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH	UINT32_C(0x20)
4966 	#define TX_CMPL_ERRORS_DMA_ERROR			UINT32_C(0x40)
4971 	#define TX_CMPL_ERRORS_HINT_TOO_SHORT		UINT32_C(0x80)
4977 	#define TX_CMPL_ERRORS_POISON_TLP_ERROR		UINT32_C(0x100)
4983 	#define TX_CMPL_ERRORS_INTERNAL_ERROR		UINT32_C(0x200)
4987 	 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4993 	#define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR	UINT32_C(0x400)
5011 	#define TX_CMPL_COAL_TYPE_MASK	UINT32_C(0x3f)
5012 	#define TX_CMPL_COAL_TYPE_SFT	0
5017 		#define TX_CMPL_COAL_TYPE_TX_L2_COAL   UINT32_C(0x2)
5019 	#define TX_CMPL_COAL_FLAGS_MASK	UINT32_C(0xffc0)
5026 	#define TX_CMPL_COAL_FLAGS_ERROR	UINT32_C(0x40)
5030 	 * by the driver. When this bit is '0', it indicates that the
5034 	#define TX_CMPL_COAL_FLAGS_PUSH	UINT32_C(0x80)
5057 	 * will write 1. The odd passes will write 0.
5059 	#define TX_CMPL_COAL_V				UINT32_C(0x1)
5060 	#define TX_CMPL_COAL_ERRORS_MASK			UINT32_C(0xfffe)
5066 	#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK		UINT32_C(0xe)
5069 		#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR	(UINT32_C(0x0) << 1)
5074 		#define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT	(UINT32_C(0x2) << 1)
5080 	#define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT		UINT32_C(0x10)
5086 	#define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH	UINT32_C(0x20)
5092 	#define TX_CMPL_COAL_ERRORS_DMA_ERROR			UINT32_C(0x40)
5097 	#define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT		UINT32_C(0x80)
5103 	#define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR		UINT32_C(0x100)
5109 	#define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR		UINT32_C(0x200)
5113 	 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
5119 	#define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR	UINT32_C(0x400)
5127 	#define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
5128 	#define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
5141 	#define TX_CMPL_PACKET_TIMESTAMP_TYPE_MASK		UINT32_C(0x3f)
5142 	#define TX_CMPL_PACKET_TIMESTAMP_TYPE_SFT		0
5147 		#define TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS	UINT32_C(0x4)
5149 	#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_MASK		UINT32_C(0xfc0)
5155 	#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_ERROR		UINT32_C(0x40)
5162 	#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE	UINT32_C(0x80)
5164 		#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PM	(UINT32_C(0x0) << 7)
5166 		#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA	(UINT32_C(0x1) << 7)
5177 	#define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_FALLBACK	UINT32_C(0x100)
5179 	 * For 2-step PTP timestamps, bits[3:0] of this field represent the
5187 	#define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_MASK	UINT32_C(0xf000)
5207 	 * will write 1. The odd passes will write 0.
5209 	#define TX_CMPL_PACKET_TIMESTAMP_V				UINT32_C(0x1)
5210 	#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_MASK			UINT32_C(0xfffe)
5217 	#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_MASK		UINT32_C(0xe)
5220 		#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_NO_ERROR	(UINT32_C(0x0) << 1)
5222 		#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT	(UINT32_C(0x2) << 1)
5228 	#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_ZERO_LENGTH_PKT		UINT32_C(0x10)
5233 	#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_EXCESSIVE_BD_LENGTH	UINT32_C(0x20)
5239 	 * for the timestamp completion and will always be '0'.
5241 	#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_DMA_ERROR			UINT32_C(0x40)
5246 	#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_HINT_TOO_SHORT		UINT32_C(0x80)
5252 	 * timestamp completion, and will always be '0'.
5254 	#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_POISON_TLP_ERROR		UINT32_C(0x100)
5260 	 * and will always be '0'.
5262 	#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_INTERNAL_ERROR		UINT32_C(0x200)
5266 	 * fields are invalid. When this bit is '0' in a timestamp
5270 	 * bit will always be '0'.
5272 	#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TIMESTAMP_INVALID_ERROR	UINT32_C(0x400)
5281 	 * and will always be '0'.
5283 	#define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TTX_OVERTIME_ERROR	UINT32_C(0x800)
5287 	 * This is bits [31:0] of the nanoseconds portion of the packet
5305 	#define RX_PKT_CMPL_TYPE_MASK			UINT32_C(0x3f)
5306 	#define RX_PKT_CMPL_TYPE_SFT			0
5311 		#define RX_PKT_CMPL_TYPE_RX_L2			UINT32_C(0x11)
5313 	#define RX_PKT_CMPL_FLAGS_MASK			UINT32_C(0xffc0)
5320 	#define RX_PKT_CMPL_FLAGS_ERROR			UINT32_C(0x40)
5322 	#define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK		UINT32_C(0x380)
5328 		#define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL		(UINT32_C(0x0) << 7)
5333 		#define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO		(UINT32_C(0x1) << 7)
5339 		#define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS		(UINT32_C(0x2) << 7)
5342 	#define RX_PKT_CMPL_FLAGS_RSS_VALID		UINT32_C(0x400)
5347 	#define RX_PKT_CMPL_FLAGS_PKT_METADATA_PRESENT	UINT32_C(0x800)
5352 	#define RX_PKT_CMPL_FLAGS_ITYPE_MASK		UINT32_C(0xf000)
5358 		#define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN		(UINT32_C(0x0) << 12)
5364 		#define RX_PKT_CMPL_FLAGS_ITYPE_IP			(UINT32_C(0x1) << 12)
5370 		#define RX_PKT_CMPL_FLAGS_ITYPE_TCP		(UINT32_C(0x2) << 12)
5376 		#define RX_PKT_CMPL_FLAGS_ITYPE_UDP		(UINT32_C(0x3) << 12)
5382 		#define RX_PKT_CMPL_FLAGS_ITYPE_FCOE		(UINT32_C(0x4) << 12)
5388 		#define RX_PKT_CMPL_FLAGS_ITYPE_ROCE		(UINT32_C(0x5) << 12)
5394 		#define RX_PKT_CMPL_FLAGS_ITYPE_ICMP		(UINT32_C(0x7) << 12)
5400 		#define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP	(UINT32_C(0x8) << 12)
5406 		#define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP	(UINT32_C(0x9) << 12)
5424 	 * will write 1. The odd passes will write 0.
5426 	#define RX_PKT_CMPL_V1	UINT32_C(0x1)
5433 	#define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
5436 	#define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
5440 	 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5457 	#define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0)
5464 	#define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1)
5471 	#define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2)
5477 	#define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3)
5506 	#define RX_PKT_CMPL_FLAGS2_IP_CS_CALC		UINT32_C(0x1)
5512 	#define RX_PKT_CMPL_FLAGS2_L4_CS_CALC		UINT32_C(0x2)
5518 	#define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC		UINT32_C(0x4)
5524 	#define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC		UINT32_C(0x8)
5526 	#define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK	UINT32_C(0xf0)
5529 		#define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE		(UINT32_C(0x0) << 4)
5532 	 * - metadata[11:0] contains the vlan VID value.
5537 		#define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN		(UINT32_C(0x1) << 4)
5542 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5543 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
5544 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
5545 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
5546 	 * - IPV4 = 0 (not populated)
5547 	 * - IPV6 = Flow Label[19:0]
5548 	 * - PPPoE = sessionID[15:0]
5549 	 * - MPLs = Outer label[19:0]
5550 	 * - UPAR = Selected[31:0] with bit mask
5552 		#define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 4)
5557 		#define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 4)
5562 	 * - metadata[8:0] contains the outer_l3_offset.
5567 		#define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET	(UINT32_C(0x4) << 4)
5571 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5575 	#define RX_PKT_CMPL_FLAGS2_IP_TYPE			UINT32_C(0x100)
5580 	#define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC	UINT32_C(0x200)
5585 	#define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK	UINT32_C(0xc00)
5593 	#define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK	UINT32_C(0xffff0000)
5601 	#define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5602 	#define RX_PKT_CMPL_METADATA_VID_SFT  0
5604 	#define RX_PKT_CMPL_METADATA_DE	UINT32_C(0x1000)
5606 	#define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5609 	#define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5615 	 * will write 1. The odd passes will write 0.
5617 	#define RX_PKT_CMPL_V2					UINT32_C(0x1)
5618 	#define RX_PKT_CMPL_ERRORS_MASK				UINT32_C(0xfffe)
5626 	#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK		UINT32_C(0xe)
5629 		#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER		(UINT32_C(0x0) << 1)
5638 		#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT		(UINT32_C(0x1) << 1)
5644 		#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP		(UINT32_C(0x2) << 1)
5649 		#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT		(UINT32_C(0x3) << 1)
5654 		#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH		(UINT32_C(0x5) << 1)
5660 	#define RX_PKT_CMPL_ERRORS_IP_CS_ERROR			UINT32_C(0x10)
5665 	#define RX_PKT_CMPL_ERRORS_L4_CS_ERROR			UINT32_C(0x20)
5670 	#define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR			UINT32_C(0x40)
5675 	#define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR			UINT32_C(0x80)
5680 	#define RX_PKT_CMPL_ERRORS_CRC_ERROR			UINT32_C(0x100)
5686 	#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK		UINT32_C(0xe00)
5692 		#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 9)
5698 		#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	(UINT32_C(0x1) << 9)
5704 		#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	(UINT32_C(0x2) << 9)
5710 		#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR	(UINT32_C(0x3) << 9)
5716 		#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	(UINT32_C(0x4) << 9)
5722 		#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	(UINT32_C(0x5) << 9)
5725 	 * have failed (e.g. TTL = 0) in the tunnel header. Valid
5728 		#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL		(UINT32_C(0x6) << 9)
5735 	#define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK			UINT32_C(0xf000)
5741 		#define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 12)
5748 		#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION		(UINT32_C(0x1) << 12)
5753 		#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN		(UINT32_C(0x2) << 12)
5756 	 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
5758 		#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL		(UINT32_C(0x3) << 12)
5764 		#define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR		(UINT32_C(0x4) << 12)
5770 		#define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR		(UINT32_C(0x5) << 12)
5775 		#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN		(UINT32_C(0x6) << 12)
5777 		#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL   (UINT32_C(0x7) << 12)
5783 		#define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN		(UINT32_C(0x8) << 12)
5798 	#define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
5799 	#define RX_PKT_CMPL_REORDER_SFT 0
5813 	#define RX_PKT_V2_CMPL_TYPE_MASK			UINT32_C(0x3f)
5814 	#define RX_PKT_V2_CMPL_TYPE_SFT			0
5821 		#define RX_PKT_V2_CMPL_TYPE_RX_L2_V2			UINT32_C(0xf)
5823 	#define RX_PKT_V2_CMPL_FLAGS_MASK			UINT32_C(0xffc0)
5830 	#define RX_PKT_V2_CMPL_FLAGS_ERROR			UINT32_C(0x40)
5832 	#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK		UINT32_C(0x380)
5838 		#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL		(UINT32_C(0x0) << 7)
5843 		#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO		(UINT32_C(0x1) << 7)
5849 		#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS		(UINT32_C(0x2) << 7)
5856 		#define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION	(UINT32_C(0x3) << 7)
5859 	#define RX_PKT_V2_CMPL_FLAGS_RSS_VALID		UINT32_C(0x400)
5868 	#define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT	UINT32_C(0x800)
5873 	#define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK		UINT32_C(0xf000)
5879 		#define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN		(UINT32_C(0x0) << 12)
5885 		#define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP			(UINT32_C(0x1) << 12)
5891 		#define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP		(UINT32_C(0x2) << 12)
5897 		#define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP		(UINT32_C(0x3) << 12)
5903 		#define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE		(UINT32_C(0x4) << 12)
5909 		#define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE		(UINT32_C(0x5) << 12)
5915 		#define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP		(UINT32_C(0x7) << 12)
5921 		#define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP	(UINT32_C(0x8) << 12)
5927 		#define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP	(UINT32_C(0x9) << 12)
5945 	 * will write 1. The odd passes will write 0.
5947 	#define RX_PKT_V2_CMPL_V1	UINT32_C(0x1)
5954 	#define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
5957 	#define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
5961 	 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5978 	#define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0)
5985 	#define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1)
5992 	#define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2)
5998 	#define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3)
6009 	#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK	UINT32_C(0x1ff)
6010 	#define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT	0
6012 	#define RX_PKT_V2_CMPL_METADATA1_MASK		UINT32_C(0xf000)
6014 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
6015 	#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK	UINT32_C(0x7000)
6017 	/* 0x88a8 */
6018 		#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8   (UINT32_C(0x0) << 12)
6019 	/* 0x8100 */
6020 		#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100   (UINT32_C(0x1) << 12)
6021 	/* 0x9100 */
6022 		#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100   (UINT32_C(0x2) << 12)
6023 	/* 0x9200 */
6024 		#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200   (UINT32_C(0x3) << 12)
6025 	/* 0x9300 */
6026 		#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300   (UINT32_C(0x4) << 12)
6028 		#define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG	(UINT32_C(0x5) << 12)
6030 	/* When meta_format != 0, this value is the VLAN valid. */
6031 	#define RX_PKT_V2_CMPL_METADATA1_VALID		UINT32_C(0x8000)
6047 	 * When this bit is '0', the cs_ok field has the following definition:-
6048 	 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
6055 	 * hdr_cnt[2:0] = The number of header groups that were parsed by the
6061 	#define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE		UINT32_C(0x8)
6063 	#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK	UINT32_C(0xf0)
6066 		#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE		(UINT32_C(0x0) << 4)
6069 	 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
6070 	 * de, vid[11:0]} The metadata2 field contains the table scope
6071 	 * and action record pointer. - metadata2[25:0] contains the
6075 		#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR	(UINT32_C(0x1) << 4)
6079 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
6082 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
6083 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
6084 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
6085 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
6086 	 * - IPv4 = 0 (not populated)
6087 	 * - IPv6 = Flow Label[19:0]
6088 	 * - PPPoE = sessionID[15:0]
6089 	 * - MPLs = Outer label[19:0]
6090 	 * - UPAR = Selected[31:0] with bit mask
6092 		#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 4)
6096 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
6100 		#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 4)
6104 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
6107 	 * - metadata2[8:0] contains the outer_l3_offset.
6112 		#define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET	(UINT32_C(0x4) << 4)
6116 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6120 	#define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE			UINT32_C(0x100)
6125 	#define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC	UINT32_C(0x200)
6131 	#define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK		UINT32_C(0xfc00)
6139 	#define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK	UINT32_C(0xffff0000)
6144 	 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
6145 	 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
6146 	 *   act_rec_ptr[25:0]}
6147 	 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
6148 	 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
6149 	 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
6158 	 * will write 1. The odd passes will write 0.
6160 	#define RX_PKT_V2_CMPL_HI_V2					UINT32_C(0x1)
6161 	#define RX_PKT_V2_CMPL_HI_ERRORS_MASK				UINT32_C(0xfffe)
6169 	#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK		UINT32_C(0xe)
6172 		#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER		(UINT32_C(0x0) << 1)
6182 		#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT		(UINT32_C(0x1) << 1)
6189 		#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP		(UINT32_C(0x2) << 1)
6194 		#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT		(UINT32_C(0x3) << 1)
6199 		#define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH		(UINT32_C(0x5) << 1)
6205 	#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK		UINT32_C(0x70)
6211 		#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 4)
6216 		#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION	(UINT32_C(0x1) << 4)
6221 		#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN	(UINT32_C(0x2) << 4)
6227 		#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR	(UINT32_C(0x3) << 4)
6233 		#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR	(UINT32_C(0x4) << 4)
6236 	 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
6239 		#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL	(UINT32_C(0x5) << 4)
6244 		#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR	(UINT32_C(0x6) << 4)
6249 		#define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR	(UINT32_C(0x7) << 4)
6255 	#define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR			UINT32_C(0x100)
6260 	#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK		UINT32_C(0xe00)
6266 		#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 9)
6271 		#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	(UINT32_C(0x1) << 9)
6276 		#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	(UINT32_C(0x2) << 9)
6282 		#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	(UINT32_C(0x3) << 9)
6288 		#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	(UINT32_C(0x4) << 9)
6291 	 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
6293 		#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL		(UINT32_C(0x5) << 9)
6298 		#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR		(UINT32_C(0x6) << 9)
6303 		#define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR		(UINT32_C(0x7) << 9)
6310 	#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK			UINT32_C(0xf000)
6316 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 12)
6323 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION		(UINT32_C(0x1) << 12)
6328 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN		(UINT32_C(0x2) << 12)
6331 	 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
6333 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL		(UINT32_C(0x3) << 12)
6339 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR		(UINT32_C(0x4) << 12)
6345 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR		(UINT32_C(0x5) << 12)
6350 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN		(UINT32_C(0x6) << 12)
6352 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL   (UINT32_C(0x7) << 12)
6358 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN		(UINT32_C(0x8) << 12)
6363 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR		(UINT32_C(0x9) << 12)
6368 		#define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR		(UINT32_C(0xa) << 12)
6376 	#define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
6377 	#define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
6379 	#define RX_PKT_V2_CMPL_HI_METADATA0_DE	UINT32_C(0x1000)
6381 	#define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
6401 	#define RX_PKT_V3_CMPL_TYPE_MASK			UINT32_C(0x3f)
6402 	#define RX_PKT_V3_CMPL_TYPE_SFT			0
6409 		#define RX_PKT_V3_CMPL_TYPE_RX_L2_V3			UINT32_C(0x17)
6411 	#define RX_PKT_V3_CMPL_FLAGS_MASK			UINT32_C(0xffc0)
6418 	#define RX_PKT_V3_CMPL_FLAGS_ERROR			UINT32_C(0x40)
6420 	#define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_MASK		UINT32_C(0x380)
6426 		#define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_NORMAL		(UINT32_C(0x0) << 7)
6431 		#define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_JUMBO		(UINT32_C(0x1) << 7)
6437 		#define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_HDS		(UINT32_C(0x2) << 7)
6444 		#define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION	(UINT32_C(0x3) << 7)
6447 	#define RX_PKT_V3_CMPL_FLAGS_RSS_VALID		UINT32_C(0x400)
6456 	#define RX_PKT_V3_CMPL_FLAGS_PKT_METADATA_PRESENT	UINT32_C(0x800)
6461 	#define RX_PKT_V3_CMPL_FLAGS_ITYPE_MASK		UINT32_C(0xf000)
6467 		#define RX_PKT_V3_CMPL_FLAGS_ITYPE_NOT_KNOWN		(UINT32_C(0x0) << 12)
6473 		#define RX_PKT_V3_CMPL_FLAGS_ITYPE_IP			(UINT32_C(0x1) << 12)
6479 		#define RX_PKT_V3_CMPL_FLAGS_ITYPE_TCP		(UINT32_C(0x2) << 12)
6485 		#define RX_PKT_V3_CMPL_FLAGS_ITYPE_UDP		(UINT32_C(0x3) << 12)
6491 		#define RX_PKT_V3_CMPL_FLAGS_ITYPE_FCOE		(UINT32_C(0x4) << 12)
6497 		#define RX_PKT_V3_CMPL_FLAGS_ITYPE_ROCE		(UINT32_C(0x5) << 12)
6503 		#define RX_PKT_V3_CMPL_FLAGS_ITYPE_ICMP		(UINT32_C(0x7) << 12)
6509 		#define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP	(UINT32_C(0x8) << 12)
6517 		#define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP	(UINT32_C(0x9) << 12)
6535 	 * will write 1. The odd passes will write 0.
6537 	#define RX_PKT_V3_CMPL_V1		UINT32_C(0x1)
6544 	#define RX_PKT_V3_CMPL_AGG_BUFS_MASK	UINT32_C(0x3e)
6547 	#define RX_PKT_V3_CMPL_UNUSED1		UINT32_C(0x40)
6550 	 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
6560 	#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_MASK   UINT32_C(0xff80)
6567 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_0   (UINT32_C(0x0) << 7)
6572 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_1   (UINT32_C(0x1) << 7)
6579 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_2   (UINT32_C(0x2) << 7)
6585 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_3   (UINT32_C(0x3) << 7)
6590 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_4   (UINT32_C(0x4) << 7)
6595 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_5   (UINT32_C(0x5) << 7)
6601 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_6   (UINT32_C(0x6) << 7)
6607 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_7   (UINT32_C(0x7) << 7)
6614 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_8   (UINT32_C(0x8) << 7)
6621 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_9   (UINT32_C(0x9) << 7)
6628 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_10  (UINT32_C(0xa) << 7)
6635 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11  (UINT32_C(0xb) << 7)
6637 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_12  (UINT32_C(0xc) << 7)
6642 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_13  (UINT32_C(0xd) << 7)
6647 		#define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14  (UINT32_C(0xe) << 7)
6661 	#define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_MASK	UINT32_C(0x1ff)
6662 	#define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_SFT	0
6664 	#define RX_PKT_V3_CMPL_METADATA1_MASK		UINT32_C(0xf000)
6666 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
6667 	#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_MASK	UINT32_C(0x7000)
6669 	/* 0x88a8 */
6670 		#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID88A8   (UINT32_C(0x0) << 12)
6671 	/* 0x8100 */
6672 		#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID8100   (UINT32_C(0x1) << 12)
6673 	/* 0x9100 */
6674 		#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9100   (UINT32_C(0x2) << 12)
6675 	/* 0x9200 */
6676 		#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9200   (UINT32_C(0x3) << 12)
6677 	/* 0x9300 */
6678 		#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9300   (UINT32_C(0x4) << 12)
6680 		#define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG	(UINT32_C(0x5) << 12)
6682 	/* When meta_format != 0, this value is the VLAN valid. */
6683 	#define RX_PKT_V3_CMPL_METADATA1_VALID		UINT32_C(0x8000)
6703 	#define RX_PKT_V3_CMPL_HI_FLAGS2_IP_CS_CALC		UINT32_C(0x1)
6709 	#define RX_PKT_V3_CMPL_HI_FLAGS2_L4_CS_CALC		UINT32_C(0x2)
6715 	#define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_CS_CALC		UINT32_C(0x4)
6721 	#define RX_PKT_V3_CMPL_HI_FLAGS2_T_L4_CS_CALC		UINT32_C(0x8)
6723 	#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_MASK	UINT32_C(0xf0)
6726 		#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_NONE		(UINT32_C(0x0) << 4)
6729 	 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
6730 	 * de, vid[11:0]} The metadata2 field contains the table scope
6731 	 * and action record pointer. - metadata2[25:0] contains the
6735 		#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR	(UINT32_C(0x1) << 4)
6739 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
6742 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
6743 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
6744 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
6745 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
6746 	 * - IPv4 = 0 (not populated)
6747 	 * - IPv6 = Flow Label[19:0]
6748 	 * - PPPoE = sessionID[15:0]
6749 	 * - MPLs = Outer label[19:0]
6750 	 * - UPAR = Selected[31:0] with bit mask
6752 		#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 4)
6756 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
6760 		#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 4)
6764 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
6767 	 * - metadata2[8:0] contains the outer_l3_offset.
6772 		#define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET	(UINT32_C(0x4) << 4)
6776 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6780 	#define RX_PKT_V3_CMPL_HI_FLAGS2_IP_TYPE			UINT32_C(0x100)
6785 	#define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC	UINT32_C(0x200)
6791 	#define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE		UINT32_C(0x400)
6793 		#define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV4		(UINT32_C(0x0) << 10)
6795 		#define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6		(UINT32_C(0x1) << 10)
6803 	#define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK	UINT32_C(0xffff0000)
6808 	 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
6809 	 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
6810 	 *   act_rec_ptr[25:0]}
6811 	 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
6812 	 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
6813 	 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
6820 	 * will write 1. The odd passes will write 0.
6822 	#define RX_PKT_V3_CMPL_HI_V2					UINT32_C(0x1)
6823 	#define RX_PKT_V3_CMPL_HI_ERRORS_MASK				UINT32_C(0xfffe)
6831 	#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_MASK		UINT32_C(0xe)
6834 		#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER		(UINT32_C(0x0) << 1)
6841 		#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT		(UINT32_C(0x1) << 1)
6848 		#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP		(UINT32_C(0x2) << 1)
6853 		#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT		(UINT32_C(0x3) << 1)
6858 		#define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH		(UINT32_C(0x5) << 1)
6861 	#define RX_PKT_V3_CMPL_HI_ERRORS_IP_CS_ERROR			UINT32_C(0x10)
6866 	#define RX_PKT_V3_CMPL_HI_ERRORS_L4_CS_ERROR			UINT32_C(0x20)
6871 	#define RX_PKT_V3_CMPL_HI_ERRORS_T_IP_CS_ERROR			UINT32_C(0x40)
6873 	#define RX_PKT_V3_CMPL_HI_ERRORS_T_L4_CS_ERROR			UINT32_C(0x80)
6878 	#define RX_PKT_V3_CMPL_HI_ERRORS_CRC_ERROR			UINT32_C(0x100)
6883 	#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_MASK		UINT32_C(0xe00)
6889 		#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 9)
6894 		#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	(UINT32_C(0x1) << 9)
6899 		#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	(UINT32_C(0x2) << 9)
6905 		#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	(UINT32_C(0x3) << 9)
6911 		#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	(UINT32_C(0x4) << 9)
6914 	 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
6916 		#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL		(UINT32_C(0x5) << 9)
6922 		#define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR		(UINT32_C(0x6) << 9)
6929 	#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_MASK			UINT32_C(0xf000)
6935 		#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 12)
6942 		#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION		(UINT32_C(0x1) << 12)
6947 		#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN		(UINT32_C(0x2) << 12)
6950 	 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
6952 		#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL		(UINT32_C(0x3) << 12)
6958 		#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR		(UINT32_C(0x4) << 12)
6964 		#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR		(UINT32_C(0x5) << 12)
6969 		#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN		(UINT32_C(0x6) << 12)
6971 		#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL   (UINT32_C(0x7) << 12)
6977 		#define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN		(UINT32_C(0x8) << 12)
6985 	#define RX_PKT_V3_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
6986 	#define RX_PKT_V3_CMPL_HI_METADATA0_VID_SFT 0
6988 	#define RX_PKT_V3_CMPL_HI_METADATA0_DE	UINT32_C(0x1000)
6990 	#define RX_PKT_V3_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
7013 	#define RX_PKT_COMPRESS_CMPL_TYPE_MASK		UINT32_C(0x3f)
7014 	#define RX_PKT_COMPRESS_CMPL_TYPE_SFT			0
7022 		#define RX_PKT_COMPRESS_CMPL_TYPE_RX_L2_COMPRESS	UINT32_C(0x10)
7024 	#define RX_PKT_COMPRESS_CMPL_FLAGS_MASK		UINT32_C(0xffc0)
7031 	#define RX_PKT_COMPRESS_CMPL_FLAGS_ERROR		UINT32_C(0x40)
7037 	#define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE		UINT32_C(0x100)
7039 		#define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV4	(UINT32_C(0x0) << 8)
7041 		#define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV6	(UINT32_C(0x1) << 8)
7045 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
7049 	#define RX_PKT_COMPRESS_CMPL_FLAGS_IP_TYPE		UINT32_C(0x200)
7051 	#define RX_PKT_COMPRESS_CMPL_FLAGS_RSS_VALID		UINT32_C(0x400)
7056 	#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_MASK		UINT32_C(0xf000)
7062 		#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_NOT_KNOWN	(UINT32_C(0x0) << 12)
7068 		#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_IP		(UINT32_C(0x1) << 12)
7074 		#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_TCP		(UINT32_C(0x2) << 12)
7080 		#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_UDP		(UINT32_C(0x3) << 12)
7086 		#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_FCOE		(UINT32_C(0x4) << 12)
7092 		#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ROCE		(UINT32_C(0x5) << 12)
7098 		#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ICMP		(UINT32_C(0x7) << 12)
7104 		#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP   (UINT32_C(0x8) << 12)
7112 		#define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP	(UINT32_C(0x9) << 12)
7132 	 * will write 1. The odd passes will write 0.
7134 	#define RX_PKT_COMPRESS_CMPL_V1				UINT32_C(0x1)
7136 	#define RX_PKT_COMPRESS_CMPL_UNUSED_MASK			UINT32_C(0xe)
7138 	#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_MASK		UINT32_C(0xff0)
7141 	#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_ERROR	UINT32_C(0x10)
7146 	#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_ERROR	UINT32_C(0x20)
7151 	#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_ERROR	UINT32_C(0x40)
7153 	#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_ERROR	UINT32_C(0x80)
7159 	#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_CALC	UINT32_C(0x100)
7165 	#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_CALC	UINT32_C(0x200)
7171 	#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_CALC	UINT32_C(0x400)
7177 	#define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_CALC	UINT32_C(0x800)
7179 	#define RX_PKT_COMPRESS_CMPL_METADATA1_MASK		UINT32_C(0xf000)
7181 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
7182 	#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_MASK	UINT32_C(0x7000)
7184 	/* 0x88a8 */
7185 		#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID88A8	(UINT32_C(0x0) << 12)
7186 	/* 0x8100 */
7187 		#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID8100	(UINT32_C(0x1) << 12)
7188 	/* 0x9100 */
7189 		#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9100	(UINT32_C(0x2) << 12)
7190 	/* 0x9200 */
7191 		#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9200	(UINT32_C(0x3) << 12)
7192 	/* 0x9300 */
7193 		#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9300	(UINT32_C(0x4) << 12)
7195 		#define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPIDCFG	(UINT32_C(0x5) << 12)
7197 	/* When meta_format != 0, this value is the VLAN valid. */
7198 	#define RX_PKT_COMPRESS_CMPL_METADATA1_VALID		UINT32_C(0x8000)
7201 	/* When meta_format!=0, this value is the VLAN VID. */
7202 	#define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_MASK UINT32_C(0xfff)
7203 	#define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_SFT 0
7204 	/* When meta_format!=0, this value is the VLAN DE. */
7205 	#define RX_PKT_COMPRESS_CMPL_VLANC_TCID_DE	UINT32_C(0x1000)
7206 	/* When meta_format!=0, this value is the VLAN PRI. */
7207 	#define RX_PKT_COMPRESS_CMPL_VLANC_TCID_PRI_MASK UINT32_C(0xe000)
7211 	#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_MASK				UINT32_C(0xffff)
7212 	#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_SFT				0
7219 	#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_MASK				UINT32_C(0x1f0000)
7221 	#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_MASK				UINT32_C(0x1fe00000)
7228 	#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_MASK			UINT32_C(0x1e00000)
7234 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 2…
7241 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_VERSION		(UINT32_C(0x1…
7246 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN		(UINT32_C(0x2…
7249 	 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
7251 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_TTL		(UINT32_C(0x3) <<…
7257 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_IP_TOTAL_ERROR		(UINT32_C(0x4…
7263 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR		(UINT32_C(0x…
7268 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN		(UINT32_C(0x6…
7270 …PRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL   (UINT32_C(0x7) << 21)
7276 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN		(UINT32_C(0x8…
7282 	#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_MASK		UINT32_C(0xe000000)
7288 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) <<…
7293 …_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	(UINT32_C(0x1) << 25)
7298 …_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	(UINT32_C(0x2) << 25)
7304 …_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	(UINT32_C(0x3) << 25)
7310 …PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	(UINT32_C(0x4) << 25)
7313 	 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
7315 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL		(UINT32_C(0x5…
7320 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR		(UINT32_C(0x…
7325 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR		(UINT32_C(0x…
7331 	#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_CRC_ERROR			UINT32_C(0x10000000)
7333 	#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_UNUSED1_MASK				UINT32_C(0xe0000000)
7339  * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7352 	#define RX_TPA_START_CMPL_TYPE_MASK		UINT32_C(0x3f)
7353 	#define RX_TPA_START_CMPL_TYPE_SFT		0
7359 		#define RX_TPA_START_CMPL_TYPE_RX_TPA_START	UINT32_C(0x13)
7361 	#define RX_TPA_START_CMPL_FLAGS_MASK		UINT32_C(0xffc0)
7363 	/* This bit will always be '0' for TPA start completions. */
7364 	#define RX_TPA_START_CMPL_FLAGS_ERROR		UINT32_C(0x40)
7366 	#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK	UINT32_C(0x380)
7376 		#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO	(UINT32_C(0x1) << 7)
7382 		#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS	(UINT32_C(0x2) << 7)
7391 		#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO   (UINT32_C(0x5) << 7)
7401 		#define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS	(UINT32_C(0x6) << 7)
7404 	#define RX_TPA_START_CMPL_FLAGS_RSS_VALID	UINT32_C(0x400)
7406 	#define RX_TPA_START_CMPL_FLAGS_UNUSED		UINT32_C(0x800)
7411 	#define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK	UINT32_C(0xf000)
7417 		#define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP		(UINT32_C(0x2) << 12)
7432 	 * will write 1. The odd passes will write 0.
7438 	 * will write 1. The odd passes will write 0.
7440 	#define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
7444 	 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
7448 	 * * 0: The RSS hash was computed over source IP address,
7479 	#define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
7480 	#define RX_TPA_START_CMPL_UNUSED2_SFT 0
7486 	#define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
7499  * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7510 	#define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC	UINT32_C(0x1)
7516 	#define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC	UINT32_C(0x2)
7522 	#define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC	UINT32_C(0x4)
7528 	#define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC	UINT32_C(0x8)
7530 	#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
7533 		#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE   (UINT32_C(0x0) << 4)
7536 	 * - metadata[11:0] contains the vlan VID value.
7541 		#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN   (UINT32_C(0x1) << 4)
7545 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
7547 	#define RX_TPA_START_CMPL_FLAGS2_IP_TYPE	UINT32_C(0x100)
7554 	#define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
7555 	#define RX_TPA_START_CMPL_METADATA_VID_SFT  0
7557 	#define RX_TPA_START_CMPL_METADATA_DE	UINT32_C(0x1000)
7559 	#define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
7562 	#define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
7568 	 * will write 1. The odd passes will write 0.
7570 	#define RX_TPA_START_CMPL_V2	UINT32_C(0x1)
7587 	#define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
7588 	#define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
7593 	#define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
7599 	#define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
7606 	#define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK  UINT32_C(0xf8000000)
7612  * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7627 	#define RX_TPA_START_V2_CMPL_TYPE_MASK			UINT32_C(0x3f)
7628 	#define RX_TPA_START_V2_CMPL_TYPE_SFT			0
7636 		#define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2		UINT32_C(0xd)
7638 	#define RX_TPA_START_V2_CMPL_FLAGS_MASK			UINT32_C(0xffc0)
7644 	#define RX_TPA_START_V2_CMPL_FLAGS_ERROR			UINT32_C(0x40)
7646 	#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK		UINT32_C(0x380)
7656 		#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO		(UINT32_C(0x1) << 7)
7662 		#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS		(UINT32_C(0x2) << 7)
7670 		#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO	(UINT32_C(0x4) << 7)
7679 		#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO	(UINT32_C(0x5) << 7)
7689 		#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS	(UINT32_C(0x6) << 7)
7697 		#define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS	(UINT32_C(0x7) << 7)
7700 	#define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID		UINT32_C(0x400)
7709 	#define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT	UINT32_C(0x800)
7714 	#define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK		UINT32_C(0xf000)
7720 		#define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP		(UINT32_C(0x2) << 12)
7737 	 * will write 1. The odd passes will write 0.
7743 	 * will write 1. The odd passes will write 0.
7745 	#define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
7749 	 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
7753 	 * * 0: The RSS hash was computed over source IP address,
7788 	#define RX_TPA_START_V2_CMPL_AGG_ID_MASK		UINT32_C(0xfff)
7789 	#define RX_TPA_START_V2_CMPL_AGG_ID_SFT		0
7790 	#define RX_TPA_START_V2_CMPL_METADATA1_MASK		UINT32_C(0xf000)
7792 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
7793 	#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK	UINT32_C(0x7000)
7795 	/* 0x88a8 */
7796 		#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8   (UINT32_C(0x0) << 12)
7797 	/* 0x8100 */
7798 		#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100   (UINT32_C(0x1) << 12)
7799 	/* 0x9100 */
7800 		#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100   (UINT32_C(0x2) << 12)
7801 	/* 0x9200 */
7802 		#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200   (UINT32_C(0x3) << 12)
7803 	/* 0x9300 */
7804 		#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300   (UINT32_C(0x4) << 12)
7806 		#define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG	(UINT32_C(0x5) << 12)
7808 	/* When meta_format != 0, this value is the VLAN valid. */
7809 	#define RX_TPA_START_V2_CMPL_METADATA1_VALID		UINT32_C(0x8000)
7823  * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7830 	#define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO			UINT32_C(0x4)
7832 	 * When this bit is '0', the cs_ok field has the following definition:-
7833 	 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
7840 	 * hdr_cnt[2:0] = The number of header groups that were parsed by the
7846 	#define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE		UINT32_C(0x8)
7848 	#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK	UINT32_C(0xf0)
7851 		#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE		(UINT32_C(0x0) << 4)
7854 	 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
7855 	 * de, vid[11:0]} The metadata2 field contains the table scope
7856 	 * and action record pointer. - metadata2[25:0] contains the
7860 		#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR	(UINT32_C(0x1) << 4)
7864 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
7867 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
7868 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
7869 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
7870 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
7871 	 * - IPv4 = 0 (not populated)
7872 	 * - IPv6 = Flow Label[19:0]
7873 	 * - PPPoE = sessionID[15:0]
7874 	 * - MPLs = Outer label[19:0]
7875 	 * - UPAR = Selected[31:0] with bit mask
7877 		#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 4)
7881 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
7885 		#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 4)
7889 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
7892 	 * - metadata2[8:0] contains the outer_l3_offset.
7897 		#define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET	(UINT32_C(0x4) << 4)
7901 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
7905 	#define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE			UINT32_C(0x100)
7910 	#define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC	UINT32_C(0x200)
7920 	#define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK		UINT32_C(0xfc00)
7930 	#define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK	UINT32_C(0xffff0000)
7935 	 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
7936 	 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
7937 	 *   act_rec_ptr[25:0]}
7938 	 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
7939 	 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
7940 	 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
7949 	 * will write 1. The odd passes will write 0.
7951 	#define RX_TPA_START_V2_CMPL_V2				UINT32_C(0x1)
7952 	#define RX_TPA_START_V2_CMPL_ERRORS_MASK			UINT32_C(0xfffe)
7959 	#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK	UINT32_C(0xe)
7962 		#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER	(UINT32_C(0x0) << 1)
7973 		#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (UINT32_C(0x1) << 1)
7978 		#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT	(UINT32_C(0x3) << 1)
7983 		#define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH	(UINT32_C(0x5) << 1)
7990 	/* When meta_format != 0, this value is the VLAN VID. */
7991 	#define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
7992 	#define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
7993 	/* When meta_format != 0, this value is the VLAN DE. */
7994 	#define RX_TPA_START_V2_CMPL_METADATA0_DE	UINT32_C(0x1000)
7995 	/* When meta_format != 0, this value is the VLAN PRI. */
7996 	#define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
8002 	 * hdr_offsets[8:0] contains the outer_l3_offset.
8012  * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
8027 	#define RX_TPA_START_V3_CMPL_TYPE_MASK			UINT32_C(0x3f)
8028 	#define RX_TPA_START_V3_CMPL_TYPE_SFT			0
8036 		#define RX_TPA_START_V3_CMPL_TYPE_RX_TPA_START_V3		UINT32_C(0x19)
8038 	#define RX_TPA_START_V3_CMPL_FLAGS_MASK			UINT32_C(0xffc0)
8044 	#define RX_TPA_START_V3_CMPL_FLAGS_ERROR			UINT32_C(0x40)
8046 	#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_MASK		UINT32_C(0x380)
8056 		#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_JUMBO		(UINT32_C(0x1) << 7)
8062 		#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_HDS		(UINT32_C(0x2) << 7)
8070 		#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_JUMBO	(UINT32_C(0x4) << 7)
8079 		#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_JUMBO	(UINT32_C(0x5) << 7)
8089 		#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_HDS	(UINT32_C(0x6) << 7)
8097 		#define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_HDS	(UINT32_C(0x7) << 7)
8100 	#define RX_TPA_START_V3_CMPL_FLAGS_RSS_VALID		UINT32_C(0x400)
8109 	#define RX_TPA_START_V3_CMPL_FLAGS_PKT_METADATA_PRESENT	UINT32_C(0x800)
8114 	#define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_MASK		UINT32_C(0xf000)
8120 		#define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_TCP		(UINT32_C(0x2) << 12)
8138 	 * will write 1. The odd passes will write 0.
8140 	#define RX_TPA_START_V3_CMPL_V1		UINT32_C(0x1)
8142 	#define RX_TPA_START_V3_CMPL_UNUSED1_MASK	UINT32_C(0x7e)
8146 	 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
8150 	 * * 0: The RSS hash was computed over source IP address,
8195 	#define RX_TPA_START_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80)
8208 	#define RX_TPA_START_V3_CMPL_AGG_ID_MASK		UINT32_C(0xfff)
8209 	#define RX_TPA_START_V3_CMPL_AGG_ID_SFT		0
8210 	#define RX_TPA_START_V3_CMPL_METADATA1_MASK		UINT32_C(0xf000)
8212 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
8213 	#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_MASK	UINT32_C(0x7000)
8215 	/* 0x88a8 */
8216 		#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID88A8   (UINT32_C(0x0) << 12)
8217 	/* 0x8100 */
8218 		#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID8100   (UINT32_C(0x1) << 12)
8219 	/* 0x9100 */
8220 		#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9100   (UINT32_C(0x2) << 12)
8221 	/* 0x9200 */
8222 		#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9200   (UINT32_C(0x3) << 12)
8223 	/* 0x9300 */
8224 		#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9300   (UINT32_C(0x4) << 12)
8226 		#define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG	(UINT32_C(0x5) << 12)
8228 	/* When meta_format != 0, this value is the VLAN valid. */
8229 	#define RX_TPA_START_V3_CMPL_METADATA1_VALID		UINT32_C(0x8000)
8243  * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
8254 	#define RX_TPA_START_V3_CMPL_FLAGS2_IP_CS_CALC		UINT32_C(0x1)
8260 	#define RX_TPA_START_V3_CMPL_FLAGS2_L4_CS_CALC		UINT32_C(0x2)
8266 	#define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_CS_CALC		UINT32_C(0x4)
8272 	#define RX_TPA_START_V3_CMPL_FLAGS2_T_L4_CS_CALC		UINT32_C(0x8)
8274 	#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_MASK	UINT32_C(0xf0)
8277 		#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_NONE		(UINT32_C(0x0) << 4)
8280 	 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
8281 	 * de, vid[11:0]} The metadata2 field contains the table scope
8282 	 * and action record pointer. - metadata2[25:0] contains the
8286 		#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR	(UINT32_C(0x1) << 4)
8290 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
8293 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
8294 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
8295 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
8296 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
8297 	 * - IPv4 = 0 (not populated)
8298 	 * - IPv6 = Flow Label[19:0]
8299 	 * - PPPoE = sessionID[15:0]
8300 	 * - MPLs = Outer label[19:0]
8301 	 * - UPAR = Selected[31:0] with bit mask
8303 		#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 4)
8307 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
8311 		#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 4)
8315 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
8318 	 * - metadata2[8:0] contains the outer_l3_offset.
8323 		#define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET	(UINT32_C(0x4) << 4)
8327 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
8331 	#define RX_TPA_START_V3_CMPL_FLAGS2_IP_TYPE			UINT32_C(0x100)
8336 	#define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC	UINT32_C(0x200)
8342 	#define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE		UINT32_C(0x400)
8344 		#define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV4		(UINT32_C(0x0) << 10)
8346 		#define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV6		(UINT32_C(0x1) << 10)
8349 	#define RX_TPA_START_V3_CMPL_FLAGS2_AGG_GRO			UINT32_C(0x800)
8358 	#define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK	UINT32_C(0xffff0000)
8363 	 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
8364 	 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
8365 	 *   act_rec_ptr[25:0]}
8366 	 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
8367 	 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
8368 	 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
8377 	 * will write 1. The odd passes will write 0.
8379 	#define RX_TPA_START_V3_CMPL_V2				UINT32_C(0x1)
8380 	#define RX_TPA_START_V3_CMPL_ERRORS_MASK			UINT32_C(0xfffe)
8387 	#define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_MASK	UINT32_C(0xe)
8390 		#define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER	(UINT32_C(0x0) << 1)
8401 		#define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (UINT32_C(0x1) << 1)
8406 		#define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT	(UINT32_C(0x3) << 1)
8411 		#define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_FLUSH	(UINT32_C(0x5) << 1)
8418 	/* When meta_format != 0, this value is the VLAN VID. */
8419 	#define RX_TPA_START_V3_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
8420 	#define RX_TPA_START_V3_CMPL_METADATA0_VID_SFT 0
8421 	/* When meta_format != 0, this value is the VLAN DE. */
8422 	#define RX_TPA_START_V3_CMPL_METADATA0_DE	UINT32_C(0x1000)
8423 	/* When meta_format != 0, this value is the VLAN PRI. */
8424 	#define RX_TPA_START_V3_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
8430 	 * hdr_offsets[8:0] contains the outer_l3_offset.
8440  * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
8453 	#define RX_TPA_END_CMPL_TYPE_MASK			UINT32_C(0x3f)
8454 	#define RX_TPA_END_CMPL_TYPE_SFT			0
8460 		#define RX_TPA_END_CMPL_TYPE_RX_TPA_END		UINT32_C(0x15)
8462 	#define RX_TPA_END_CMPL_FLAGS_MASK			UINT32_C(0xffc0)
8469 	#define RX_TPA_END_CMPL_FLAGS_ERROR			UINT32_C(0x40)
8471 	#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK		UINT32_C(0x380)
8481 		#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO		(UINT32_C(0x1) << 7)
8487 		#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS		(UINT32_C(0x2) << 7)
8495 		#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO	(UINT32_C(0x4) << 7)
8504 		#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO	(UINT32_C(0x5) << 7)
8514 		#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS	(UINT32_C(0x6) << 7)
8522 		#define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS	(UINT32_C(0x7) << 7)
8525 	#define RX_TPA_END_CMPL_FLAGS_TIMESTAMP_VALID	UINT32_C(0x400)
8534 	#define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT	UINT32_C(0x800)
8544 	#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK		UINT32_C(0xf000)
8560 	 * will write 1. The odd passes will write 0.
8566 	 * will write 1. The odd passes will write 0.
8568 	#define RX_TPA_END_CMPL_V1	UINT32_C(0x1)
8576 	#define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
8590 	#define RX_TPA_END_CMPL_UNUSED2	UINT32_C(0x1)
8596 	#define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
8607 	 *	Timestamp present indication. When '0', no Timestamp
8618  * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
8628 	#define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
8629 	#define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
8650 	 * will write 1. The odd passes will write 0.
8652 	#define RX_TPA_END_CMPL_V2				UINT32_C(0x1)
8653 	#define RX_TPA_END_CMPL_ERRORS_MASK			UINT32_C(0xfffe)
8661 	#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK	UINT32_C(0xe)
8669 		#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP   (UINT32_C(0x2) << 1)
8680 		#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR	(UINT32_C(0x4) << 1)
8696  * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
8709 	#define RX_TPA_V2_START_CMPL_TYPE_MASK			UINT32_C(0x3f)
8710 	#define RX_TPA_V2_START_CMPL_TYPE_SFT			0
8716 		#define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START		UINT32_C(0x13)
8718 	#define RX_TPA_V2_START_CMPL_FLAGS_MASK			UINT32_C(0xffc0)
8720 	/* This bit will always be '0' for TPA start completions. */
8721 	#define RX_TPA_V2_START_CMPL_FLAGS_ERROR			UINT32_C(0x40)
8723 	#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK		UINT32_C(0x380)
8733 		#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO		(UINT32_C(0x1) << 7)
8739 		#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS		(UINT32_C(0x2) << 7)
8748 		#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO	(UINT32_C(0x5) << 7)
8758 		#define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS	(UINT32_C(0x6) << 7)
8761 	#define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID		UINT32_C(0x400)
8771 	#define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT	UINT32_C(0x800)
8776 	#define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK		UINT32_C(0xf000)
8782 		#define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP		(UINT32_C(0x2) << 12)
8797 	 * will write 1. The odd passes will write 0.
8803 	 * will write 1. The odd passes will write 0.
8805 	#define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
8809 	 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
8813 	 * * 0: The RSS hash was computed over source IP address,
8854  * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
8865 	#define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC		UINT32_C(0x1)
8871 	#define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC		UINT32_C(0x2)
8877 	#define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC		UINT32_C(0x4)
8883 	#define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC		UINT32_C(0x8)
8885 	#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK	UINT32_C(0xf0)
8888 		#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE		(UINT32_C(0x0) << 4)
8891 	 * - metadata[11:0] contains the vlan VID value.
8896 		#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN		(UINT32_C(0x1) << 4)
8901 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
8902 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
8903 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
8904 	 * - GRE = KEY[31:0] -> key field with bit mask. Zero if K = 0
8905 	 * - IPV4 = 0 (not populated)
8906 	 * - IPV6 = Flow Label[19:0]
8907 	 * - PPPoE = sessionID[15:0]
8908 	 * - MPLs = Outer label[19:0]
8909 	 * - UPAR = Selected[31:0] with bit mask
8911 		#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 4)
8916 		#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 4)
8921 	 * - metadata[8:0] contains the outer_l3_offset.
8926 		#define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET	(UINT32_C(0x4) << 4)
8930 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
8932 	#define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE			UINT32_C(0x100)
8937 	#define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC	UINT32_C(0x200)
8942 	#define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK	UINT32_C(0xc00)
8952 	#define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK	UINT32_C(0xffff0000)
8960 	#define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
8961 	#define RX_TPA_V2_START_CMPL_METADATA_VID_SFT  0
8963 	#define RX_TPA_V2_START_CMPL_METADATA_DE	UINT32_C(0x1000)
8965 	#define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
8968 	#define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
8974 	 * will write 1. The odd passes will write 0.
8976 	#define RX_TPA_V2_START_CMPL_V2				UINT32_C(0x1)
8977 	#define RX_TPA_V2_START_CMPL_ERRORS_MASK		UINT32_C(0xfffe)
8985 	#define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK	UINT32_C(0xe)
8988 		#define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER	(UINT32_C(0x0) << 1)
8993 		#define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT   (UINT32_C(0x3) << 1)
8998 		#define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH	(UINT32_C(0x5) << 1)
9021 	#define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
9022 	#define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
9027 	#define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
9033 	#define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
9040 	#define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK  UINT32_C(0xf8000000)
9046  * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
9059 	#define RX_TPA_V2_END_CMPL_TYPE_MASK			UINT32_C(0x3f)
9060 	#define RX_TPA_V2_END_CMPL_TYPE_SFT			0
9066 		#define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END		UINT32_C(0x15)
9068 	#define RX_TPA_V2_END_CMPL_FLAGS_MASK			UINT32_C(0xffc0)
9075 	#define RX_TPA_V2_END_CMPL_FLAGS_ERROR			UINT32_C(0x40)
9077 	#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK		UINT32_C(0x380)
9087 		#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO		(UINT32_C(0x1) << 7)
9093 		#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS		(UINT32_C(0x2) << 7)
9102 		#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO	(UINT32_C(0x5) << 7)
9112 		#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS	(UINT32_C(0x6) << 7)
9120 		#define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS	(UINT32_C(0x7) << 7)
9123 	#define RX_TPA_V2_END_CMPL_FLAGS_UNUSED			UINT32_C(0x400)
9132 	#define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT	UINT32_C(0x800)
9142 	#define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK		UINT32_C(0xf000)
9159 	 * will write 1. The odd passes will write 0.
9161 	#define RX_TPA_V2_END_CMPL_V1	UINT32_C(0x1)
9179 	 *	Timestamp present indication. When '0', no Timestamp
9190  * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
9204 	#define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
9205 	#define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
9237 	 * will write 1. The odd passes will write 0.
9239 	#define RX_TPA_V2_END_CMPL_V2				UINT32_C(0x1)
9240 	#define RX_TPA_V2_END_CMPL_ERRORS_MASK			UINT32_C(0xfffe)
9248 	#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK	UINT32_C(0xe)
9251 		#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER	(UINT32_C(0x0) << 1)
9258 		#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP   (UINT32_C(0x2) << 1)
9263 		#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT	(UINT32_C(0x3) << 1)
9274 		#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR	(UINT32_C(0x4) << 1)
9279 		#define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH	(UINT32_C(0x5) << 1)
9291  * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
9304 	#define RX_TPA_V2_ABUF_CMPL_TYPE_MASK	UINT32_C(0x3f)
9305 	#define RX_TPA_V2_ABUF_CMPL_TYPE_SFT	0
9311 		#define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG  UINT32_C(0x16)
9331 	 * will write 1. The odd passes will write 0.
9333 	#define RX_TPA_V2_ABUF_CMPL_V	UINT32_C(0x1)
9354 	#define RX_ABUF_CMPL_TYPE_MASK  UINT32_C(0x3f)
9355 	#define RX_ABUF_CMPL_TYPE_SFT   0
9361 		#define RX_ABUF_CMPL_TYPE_RX_AGG  UINT32_C(0x12)
9381 	 * will write 1. The odd passes will write 0.
9383 	#define RX_ABUF_CMPL_V	UINT32_C(0x1)
9400 	#define VEE_FLUSH_TYPE_MASK	UINT32_C(0x3f)
9401 	#define VEE_FLUSH_TYPE_SFT		0
9409 		#define VEE_FLUSH_TYPE_VEE_FLUSH	UINT32_C(0x1c)
9412 	#define VEE_FLUSH_DOWNSTREAM_PATH	UINT32_C(0x40)
9414 		#define VEE_FLUSH_DOWNSTREAM_PATH_TX	(UINT32_C(0x0) << 6)
9416 		#define VEE_FLUSH_DOWNSTREAM_PATH_RX	(UINT32_C(0x1) << 6)
9428 	 * write 1. The odd passes will write 0.
9430 	#define VEE_FLUSH_V	UINT32_C(0x1)
9446 	#define EJECT_CMPL_TYPE_MASK	UINT32_C(0x3f)
9447 	#define EJECT_CMPL_TYPE_SFT	0
9453 		#define EJECT_CMPL_TYPE_STAT_EJECT   UINT32_C(0x1a)
9455 	#define EJECT_CMPL_FLAGS_MASK	UINT32_C(0xffc0)
9462 	#define EJECT_CMPL_FLAGS_ERROR	UINT32_C(0x40)
9477 	 * will write 1. The odd passes will write 0.
9479 	#define EJECT_CMPL_V				UINT32_C(0x1)
9480 	#define EJECT_CMPL_ERRORS_MASK			UINT32_C(0xfffe)
9487 	#define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK	UINT32_C(0xe)
9490 		#define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER	(UINT32_C(0x0) << 1)
9495 		#define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (UINT32_C(0x1) << 1)
9500 		#define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT	(UINT32_C(0x3) << 1)
9505 		#define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH	(UINT32_C(0x5) << 1)
9524 	#define HWRM_CMPL_TYPE_MASK	UINT32_C(0x3f)
9525 	#define HWRM_CMPL_TYPE_SFT	0
9530 		#define HWRM_CMPL_TYPE_HWRM_DONE  UINT32_C(0x20)
9540 	 * will write 1. The odd passes will write 0.
9542 	#define HWRM_CMPL_V	UINT32_C(0x1)
9565 	#define HWRM_FWD_REQ_CMPL_TYPE_MASK	UINT32_C(0x3f)
9566 	#define HWRM_FWD_REQ_CMPL_TYPE_SFT	0
9568 		#define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ  UINT32_C(0x22)
9571 	#define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK	UINT32_C(0xffc0)
9576 	 * 0x0 - 0xFFF8 - Used for function ids
9577 	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
9578 	 * 0xFFFF - HWRM
9588 	 * will write 1. The odd passes will write 0.
9590 	#define HWRM_FWD_REQ_CMPL_V		UINT32_C(0x1)
9592 	#define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
9607 	#define HWRM_FWD_RESP_CMPL_TYPE_MASK	UINT32_C(0x3f)
9608 	#define HWRM_FWD_RESP_CMPL_TYPE_SFT	0
9610 		#define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP  UINT32_C(0x24)
9615 	 * 0x0 - 0xFFF8 - Used for function ids
9616 	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
9617 	 * 0xFFFF - HWRM
9629 	 * will write 1. The odd passes will write 0.
9631 	#define HWRM_FWD_RESP_CMPL_V		UINT32_C(0x1)
9633 	#define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
9648 	#define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK		UINT32_C(0x3f)
9649 	#define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT		0
9651 		#define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
9656 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE		UINT32_C(0x0)
9658 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE		UINT32_C(0x1)
9660 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE		UINT32_C(0x2)
9662 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE		UINT32_C(0x3)
9664 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED	UINT32_C(0x4)
9666 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED	UINT32_C(0x5)
9668 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE	UINT32_C(0x6)
9670 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE		UINT32_C(0x7)
9672 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY			UINT32_C(0x8)
9674 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY		UINT32_C(0x9)
9679 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG		UINT32_C(0xa)
9681 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD		UINT32_C(0x10)
9683 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD		UINT32_C(0x11)
9685 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT		UINT32_C(0x12)
9687 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD		UINT32_C(0x20)
9689 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD			UINT32_C(0x21)
9691 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR			UINT32_C(0x30)
9693 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE		UINT32_C(0x31)
9695 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE	UINT32_C(0x32)
9697 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE		UINT32_C(0x33)
9699 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE		UINT32_C(0x34)
9701 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE		UINT32_C(0x35)
9703 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED			UINT32_C(0x36)
9710 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION		UINT32_C(0x37)
9715 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ		UINT32_C(0x38)
9721 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE		UINT32_C(0x39)
9728 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE	UINT32_C(0x3a)
9734 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE		UINT32_C(0x3b)
9739 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE		UINT32_C(0x3c)
9744 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE	UINT32_C(0x3d)
9749 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE	UINT32_C(0x3e)
9754 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE			UINT32_C(0x3f)
9760 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE		UINT32_C(0x40)
9765 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE	UINT32_C(0x41)
9770 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST			UINT32_C(0x42)
9776 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE			UINT32_C(0x43)
9781 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP		UINT32_C(0x44)
9787 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT			UINT32_C(0x45)
9794 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD	UINT32_C(0x46)
9799 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE			UINT32_C(0x47)
9806 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE	UINT32_C(0x48)
9813 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR UINT32_C(0x49)
9819 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR			UINT32_C(0x4a)
9825 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE		UINT32_C(0x4b)
9832 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER		UINT32_C(0x4c)
9837 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE		UINT32_C(0x4d)
9842 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE	UINT32_C(0x4e)
9847 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE		UINT32_C(0x4f)
9852 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP		UINT32_C(0x50)
9854 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID		UINT32_C(0x51)
9860 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG			UINT32_C(0xfe)
9862 	#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR			UINT32_C(0xff)
9870 	 * will write 1. The odd passes will write 0.
9872 	#define HWRM_ASYNC_EVENT_CMPL_V	UINT32_C(0x1)
9874 	#define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
9885 	(((x) < 0x80) ? \
9886 	((x) == 0x0 ? "LINK_STATUS_CHANGE": \
9887 	((x) == 0x1 ? "LINK_MTU_CHANGE": \
9888 	((x) == 0x2 ? "LINK_SPEED_CHANGE": \
9889 	((x) == 0x3 ? "DCB_CONFIG_CHANGE": \
9890 	((x) == 0x4 ? "PORT_CONN_NOT_ALLOWED": \
9891 	((x) == 0x5 ? "LINK_SPEED_CFG_NOT_ALLOWED": \
9892 	((x) == 0x6 ? "LINK_SPEED_CFG_CHANGE": \
9893 	((x) == 0x7 ? "PORT_PHY_CFG_CHANGE": \
9894 	((x) == 0x8 ? "RESET_NOTIFY": \
9895 	((x) == 0x9 ? "ERROR_RECOVERY": \
9896 	((x) == 0xa ? "RING_MONITOR_MSG": \
9897 	((x) == 0x10 ? "FUNC_DRVR_UNLOAD": \
9898 	((x) == 0x11 ? "FUNC_DRVR_LOAD": \
9899 	((x) == 0x12 ? "FUNC_FLR_PROC_CMPLT": \
9900 	((x) == 0x20 ? "PF_DRVR_UNLOAD": \
9901 	((x) == 0x21 ? "PF_DRVR_LOAD": \
9902 	((x) == 0x30 ? "VF_FLR": \
9903 	((x) == 0x31 ? "VF_MAC_ADDR_CHANGE": \
9904 	((x) == 0x32 ? "PF_VF_COMM_STATUS_CHANGE": \
9905 	((x) == 0x33 ? "VF_CFG_CHANGE": \
9906 	((x) == 0x34 ? "LLFC_PFC_CHANGE": \
9907 	((x) == 0x35 ? "DEFAULT_VNIC_CHANGE": \
9908 	((x) == 0x36 ? "HW_FLOW_AGED": \
9909 	((x) == 0x37 ? "DEBUG_NOTIFICATION": \
9910 	((x) == 0x38 ? "EEM_CACHE_FLUSH_REQ": \
9911 	((x) == 0x39 ? "EEM_CACHE_FLUSH_DONE": \
9912 	((x) == 0x3a ? "TCP_FLAG_ACTION_CHANGE": \
9913 	((x) == 0x3b ? "EEM_FLOW_ACTIVE": \
9914 	((x) == 0x3c ? "EEM_CFG_CHANGE": \
9915 	((x) == 0x3d ? "TFLIB_DEFAULT_VNIC_CHANGE": \
9916 	((x) == 0x3e ? "TFLIB_LINK_STATUS_CHANGE": \
9917 	((x) == 0x3f ? "QUIESCE_DONE": \
9918 	((x) == 0x40 ? "DEFERRED_RESPONSE": \
9919 	((x) == 0x41 ? "PFC_WATCHDOG_CFG_CHANGE": \
9920 	((x) == 0x42 ? "ECHO_REQUEST": \
9921 	((x) == 0x43 ? "PHC_UPDATE": \
9922 	((x) == 0x44 ? "PPS_TIMESTAMP": \
9923 	((x) == 0x45 ? "ERROR_REPORT": \
9924 	((x) == 0x46 ? "DOORBELL_PACING_THRESHOLD": \
9925 	((x) == 0x47 ? "RSS_CHANGE": \
9926 	((x) == 0x48 ? "DOORBELL_PACING_NQ_UPDATE": \
9927 	((x) == 0x49 ? "HW_DOORBELL_RECOVERY_READ_ERROR": \
9928 	((x) == 0x4a ? "CTX_ERROR": \
9929 	((x) == 0x4b ? "UDCC_SESSION_CHANGE": \
9930 	((x) == 0x4c ? "DBG_BUF_PRODUCER": \
9931 	((x) == 0x4d ? "PEER_MMAP_CHANGE": \
9932 	((x) == 0x4e ? "REPRESENTOR_PAIR_CHANGE": \
9933 	((x) == 0x4f ? "VF_STAT_CHANGE": \
9934 	((x) == 0x50 ? "HOST_COREDUMP": \
9935 	((x) == 0x51 ? "MAX_RGTR_EVENT_ID": \
9937 	(((x) < 0x100) ? \
9938 	((x) == 0xfe ? "FW_TRACE_MSG": \
9939 	((x) == 0xff ? "HWRM_ERROR": \
9955 	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK		UINT32_C(0x3f)
9956 	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT		0
9958 		#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
9963 	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE UINT32_C(0x0)
9971 	 * will write 1. The odd passes will write 0.
9973 	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V	UINT32_C(0x1)
9975 	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
9984 	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE	UINT32_C(0x1)
9986 	 * If this bit set to 0, then it indicates that the link
9989 		#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN  UINT32_C(0x0)
9994 		#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP	UINT32_C(0x1)
9997 	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK	UINT32_C(0xe)
10000 	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK	UINT32_C(0xffff0)
10003 	#define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK	UINT32_C(0xff00000)
10018 	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK		UINT32_C(0x3f)
10019 	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT		0
10021 		#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10026 	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE UINT32_C(0x1)
10034 	 * will write 1. The odd passes will write 0.
10036 	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V	UINT32_C(0x1)
10038 	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10047 	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK UINT32_C(0xffff)
10048 	#define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
10062 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK		UINT32_C(0x3f)
10063 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT		0
10065 		#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10070 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE UINT32_C(0x2)
10078 	 * will write 1. The odd passes will write 0.
10080 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V	UINT32_C(0x1)
10082 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10094 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE			UINT32_C(0x1)
10096 …#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK UINT32_C(0…
10099 …M_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB  (UINT32_C(0x1) << 1)
10101 …HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB	(UINT32_C(0xa) << 1)
10103 …WRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB	(UINT32_C(0x14) << 1)
10105 …_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB  (UINT32_C(0x19) << 1)
10107 …_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB   (UINT32_C(0x64) << 1)
10109 …_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB   (UINT32_C(0xc8) << 1)
10111 …_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB   (UINT32_C(0xfa) << 1)
10113 …ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB   (UINT32_C(0x190) << 1)
10115 …ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB   (UINT32_C(0x1f4) << 1)
10117 …ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB  (UINT32_C(0x3e8) << 1)
10120 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK		UINT32_C(0xffff0000)
10135 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK		UINT32_C(0x3f)
10136 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT		0
10138 		#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10143 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)
10148 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS	UINT32_C(0x1)
10150 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC	UINT32_C(0x2)
10152 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP	UINT32_C(0x4)
10154 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_DSCP	UINT32_C(0x8)
10159 	 * will write 1. The odd passes will write 0.
10161 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V	UINT32_C(0x1)
10163 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10172 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK		UINT32_C(0xffff)
10173 	#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT		0
10175 …HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK UINT32_C(0xff0000)
10178 …ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE  (UINT32_C(0xff) << 16)
10181 …#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK  UINT32_C(0…
10184 …RM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE	(UINT32_C(0xff) << 24)
10199 	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK		UINT32_C(0x3f)
10200 	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT		0
10202 		#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10207 	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED UINT32_C(0x4)
10215 	 * will write 1. The odd passes will write 0.
10217 	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V	UINT32_C(0x1)
10219 	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK UINT32_C(0xfe)
10228 	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK		UINT32_C(0xffff)
10229 	#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT		0
10235 …#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK	UINT32_C(0…
10238 …RM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE	(UINT32_C(0x0) << 16)
10240 …C_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX   (UINT32_C(0x1) << 16)
10242 …C_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG  (UINT32_C(0x2) << 16)
10244 …ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN	(UINT32_C(0x3) << 16)
10259 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK		UINT32_C(0x3f)
10260 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT		0
10262 		#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10267 … HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED UINT32_C(0x5)
10275 	 * will write 1. The odd passes will write 0.
10277 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V	UINT32_C(0x1)
10279 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK UINT32_C(0xfe)
10288 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
10289 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
10303 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK		UINT32_C(0x3f)
10304 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT		0
10306 		#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10311 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE UINT32_C(0x6)
10319 	 * will write 1. The odd passes will write 0.
10321 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V	UINT32_C(0x1)
10323 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10332 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK			UINT32_C(0xffff)
10333 	#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT			0
10337 	 * If set to 0, then there is no change in supported link speeds
10340 …M_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE	UINT32_C(0x10000)
10344 	 * If set to 0, then the link speed configuration on the port is
10347 …#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG	UINT32_C(0x…
10361 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK		UINT32_C(0x3f)
10362 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT		0
10364 		#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10369 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE UINT32_C(0x7)
10378 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_MASK	UINT32_C(0xff)
10379 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_SFT	0
10381 		#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_NONE	UINT32_C(0x0)
10383 …#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_DISABLETX	UINT32_C(0x1)
10385 		#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_MISMATCH	UINT32_C(0x2)
10387 		#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_PWRDOWN	UINT32_C(0x3)
10389 …efine HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_NOTINSERTED	UINT32_C(0x4)
10391 …ne HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_CURRENTFAULT   UINT32_C(0x5)
10393 …#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_OVERHEATED	UINT32_C(0x…
10395 …e HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA2_MODULE_STATUS_NOTAPPLICABLE  UINT32_C(0xff)
10401 	 * will write 1. The odd passes will write 0.
10403 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V	UINT32_C(0x1)
10405 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10414 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK	UINT32_C(0xffff)
10415 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT	0
10419 	 * If set to 0, then there is no change in FEC configuration.
10421 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE	UINT32_C(0x10000)
10425 	 * If set to 0, then there is no change in EEE configuration
10428 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE	UINT32_C(0x20000)
10432 	 * If set to 0, then there is no change in the pause
10435 	#define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE	UINT32_C(0x40000)
10449 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK		UINT32_C(0x3f)
10450 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT		0
10452 		#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10457 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY UINT32_C(0x8)
10464 	 * If the status code is equal to 0x8000, then the reset is initiated
10466 	 * state. If the status code is not equal to 0x8000, then the reset is
10469 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK UINT32_C(0xffff)
10470 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0
10475 	 * will write 1. The odd passes will write 0.
10477 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V	UINT32_C(0x1)
10479 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
10498 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK		UINT32_C(0xff)
10499 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT		0
10503 	 * if set to 0, there is no change in L2 client behavior.
10505 …ine HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE	UINT32_C(0x1)
10509 	 * If set to 0, then there is no change in L2 client behavior.
10511 		#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN	UINT32_C(0x2)
10514 	#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK			UINT32_C(0xff00)
10517 …SYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST  (UINT32_C(0x1) << 8)
10519 …#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL	(UINT32_C(0x…
10521 …M_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL	(UINT32_C(0x3) << 8)
10523 …#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET		(UINT32_C(0x4) << 8)
10528 …#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION		(UINT32_C(0x5) <…
10533 	 * Range 0-65535
10535 …#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK	UINT32_C(0xffff00…
10550 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK		UINT32_C(0x3f)
10551 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT		0
10553 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10563 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY UINT32_C(0x9)
10571 	 * will write 1. The odd passes will write 0.
10573 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V	UINT32_C(0x1)
10575 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
10584 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK		UINT32_C(0xff)
10585 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT		0
10589 	 * detects a fatal error. If set to 0, master function functionality
10592 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC	UINT32_C(0x1)
10595 	 * If set to 0, error recovery is disabled.
10597 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED	UINT32_C(0x2)
10611 	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK		UINT32_C(0x3f)
10612 	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT		0
10614 		#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10619 	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG UINT32_C(0xa)
10624 	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK UINT32_C(0xff)
10625 	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0
10627 		#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX	UINT32_C(0x0)
10629 		#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX	UINT32_C(0x1)
10631 		#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL  UINT32_C(0x2)
10637 	 * will write 1. The odd passes will write 0.
10639 	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V	UINT32_C(0x1)
10641 	#define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK UINT32_C(0xfe)
10665 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK		UINT32_C(0x3f)
10666 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT		0
10668 		#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10673 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD UINT32_C(0x10)
10681 	 * will write 1. The odd passes will write 0.
10683 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V	UINT32_C(0x1)
10685 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
10694 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
10695 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
10709 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK		UINT32_C(0x3f)
10710 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT		0
10712 		#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10717 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD UINT32_C(0x11)
10725 	 * will write 1. The odd passes will write 0.
10727 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V	UINT32_C(0x1)
10729 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
10738 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
10739 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
10753 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK		UINT32_C(0x3f)
10754 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT		0
10756 		#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10761 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT UINT32_C(0x12)
10769 	 * will write 1. The odd passes will write 0.
10771 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V	UINT32_C(0x1)
10773 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK UINT32_C(0xfe)
10782 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
10783 	#define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0
10797 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK		UINT32_C(0x3f)
10798 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT		0
10800 		#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10805 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD UINT32_C(0x20)
10813 	 * will write 1. The odd passes will write 0.
10815 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V	UINT32_C(0x1)
10817 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
10826 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
10827 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
10829 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK   UINT32_C(0x70000)
10844 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK		UINT32_C(0x3f)
10845 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT		0
10847 		#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10852 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD UINT32_C(0x21)
10860 	 * will write 1. The odd passes will write 0.
10862 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V	UINT32_C(0x1)
10864 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
10873 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
10874 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
10876 	#define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK   UINT32_C(0x70000)
10891 	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK		UINT32_C(0x3f)
10892 	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT		0
10894 		#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10899 	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
10907 	 * will write 1. The odd passes will write 0.
10909 	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V	UINT32_C(0x1)
10911 	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
10920 	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK UINT32_C(0xffff)
10921 	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
10923 	#define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK UINT32_C(0xff0000)
10938 	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK		UINT32_C(0x3f)
10939 	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT		0
10941 		#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10946 	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE UINT32_C(0x31)
10954 	 * will write 1. The odd passes will write 0.
10956 	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V	UINT32_C(0x1)
10958 	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10967 	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK UINT32_C(0xffff)
10968 	#define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
10982 	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK		UINT32_C(0x3f)
10983 	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT		0
10985 		#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
10990 …ine HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32)
10998 	 * will write 1. The odd passes will write 0.
11000 	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V	UINT32_C(0x1)
11002 	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11013 	 * If this bit set to 0, then it indicates that the PF-VF
11016 	#define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED	UINT32_C(0x1)
11030 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK		UINT32_C(0x3f)
11031 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT		0
11033 		#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11038 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33)
11050 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK UINT32_C(0xffff)
11051 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
11056 	 * will write 1. The odd passes will write 0.
11058 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V	UINT32_C(0x1)
11060 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11076 	 * If set to 0, then this bit should be ignored.
11078 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE		UINT32_C(0x1)
11082 	 * If set to 0, then this bit should be ignored.
11084 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE		UINT32_C(0x2)
11088 	 * If set to 0, then this bit should be ignored.
11090 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE	UINT32_C(0x4)
11094 	 * If set to 0, then this bit should be ignored.
11096 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE	UINT32_C(0x8)
11100 	 * If set to 0, then this bit should be ignored.
11102 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE	UINT32_C(0x10)
11107 	 * If set to 0, then this bit should be ignored.
11109 	#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE	UINT32_C(0x20)
11123 	#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK		UINT32_C(0x3f)
11124 	#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT		0
11126 		#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11129 	#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK	UINT32_C(0xffc0)
11134 	#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE UINT32_C(0x34)
11142 	 * will write 1. The odd passes will write 0.
11144 	#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V	UINT32_C(0x1)
11146 	#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11155 	#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK UINT32_C(0x3)
11156 	#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT 0
11161 		#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC  UINT32_C(0x1)
11166 		#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC   UINT32_C(0x2)
11169 	#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK	UINT32_C(0x1c)
11172 	#define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0x1fffe0)
11187 	#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK		UINT32_C(0x3f)
11188 	#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT		0
11190 		#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11193 	#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK	UINT32_C(0xffc0)
11198 	#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION UINT32_C(0x35)
11206 	 * will write 1. The odd passes will write 0.
11208 	#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V	UINT32_C(0x1)
11210 	#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11219 	#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK	UINT32_C(0x3)
11220 	#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT	0
11225 … HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC  UINT32_C(0x1)
11230 … HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE   UINT32_C(0x2)
11233 	#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK		UINT32_C(0x3fc)
11236 	#define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK		UINT32_C(0x3fffc00)
11251 	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK		UINT32_C(0x3f)
11252 	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT		0
11254 		#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11259 	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED UINT32_C(0x36)
11267 	 * will write 1. The odd passes will write 0.
11269 	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V	UINT32_C(0x1)
11271 	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
11280 	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK	UINT32_C(0x7fffffff)
11281 	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT	0
11283 	#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION	UINT32_C(0x80000000)
11285 	 * If this bit set to 0, then it indicates that the aged
11288 		#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX	(UINT32_C(0x0) << 31)
11293 		#define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX	(UINT32_C(0x1) << 31)
11308 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK		UINT32_C(0x3f)
11309 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT		0
11311 		#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11316 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ UINT32_C(0x38)
11324 	 * will write 1. The odd passes will write 0.
11326 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V	UINT32_C(0x1)
11328 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK UINT32_C(0xfe)
11349 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK		UINT32_C(0x3f)
11350 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT		0
11352 		#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11360 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE UINT32_C(0x39)
11368 	 * will write 1. The odd passes will write 0.
11370 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V	UINT32_C(0x1)
11372 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK UINT32_C(0xfe)
11381 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK UINT32_C(0xffff)
11382 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
11396 	#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK		UINT32_C(0x3f)
11397 	#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT		0
11399 		#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11404 	#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE UINT32_C(0x3a)
11412 	 * will write 1. The odd passes will write 0.
11414 	#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V	UINT32_C(0x1)
11416 	#define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11437 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK		UINT32_C(0x3f)
11438 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT		0
11440 		#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11445 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE UINT32_C(0x3b)
11450 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK   UINT32_C(0x3fffffff)
11451 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT	0
11456 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION	UINT32_C(0x40000000)
11457 	/* If this bit is set to 0, then it indicates that this rx flow. */
11458 		#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX	(UINT32_C(0x0) << 30)
11460 		#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX	(UINT32_C(0x1) << 30)
11466 	 * will write 1. The odd passes will write 0.
11468 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V	UINT32_C(0x1)
11470 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK UINT32_C(0xfe)
11479 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK   UINT32_C(0x3fffffff)
11480 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT	0
11485 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION	UINT32_C(0x40000000)
11486 	/* If this bit is set to 0, then it indicates that this is rx flow. */
11487 		#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX	(UINT32_C(0x0) << 30)
11489 		#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX	(UINT32_C(0x1) << 30)
11493 	 * this bit is set to 0, the event_data1 is the EEM global
11497 	#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE		UINT32_C(0x80000000)
11498 	/* EEM flow aging mode 0. */
11499 		#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0		(UINT32_C(0x0) << 31)
11501 		#define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1		(UINT32_C(0x1) << 31)
11516 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK		UINT32_C(0x3f)
11517 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT		0
11519 		#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11524 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE UINT32_C(0x3c)
11532 	 * will write 1. The odd passes will write 0.
11534 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V	UINT32_C(0x1)
11536 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11546 	 * 0 to indicate the EEM TX configuration is disabled.
11548 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE	UINT32_C(0x1)
11550 	 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
11553 	#define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE	UINT32_C(0x2)
11567 	#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK		UINT32_C(0x3f)
11568 	#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT		0
11570 		#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11575 	#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE UINT32_C(0x3f)
11580 	#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK		UINT32_C(0xff)
11581 	#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT		0
11586 		#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS		UINT32_C(0x0)
11591 		#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT		UINT32_C(0x1)
11596 		#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR		UINT32_C(0x2)
11599 	#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK			UINT32_C(0xff00)
11607 	#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK		UINT32_C(0xff0000)
11613 …#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ	UINT32_C(0x1…
11615 …#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1	UINT32_C(0x2…
11617 …#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2	UINT32_C(0x4…
11619 …#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3	UINT32_C(0x8…
11624 	 * will write 1. The odd passes will write 0.
11626 	#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V	UINT32_C(0x1)
11628 	#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
11637 	#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP	UINT32_C(0x1)
11651 	#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK		UINT32_C(0x3f)
11652 	#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT		0
11654 		#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11662 	#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE UINT32_C(0x40)
11673 	#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK UINT32_C(0xffff)
11674 	#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0
11679 	 * will write 1. The odd passes will write 0.
11681 	#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V	UINT32_C(0x1)
11683 	#define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK UINT32_C(0xfe)
11704 	#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK		UINT32_C(0x3f)
11705 	#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT		0
11707 		#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11712 …#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE UINT32_C(0x…
11720 	 * will write 1. The odd passes will write 0.
11722 	#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V	UINT32_C(0x1)
11724 	#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11736 	#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK		UINT32_C(0xff)
11737 	#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT		0
11738 	/* 1 means PFC WD for COS0 is on, 0 - off. */
11739 …fine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0	UINT32_C(0x1)
11740 	/* 1 means PFC WD for COS1 is on, 0 - off. */
11741 …fine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1	UINT32_C(0x2)
11742 	/* 1 means PFC WD for COS2 is on, 0 - off. */
11743 …fine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2	UINT32_C(0x4)
11744 	/* 1 means PFC WD for COS3 is on, 0 - off. */
11745 …fine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3	UINT32_C(0x8)
11746 	/* 1 means PFC WD for COS4 is on, 0 - off. */
11747 …ine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4	UINT32_C(0x10)
11748 	/* 1 means PFC WD for COS5 is on, 0 - off. */
11749 …ine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5	UINT32_C(0x20)
11750 	/* 1 means PFC WD for COS6 is on, 0 - off. */
11751 …ine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6	UINT32_C(0x40)
11752 	/* 1 means PFC WD for COS7 is on, 0 - off. */
11753 …ine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7	UINT32_C(0x80)
11755 	#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK		UINT32_C(0xffff00)
11770 	#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK		UINT32_C(0x3f)
11771 	#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT		0
11773 		#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11781 	#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST UINT32_C(0x42)
11789 	 * will write 1. The odd passes will write 0.
11791 	#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V	UINT32_C(0x1)
11793 	#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe)
11814 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK		UINT32_C(0x3f)
11815 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT		0
11817 		#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11826 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE UINT32_C(0x43)
11831 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK UINT32_C(0xffff)
11832 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0
11834 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK   UINT32_C(0xffff0000)
11840 	 * will write 1. The odd passes will write 0.
11842 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_V	UINT32_C(0x1)
11844 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK UINT32_C(0xfe)
11853 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK	UINT32_C(0xf)
11854 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT	0
11859 		#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER	UINT32_C(0x1)
11864 		#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY   UINT32_C(0x2)
11869 		#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER	UINT32_C(0x3)
11875 		#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE  UINT32_C(0x4)
11881 	#define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK   UINT32_C(0xffff0)
11896 	#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK		UINT32_C(0x3f)
11897 	#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT		0
11899 		#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11910 	#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP UINT32_C(0x44)
11915 	#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE		UINT32_C(0x1)
11917 		#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL	UINT32_C(0x0)
11919 		#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL	UINT32_C(0x1)
11925 	#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK	UINT32_C(0xe)
11932 	#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK UINT32_C(0xffff0)
11938 	 * will write 1. The odd passes will write 0.
11940 	#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V	UINT32_C(0x1)
11942 	#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK UINT32_C(0xfe)
11951 …#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK UINT32_C(0xffffff…
11952 	#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0
11966 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK		UINT32_C(0x3f)
11967 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT		0
11969 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
11978 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
11986 	 * will write 1. The odd passes will write 0.
11988 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_V	UINT32_C(0x1)
11990 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK UINT32_C(0xfe)
12002 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
12003 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
12017 	#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_MASK		UINT32_C(0x3f)
12018 	#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_SFT		0
12020 		#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12030 …e HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_DOORBELL_PACING_THRESHOLD UINT32_C(0x46)
12038 	 * will write 1. The odd passes will write 0.
12040 	#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_V	UINT32_C(0x1)
12042 	#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_OPAQUE_MASK UINT32_C(0xfe)
12063 	#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_MASK		UINT32_C(0x3f)
12064 	#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_SFT		0
12066 		#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12075 	#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE UINT32_C(0x47)
12083 	 * will write 1. The odd passes will write 0.
12085 	#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_V	UINT32_C(0x1)
12087 	#define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
12108 	#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_MASK		UINT32_C(0x3f)
12109 	#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_SFT		0
12111 		#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12121 …e HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE UINT32_C(0x48)
12129 	 * will write 1. The odd passes will write 0.
12131 	#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_V	UINT32_C(0x1)
12133 	#define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_MASK UINT32_C(0xfe)
12154 	#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_MASK		UINT32_C(0x3f)
12155 	#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_SFT		0
12157 …#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12168 …_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR UINT32_C(0x49)
12176 	 * will write 1. The odd passes will write 0.
12178 	#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_V	UINT32_C(0x1)
12180 	#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_MASK UINT32_C(0xfe)
12192 …RM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_MASK	UINT32_C(0xf)
12193 	#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SFT	0
12198 …_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SQ_ERR	UINT32_C(0x1)
12203 …_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_RQ_ERR	UINT32_C(0x2)
12208 …ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SRQ_ERR	UINT32_C(0x4)
12213 …_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR	UINT32_C(0x8)
12227 	#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_MASK		UINT32_C(0x3f)
12228 	#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_SFT		0
12230 		#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12241 	#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_CTX_ERROR UINT32_C(0x4a)
12246 	#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE	UINT32_C(0x1)
12248 		#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_ALLOC  UINT32_C(0x0)
12250 		#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_FREE   UINT32_C(0x1)
12253 	#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_NUM_CTXS_MASK	UINT32_C(0xfffe)
12256 	#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_FID_MASK	UINT32_C(0xffff0000)
12262 	 * will write 1. The odd passes will write 0.
12264 	#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_V	UINT32_C(0x1)
12266 	#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_OPAQUE_MASK UINT32_C(0xfe)
12275 	#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_MASK UINT32_C(0xffffffff)
12276 	#define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_SFT 0
12290 	#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_MASK		UINT32_C(0x3f)
12291 	#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_SFT		0
12293 		#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12301 	#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_UDCC_SESSION_CHANGE UINT32_C(0x4b)
12306 	#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_MASK   UINT32_C(0xff)
12307 	#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_SFT	0
12309 		#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_CREATED  UINT32_C(0x0)
12311 		#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_FREED	UINT32_C(0x1)
12317 	 * will write 1. The odd passes will write 0.
12319 	#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_V	UINT32_C(0x1)
12321 	#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
12330 	#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_MASK UINT32_C(0xffff)
12331 	#define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_SFT 0
12345 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_TYPE_MASK		UINT32_C(0x3f)
12346 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_TYPE_SFT		0
12348 		#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12356 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_ID_REPRESENTOR_PAIR_CHANGE UINT32_C(0x4e)
12361 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_MASK   UINT32_C(0xff)
12362 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_SFT	0
12364 		#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_CREATED  UINT32_C(0x0)
12366 		#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_PAIR_OP_CODE_DELETED  UINT32_C(0x1)
12369 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_MASK   UINT32_C(0xff00)
12372 …#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_MODIFY   (UINT32_C(0x0) …
12374 …#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA2_DSCP_OP_CODE_IGNORE   (UINT32_C(0x1) …
12380 	 * will write 1. The odd passes will write 0.
12382 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_V	UINT32_C(0x1)
12384 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
12393 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA1_PAIR_EP_FID_MASK UINT32_C(0xffff)
12394 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA1_PAIR_EP_FID_SFT  0
12396 	#define HWRM_ASYNC_EVENT_REPRESENTOR_PAIR_CHANGE_EVENT_DATA1_PAIR_REP_FID_MASK UINT32_C(0xffff0000)
12411 	#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK		UINT32_C(0x3f)
12412 	#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT		0
12414 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12424 	#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER UINT32_C(0x4c)
12435 …#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_MASK UINT32_C(0xf…
12436 	#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_SFT 0
12441 	 * will write 1. The odd passes will write 0.
12443 	#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V	UINT32_C(0x1)
12445 	#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK UINT32_C(0xfe)
12454 	#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK	UINT32_C(0xffff)
12455 	#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT		0
12457 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE	UINT32_C(0x0)
12459 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE	UINT32_C(0x1)
12461 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE	UINT32_C(0x2)
12463 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE	UINT32_C(0x3)
12465 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE	UINT32_C(0x4)
12467 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE	UINT32_C(0x5)
12469 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE  UINT32_C(0x6)
12470 	/* Context Accelerator CPU 0 trace. */
12471 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE	UINT32_C(0x7)
12473 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE	UINT32_C(0x8)
12475 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE	UINT32_C(0x9)
12477 		#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE	UINT32_C(0xa)
12492 	#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_TYPE_MASK		UINT32_C(0x3f)
12493 	#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_TYPE_SFT		0
12495 		#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12504 	#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_EVENT_ID_PEER_MMAP_CHANGE UINT32_C(0x4d)
12512 	 * will write 1. The odd passes will write 0.
12514 	#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_V	UINT32_C(0x1)
12516 	#define HWRM_ASYNC_EVENT_CMPL_PEER_MMAP_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
12537 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK		UINT32_C(0x3f)
12538 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT		0
12540 		#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12545 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG UINT32_C(0xfe)
12547 	/* Trace byte 0 to 3 */
12550 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK UINT32_C(0xff)
12551 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
12553 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK UINT32_C(0xff00)
12556 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK UINT32_C(0xff0000)
12559 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK UINT32_C(0xff000000)
12565 	 * will write 1. The odd passes will write 0.
12567 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V	UINT32_C(0x1)
12569 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
12574 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING		UINT32_C(0x1)
12576 		#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE	UINT32_C(0x0)
12578 		#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL	UINT32_C(0x1)
12581 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE	UINT32_C(0x2)
12583 		#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY	(UINT32_C(0x0) << 1)
12585 		#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY  (UINT32_C(0x1) << 1)
12590 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK UINT32_C(0xff)
12591 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
12593 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK UINT32_C(0xff00)
12598 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK UINT32_C(0xff)
12599 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
12601 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK UINT32_C(0xff00)
12604 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK UINT32_C(0xff0000)
12607 	#define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK UINT32_C(0xff000000)
12622 	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK		UINT32_C(0x3f)
12623 	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT		0
12625 		#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12630 	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR UINT32_C(0xff)
12635 	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK	UINT32_C(0xff)
12636 	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT	0
12638 		#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING   UINT32_C(0x0)
12640 		#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL  UINT32_C(0x1)
12642 		#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL	UINT32_C(0x2)
12648 	 * will write 1. The odd passes will write 0.
12650 	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V	UINT32_C(0x1)
12652 	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
12661 	#define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP	UINT32_C(0x1)
12675 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK		UINT32_C(0x3f)
12676 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT		0
12678 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12687 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12695 	 * will write 1. The odd passes will write 0.
12697 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V	UINT32_C(0x1)
12699 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK UINT32_C(0xfe)
12708 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK			UINT32_C(0xff)
12709 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT			0
12711 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED			UINT32_C(0x0)
12716 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM		UINT32_C(0x1)
12724 …#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL		UINT32_C(0x…
12729 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM			UINT32_C(0x3)
12735 …WRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD	UINT32_C(0x4)
12740 …ine HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD		UINT32_C(0x5)
12745 …YNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED  UINT32_C(0x6)
12750 	(((x) < 0x80) ? \
12751 	((x) == 0x0 ? "RESERVED": \
12752 	((x) == 0x1 ? "PAUSE_STORM": \
12753 	((x) == 0x2 ? "INVALID_SIGNAL": \
12754 	((x) == 0x3 ? "NVM": \
12755 	((x) == 0x4 ? "DOORBELL_DROP_THRESHOLD": \
12756 	((x) == 0x5 ? "THERMAL_THRESHOLD": \
12757 	((x) == 0x6 ? "DUAL_DATA_RATE_NOT_SUPPORTED": \
12773 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK		UINT32_C(0x3f)
12774 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT		0
12776 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12785 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12793 	 * will write 1. The odd passes will write 0.
12795 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V	UINT32_C(0x1)
12797 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK UINT32_C(0xfe)
12806 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK	UINT32_C(0xff)
12807 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT	0
12812 …ne HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM  UINT32_C(0x1)
12827 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK		UINT32_C(0x3f)
12828 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT		0
12830 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12839 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12844 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK UINT32_C(0xff)
12845 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0
12850 	 * will write 1. The odd passes will write 0.
12852 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V	UINT32_C(0x1)
12854 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK UINT32_C(0xfe)
12863 …#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK	UINT32_C(0xf…
12864 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT	0
12872 …M_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL  UINT32_C(0x2)
12887 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK		UINT32_C(0x3f)
12888 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT		0
12890 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12899 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12904 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK UINT32_C(0xffffffff)
12905 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0
12910 	 * will write 1. The odd passes will write 0.
12912 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V	UINT32_C(0x1)
12914 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK UINT32_C(0xfe)
12923 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK	UINT32_C(0xff)
12924 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT	0
12929 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR  UINT32_C(0x3)
12932 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK   UINT32_C(0xff00)
12939 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE	(UINT32_C(0x1) << 8)
12945 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE	(UINT32_C(0x2) << 8)
12960 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK		UINT32_C(0x3f)
12961 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT		0
12963 …ne HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
12972 …ine HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12980 	 * will write 1. The odd passes will write 0.
12982 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V	UINT32_C(0x1)
12984 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK UINT32_C(0xfe)
12993 …M_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK		UINT32_C(0xff)
12994 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT			0
13000 …_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD  UINT32_C(0x4)
13006 …ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK			UINT32_C(0xffffff00)
13021 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK		UINT32_C(0x3f)
13022 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT		0
13024 		#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
13033 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
13038 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK  UINT32_C(0xff)
13039 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT   0
13044 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK UINT32_C(0xff00)
13050 	 * will write 1. The odd passes will write 0.
13052 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V	UINT32_C(0x1)
13054 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK UINT32_C(0xfe)
13063 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK	UINT32_C(0xff)
13064 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT	0
13073 …ine HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT   UINT32_C(0x5)
13076 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK	UINT32_C(0x700)
13079 …#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN	(UINT32_C(0x0) …
13081 …HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL	(UINT32_C(0x1) << 8)
13083 …#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL	(UINT32_C(0x2)…
13089 …HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN	(UINT32_C(0x3) << 8)
13095 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR	UINT32_C(0x800)
13097 …_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING  (UINT32_C(0x0) << 11)
13099 …_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING  (UINT32_C(0x1) << 11)
13114 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK		UINT32_C(0x3f)
13115 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT		0
13117 …RM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
13126 …WRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
13134 	 * will write 1. The odd passes will write 0.
13136 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V	UINT32_C(0x1)
13138 	#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK UINT32_C(0xfe)
13147 …C_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK			UINT32_C(0xff)
13148 …fine HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT			0
13153 …ORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED  UINT32_C(0x6)
13168 	#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_TYPE_MASK		UINT32_C(0x3f)
13169 	#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_TYPE_SFT		0
13171 		#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
13179 	#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_ID_VF_STAT_CHANGE UINT32_C(0x4f)
13187 	#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA2_VF_ID_MASK		UINT32_C(0xffff)
13188 	#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA2_VF_ID_SFT		0
13198 …#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA2_ACTION_SEQUENCE_ID_MASK UINT32_C(0xffff00…
13204 	 * will write 1. The odd passes will write 0.
13206 	#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_V	UINT32_C(0x1)
13208 	#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
13217 	#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA1_STAT_CTX_ID_MASK UINT32_C(0xffffffff)
13218 	#define HWRM_ASYNC_EVENT_CMPL_VF_STAT_CHANGE_EVENT_DATA1_STAT_CTX_ID_SFT 0
13232 	#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_TYPE_MASK		UINT32_C(0x3f)
13233 	#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_TYPE_SFT		0
13235 		#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_TYPE_HWRM_ASYNC_EVENT  UINT32_C(0x2e)
13243 	#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_EVENT_ID_HOST_COREDUMP UINT32_C(0x50)
13251 	 * will write 1. The odd passes will write 0.
13253 	#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_V	UINT32_C(0x1)
13255 	#define HWRM_ASYNC_EVENT_CMPL_HOST_COREDUMP_OPAQUE_MASK UINT32_C(0xfe)
13270 	#define METADATA_BASE_MSG_MD_TYPE_MASK	UINT32_C(0x1f)
13271 	#define METADATA_BASE_MSG_MD_TYPE_SFT	0
13273 		#define METADATA_BASE_MSG_MD_TYPE_NONE	UINT32_C(0x0)
13279 		#define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC  UINT32_C(0x1)
13284 		#define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC  UINT32_C(0x2)
13286 		#define METADATA_BASE_MSG_MD_TYPE_QUIC	UINT32_C(0x3)
13291 		#define METADATA_BASE_MSG_MD_TYPE_ILLEGAL	UINT32_C(0x1f)
13300 	#define METADATA_BASE_MSG_LINK_MASK	UINT32_C(0x1e0)
13311 	#define TLS_METADATA_BASE_MSG_MD_TYPE_MASK				UINT32_C(0x1f)
13312 	#define TLS_METADATA_BASE_MSG_MD_TYPE_SFT				0
13318 		#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC				UINT32_C(0x1)
13323 		#define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC				UINT32_C(0x2)
13330 	#define TLS_METADATA_BASE_MSG_LINK_MASK					UINT32_C(0x1e0)
13333 	#define TLS_METADATA_BASE_MSG_FLAGS_MASK				UINT32_C(0x1fffe00)
13339 	#define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED				UINT32_C(0x200)
13344 	#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK				UINT32_C(0xc00)
13350 		#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID			(UINT32_C(0x0) << 10)
13356 		#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC				(UINT32_C(0x1) << 10)
13362 		#define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC			(UINT32_C(0x2) << 10)
13365 	#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK			UINT32_C(0x3000)
13371 		#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED		(UINT32_C(0x0) << 12)
13376 		#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS		(UINT32_C(0x1) << 12)
13382 		#define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE		(UINT32_C(0x2) << 12)
13388 	#define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID			UINT32_C(0x4000)
13394 	#define TLS_METADATA_BASE_MSG_FLAGS_CTX_LOAD_ERR				UINT32_C(0x8000)
13396 	#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_MASK		UINT32_C(0x70000)
13399 		#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER		(UINT32_C(0x0) << 16)
13401 		#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER	(UINT32_C(0x1) << 16)
13403 		#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH	(UINT32_C(0x2) << 16)
13405 		#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC		(UINT32_C(0x3) << 16)
13410 		#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT	(UINT32_C(0x4) << 16)
13415 …#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL   (UINT32_C(0x5) << 16)
13417 		#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS	(UINT32_C(0x6) << 16)
13422 …#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT   (UINT32_C(0x7) << 16)
13428 	#define TLS_METADATA_BASE_MSG_KID_LO_MASK				UINT32_C(0xfe000000)
13435 	#define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
13436 	#define TLS_METADATA_BASE_MSG_KID_HI_SFT 0
13445 	#define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK				UINT32_C(0x1f)
13446 	#define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT				0
13452 		#define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC				UINT32_C(0x1)
13459 	#define TLS_METADATA_INSYNC_MSG_LINK_MASK					UINT32_C(0x1e0)
13462 	#define TLS_METADATA_INSYNC_MSG_FLAGS_MASK				UINT32_C(0x1fffe00)
13468 	#define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED				UINT32_C(0x200)
13473 	#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK				UINT32_C(0xc00)
13479 		#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID			(UINT32_C(0x0) << 10)
13485 		#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC				(UINT32_C(0x1) << 10)
13491 		#define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC			(UINT32_C(0x2) << 10)
13494 	#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK			UINT32_C(0x3000)
13500 		#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED		(UINT32_C(0x0) << 12)
13505 		#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS		(UINT32_C(0x1) << 12)
13511 		#define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE		(UINT32_C(0x2) << 12)
13517 	#define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID			UINT32_C(0x4000)
13523 	#define TLS_METADATA_INSYNC_MSG_FLAGS_CTX_LOAD_ERR				UINT32_C(0x8000)
13525 	#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK		UINT32_C(0x70000)
13528 		#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER		(UINT32_C(0x0) << 16)
13530 		#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER	(UINT32_C(0x1) << 16)
13532 		#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH	(UINT32_C(0x2) << 16)
13534 		#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC		(UINT32_C(0x3) << 16)
13539 		#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT	(UINT32_C(0x4) << 16)
13544 …#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL   (UINT32_C(0x5) << …
13546 		#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS	(UINT32_C(0x6) << 16)
13551 …#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT   (UINT32_C(0x7) << …
13557 	#define TLS_METADATA_INSYNC_MSG_KID_LO_MASK				UINT32_C(0xfe000000)
13564 	#define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
13565 	#define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
13598 	#define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK				UINT32_C(0x1f)
13599 	#define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT				0
13604 		#define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC				UINT32_C(0x2)
13611 	#define TLS_METADATA_RESYNC_MSG_LINK_MASK					UINT32_C(0x1e0)
13614 	#define TLS_METADATA_RESYNC_MSG_FLAGS_MASK				UINT32_C(0x1fffe00)
13620 	#define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED				UINT32_C(0x200)
13625 	#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK				UINT32_C(0xc00)
13631 		#define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID			(UINT32_C(0x0) << 10)
13634 	#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK			UINT32_C(0x3000)
13640 		#define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED		(UINT32_C(0x0) << 12)
13646 	#define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID			UINT32_C(0x4000)
13652 	#define TLS_METADATA_RESYNC_MSG_FLAGS_CTX_LOAD_ERR				UINT32_C(0x8000)
13654 	#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK		UINT32_C(0x70000)
13657 		#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER		(UINT32_C(0x0) << 16)
13659 		#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER	(UINT32_C(0x1) << 16)
13661 		#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH	(UINT32_C(0x2) << 16)
13663 		#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC		(UINT32_C(0x3) << 16)
13668 		#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT	(UINT32_C(0x4) << 16)
13673 …#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL   (UINT32_C(0x5) << …
13675 		#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS	(UINT32_C(0x6) << 16)
13680 …#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT   (UINT32_C(0x7) << …
13686 	#define TLS_METADATA_RESYNC_MSG_KID_LO_MASK				UINT32_C(0xfe000000)
13693 	#define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
13694 	#define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0
13723 	#define TX_DOORBELL_IDX_MASK UINT32_C(0xffffff)
13724 	#define TX_DOORBELL_IDX_SFT 0
13727 	 * that is begin requested. This value is '0' for TX
13730 	#define TX_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
13733 		#define TX_DOORBELL_KEY_TX	(UINT32_C(0x0) << 28)
13747 	#define RX_DOORBELL_IDX_MASK UINT32_C(0xffffff)
13748 	#define RX_DOORBELL_IDX_SFT 0
13754 	#define RX_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
13757 		#define RX_DOORBELL_KEY_RX	(UINT32_C(0x1) << 28)
13771 	#define CMPL_DOORBELL_IDX_MASK	UINT32_C(0xffffff)
13772 	#define CMPL_DOORBELL_IDX_SFT	0
13775 	 * update when it is '1'. When it is '0', the BDIDX
13778 	#define CMPL_DOORBELL_IDX_VALID	UINT32_C(0x4000000)
13782 	 * interrupt is to be masked. A '0' indicates the interrupt
13785 	#define CMPL_DOORBELL_MASK	UINT32_C(0x8000000)
13791 	#define CMPL_DOORBELL_KEY_MASK	UINT32_C(0xf0000000)
13794 		#define CMPL_DOORBELL_KEY_CMPL	(UINT32_C(0x2) << 28)
13811 	#define STATUS_DOORBELL_IDX_MASK UINT32_C(0xffffff)
13812 	#define STATUS_DOORBELL_IDX_SFT 0
13818 	#define STATUS_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
13821 		#define STATUS_DOORBELL_KEY_STAT  (UINT32_C(0x3) << 28)
13834 	#define PUSH32_DOORBELL_IDX_MASK UINT32_C(0xffffff)
13835 	#define PUSH32_DOORBELL_IDX_SFT 0
13843 	 * A value of 0 indicates 16x16B BD spaces are consumed.
13845 	#define PUSH32_DOORBELL_SZ_MASK UINT32_C(0xf000000)
13852 	#define PUSH32_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
13855 		#define PUSH32_DOORBELL_KEY_PUSH  (UINT32_C(0x4) << 28)
13859 	#define PUSH32_DOORBELL_TYPE_MASK		UINT32_C(0x3f)
13860 	#define PUSH32_DOORBELL_TYPE_SFT		0
13865 		#define PUSH32_DOORBELL_TYPE_TX_BD_LONG	UINT32_C(0x10)
13872 	#define PUSH32_DOORBELL_FLAGS_MASK	UINT32_C(0xffc0)
13881 	#define PUSH32_DOORBELL_FLAGS_PACKET_END	UINT32_C(0x40)
13887 	 * is set to 0, then the packet will be completed normally.
13891 	#define PUSH32_DOORBELL_FLAGS_NO_CMPL	UINT32_C(0x80)
13899 	#define PUSH32_DOORBELL_FLAGS_BD_CNT_MASK	UINT32_C(0x1f00)
13909 	#define PUSH32_DOORBELL_FLAGS_LHINT_MASK	UINT32_C(0x6000)
13912 		#define PUSH32_DOORBELL_FLAGS_LHINT_LT512	(UINT32_C(0x0) << 13)
13914 		#define PUSH32_DOORBELL_FLAGS_LHINT_LT1K	(UINT32_C(0x1) << 13)
13916 		#define PUSH32_DOORBELL_FLAGS_LHINT_LT2K	(UINT32_C(0x2) << 13)
13918 		#define PUSH32_DOORBELL_FLAGS_LHINT_GTE2K	(UINT32_C(0x3) << 13)
13926 	 * is set to 0, then the Consumer Index is only updated as soon
13931 	#define PUSH32_DOORBELL_FLAGS_COAL_NOW	UINT32_C(0x8000)
13961 	#define PUSH32_DOORBELL_LFLAGS_TCP_UDP_CHKSUM	UINT32_C(0x1)
13970 	#define PUSH32_DOORBELL_LFLAGS_IP_CHKSUM	UINT32_C(0x2)
13982 	#define PUSH32_DOORBELL_LFLAGS_NOCRC		UINT32_C(0x4)
13989 	#define PUSH32_DOORBELL_LFLAGS_STAMP		UINT32_C(0x8)
14006 	#define PUSH32_DOORBELL_LFLAGS_T_IP_CHKSUM	UINT32_C(0x10)
14018 	#define PUSH32_DOORBELL_LFLAGS_LSO		UINT32_C(0x20)
14022 	 * 0xffff.
14026 	 * 0x7fff.
14028 	#define PUSH32_DOORBELL_LFLAGS_IPID_FMT	UINT32_C(0x40)
14040 	#define PUSH32_DOORBELL_LFLAGS_T_IPID		UINT32_C(0x80)
14045 	#define PUSH32_DOORBELL_LFLAGS_ROCE_CRC	UINT32_C(0x100)
14050 	#define PUSH32_DOORBELL_LFLAGS_FCOE_CRC	UINT32_C(0x200)
14061 	#define PUSH32_DOORBELL_HDR_SIZE_MASK UINT32_C(0x1ff)
14062 	#define PUSH32_DOORBELL_HDR_SIZE_SFT 0
14071 	#define PUSH32_DOORBELL_MSS_MASK UINT32_C(0x7fff)
14072 	#define PUSH32_DOORBELL_MSS_SFT 0
14087 	#define PUSH32_DOORBELL_CFA_META_VLAN_VID_MASK	UINT32_C(0xfff)
14088 	#define PUSH32_DOORBELL_CFA_META_VLAN_VID_SFT	0
14090 	#define PUSH32_DOORBELL_CFA_META_VLAN_DE	UINT32_C(0x1000)
14092 	#define PUSH32_DOORBELL_CFA_META_VLAN_PRI_MASK	UINT32_C(0xe000)
14095 	#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_MASK	UINT32_C(0x70000)
14097 	/* 0x88a8 */
14098 		#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID88A8  (UINT32_C(0x0) << 16)
14099 	/* 0x8100 */
14100 		#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID8100  (UINT32_C(0x1) << 16)
14101 	/* 0x9100 */
14102 		#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9100  (UINT32_C(0x2) << 16)
14103 	/* 0x9200 */
14104 		#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9200  (UINT32_C(0x3) << 16)
14105 	/* 0x9300 */
14106 		#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9300  (UINT32_C(0x4) << 16)
14108 		#define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPIDCFG   (UINT32_C(0x5) << 16)
14111 	#define PUSH32_DOORBELL_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
14119 	#define PUSH32_DOORBELL_CFA_META_KEY_MASK	UINT32_C(0xf0000000)
14122 		#define PUSH32_DOORBELL_CFA_META_KEY_NONE		(UINT32_C(0x0) << 28)
14124 	 * - meta[17:16] - TPID select value (0 = 0x8100).
14126 	 * - meta[11:0] - VID value.
14128 		#define PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG	(UINT32_C(0x1) << 28)
14162 	 * * 0x0-0xFFF8 - The function ID
14163 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14164 	 * * 0xFFFD - Reserved for user-space HWRM interface
14165 	 * * 0xFFFF - HWRM
14180 	#define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID	UINT32_C(0x1)
14195 	#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL	UINT32_C(0x0)
14197 	#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME	UINT32_C(0x1)
14205 	#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN UINT32_C(0x2)
14213 	#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF	UINT32_C(0x3)
14263 	 * * 0x0-0xFFF8 - The function ID
14264 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14265 	 * * 0xFFFD - Reserved for user-space HWRM interface
14266 	 * * 0xFFFF - HWRM
14281 	#define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID	UINT32_C(0x1)
14342 	 * * 0x0-0xFFF8 - The function ID
14343 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14344 	 * * 0xFFFD - Reserved for user-space HWRM interface
14345 	 * * 0xFFFF - HWRM
14360 	#define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID	UINT32_C(0x1)
14417 	 * * 0x0-0xFFF8 - The function ID
14418 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14419 	 * * 0xFFFD - Reserved for user-space HWRM interface
14420 	 * * 0xFFFF - HWRM
14435 	#define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID	UINT32_C(0x1)
14443 	 * 0xFFFF - Cleanup all children of this PF.
14493 	 * * 0x0-0xFFF8 - The function ID
14494 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14495 	 * * 0xFFFD - Reserved for user-space HWRM interface
14496 	 * * 0xFFFF - HWRM
14511 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU			UINT32_C(0x1)
14516 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN		UINT32_C(0x2)
14521 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR	UINT32_C(0x4)
14526 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR		UINT32_C(0x8)
14531 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS	UINT32_C(0x10)
14536 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS	UINT32_C(0x20)
14541 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS		UINT32_C(0x40)
14546 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS		UINT32_C(0x80)
14551 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS		UINT32_C(0x100)
14556 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS		UINT32_C(0x200)
14561 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS		UINT32_C(0x400)
14566 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS	UINT32_C(0x800)
14571 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_TX_KEY_CTXS	UINT32_C(0x1000)
14576 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_RX_KEY_CTXS	UINT32_C(0x2000)
14581 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_TX_KEY_CTXS	UINT32_C(0x4000)
14586 	#define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_RX_KEY_CTXS	UINT32_C(0x8000)
14638 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST		UINT32_C(0x1)
14646 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST		UINT32_C(0x2)
14654 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST	UINT32_C(0x4)
14662 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST	UINT32_C(0x8)
14670 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST	UINT32_C(0x10)
14678 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST	UINT32_C(0x20)
14686 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST	UINT32_C(0x40)
14694 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST	UINT32_C(0x80)
14703 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE	UINT32_C(0x100)
14709 	#define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE	UINT32_C(0x200)
14784 	 * * 0x0-0xFFF8 - The function ID
14785 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14786 	 * * 0xFFFD - Reserved for user-space HWRM interface
14787 	 * * 0xFFFF - HWRM
14799 	 * 0xFF... (All Fs) if the query is for the requesting
14801 	 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
14827 	 * 0xFF... (All Fs) if this function is not associated with
14829 	 * 0xFF... (All Fs) if this function is called from a VF.
14834 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED		UINT32_C(0x1)
14839 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING		UINT32_C(0x2)
14846 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED			UINT32_C(0x4)
14851 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED			UINT32_C(0x8)
14856 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED			UINT32_C(0x10)
14861 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED		UINT32_C(0x20)
14866 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED			UINT32_C(0x40)
14871 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED		UINT32_C(0x80)
14876 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED		UINT32_C(0x100)
14882 	 * If this query is for a PF and this flag is set to 0, then
14886 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED		UINT32_C(0x200)
14892 	 * If this query is for a PF and this flag is set to 0, then
14896 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED		UINT32_C(0x400)
14903 	 * If set to 0, then standard TX ring mode is not available
14906 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED		UINT32_C(0x800)
14913 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED		UINT32_C(0x1000)
14920 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED		UINT32_C(0x2000)
14927 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED		UINT32_C(0x4000)
14934 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED		UINT32_C(0x8000)
14940 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED		UINT32_C(0x10000)
14947 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED		UINT32_C(0x20000)
14954 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED			UINT32_C(0x40000)
14961 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED	UINT32_C(0x80000)
14966 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE			UINT32_C(0x100000)
14972 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC		UINT32_C(0x200000)
14977 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE			UINT32_C(0x400000)
14982 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE		UINT32_C(0x800000)
14988 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED		UINT32_C(0x1000000)
14995 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD			UINT32_C(0x2000000)
14997 	 * If the query is for a VF, then this flag (always set to 0) shall
15003 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED	UINT32_C(0x4000000)
15005 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED	UINT32_C(0x8000000)
15010 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED		UINT32_C(0x10000000)
15015 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED		UINT32_C(0x20000000)
15026 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED		UINT32_C(0x40000000)
15031 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED		UINT32_C(0x80000000)
15071 	 * 0xFF... (All Fs) if this command is called on a PF with
15078 	 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
15155 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED			UINT32_C(0x1)
15160 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED			UINT32_C(0x2)
15165 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED			UINT32_C(0x4)
15171 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT			UINT32_C(0x8)
15173 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT			UINT32_C(0x10)
15178 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT	UINT32_C(0x20)
15183 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED				UINT32_C(0x40)
15188 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED			UINT32_C(0x80)
15193 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED		UINT32_C(0x100)
15201 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED			UINT32_C(0x200)
15206 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED			UINT32_C(0x400)
15211 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE			UINT32_C(0x800)
15216 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE			UINT32_C(0x1000)
15221 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED		UINT32_C(0x2000)
15226 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED			UINT32_C(0x4000)
15234 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED			UINT32_C(0x8000)
15239 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED			UINT32_C(0x10000)
15241 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED			UINT32_C(0x20000)
15243 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED			UINT32_C(0x40000)
15249 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED		UINT32_C(0x80000)
15256 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED			UINT32_C(0x100000)
15261 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED		UINT32_C(0x200000)
15263 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_KTLS_SUPPORTED				UINT32_C(0x400000)
15271 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL				UINT32_C(0x800000)
15279 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_MIN_BW_SUPPORTED				UINT32_C(0x1000000)
15284 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP				UINT32_C(0x2000000)
15290 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED				UINT32_C(0x4000000)
15295 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_REQUIRED				UINT32_C(0x8000000)
15300 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED			UINT32_C(0x10000000)
15305 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DBR_PACING_SUPPORTED			UINT32_C(0x20000000)
15310 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED		UINT32_C(0x40000000)
15315 …#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED	UINT32_C(0x800000…
15324 	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE	UINT32_C(0x1)
15330 	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE	UINT32_C(0x2)
15336 	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA	UINT32_C(0x4)
15342 	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA	UINT32_C(0x8)
15348 	#define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE	UINT32_C(0x10)
15359 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED	UINT32_C(0x1)
15361 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED			UINT32_C(0x2)
15367 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED			UINT32_C(0x4)
15372 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED		UINT32_C(0x8)
15377 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED	UINT32_C(0x10)
15382 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_GENERIC_STATS_SUPPORTED		UINT32_C(0x20)
15387 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDP_GSO_SUPPORTED			UINT32_C(0x40)
15392 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SYNCE_SUPPORTED			UINT32_C(0x80)
15395 	 * supporting doorbell pacing version 0. As doorbell pacing
15405 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED		UINT32_C(0x100)
15415 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED		UINT32_C(0x200)
15422 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED			UINT32_C(0x400)
15427 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED		UINT32_C(0x800)
15434 	 * support steering to multiple address domains, a value of 0 in
15435 	 * bit 0 of the steering tag specifies the address is associated
15439 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_STEERING_TAG_SUPPORTED		UINT32_C(0x1000)
15444 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED	UINT32_C(0x2000)
15450 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED	UINT32_C(0x4000)
15457 	 * 2. If it is cleared to '0', it indicates that the driver has to
15461 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED	UINT32_C(0x8000)
15466 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED	UINT32_C(0x10000)
15471 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED		UINT32_C(0x20000)
15476 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED	UINT32_C(0x40000)
15481 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED		UINT32_C(0x80000)
15486 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED	UINT32_C(0x100000)
15491 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDCC_SUPPORTED			UINT32_C(0x200000)
15499 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED	UINT32_C(0x400000)
15510 	 * If this bit is '0', the FW will use to legacy behavior.
15516 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED	UINT32_C(0x800000)
15521 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED	UINT32_C(0x1000000)
15526 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_LPBK_STATS_SUPPORTED		UINT32_C(0x2000000)
15531 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED	UINT32_C(0x4000000)
15536 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED	UINT32_C(0x8000000)
15541 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_PEER_MMAP_SUPPORTED		UINT32_C(0x10000000)
15549 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TIMED_TX_PACING_SUPPORTED		UINT32_C(0x20000000)
15557 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_VF_STAT_EJECTION_SUPPORTED		UINT32_C(0x40000000)
15563 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HOST_COREDUMP_SUPPORTED		UINT32_C(0x80000000)
15569 	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN	UINT32_C(0x1)
15574 	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE	UINT32_C(0x2)
15579 	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE	UINT32_C(0x4)
15584 	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE	UINT32_C(0x8)
15589 	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE	UINT32_C(0x10)
15594 	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP	UINT32_C(0x20)
15599 	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_MPLS	UINT32_C(0x40)
15604 	#define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE	UINT32_C(0x80)
15611 	#define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_TX_CK	UINT32_C(0x1)
15617 	#define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_RX_CK	UINT32_C(0x2)
15690 	#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP	UINT32_C(0x1)
15726 	 * * 0x0-0xFFF8 - The function ID
15727 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15728 	 * * 0xFFFD - Reserved for user-space HWRM interface
15729 	 * * 0xFFFF - HWRM
15741 	 * 0xFF... (All Fs) if the query is for the requesting
15743 	 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
15768 	 * 0xFF... (All Fs) if this function is not associated with
15774 	 * function. The value of 0 for this field indicates
15786 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED	UINT32_C(0x1)
15791 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED	UINT32_C(0x2)
15795 	 * If set to 0, then DCBX agent is not running in the firmware.
15797 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED	UINT32_C(0x4)
15804 	 * If set to 0, then the standard TX ring mode is disabled
15810 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED	UINT32_C(0x8)
15814 	 * If set to 0 then the LLDP agent is not running in the firmware.
15816 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED	UINT32_C(0x10)
15821 	 * If set to 0, then multi-host mode is inactive for this function
15824 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST		UINT32_C(0x20)
15827 	 * set this field to 0 and the HWRM client shall ignore this field.
15830 	 * HWRM shall set this field to 0.
15832 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF		UINT32_C(0x40)
15835 	 * device. If set to 0, then secure mode is disabled (or normal mode)
15838 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED	UINT32_C(0x80)
15842 	 * doorbells. If set to 0, then this PF is not allowed to use
15847 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS	UINT32_C(0x100)
15852 	 * If set to 0, then the adapter is not currently able to initiate
15855 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED		UINT32_C(0x200)
15858 	 * reserved TX rings of this function. If set to 0, then PPP tx push
15861 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED	UINT32_C(0x400)
15866 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED	UINT32_C(0x800)
15871 	 * If set to 0, then the adapter is not currently able to initiate
15874 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED	UINT32_C(0x1000)
15879 	 * If set to 0, then multi-root mode is inactive for this function
15882 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT		UINT32_C(0x2000)
15887 	 * If set to 0, RoCE is disabled on all child VFs.
15889 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV		UINT32_C(0x4000)
15892 	 * is valid. If this bit is 0, the driver should not use the
15895 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ROCE_VNIC_ID_VALID	UINT32_C(0x8000)
15962 	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF	UINT32_C(0x0)
15964 	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS	UINT32_C(0x1)
15966 	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
15968 	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
15970 	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
15972 	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2 UINT32_C(0x5)
15974 	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN UINT32_C(0xff)
15978 	 * port_partition. HWRM shall return unavail (i.e. value of 0) for this
15984 	#define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
15995 	 * A value of 0 indicates the minimum bandwidth is not configured.
15999 	#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
16000 	#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT		0
16002 	#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE			UINT32_C(0x10000000)
16004 		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
16006 		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
16009 	#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
16012 		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
16014 		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
16016 		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
16018 		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
16020 		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
16022 		#define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
16027 	 * A value of 0 indicates that the maximum bandwidth is not configured.
16031 	#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
16032 	#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT		0
16034 	#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE			UINT32_C(0x10000000)
16036 		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
16038 		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
16041 	#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
16044 		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
16046 		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
16048 		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
16050 		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
16052 		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
16054 		#define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
16062 	#define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
16064 	#define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB	UINT32_C(0x1)
16066 	#define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA   UINT32_C(0x2)
16074 	#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK	UINT32_C(0x3)
16075 	#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT	0
16077 		#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64	UINT32_C(0x0)
16079 		#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128	UINT32_C(0x1)
16082 	#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK	UINT32_C(0xc)
16085 		#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (UINT32_C(0x0) << 2)
16087 		#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP	(UINT32_C(0x1) << 2)
16092 		#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO	(UINT32_C(0x2) << 2)
16095 	#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK		UINT32_C(0xf0)
16100 	 * 0xFF... (All Fs) if this command is called on a PF with
16150 	 * specific endpoint, with bit 0 indicating EP 0 and bit 3 indicating
16152 	 * - a single root system would return 0x1
16153 	 * - a 2x8 system (where EPs 0 and 2 are active) would return 0x5
16154 	 * - a 4x4 system (where EPs 0-3 are active) would return 0xF
16181 	#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK	UINT32_C(0x7fff)
16182 	#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT	0
16184 	#define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID	UINT32_C(0x8000)
16190 	#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED	UINT32_C(0x1)
16195 	#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED	UINT32_C(0x2)
16201 	#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED	UINT32_C(0x4)
16207 	#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED	UINT32_C(0x8)
16212 	#define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED	UINT32_C(0x10)
16219 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4KB   UINT32_C(0x0)
16221 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_8KB   UINT32_C(0x1)
16223 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_16KB  UINT32_C(0x2)
16225 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_32KB  UINT32_C(0x3)
16227 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_64KB  UINT32_C(0x4)
16229 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)
16231 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)
16233 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)
16235 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_1MB   UINT32_C(0x8)
16237 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_2MB   UINT32_C(0x9)
16239 	#define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB   UINT32_C(0xa)
16243 	 * RoCE vnic id, then the roce_vnic_id_valid bit in flags is set to 0.
16250 	 * of the link the partition is associated with. A value of 0
16257 	#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
16258 	#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_SFT		0
16263 	#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE			UINT32_C(0x10000000)
16265 		#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
16267 		#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
16270 	#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
16273 		#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
16279 	 * of the link the partition is associated with. A value of 0
16286 	#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
16287 	#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_SFT		0
16292 	#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE			UINT32_C(0x10000000)
16294 		#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
16296 		#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
16299 	#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
16302 		#define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
16317 	#define HWRM_FUNC_QCFG_OUTPUT_FLAGS2_SRIOV_DSCP_INSERT_ENABLED	UINT32_C(0x1)
16325 	#define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)
16327 	#define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED  UINT32_C(0x1)
16337 	 * feature, 0xffff will be returned.
16347 	 * valid lag_id is from 0 to 7, if there is no valid lag_id,
16348 	 * 0xff will be returned.
16358 	 * function is not a member of any LAG, the fw_lag_id will be 0xff.
16409 	#define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_TX_CK	UINT32_C(0x1)
16414 	#define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_RX_CK	UINT32_C(0x2)
16449 	 * * 0x0-0xFFF8 - The function ID
16450 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16451 	 * * 0xFFFD - Reserved for user-space HWRM interface
16452 	 * * 0xFFFF - HWRM
16465 	 * If set to 0xFF... (All Fs), then the configuration is
16485 	#define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE	UINT32_C(0x1)
16494 	#define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE	UINT32_C(0x2)
16496 	#define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK			UINT32_C(0x1fc)
16505 	#define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE	UINT32_C(0x200)
16516 	#define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE	UINT32_C(0x400)
16521 	#define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST		UINT32_C(0x800)
16529 	#define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC	UINT32_C(0x1000)
16537 	#define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST		UINT32_C(0x2000)
16545 	#define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST		UINT32_C(0x4000)
16553 	#define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST		UINT32_C(0x8000)
16561 	#define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST	UINT32_C(0x10000)
16569 	#define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST	UINT32_C(0x20000)
16577 	#define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST	UINT32_C(0x40000)
16585 	#define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST		UINT32_C(0x80000)
16593 	#define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST		UINT32_C(0x100000)
16602 	#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE		UINT32_C(0x200000)
16608 	#define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC	UINT32_C(0x400000)
16616 	#define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST		UINT32_C(0x800000)
16625 	#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE		UINT32_C(0x1000000)
16632 	#define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS	UINT32_C(0x2000000)
16634 	 * If this bit is set to 0, then the interface does not support hot
16637 	 * flag to 0, adapter cannot do the hot reset. In this state, if the
16642 	#define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS		UINT32_C(0x4000000)
16651 	#define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE	UINT32_C(0x8000000)
16659 	#define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE	UINT32_C(0x10000000)
16665 	#define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE		UINT32_C(0x20000000)
16671 	#define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE		UINT32_C(0x40000000)
16677 	#define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU		UINT32_C(0x1)
16682 	#define HWRM_FUNC_CFG_INPUT_ENABLES_MRU			UINT32_C(0x2)
16687 	#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS	UINT32_C(0x4)
16692 	#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS	UINT32_C(0x8)
16697 	#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS		UINT32_C(0x10)
16702 	#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS		UINT32_C(0x20)
16707 	#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS		UINT32_C(0x40)
16712 	#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS		UINT32_C(0x80)
16717 	#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS		UINT32_C(0x100)
16722 	#define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR		UINT32_C(0x200)
16727 	#define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN		UINT32_C(0x400)
16732 	#define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR		UINT32_C(0x800)
16737 	#define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW		UINT32_C(0x1000)
16742 	#define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW		UINT32_C(0x2000)
16747 	#define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR	UINT32_C(0x4000)
16752 	#define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE	UINT32_C(0x8000)
16757 	#define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS	UINT32_C(0x10000)
16762 	#define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE		UINT32_C(0x20000)
16767 	#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS	UINT32_C(0x40000)
16772 	#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS	UINT32_C(0x80000)
16777 	#define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE	UINT32_C(0x100000)
16782 	#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX		UINT32_C(0x200000)
16787 	#define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE	UINT32_C(0x400000)
16792 	#define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT	UINT32_C(0x800000)
16797 	#define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID		UINT32_C(0x1000000)
16802 	#define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS		UINT32_C(0x2000000)
16807 	#define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MIN_BW	UINT32_C(0x4000000)
16812 	#define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MAX_BW	UINT32_C(0x8000000)
16818 	#define HWRM_FUNC_CFG_INPUT_ENABLES_TPID			UINT32_C(0x10000000)
16823 	#define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU		UINT32_C(0x20000000)
16828 	#define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_TX_KEY_CTXS	UINT32_C(0x40000000)
16833 	#define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_RX_KEY_CTXS	UINT32_C(0x80000000)
16915 	 * A value of 0 indicates the minimum bandwidth is not configured.
16919 	#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
16920 	#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT		0
16922 	#define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE			UINT32_C(0x10000000)
16924 		#define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
16926 		#define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
16929 	#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
16932 		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
16934 		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
16936 		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
16938 		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
16940 		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
16942 		#define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
16947 	 * A value of 0 indicates that the maximum bandwidth is not configured.
16951 	#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
16952 	#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT		0
16954 	#define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE			UINT32_C(0x10000000)
16956 		#define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
16958 		#define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
16961 	#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
16964 		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
16966 		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
16968 		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
16970 		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
16972 		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
16974 		#define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
16992 	#define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK		UINT32_C(0x0)
16994 	#define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN	UINT32_C(0x1)
16996 	#define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE	UINT32_C(0x2)
16998 	#define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN UINT32_C(0x3)
17032 	#define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
17034 	#define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB	UINT32_C(0x1)
17036 	#define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA   UINT32_C(0x2)
17044 	#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK	UINT32_C(0x3)
17045 	#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT	0
17047 		#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64	UINT32_C(0x0)
17049 		#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128	UINT32_C(0x1)
17052 	#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK	UINT32_C(0xc)
17055 		#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (UINT32_C(0x0) << 2)
17057 		#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP	(UINT32_C(0x1) << 2)
17062 		#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO	(UINT32_C(0x2) << 2)
17065 	#define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK		UINT32_C(0xf0)
17078 	 * When this bit is '0', this flag has no effect.
17080 	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE	UINT32_C(0x1)
17084 	 * When this bit is '0', this flag has no effect.
17086 	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE	UINT32_C(0x2)
17090 	 * When this bit is '0', this flag has no effect.
17092 	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE	UINT32_C(0x4)
17096 	 * When this bit is '0', this flag has no effect.
17098 	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE	UINT32_C(0x8)
17102 	 * block. When this bit is '0', this flag has no effect.
17104 	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE	UINT32_C(0x10)
17108 	 * block. When this bit is '0', this flag has no effect.
17110 	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE	UINT32_C(0x20)
17114 	 * block. When this bit is '0', this flag has no effect.
17116 	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE	UINT32_C(0x40)
17120 	 * block. When this bit is '0', this flag has no effect.
17122 	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE	UINT32_C(0x80)
17126 	 * When this bit is '0', this flag has no effect.
17128 	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE	UINT32_C(0x100)
17132 	 * When this bit is '0', this flag has no effect.
17134 	#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE	UINT32_C(0x200)
17139 	 * of the link the partition is associated with. A value of 0
17148 	#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
17149 	#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_SFT		0
17154 	#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE			UINT32_C(0x10000000)
17156 		#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
17158 		#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
17161 	#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
17164 		#define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
17170 	 * of the link the partition is associated with. A value of 0
17177 	#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
17178 	#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_SFT		0
17183 	#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE			UINT32_C(0x10000000)
17185 		#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
17187 		#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
17190 	#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
17193 		#define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
17200 	 * 0x8100 will be used. This field is specified in
17228 	#define HWRM_FUNC_CFG_INPUT_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST	UINT32_C(0x1)
17236 	#define HWRM_FUNC_CFG_INPUT_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST	UINT32_C(0x2)
17242 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_KDNET		UINT32_C(0x1)
17248 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE		UINT32_C(0x2)
17253 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_TX_KEY_CTXS	UINT32_C(0x4)
17258 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_RX_KEY_CTXS	UINT32_C(0x8)
17263 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_AV_PER_VF	UINT32_C(0x10)
17268 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_CQ_PER_VF	UINT32_C(0x20)
17273 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_MRW_PER_VF	UINT32_C(0x40)
17278 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_QP_PER_VF	UINT32_C(0x80)
17283 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_SRQ_PER_VF	UINT32_C(0x100)
17288 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_GID_PER_VF	UINT32_C(0x200)
17293 	#define HWRM_FUNC_CFG_INPUT_ENABLES2_XID_PARTITION_CFG	UINT32_C(0x400)
17301 	#define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)
17303 	#define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED  UINT32_C(0x1)
17316 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4KB   UINT32_C(0x0)
17318 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_8KB   UINT32_C(0x1)
17320 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_16KB  UINT32_C(0x2)
17322 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_32KB  UINT32_C(0x3)
17324 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_64KB  UINT32_C(0x4)
17326 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)
17328 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)
17330 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)
17332 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_1MB   UINT32_C(0x8)
17334 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_2MB   UINT32_C(0x9)
17336 	#define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB   UINT32_C(0xa)
17368 	#define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_TX_CK	UINT32_C(0x1)
17373 	#define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_RX_CK	UINT32_C(0x2)
17405 	#define HWRM_FUNC_CFG_CMD_ERR_CODE_UNKNOWN			UINT32_C(0x0)
17407 	#define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE	UINT32_C(0x1)
17409 	#define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX  UINT32_C(0x2)
17414 	#define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED UINT32_C(0x3)
17416 	#define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT	UINT32_C(0x4)
17444 	 * * 0x0-0xFFF8 - The function ID
17445 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17446 	 * * 0xFFFD - Reserved for user-space HWRM interface
17447 	 * * 0xFFFF - HWRM
17459 	 * 0xFF... (All Fs) if the query is for the requesting
17471 	#define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY	UINT32_C(0x1)
17477 	#define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK	UINT32_C(0x2)
17484 	#define HWRM_FUNC_QSTATS_INPUT_FLAGS_L2_ONLY	UINT32_C(0x4)
17605 	 * * 0x0-0xFFF8 - The function ID
17606 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17607 	 * * 0xFFFD - Reserved for user-space HWRM interface
17608 	 * * 0xFFFF - HWRM
17620 	 * 0xFF... (All Fs) if the query is for the requesting
17632 	#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY	UINT32_C(0x1)
17638 	#define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK	UINT32_C(0x2)
17645 	#define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID	UINT32_C(0x1)
17650 	 * values are 0 through (max_configurable_queues - 1), where
17746 	 * * 0x0-0xFFF8 - The function ID
17747 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17748 	 * * 0xFFFD - Reserved for user-space HWRM interface
17749 	 * * 0xFFFF - HWRM
17761 	 * 0xFF... (All Fs) if the query is for the requesting
17813 	 * * 0x0-0xFFF8 - The function ID
17814 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17815 	 * * 0xFFFD - Reserved for user-space HWRM interface
17816 	 * * 0xFFFF - HWRM
17879 	 * * 0x0-0xFFF8 - The function ID
17880 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17881 	 * * 0xFFFD - Reserved for user-space HWRM interface
17882 	 * * 0xFFFF - HWRM
17901 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE			UINT32_C(0x1)
17910 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE			UINT32_C(0x2)
17915 	 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
17919 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE		UINT32_C(0x4)
17933 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE	UINT32_C(0x8)
17943 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT		UINT32_C(0x10)
17955 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT	UINT32_C(0x20)
17965 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT		UINT32_C(0x40)
17977 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT		UINT32_C(0x80)
17985 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT	UINT32_C(0x100)
17989 	 * a value other than 0x8100 or 0x88a8.
17991 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT		UINT32_C(0x200)
17998 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT	UINT32_C(0x400)
18006 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_TF_INGRESS_NIC_FLOW_MODE	UINT32_C(0x800)
18014 	#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_TF_EGRESS_NIC_FLOW_MODE	UINT32_C(0x1000)
18020 	#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE		UINT32_C(0x1)
18025 	#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER		UINT32_C(0x2)
18030 	#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP	UINT32_C(0x4)
18035 	#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD	UINT32_C(0x8)
18040 	#define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD	UINT32_C(0x10)
18047 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN   UINT32_C(0x0)
18049 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER	UINT32_C(0x1)
18051 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS	UINT32_C(0xe)
18053 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS   UINT32_C(0x12)
18055 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS   UINT32_C(0x1d)
18057 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX	UINT32_C(0x24)
18059 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD   UINT32_C(0x2a)
18061 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI	UINT32_C(0x68)
18063 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864	UINT32_C(0x73)
18065 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
18067 	#define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI	UINT32_C(0x8000)
18107 	 * If all bits are set to 0 (value of 0), then the HWRM shall
18138 	#define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED	UINT32_C(0x1)
18173 	 * * 0x0-0xFFF8 - The function ID
18174 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18175 	 * * 0xFFFD - Reserved for user-space HWRM interface
18176 	 * * 0xFFFF - HWRM
18191 	#define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN	UINT32_C(0x1)
18240 	 * * 0x0-0xFFF8 - The function ID
18241 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18242 	 * * 0xFFFD - Reserved for user-space HWRM interface
18243 	 * * 0xFFFF - HWRM
18258 	#define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID		UINT32_C(0x1)
18263 	#define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR	UINT32_C(0x2)
18280 	#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
18282 	#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K  UINT32_C(0xc)
18284 	#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K  UINT32_C(0xd)
18286 	#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
18288 	#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M  UINT32_C(0x15)
18290 	#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M  UINT32_C(0x16)
18292 	#define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G  UINT32_C(0x1e)
18299 	/* This field represents the page address of page #0. */
18376 	 * * 0x0-0xFFF8 - The function ID
18377 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18378 	 * * 0xFFFD - Reserved for user-space HWRM interface
18379 	 * * 0xFFFF - HWRM
18394 	#define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID	UINT32_C(0x1)
18448 	 * * 0x0-0xFFF8 - The function ID
18449 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18450 	 * * 0xFFFD - Reserved for user-space HWRM interface
18451 	 * * 0xFFFF - HWRM
18465 	 * 0xFF... (All Fs) if the query is for the requesting
18475 	#define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_L2   UINT32_C(0x0)
18477 	#define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_ROCE UINT32_C(0x1)
18499 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN   UINT32_C(0x0)
18501 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER	UINT32_C(0x1)
18503 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS	UINT32_C(0xe)
18505 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS   UINT32_C(0x12)
18507 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS   UINT32_C(0x1d)
18509 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX	UINT32_C(0x24)
18511 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD   UINT32_C(0x2a)
18513 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI	UINT32_C(0x68)
18515 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864	UINT32_C(0x73)
18517 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
18519 	#define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI	UINT32_C(0x8000)
18570 	 * * 0x0-0xFFF8 - The function ID
18571 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18572 	 * * 0xFFFD - Reserved for user-space HWRM interface
18573 	 * * 0xFFFF - HWRM
18585 	 * 0xFF... (All Fs) if the query is for the requesting
18619 	#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL	UINT32_C(0x0)
18621 	#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL	UINT32_C(0x1)
18626 	#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC UINT32_C(0x2)
18672 	#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED	UINT32_C(0x1)
18725 	 * * 0x0-0xFFF8 - The function ID
18726 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18727 	 * * 0xFFFD - Reserved for user-space HWRM interface
18728 	 * * 0xFFFF - HWRM
18780 	#define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED	UINT32_C(0x1)
18870 	 * * 0x0-0xFFF8 - The function ID
18871 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18872 	 * * 0xFFFD - Reserved for user-space HWRM interface
18873 	 * * 0xFFFF - HWRM
18990 	 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
18993 	 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
19019 	#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP	UINT32_C(0x1)
19024 	#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ	UINT32_C(0x2)
19029 	#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ	UINT32_C(0x4)
19034 	#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC	UINT32_C(0x8)
19039 	#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT	UINT32_C(0x10)
19044 	#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV	UINT32_C(0x20)
19049 	#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_TKC	UINT32_C(0x40)
19054 	#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_RKC	UINT32_C(0x80)
19146 	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK	UINT32_C(0xf)
19147 	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT	0
19149 		#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0	UINT32_C(0x0)
19151 		#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1	UINT32_C(0x1)
19156 		#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2	UINT32_C(0x2)
19159 	#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK  UINT32_C(0xf0)
19162 		#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19164 		#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19166 		#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19168 		#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19170 		#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19172 		#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19204 	 * * 0x0-0xFFF8 - The function ID
19205 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19206 	 * * 0xFFFD - Reserved for user-space HWRM interface
19207 	 * * 0xFFFF - HWRM
19224 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE		UINT32_C(0x1)
19229 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT	UINT32_C(0x2)
19235 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP		UINT32_C(0x1)
19240 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ		UINT32_C(0x2)
19245 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ		UINT32_C(0x4)
19250 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC		UINT32_C(0x8)
19255 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT		UINT32_C(0x10)
19260 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP	UINT32_C(0x20)
19265 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0	UINT32_C(0x40)
19270 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1	UINT32_C(0x80)
19275 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2	UINT32_C(0x100)
19280 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3	UINT32_C(0x200)
19285 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4	UINT32_C(0x400)
19290 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5	UINT32_C(0x800)
19295 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6	UINT32_C(0x1000)
19300 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7	UINT32_C(0x2000)
19305 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV		UINT32_C(0x4000)
19310 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM		UINT32_C(0x8000)
19315 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8	UINT32_C(0x10000)
19320 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9	UINT32_C(0x20000)
19325 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10	UINT32_C(0x40000)
19330 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TKC		UINT32_C(0x80000)
19335 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC		UINT32_C(0x100000)
19340 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP_FAST_QPMD	UINT32_C(0x200000)
19344 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK	UINT32_C(0xf)
19345 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT	0
19347 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0	UINT32_C(0x0)
19349 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1	UINT32_C(0x1)
19354 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2	UINT32_C(0x2)
19357 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK  UINT32_C(0xf0)
19360 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19362 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19364 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19366 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19368 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19370 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19375 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK	UINT32_C(0xf)
19376 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT	0
19378 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0	UINT32_C(0x0)
19380 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1	UINT32_C(0x1)
19385 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2	UINT32_C(0x2)
19388 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK  UINT32_C(0xf0)
19391 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19393 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19395 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19397 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19399 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19401 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19406 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK	UINT32_C(0xf)
19407 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT	0
19409 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0	UINT32_C(0x0)
19411 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1	UINT32_C(0x1)
19416 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2	UINT32_C(0x2)
19419 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK  UINT32_C(0xf0)
19422 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19424 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19426 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19428 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19430 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19432 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19437 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK	UINT32_C(0xf)
19438 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT	0
19440 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0	UINT32_C(0x0)
19442 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1	UINT32_C(0x1)
19447 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2	UINT32_C(0x2)
19450 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK  UINT32_C(0xf0)
19453 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19455 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19457 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19459 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19461 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19463 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19468 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK	UINT32_C(0xf)
19469 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT	0
19471 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0	UINT32_C(0x0)
19473 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1	UINT32_C(0x1)
19478 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2	UINT32_C(0x2)
19481 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK  UINT32_C(0xf0)
19484 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19486 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19488 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19490 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19492 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19494 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19499 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK	UINT32_C(0xf)
19500 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT	0
19502 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0	UINT32_C(0x0)
19504 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1	UINT32_C(0x1)
19509 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2	UINT32_C(0x2)
19512 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK  UINT32_C(0xf0)
19515 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19517 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19519 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19521 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19523 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19525 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19527 	/* TQM ring 0 page size and level. */
19529 	/* TQM ring 0 PBL indirect levels. */
19530 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK	UINT32_C(0xf)
19531 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT	0
19533 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0	UINT32_C(0x0)
19535 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1	UINT32_C(0x1)
19540 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2	UINT32_C(0x2)
19542 	/* TQM ring 0 page size. */
19543 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK  UINT32_C(0xf0)
19546 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19548 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19550 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19552 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19554 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19556 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19561 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK	UINT32_C(0xf)
19562 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT	0
19564 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0	UINT32_C(0x0)
19566 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1	UINT32_C(0x1)
19571 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2	UINT32_C(0x2)
19574 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK  UINT32_C(0xf0)
19577 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19579 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19581 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19583 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19585 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19587 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19592 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK	UINT32_C(0xf)
19593 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT	0
19595 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0	UINT32_C(0x0)
19597 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1	UINT32_C(0x1)
19602 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2	UINT32_C(0x2)
19605 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK  UINT32_C(0xf0)
19608 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19610 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19612 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19614 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19616 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19618 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19623 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK	UINT32_C(0xf)
19624 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT	0
19626 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0	UINT32_C(0x0)
19628 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1	UINT32_C(0x1)
19633 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2	UINT32_C(0x2)
19636 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK  UINT32_C(0xf0)
19639 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19641 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19643 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19645 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19647 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19649 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19654 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK	UINT32_C(0xf)
19655 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT	0
19657 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0	UINT32_C(0x0)
19659 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1	UINT32_C(0x1)
19664 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2	UINT32_C(0x2)
19667 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK  UINT32_C(0xf0)
19670 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19672 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19674 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19676 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19678 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19680 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19685 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK	UINT32_C(0xf)
19686 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT	0
19688 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0	UINT32_C(0x0)
19690 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1	UINT32_C(0x1)
19695 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2	UINT32_C(0x2)
19698 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK  UINT32_C(0xf0)
19701 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19703 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19705 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19707 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19709 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19711 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19716 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK	UINT32_C(0xf)
19717 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT	0
19719 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0	UINT32_C(0x0)
19721 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1	UINT32_C(0x1)
19726 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2	UINT32_C(0x2)
19729 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK  UINT32_C(0xf0)
19732 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19734 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19736 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19738 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19740 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19742 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19747 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK	UINT32_C(0xf)
19748 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT	0
19750 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0	UINT32_C(0x0)
19752 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1	UINT32_C(0x1)
19757 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2	UINT32_C(0x2)
19760 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK  UINT32_C(0xf0)
19763 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19765 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19767 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19769 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19771 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19773 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19778 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK	UINT32_C(0xf)
19779 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT	0
19781 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0	UINT32_C(0x0)
19783 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1	UINT32_C(0x1)
19788 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2	UINT32_C(0x2)
19791 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK  UINT32_C(0xf0)
19794 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19796 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19798 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19800 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19802 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19804 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19809 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK	UINT32_C(0xf)
19810 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT	0
19812 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0	UINT32_C(0x0)
19814 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1	UINT32_C(0x1)
19819 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2	UINT32_C(0x2)
19822 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK  UINT32_C(0xf0)
19825 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
19827 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
19829 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
19831 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
19833 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
19835 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
19849 	/* TQM ring 0 page directory. */
19898 	 * Number of TQM ring 0 entries.
20010 	 * represents the `mr_num_entries` and bits `[15:0]` represents
20049 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK	UINT32_C(0xf)
20050 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT	0
20052 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0	UINT32_C(0x0)
20054 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1	UINT32_C(0x1)
20059 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2	UINT32_C(0x2)
20062 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK  UINT32_C(0xf0)
20065 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20067 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20069 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20071 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20073 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20075 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20085 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK	UINT32_C(0xf)
20086 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT	0
20088 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0	UINT32_C(0x0)
20090 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1	UINT32_C(0x1)
20095 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2	UINT32_C(0x2)
20098 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK  UINT32_C(0xf0)
20101 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20103 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20105 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20107 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20109 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20111 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20121 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK	UINT32_C(0xf)
20122 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT	0
20124 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0	UINT32_C(0x0)
20126 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1	UINT32_C(0x1)
20131 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2	UINT32_C(0x2)
20134 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK  UINT32_C(0xf0)
20137 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20139 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20141 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20143 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20145 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20147 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20169 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_MASK	UINT32_C(0xf)
20170 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_SFT	0
20172 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0	UINT32_C(0x0)
20174 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1	UINT32_C(0x1)
20179 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2	UINT32_C(0x2)
20182 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_MASK  UINT32_C(0xf0)
20185 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20187 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20189 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20191 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20193 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20195 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20200 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_MASK	UINT32_C(0xf)
20201 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_SFT	0
20203 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_0	UINT32_C(0x0)
20205 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_1	UINT32_C(0x1)
20210 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2	UINT32_C(0x2)
20213 	#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_MASK  UINT32_C(0xf0)
20216 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20218 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20220 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20222 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20224 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20226 		#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20280 	 * * 0x0-0xFFF8 - The function ID
20281 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20282 	 * * 0xFFFD - Reserved for user-space HWRM interface
20283 	 * * 0xFFFF - HWRM
20313 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE		UINT32_C(0x1)
20318 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT	UINT32_C(0x2)
20324 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP		UINT32_C(0x1)
20329 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ		UINT32_C(0x2)
20334 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ		UINT32_C(0x4)
20339 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC		UINT32_C(0x8)
20344 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT		UINT32_C(0x10)
20349 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP	UINT32_C(0x20)
20354 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0	UINT32_C(0x40)
20359 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1	UINT32_C(0x80)
20364 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2	UINT32_C(0x100)
20369 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3	UINT32_C(0x200)
20374 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4	UINT32_C(0x400)
20379 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5	UINT32_C(0x800)
20384 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6	UINT32_C(0x1000)
20389 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7	UINT32_C(0x2000)
20394 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV		UINT32_C(0x4000)
20399 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM		UINT32_C(0x8000)
20404 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8	UINT32_C(0x10000)
20409 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9	UINT32_C(0x20000)
20414 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10	UINT32_C(0x40000)
20419 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TKC		UINT32_C(0x80000)
20424 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC		UINT32_C(0x100000)
20429 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP_FAST_QPMD	UINT32_C(0x200000)
20433 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK	UINT32_C(0xf)
20434 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT	0
20436 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0	UINT32_C(0x0)
20438 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1	UINT32_C(0x1)
20443 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2	UINT32_C(0x2)
20446 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK  UINT32_C(0xf0)
20449 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20451 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20453 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20455 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20457 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20459 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20464 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK	UINT32_C(0xf)
20465 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT	0
20467 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0	UINT32_C(0x0)
20469 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1	UINT32_C(0x1)
20474 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2	UINT32_C(0x2)
20477 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK  UINT32_C(0xf0)
20480 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20482 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20484 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20486 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20488 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20490 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20495 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK	UINT32_C(0xf)
20496 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT	0
20498 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0	UINT32_C(0x0)
20500 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1	UINT32_C(0x1)
20505 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2	UINT32_C(0x2)
20508 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK  UINT32_C(0xf0)
20511 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20513 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20515 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20517 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20519 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20521 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20526 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK	UINT32_C(0xf)
20527 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT	0
20529 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0	UINT32_C(0x0)
20531 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1	UINT32_C(0x1)
20536 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2	UINT32_C(0x2)
20539 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK  UINT32_C(0xf0)
20542 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20544 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20546 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20548 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20550 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20552 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20557 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK	UINT32_C(0xf)
20558 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT	0
20560 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0	UINT32_C(0x0)
20562 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1	UINT32_C(0x1)
20567 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2	UINT32_C(0x2)
20570 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK  UINT32_C(0xf0)
20573 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20575 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20577 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20579 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20581 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20583 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20588 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK	UINT32_C(0xf)
20589 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT	0
20591 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0	UINT32_C(0x0)
20593 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1	UINT32_C(0x1)
20598 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2	UINT32_C(0x2)
20601 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK  UINT32_C(0xf0)
20604 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20606 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20608 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20610 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20612 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20614 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20616 	/* TQM ring 0 page size and level. */
20618 	/* TQM ring 0 PBL indirect levels. */
20619 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK	UINT32_C(0xf)
20620 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT	0
20622 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0	UINT32_C(0x0)
20624 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1	UINT32_C(0x1)
20629 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2	UINT32_C(0x2)
20631 	/* TQM ring 0 page size. */
20632 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK  UINT32_C(0xf0)
20635 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20637 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20639 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20641 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20643 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20645 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20650 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK	UINT32_C(0xf)
20651 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT	0
20653 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0	UINT32_C(0x0)
20655 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1	UINT32_C(0x1)
20660 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2	UINT32_C(0x2)
20663 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK  UINT32_C(0xf0)
20666 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20668 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20670 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20672 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20674 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20676 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20681 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK	UINT32_C(0xf)
20682 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT	0
20684 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0	UINT32_C(0x0)
20686 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1	UINT32_C(0x1)
20691 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2	UINT32_C(0x2)
20694 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK  UINT32_C(0xf0)
20697 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20699 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20701 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20703 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20705 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20707 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20712 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK	UINT32_C(0xf)
20713 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT	0
20715 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0	UINT32_C(0x0)
20717 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1	UINT32_C(0x1)
20722 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2	UINT32_C(0x2)
20725 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK  UINT32_C(0xf0)
20728 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20730 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20732 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20734 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20736 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20738 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20743 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK	UINT32_C(0xf)
20744 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT	0
20746 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0	UINT32_C(0x0)
20748 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1	UINT32_C(0x1)
20753 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2	UINT32_C(0x2)
20756 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK  UINT32_C(0xf0)
20759 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20761 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20763 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20765 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20767 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20769 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20774 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK	UINT32_C(0xf)
20775 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT	0
20777 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0	UINT32_C(0x0)
20779 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1	UINT32_C(0x1)
20784 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2	UINT32_C(0x2)
20787 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK  UINT32_C(0xf0)
20790 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20792 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20794 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20796 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20798 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20800 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20805 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK	UINT32_C(0xf)
20806 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT	0
20808 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0	UINT32_C(0x0)
20810 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1	UINT32_C(0x1)
20815 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2	UINT32_C(0x2)
20818 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK  UINT32_C(0xf0)
20821 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20823 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20825 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20827 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20829 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20831 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20836 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK	UINT32_C(0xf)
20837 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT	0
20839 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0	UINT32_C(0x0)
20841 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1	UINT32_C(0x1)
20846 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2	UINT32_C(0x2)
20849 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK  UINT32_C(0xf0)
20852 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20854 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20856 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20858 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20860 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20862 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20867 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK	UINT32_C(0xf)
20868 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT	0
20870 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0	UINT32_C(0x0)
20872 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1	UINT32_C(0x1)
20877 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2	UINT32_C(0x2)
20880 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK  UINT32_C(0xf0)
20883 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20885 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20887 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20889 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20891 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20893 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20898 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK	UINT32_C(0xf)
20899 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT	0
20901 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0	UINT32_C(0x0)
20903 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1	UINT32_C(0x1)
20908 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2	UINT32_C(0x2)
20911 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK  UINT32_C(0xf0)
20914 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
20916 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
20918 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
20920 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
20922 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
20924 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
20938 	/* TQM ring 0 page directory. */
20980 	/* Number of TQM ring 0 entries. */
21005 	 * represents the `mr_num_entries` and bits `[15:0]` represents
21016 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK	UINT32_C(0xf)
21017 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT	0
21019 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0	UINT32_C(0x0)
21021 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1	UINT32_C(0x1)
21026 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2	UINT32_C(0x2)
21029 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK  UINT32_C(0xf0)
21032 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
21034 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
21036 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
21038 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
21040 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
21042 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
21052 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK	UINT32_C(0xf)
21053 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT	0
21055 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0	UINT32_C(0x0)
21057 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1	UINT32_C(0x1)
21062 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2	UINT32_C(0x2)
21065 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK  UINT32_C(0xf0)
21068 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
21070 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
21072 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
21074 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
21076 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
21078 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
21088 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK	UINT32_C(0xf)
21089 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT	0
21091 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0	UINT32_C(0x0)
21093 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1	UINT32_C(0x1)
21098 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2	UINT32_C(0x2)
21101 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK  UINT32_C(0xf0)
21104 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
21106 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
21108 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
21110 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
21112 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
21114 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
21132 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_MASK	UINT32_C(0xf)
21133 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_SFT	0
21135 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_0	UINT32_C(0x0)
21137 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_1	UINT32_C(0x1)
21142 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2	UINT32_C(0x2)
21145 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_MASK  UINT32_C(0xf0)
21148 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
21150 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
21152 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
21154 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
21156 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
21158 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
21163 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_MASK	UINT32_C(0xf)
21164 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_SFT	0
21166 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_0	UINT32_C(0x0)
21168 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_1	UINT32_C(0x1)
21173 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2	UINT32_C(0x2)
21176 	#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_MASK  UINT32_C(0xf0)
21179 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
21181 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
21183 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
21185 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
21187 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
21189 		#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
21231 	 * * 0x0-0xFFF8 - The function ID
21232 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21233 	 * * 0xFFFD - Reserved for user-space HWRM interface
21234 	 * * 0xFFFF - HWRM
21263 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST	UINT32_C(0x1)
21268 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU	UINT32_C(0x2)
21312 	 * A value of 0xFFFF-FFFF indicates this register does not exist.
21316 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK	UINT32_C(0x3)
21317 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT	0
21319 	 * If value is 0, this register is located in PCIe config space.
21323 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG  UINT32_C(0x0)
21329 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC	UINT32_C(0x1)
21335 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0	UINT32_C(0x2)
21342 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1	UINT32_C(0x3)
21345 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK	UINT32_C(0xfffffffc)
21351 	 * A value of 0xFFFF-FFFF indicates this register does not exist.
21355 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK	UINT32_C(0x3)
21356 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT	0
21358 	 * If value is 0, this register is located in PCIe config space.
21362 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG  UINT32_C(0x0)
21368 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC	UINT32_C(0x1)
21374 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0	UINT32_C(0x2)
21380 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1	UINT32_C(0x3)
21383 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK	UINT32_C(0xfffffffc)
21389 	 * A value of 0xFFFF-FFFF indicates this register does not exist.
21393 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK	UINT32_C(0x3)
21394 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT	0
21396 	 * If value is 0, this register is located in PCIe config space.
21400 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG  UINT32_C(0x0)
21406 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC	UINT32_C(0x1)
21412 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0	UINT32_C(0x2)
21418 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1	UINT32_C(0x3)
21421 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK	UINT32_C(0xfffffffc)
21427 	 * A value of 0xFFFF-FFFF indicates this register does not exist.
21431 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK	UINT32_C(0x3)
21432 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT	0
21434 	 * If value is 0, this register is located in PCIe config space.
21438 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG  UINT32_C(0x0)
21444 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC	UINT32_C(0x1)
21450 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0	UINT32_C(0x2)
21456 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1	UINT32_C(0x3)
21459 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK	UINT32_C(0xfffffffc)
21477 	 * A value of 0xFFFF-FFFF indicates this register does not exist.
21481 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK	UINT32_C(0x3)
21482 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT	0
21484 	 * If value is 0, this register is located in PCIe config space.
21488 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG  UINT32_C(0x0)
21494 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC	UINT32_C(0x1)
21500 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0	UINT32_C(0x2)
21506 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1	UINT32_C(0x3)
21509 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK	UINT32_C(0xfffffffc)
21526 	 * A value of 0xFFFF-FFFF indicates this register does not exist.
21530 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK	UINT32_C(0x3)
21531 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT	0
21533 	 * If value is 0, this register is located in PCIe config space.
21537 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG  UINT32_C(0x0)
21543 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC	UINT32_C(0x1)
21549 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0	UINT32_C(0x2)
21555 		#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1	UINT32_C(0x3)
21558 	#define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK	UINT32_C(0xfffffffc)
21595 	 * * 0x0-0xFFF8 - The function ID
21596 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21597 	 * * 0xFFFD - Reserved for user-space HWRM interface
21598 	 * * 0xFFFF - HWRM
21657 	 * * 0x0-0xFFF8 - The function ID
21658 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21659 	 * * 0xFFFD - Reserved for user-space HWRM interface
21660 	 * * 0xFFFF - HWRM
21692 	 * When this bit is '1', TSIO pin 0 is enabled.
21693 	 * When this bit is '0', TSIO pin 0 is disabled.
21695 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED	UINT32_C(0x1)
21698 	 * When this bit is '0', TSIO pin 1 is disabled.
21700 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED	UINT32_C(0x2)
21703 	 * When this bit is '0', TSIO pin 2 is disabled.
21705 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED	UINT32_C(0x4)
21708 	 * When this bit is '0', TSIO pin 3 is disabled.
21710 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED	UINT32_C(0x8)
21711 	/* Type of function for Pin #0. */
21714 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE	UINT32_C(0x0)
21716 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN   UINT32_C(0x1)
21718 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT  UINT32_C(0x2)
21720 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN  UINT32_C(0x3)
21722 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
21727 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE	UINT32_C(0x0)
21729 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN   UINT32_C(0x1)
21731 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT  UINT32_C(0x2)
21733 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN  UINT32_C(0x3)
21735 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
21740 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE			UINT32_C(0x0)
21742 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN			UINT32_C(0x1)
21744 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT		UINT32_C(0x2)
21746 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN		UINT32_C(0x3)
21748 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT		UINT32_C(0x4)
21750 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT   UINT32_C(0x5)
21752 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
21757 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE			UINT32_C(0x0)
21759 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN			UINT32_C(0x1)
21761 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT		UINT32_C(0x2)
21763 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN		UINT32_C(0x3)
21765 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT		UINT32_C(0x4)
21767 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT   UINT32_C(0x5)
21769 	#define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
21805 	 * * 0x0-0xFFF8 - The function ID
21806 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21807 	 * * 0xFFFD - Reserved for user-space HWRM interface
21808 	 * * 0xFFFF - HWRM
21823 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE	UINT32_C(0x1)
21828 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE	UINT32_C(0x2)
21833 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE	UINT32_C(0x4)
21838 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE	UINT32_C(0x8)
21843 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE	UINT32_C(0x10)
21848 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE	UINT32_C(0x20)
21853 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE	UINT32_C(0x40)
21858 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE	UINT32_C(0x80)
21859 	/* Enable or disable functionality of Pin #0. */
21862 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0)
21864 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED  UINT32_C(0x1)
21866 	/* Configure function for TSIO pin#0. */
21869 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE	UINT32_C(0x0)
21871 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN   UINT32_C(0x1)
21873 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT  UINT32_C(0x2)
21875 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN  UINT32_C(0x3)
21877 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
21882 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0)
21884 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED  UINT32_C(0x1)
21889 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE	UINT32_C(0x0)
21891 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN   UINT32_C(0x1)
21893 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT  UINT32_C(0x2)
21895 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN  UINT32_C(0x3)
21897 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
21902 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0)
21904 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED  UINT32_C(0x1)
21909 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE			UINT32_C(0x0)
21911 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN			UINT32_C(0x1)
21913 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT		UINT32_C(0x2)
21915 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN		UINT32_C(0x3)
21917 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT		UINT32_C(0x4)
21919 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT   UINT32_C(0x5)
21921 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
21926 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0)
21928 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED  UINT32_C(0x1)
21933 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE			UINT32_C(0x0)
21935 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN			UINT32_C(0x1)
21937 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT		UINT32_C(0x2)
21939 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN		UINT32_C(0x3)
21941 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT		UINT32_C(0x4)
21943 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT   UINT32_C(0x5)
21945 	#define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
21995 	 * * 0x0-0xFFF8 - The function ID
21996 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21997 	 * * 0xFFFD - Reserved for user-space HWRM interface
21998 	 * * 0xFFFF - HWRM
22013 	#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT		UINT32_C(0x1)
22018 	#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE	UINT32_C(0x2)
22023 	#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE	UINT32_C(0x4)
22028 	#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD	UINT32_C(0x8)
22033 	#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP	UINT32_C(0x10)
22038 	#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE	UINT32_C(0x20)
22040 	#define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_SET_TIME		UINT32_C(0x40)
22049 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL	UINT32_C(0x1)
22054 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL	UINT32_C(0x2)
22061 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE	UINT32_C(0x0)
22062 	/* TSIO Pin #0 is selected as source signal. */
22063 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0  UINT32_C(0x1)
22065 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1  UINT32_C(0x2)
22067 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2  UINT32_C(0x3)
22069 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3  UINT32_C(0x4)
22070 	/* Port #0 is selected as source signal. */
22071 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0  UINT32_C(0x5)
22073 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1  UINT32_C(0x6)
22075 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2  UINT32_C(0x7)
22077 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3  UINT32_C(0x8)
22079 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID UINT32_C(0xff)
22087 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE UINT32_C(0x0)
22089 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K   UINT32_C(0x1)
22091 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K   UINT32_C(0x2)
22093 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M  UINT32_C(0x3)
22095 	#define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_25M  UINT32_C(0x4)
22179 	 * * 0x0-0xFFF8 - The function ID
22180 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22181 	 * * 0xFFFD - Reserved for user-space HWRM interface
22182 	 * * 0xFFFF - HWRM
22194 	#define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME	UINT32_C(0x1)
22196 	#define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME	UINT32_C(0x2)
22266 	 * * 0x0-0xFFF8 - The function ID
22267 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22268 	 * * 0xFFFD - Reserved for user-space HWRM interface
22269 	 * * 0xFFFF - HWRM
22284 	#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID	UINT32_C(0x1)
22289 	#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID	UINT32_C(0x2)
22294 	#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE	UINT32_C(0x4)
22299 	#define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER	UINT32_C(0x8)
22327 	#define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH  UINT32_C(0x0)
22333 	#define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL	UINT32_C(0x1)
22339 	#define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2)
22346 	 * 0 - Failover timer is automatically selected based on the last
22353 	 * 0xFFFFFFFF - If driver specifies this value, then failover never
22410 	 * * 0x0-0xFFF8 - The function ID
22411 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22412 	 * * 0xFFFD - Reserved for user-space HWRM interface
22413 	 * * 0xFFFF - HWRM
22507 	 * * 0x0-0xFFF8 - The function ID
22508 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22509 	 * * 0xFFFD - Reserved for user-space HWRM interface
22510 	 * * 0xFFFF - HWRM
22582 	 * * 0x0-0xFFF8 - The function ID
22583 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22584 	 * * 0xFFFD - Reserved for user-space HWRM interface
22585 	 * * 0xFFFF - HWRM
22648 	 * * 0x0-0xFFF8 - The function ID
22649 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22650 	 * * 0xFFFD - Reserved for user-space HWRM interface
22651 	 * * 0xFFFF - HWRM
22678 	 * with index 0, registered rates are populated in the initial entries
22679 	 * of the array, remaining entries are filled up with 0.
22716 	 * * 0x0-0xFFF8 - The function ID
22717 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22718 	 * * 0xFFFD - Reserved for user-space HWRM interface
22719 	 * * 0xFFFF - HWRM
22755 	#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX	UINT32_C(0x0)
22757 	#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX	UINT32_C(0x1)
22759 	#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_TX UINT32_C(0x2)
22761 	#define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3)
22804 	#define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS	UINT32_C(0x1)
22845 	 * * 0x0-0xFFF8 - The function ID
22846 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22847 	 * * 0xFFFD - Reserved for user-space HWRM interface
22848 	 * * 0xFFFF - HWRM
22863 	#define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_TX	UINT32_C(0x0)
22865 	#define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_RX	UINT32_C(0x1)
22867 	#define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_TX UINT32_C(0x2)
22869 	#define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3)
22933 	 * * 0x0-0xFFF8 - The function ID
22934 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22935 	 * * 0xFFFD - Reserved for user-space HWRM interface
22936 	 * * 0xFFFF - HWRM
22949 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP		UINT32_C(0x0)
22951 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ		UINT32_C(0x1)
22953 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ		UINT32_C(0x2)
22955 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC		UINT32_C(0x3)
22957 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT		UINT32_C(0x4)
22959 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING	UINT32_C(0x5)
22961 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING	UINT32_C(0x6)
22963 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV		UINT32_C(0xe)
22965 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM		UINT32_C(0xf)
22967 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TX_CK		UINT32_C(0x13)
22969 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RX_CK		UINT32_C(0x14)
22971 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING	UINT32_C(0x15)
22973 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW	UINT32_C(0x16)
22975 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW	UINT32_C(0x17)
22977 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW	UINT32_C(0x18)
22979 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW	UINT32_C(0x19)
22981 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TBL_SCOPE	UINT32_C(0x1c)
22983 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_XID_PARTITION	UINT32_C(0x1d)
22985 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT_TRACE	UINT32_C(0x1e)
22987 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT2_TRACE	UINT32_C(0x1f)
22989 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT_TRACE	UINT32_C(0x20)
22991 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT2_TRACE	UINT32_C(0x21)
22993 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RIGP0_TRACE	UINT32_C(0x22)
22995 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_L2_HWRM_TRACE	UINT32_C(0x23)
22997 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE	UINT32_C(0x24)
22999 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TTX_PACING_TQM_RING UINT32_C(0x25)
23000 	/* Context Accelerator CPU 0 trace. */
23001 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CA0_TRACE	UINT32_C(0x26)
23003 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CA1_TRACE	UINT32_C(0x27)
23005 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CA2_TRACE	UINT32_C(0x28)
23007 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RIGP1_TRACE	UINT32_C(0x29)
23009 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID		UINT32_C(0xffff)
23013 	 * which means "0" indicates the first instance. For backing
23014 	 * stores with single instance only, leave this field to 0.
23017 	 *	TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
23020 	 *	RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)
23023 	 *	TX_CK (0), RX_CK (1)
23034 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE	UINT32_C(0x1)
23043 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_CFG_ALL_DONE	UINT32_C(0x2)
23057 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_EXTEND	UINT32_C(0x4)
23067 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_MASK  UINT32_C(0xf)
23068 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_SFT   0
23070 		#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_0   UINT32_C(0x0)
23072 		#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_1   UINT32_C(0x1)
23077 		#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2   UINT32_C(0x2)
23080 	#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_MASK  UINT32_C(0xf0)
23083 		#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_4K   (UINT32_C(0x0) << 4)
23085 		#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8K   (UINT32_C(0x1) << 4)
23087 		#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_64K  (UINT32_C(0x2) << 4)
23089 		#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_2M   (UINT32_C(0x3) << 4)
23091 		#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8M   (UINT32_C(0x4) << 4)
23093 		#define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G   (UINT32_C(0x5) << 4)
23100 	 * |   0   | None of the split entries has valid data.	|
23108 	 * Split entry #0. Note that the four split entries (as a group)
23134        #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_ENABLES_NEXT_BS_OFFSET     UINT32_C(0x1)
23191 	 * * 0x0-0xFFF8 - The function ID
23192 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23193 	 * * 0xFFFD - Reserved for user-space HWRM interface
23194 	 * * 0xFFFF - HWRM
23207 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP		UINT32_C(0x0)
23209 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ		UINT32_C(0x1)
23211 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ		UINT32_C(0x2)
23213 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC		UINT32_C(0x3)
23215 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT		UINT32_C(0x4)
23217 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING	UINT32_C(0x5)
23219 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING	UINT32_C(0x6)
23221 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV		UINT32_C(0xe)
23223 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM		UINT32_C(0xf)
23225 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TX_CK		UINT32_C(0x13)
23227 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RX_CK		UINT32_C(0x14)
23229 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING	UINT32_C(0x15)
23231 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SQ_DB_SHADOW	UINT32_C(0x16)
23233 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RQ_DB_SHADOW	UINT32_C(0x17)
23235 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ_DB_SHADOW	UINT32_C(0x18)
23237 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW	UINT32_C(0x19)
23239 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TBL_SCOPE	UINT32_C(0x1c)
23241 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_XID_PARTITION_TABLE UINT32_C(0x1d)
23243 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT_TRACE	UINT32_C(0x1e)
23245 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT2_TRACE	UINT32_C(0x1f)
23247 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT_TRACE	UINT32_C(0x20)
23249 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT2_TRACE	UINT32_C(0x21)
23251 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RIGP0_TRACE	UINT32_C(0x22)
23253 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_L2_HWRM_TRACE	UINT32_C(0x23)
23255 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE	UINT32_C(0x24)
23257 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TTX_PACING_TQM_RING UINT32_C(0x25)
23258 	/* Context Accelerator CPU 0 trace. */
23259 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CA0_TRACE	UINT32_C(0x26)
23261 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CA1_TRACE	UINT32_C(0x27)
23263 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CA2_TRACE	UINT32_C(0x28)
23265 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RIGP1_TRACE	UINT32_C(0x29)
23267 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID		UINT32_C(0xffff)
23271 	 * which means "0" indicates the first instance. For backing
23272 	 * stores with single instance only, leave this field to 0.
23275 	 *	TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
23278 	 *	RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)
23281 	 *	TX_CK (0), RX_CK (1)
23301 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP		UINT32_C(0x0)
23303 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ		UINT32_C(0x1)
23305 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ		UINT32_C(0x2)
23307 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC		UINT32_C(0x3)
23309 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT		UINT32_C(0x4)
23311 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING	UINT32_C(0x5)
23313 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING	UINT32_C(0x6)
23315 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV		UINT32_C(0xe)
23317 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM		UINT32_C(0xf)
23319 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TX_CK		UINT32_C(0x13)
23321 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RX_CK		UINT32_C(0x14)
23323 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING	UINT32_C(0x15)
23325 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TBL_SCOPE	UINT32_C(0x1c)
23327 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_XID_PARTITION	UINT32_C(0x1d)
23329 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT_TRACE	UINT32_C(0x1e)
23331 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT2_TRACE	UINT32_C(0x1f)
23333 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT_TRACE	UINT32_C(0x20)
23335 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT2_TRACE	UINT32_C(0x21)
23337 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RIGP0_TRACE	UINT32_C(0x22)
23339 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_L2_HWRM_TRACE	UINT32_C(0x23)
23341 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE	UINT32_C(0x24)
23343 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TTX_PACING_TQM_RING UINT32_C(0x25)
23344 	/* Context Accelerator CPU 0 trace. */
23345 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CA0_TRACE	UINT32_C(0x26)
23347 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CA1_TRACE	UINT32_C(0x27)
23349 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CA2_TRACE	UINT32_C(0x28)
23351 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RIGP1_TRACE	UINT32_C(0x29)
23353 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID		UINT32_C(0xffff)
23357 	 * which means "0" indicates the first instance. For backing
23358 	 * stores with single instance only, leave this field to 0.
23361 	 *	TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
23364 	 *	RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)
23367 	 *	TX_CK (0), RX_CK (1)
23379 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_MASK  UINT32_C(0xf)
23380 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_SFT   0
23382 		#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_0   UINT32_C(0x0)
23384 		#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_1   UINT32_C(0x1)
23389 		#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2   UINT32_C(0x2)
23392 	#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_MASK  UINT32_C(0xf0)
23395 		#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_4K   (UINT32_C(0x0) << 4)
23397 		#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8K   (UINT32_C(0x1) << 4)
23399 		#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_64K  (UINT32_C(0x2) << 4)
23401 		#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_2M   (UINT32_C(0x3) << 4)
23403 		#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8M   (UINT32_C(0x4) << 4)
23405 		#define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G   (UINT32_C(0x5) << 4)
23412 	 * |   0   | None of the split entries has valid data.	|
23421 	 * Split entry #0. Note that the four split entries (as a group)
23564 	 * * 0x0-0xFFF8 - The function ID
23565 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23566 	 * * 0xFFFD - Reserved for user-space HWRM interface
23567 	 * * 0xFFFF - HWRM
23580 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QP		UINT32_C(0x0)
23582 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ		UINT32_C(0x1)
23584 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ		UINT32_C(0x2)
23586 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_VNIC		UINT32_C(0x3)
23588 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_STAT		UINT32_C(0x4)
23590 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SP_TQM_RING	UINT32_C(0x5)
23592 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_FP_TQM_RING	UINT32_C(0x6)
23594 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MRAV		UINT32_C(0xe)
23596 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM		UINT32_C(0xf)
23598 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TX_CK		UINT32_C(0x13)
23600 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RX_CK		UINT32_C(0x14)
23602 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING	UINT32_C(0x15)
23604 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SQ_DB_SHADOW	UINT32_C(0x16)
23606 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RQ_DB_SHADOW	UINT32_C(0x17)
23608 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ_DB_SHADOW	UINT32_C(0x18)
23610 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW	UINT32_C(0x19)
23612 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TBL_SCOPE	UINT32_C(0x1c)
23614 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_XID_PARTITION	UINT32_C(0x1d)
23616 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT_TRACE	UINT32_C(0x1e)
23618 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT2_TRACE	UINT32_C(0x1f)
23620 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT_TRACE	UINT32_C(0x20)
23622 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT2_TRACE	UINT32_C(0x21)
23624 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RIGP0_TRACE	UINT32_C(0x22)
23626 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_L2_HWRM_TRACE	UINT32_C(0x23)
23628 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_ROCE_HWRM_TRACE	UINT32_C(0x24)
23630 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TTX_PACING_TQM_RING UINT32_C(0x25)
23631 	/* Context Accelerator CPU 0 trace. */
23632 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CA0_TRACE	UINT32_C(0x26)
23634 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CA1_TRACE	UINT32_C(0x27)
23636 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CA2_TRACE	UINT32_C(0x28)
23638 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RIGP1_TRACE	UINT32_C(0x29)
23640 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID		UINT32_C(0xffff)
23659 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QP		UINT32_C(0x0)
23661 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ		UINT32_C(0x1)
23663 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ		UINT32_C(0x2)
23665 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_VNIC		UINT32_C(0x3)
23667 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_STAT		UINT32_C(0x4)
23669 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SP_TQM_RING	UINT32_C(0x5)
23671 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_FP_TQM_RING	UINT32_C(0x6)
23673 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MRAV		UINT32_C(0xe)
23675 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM		UINT32_C(0xf)
23677 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TX_CK		UINT32_C(0x13)
23679 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RX_CK		UINT32_C(0x14)
23681 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING	UINT32_C(0x15)
23683 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW	UINT32_C(0x16)
23685 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW	UINT32_C(0x17)
23687 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW	UINT32_C(0x18)
23689 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW	UINT32_C(0x19)
23691 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TBL_SCOPE	UINT32_C(0x1c)
23693 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_XID_PARTITION	UINT32_C(0x1d)
23695 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT_TRACE	UINT32_C(0x1e)
23697 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT2_TRACE	UINT32_C(0x1f)
23699 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT_TRACE	UINT32_C(0x20)
23701 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT2_TRACE	UINT32_C(0x21)
23703 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RIGP0_TRACE	UINT32_C(0x22)
23705 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_L2_HWRM_TRACE	UINT32_C(0x23)
23707 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE	UINT32_C(0x24)
23709 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TTX_PACING_TQM_RING UINT32_C(0x25)
23710 	/* Context Accelerator CPU 0 trace. */
23711 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CA0_TRACE	UINT32_C(0x26)
23713 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CA1_TRACE	UINT32_C(0x27)
23715 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CA2_TRACE	UINT32_C(0x28)
23717 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RIGP1_TRACE	UINT32_C(0x29)
23719 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID		UINT32_C(0xffff)
23729 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT		UINT32_C(0x1)
23731 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID			UINT32_C(0x2)
23737 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_DRIVER_MANAGED_MEMORY	UINT32_C(0x4)
23754 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC	UINT32_C(0x8)
23755 …#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_FW_DBG_TRACE                      UINT32_C(0…
23757 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_FW_BIN_DBG_TRACE          UINT32_C(0x20)
23759 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_NEXT_BS_OFFSET            UINT32_C(0x40)
23765 	 *	TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
23768 	 *	RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)
23771 	 *	TX_CK (0), RX_CK (1)
23789 	 * this field with "0".
23798 	 * TQM rings. If not applicable, leave this field with "0".
23811 	 * |   0   | None of the split entries has valid data.	|
23831 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT	UINT32_C(0x1)
23836 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT	UINT32_C(0x2)
23841 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT	UINT32_C(0x4)
23846 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT	UINT32_C(0x8)
23847 	#define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_UNUSED_MASK		UINT32_C(0xf0)
23850 	 * Split entry #0. Note that the four split entries (as a group)
23905 	 * * 0x0-0xFFF8 - The function ID
23906 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23907 	 * * 0xFFFD - Reserved for user-space HWRM interface
23908 	 * * 0xFFFF - HWRM
23924 	#define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_ENABLE	UINT32_C(0x1)
23926 	#define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_DISABLE	UINT32_C(0x2)
23933 	#define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PRIMARY_NQ_ID_VALID	UINT32_C(0x1)
23938 	#define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PACING_THRESHOLD_VALID	UINT32_C(0x2)
23998 	 * * 0x0-0xFFF8 - The function ID
23999 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24000 	 * * 0xFFFD - Reserved for user-space HWRM interface
24001 	 * * 0xFFFF - HWRM
24026 	#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_FLAGS_DBR_NQ_EVENT_ENABLED	UINT32_C(0x1)
24033 	 * 0xFFFF-FFFF indicates this register does not exist.
24037 	#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK	UINT32_C(0x3)
24038 	#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT	0
24040 	 * If value is 0, this register is located in PCIe config space.
24044 		#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG  UINT32_C(0x0)
24050 		#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC	UINT32_C(0x1)
24056 		#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0	UINT32_C(0x2)
24063 		#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1	UINT32_C(0x3)
24066 	#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_MASK	UINT32_C(0xfffffffc)
24096 	 * address. A value of 0xFFFF-FFFF indicates this register does not
24101 	#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK	UINT32_C(0x3)
24102 	#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT	0
24104 	 * If value is 0, this register is located in PCIe config space.
24108 …fine HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG  UINT32_C(0x0)
24114 		#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC	UINT32_C(0x1)
24120 		#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0	UINT32_C(0x2)
24127 		#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1	UINT32_C(0x3)
24130 	#define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK	UINT32_C(0xfffffffc)
24142 	 * A value of 0xFFFF FFFF indicates NQ ID is invalid.
24185 	 * * 0x0-0xFFF8 - The function ID
24186 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24187 	 * * 0xFFFD - Reserved for user-space HWRM interface
24188 	 * * 0xFFFF - HWRM
24246 	 * * 0x0-0xFFF8 - The function ID
24247 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24248 	 * * 0xFFFD - Reserved for user-space HWRM interface
24249 	 * * 0xFFFF - HWRM
24340 	 * * 0x0-0xFFF8 - The function ID
24341 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24342 	 * * 0xFFFD - Reserved for user-space HWRM interface
24343 	 * * 0xFFFF - HWRM
24360 	#define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_MASK UINT32_C(0xffffff)
24361 	#define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_SFT 0
24411 	 * * 0x0-0xFFF8 - The function ID
24412 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24413 	 * * 0xFFFD - Reserved for user-space HWRM interface
24414 	 * * 0xFFFF - HWRM
24429 	#define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_FREQ_PROFILE	UINT32_C(0x1)
24434 	#define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_PRIMARY_CLOCK	UINT32_C(0x2)
24439 	#define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_SECONDARY_CLOCK	UINT32_C(0x4)
24443 	#define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)
24445 	#define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ   UINT32_C(0x1)
24453 	#define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_DISABLE UINT32_C(0x0)
24455 	#define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE  UINT32_C(0x1)
24463 	#define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_DISABLE UINT32_C(0x0)
24465 	#define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE  UINT32_C(0x1)
24515 	 * * 0x0-0xFFF8 - The function ID
24516 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24517 	 * * 0xFFFD - Reserved for user-space HWRM interface
24518 	 * * 0xFFFF - HWRM
24545 	#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)
24547 	#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ   UINT32_C(0x1)
24553 	 * When this bit is '0', primary clock is disabled for this PF/port.
24555 	#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_PRIMARY_CLOCK_ENABLED	UINT32_C(0x1)
24559 	 * When this bit is '0', secondary clock is disabled for this
24562 	#define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_SECONDARY_CLOCK_ENABLED	UINT32_C(0x2)
24597 	 * * 0x0-0xFFF8 - The function ID
24598 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24599 	 * * 0xFFFD - Reserved for user-space HWRM interface
24600 	 * * 0xFFFF - HWRM
24615 	#define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_ACTIVE_PORT_MAP	UINT32_C(0x1)
24620 	#define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_MEMBER_PORT_MAP	UINT32_C(0x2)
24622 	#define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_AGGR_MODE	UINT32_C(0x4)
24624 	#define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_RSVD1_MASK	UINT32_C(0xf8)
24629 	 * from 0 to n - 1 on a device with n ports. The number of front panel
24651 	#define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_0	UINT32_C(0x1)
24653 	#define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_1	UINT32_C(0x2)
24655 	#define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_2	UINT32_C(0x4)
24657 	#define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_3	UINT32_C(0x8)
24659 	#define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
24664 	 * from 0 to n - 1 on a device with n ports. The number of front panel
24673 	#define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_0	UINT32_C(0x1)
24675 	#define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_1	UINT32_C(0x2)
24677 	#define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_2	UINT32_C(0x4)
24679 	#define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_3	UINT32_C(0x8)
24681 	#define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
24686 	#define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
24688 	#define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
24690 	#define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_BALANCE_XOR   UINT32_C(0x3)
24692 	#define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_802_3_AD	UINT32_C(0x4)
24747 	 * * 0x0-0xFFF8 - The function ID
24748 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24749 	 * * 0xFFFD - Reserved for user-space HWRM interface
24750 	 * * 0xFFFF - HWRM
24767 	#define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_ACTIVE_PORT_MAP	UINT32_C(0x1)
24772 	#define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_MEMBER_PORT_MAP	UINT32_C(0x2)
24774 	#define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_AGGR_MODE	UINT32_C(0x4)
24776 	#define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_RSVD1_MASK	UINT32_C(0xf8)
24781 	 * from 0 to n - 1 on a device with n ports. The number of front panel
24803 	#define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_0	UINT32_C(0x1)
24805 	#define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_1	UINT32_C(0x2)
24807 	#define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_2	UINT32_C(0x4)
24809 	#define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_3	UINT32_C(0x8)
24811 	#define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
24816 	 * from 0 to n - 1 on a device with n ports. The number of front panel
24825 	#define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_0	UINT32_C(0x1)
24827 	#define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_1	UINT32_C(0x2)
24829 	#define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_2	UINT32_C(0x4)
24831 	#define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_3	UINT32_C(0x8)
24833 	#define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
24838 	#define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
24840 	#define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
24842 	#define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_BALANCE_XOR   UINT32_C(0x3)
24844 	#define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_802_3_AD	UINT32_C(0x4)
24894 	 * * 0x0-0xFFF8 - The function ID
24895 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24896 	 * * 0xFFFD - Reserved for user-space HWRM interface
24897 	 * * 0xFFFF - HWRM
24957 	 * * 0x0-0xFFF8 - The function ID
24958 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24959 	 * * 0xFFFD - Reserved for user-space HWRM interface
24960 	 * * 0xFFFF - HWRM
24989 	 * from 0 to n - 1 on a device with n ports. The number of front panel
25011 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0	UINT32_C(0x1)
25013 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1	UINT32_C(0x2)
25015 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2	UINT32_C(0x4)
25017 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3	UINT32_C(0x8)
25019 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
25024 	 * from 0 to n - 1 on a device with n ports. The number of front panel
25033 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0	UINT32_C(0x1)
25035 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1	UINT32_C(0x2)
25037 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2	UINT32_C(0x4)
25039 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3	UINT32_C(0x8)
25041 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
25046 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
25048 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
25050 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR   UINT32_C(0x3)
25052 	#define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_802_3_AD	UINT32_C(0x4)
25088 	 * * 0x0-0xFFF8 - The function ID
25089 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25090 	 * * 0xFFFD - Reserved for user-space HWRM interface
25091 	 * * 0xFFFF - HWRM
25106 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_FLAGS		UINT32_C(0x1)
25111 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_ACTIVE_PORT_MAP	UINT32_C(0x2)
25116 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_MEMBER_PORT_MAP	UINT32_C(0x4)
25118 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_AGGR_MODE	UINT32_C(0x8)
25120 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_LAG_ID		UINT32_C(0x10)
25122 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_RSVD1_MASK	UINT32_C(0xe0)
25129 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_DISABLE	UINT32_C(0x1)
25134 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_ENABLE	UINT32_C(0x2)
25136 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_RSVD2_MASK	UINT32_C(0xfc)
25140 	 * represents a front panel port of the device starting from port 0.
25158 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_0	UINT32_C(0x1)
25160 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_1	UINT32_C(0x2)
25162 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_2	UINT32_C(0x4)
25164 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_3	UINT32_C(0x8)
25166 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
25170 	 * represents a front panel port of the device starting from port 0.
25187 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_0	UINT32_C(0x1)
25189 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_1	UINT32_C(0x2)
25191 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_2	UINT32_C(0x4)
25193 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_3	UINT32_C(0x8)
25195 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
25200 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
25202 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
25204 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_BALANCE_XOR   UINT32_C(0x3)
25206 	#define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_802_3_AD	UINT32_C(0x4)
25260 	 * * 0x0-0xFFF8 - The function ID
25261 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25262 	 * * 0xFFFD - Reserved for user-space HWRM interface
25263 	 * * 0xFFFF - HWRM
25292 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_ENABLED	UINT32_C(0x1)
25294 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_RSVD1_MASK	UINT32_C(0xfe)
25298 	 * represents a front panel port of the device starting from port 0.
25316 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0	UINT32_C(0x1)
25318 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1	UINT32_C(0x2)
25320 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2	UINT32_C(0x4)
25322 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3	UINT32_C(0x8)
25324 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD2_MASK UINT32_C(0xf0)
25328 	 * represents a front panel port of the device starting from port 0.
25345 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0	UINT32_C(0x1)
25347 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1	UINT32_C(0x2)
25349 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2	UINT32_C(0x4)
25351 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3	UINT32_C(0x8)
25353 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
25358 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
25360 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
25362 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR   UINT32_C(0x3)
25364 	#define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_802_3_AD	UINT32_C(0x4)
25400 	 * * 0x0-0xFFF8 - The function ID
25401 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25402 	 * * 0xFFFD - Reserved for user-space HWRM interface
25403 	 * * 0xFFFF - HWRM
25416 	 * If set to 0xFF... (All Fs), then the configuration is
25493 	 * * 0x0-0xFFF8 - The function ID
25494 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25495 	 * * 0xFFFD - Reserved for user-space HWRM interface
25496 	 * * 0xFFFF - HWRM
25509 	 * If set to 0xFF... (All Fs), then the configuration is
25519 	#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID	UINT32_C(0x1)
25524 	#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID	UINT32_C(0x2)
25529 	#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP	UINT32_C(0x4)
25534 	#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP	UINT32_C(0x8)
25539 	#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID	UINT32_C(0x10)
25544 	#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID	UINT32_C(0x20)
25617 	 * * 0x0-0xFFF8 - The function ID
25618 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25619 	 * * 0xFFFD - Reserved for user-space HWRM interface
25620 	 * * 0xFFFF - HWRM
25693 	 * * 0x0-0xFFF8 - The function ID
25694 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25695 	 * * 0xFFFD - Reserved for user-space HWRM interface
25696 	 * * 0xFFFF - HWRM
25715 	#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK	UINT32_C(0xfff)
25716 	#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT	0
25721 	#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK	UINT32_C(0xf000)
25723 	/* 0% of the max tx rate */
25724 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0	(UINT32_C(0x0) << 12)
25726 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66   (UINT32_C(0x1) << 12)
25728 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33  (UINT32_C(0x2) << 12)
25730 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20	(UINT32_C(0x3) << 12)
25732 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66  (UINT32_C(0x4) << 12)
25734 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33  (UINT32_C(0x5) << 12)
25736 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40	(UINT32_C(0x6) << 12)
25738 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66  (UINT32_C(0x7) << 12)
25740 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33  (UINT32_C(0x8) << 12)
25742 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60	(UINT32_C(0x9) << 12)
25744 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66  (UINT32_C(0xa) << 12)
25746 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33  (UINT32_C(0xb) << 12)
25748 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80	(UINT32_C(0xc) << 12)
25750 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66  (UINT32_C(0xd) << 12)
25752 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33  (UINT32_C(0xe) << 12)
25754 		#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100	(UINT32_C(0xf) << 12)
25803 	 * * 0x0-0xFFF8 - The function ID
25804 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25805 	 * * 0xFFFD - Reserved for user-space HWRM interface
25806 	 * * 0xFFFF - HWRM
25826 	#define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
25827 	#define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
25851 	#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK	UINT32_C(0xfff)
25852 	#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT	0
25857 	#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK	UINT32_C(0xf000)
25859 	/* 0% of the max tx rate */
25860 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0	(UINT32_C(0x0) << 12)
25862 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66   (UINT32_C(0x1) << 12)
25864 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33  (UINT32_C(0x2) << 12)
25866 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20	(UINT32_C(0x3) << 12)
25868 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66  (UINT32_C(0x4) << 12)
25870 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33  (UINT32_C(0x5) << 12)
25872 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40	(UINT32_C(0x6) << 12)
25874 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66  (UINT32_C(0x7) << 12)
25876 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33  (UINT32_C(0x8) << 12)
25878 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60	(UINT32_C(0x9) << 12)
25880 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66  (UINT32_C(0xa) << 12)
25882 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33  (UINT32_C(0xb) << 12)
25884 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80	(UINT32_C(0xc) << 12)
25886 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66  (UINT32_C(0xd) << 12)
25888 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33  (UINT32_C(0xe) << 12)
25890 		#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100	(UINT32_C(0xf) << 12)
25926 	 * * 0x0-0xFFF8 - The function ID
25927 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25928 	 * * 0xFFFD - Reserved for user-space HWRM interface
25929 	 * * 0xFFFF - HWRM
25953 	#define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP	UINT32_C(0x1)
25975 	#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE	UINT32_C(0x1)
25981 	#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE	UINT32_C(0x2)
25990 	#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_CAPS_CHANGE	UINT32_C(0x4)
26025 	 * * 0x0-0xFFF8 - The function ID
26026 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26027 	 * * 0xFFFD - Reserved for user-space HWRM interface
26028 	 * * 0xFFFF - HWRM
26043 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC	UINT32_C(0x1)
26048 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0	UINT32_C(0x2)
26053 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1	UINT32_C(0x4)
26058 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2	UINT32_C(0x8)
26063 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3	UINT32_C(0x10)
26073 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL  UINT32_C(0x0)
26078 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2   UINT32_C(0x1)
26083 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
26106 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0	UINT32_C(0x1)
26111 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1	UINT32_C(0x2)
26116 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2	UINT32_C(0x4)
26121 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3	UINT32_C(0x8)
26126 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4	UINT32_C(0x10)
26131 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5	UINT32_C(0x20)
26136 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6	UINT32_C(0x40)
26141 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7	UINT32_C(0x80)
26146 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8	UINT32_C(0x100)
26151 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9	UINT32_C(0x200)
26156 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10	UINT32_C(0x400)
26161 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11	UINT32_C(0x800)
26166 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12	UINT32_C(0x1000)
26171 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13	UINT32_C(0x2000)
26176 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14	UINT32_C(0x4000)
26181 	#define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15	UINT32_C(0x8000)
26216 	 * * 0x0-0xFFF8 - The function ID
26217 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26218 	 * * 0xFFFD - Reserved for user-space HWRM interface
26219 	 * * 0xFFFF - HWRM
26231 	#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE	UINT32_C(0x1)
26233 	#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE	UINT32_C(0x2)
26238 	#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE	UINT32_C(0x4)
26243 	#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE	UINT32_C(0x8)
26248 	#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE	UINT32_C(0x10)
26253 	#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE	UINT32_C(0x20)
26259 	#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE		UINT32_C(0x1)
26264 	#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS	UINT32_C(0x2)
26269 	#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE		UINT32_C(0x4)
26274 	#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR	UINT32_C(0x8)
26279 	#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR	UINT32_C(0x10)
26284 	 * value of 0xffff is used if there is no user specified value.
26293 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT	UINT32_C(0x1)
26301 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4	UINT32_C(0x2)
26308 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2	UINT32_C(0x4)
26316 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4	UINT32_C(0x8)
26323 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2	UINT32_C(0x10)
26331 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4	UINT32_C(0x1)
26337 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4	UINT32_C(0x2)
26343 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4	UINT32_C(0x4)
26349 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6	UINT32_C(0x8)
26355 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6	UINT32_C(0x10)
26361 	#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6	UINT32_C(0x20)
26413 	 * * 0x0-0xFFF8 - The function ID
26414 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26415 	 * * 0xFFFD - Reserved for user-space HWRM interface
26416 	 * * 0xFFFF - HWRM
26444 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED	UINT32_C(0x1)
26449 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED	UINT32_C(0x2)
26454 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED	UINT32_C(0x4)
26461 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4	UINT32_C(0x1)
26467 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4	UINT32_C(0x2)
26473 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4	UINT32_C(0x4)
26479 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6	UINT32_C(0x8)
26485 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6	UINT32_C(0x10)
26491 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6	UINT32_C(0x20)
26500 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT	UINT32_C(0x1)
26508 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4	UINT32_C(0x2)
26515 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2	UINT32_C(0x4)
26523 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4	UINT32_C(0x8)
26530 	#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2	UINT32_C(0x10)
26536 	 * value of 0xffff is used if there is no user specified value.
26573 	 * * 0x0-0xFFF8 - The function ID
26574 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26575 	 * * 0xFFFD - Reserved for user-space HWRM interface
26576 	 * * 0xFFFF - HWRM
26601 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY		UINT32_C(0x1)
26603 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED		UINT32_C(0x2)
26606 	 * bit in the 'enables' field is '0', the link shall be forced
26623 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE			UINT32_C(0x4)
26628 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG		UINT32_C(0x8)
26635 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE		UINT32_C(0x10)
26642 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE		UINT32_C(0x20)
26651 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE	UINT32_C(0x40)
26660 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE	UINT32_C(0x80)
26672 	 * When set to 0, then this flag shall be ignored.
26676 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE	UINT32_C(0x100)
26681 	 * When set to 0, then this flag shall be ignored.
26685 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE	UINT32_C(0x200)
26690 	 * When set to 0, then this flag shall be ignored.
26694 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE	UINT32_C(0x400)
26699 	 * When set to 0, then this flag shall be ignored.
26703 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE	UINT32_C(0x800)
26712 	 * When set to 0, then this flag shall be ignored.
26716 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE	UINT32_C(0x1000)
26721 	 * force disabled otherwise. When set to 0, then this flag shall be
26725 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE	UINT32_C(0x2000)
26735 	 * to '0'.
26736 	 * # If this flag is set to '0', then the link shall be
26744 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN		UINT32_C(0x4000)
26752 	 * When set to 0, then this flag shall be ignored.
26756 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE	UINT32_C(0x8000)
26761 	 * When set to 0, then this flag shall be ignored.
26765 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE	UINT32_C(0x10000)
26773 	 * When set to 0, then this flag shall be ignored.
26777 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE	UINT32_C(0x20000)
26782 	 * When set to 0, then this flag shall be ignored.
26786 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE	UINT32_C(0x40000)
26795 	 * When set to 0, then this flag shall be ignored.
26799 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE	UINT32_C(0x80000)
26804 	 * When set to 0, then this flag shall be ignored.
26808 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE	UINT32_C(0x100000)
26817 	 * When set to 0, then this flag shall be ignored.
26821 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE	UINT32_C(0x200000)
26826 	 * When set to 0, then this flag shall be ignored.
26830 	#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE	UINT32_C(0x400000)
26836 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE			UINT32_C(0x1)
26841 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX		UINT32_C(0x2)
26846 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE			UINT32_C(0x4)
26851 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED		UINT32_C(0x8)
26856 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK	UINT32_C(0x10)
26861 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED			UINT32_C(0x20)
26866 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK			UINT32_C(0x40)
26871 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS		UINT32_C(0x80)
26876 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE		UINT32_C(0x100)
26881 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK	UINT32_C(0x200)
26886 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER		UINT32_C(0x400)
26891 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED	UINT32_C(0x800)
26896 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK	UINT32_C(0x1000)
26901 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_LINK_SPEEDS2		UINT32_C(0x2000)
26906 	#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEEDS2_MASK	UINT32_C(0x4000)
26916 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
26918 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB   UINT32_C(0xa)
26920 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB   UINT32_C(0x14)
26922 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
26924 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB  UINT32_C(0x64)
26926 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB  UINT32_C(0xc8)
26928 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB  UINT32_C(0xfa)
26930 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB  UINT32_C(0x190)
26932 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB  UINT32_C(0x1f4)
26934 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
26936 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB  UINT32_C(0xffff)
26944 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE	UINT32_C(0x0)
26946 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS   UINT32_C(0x1)
26951 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED	UINT32_C(0x2)
26957 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
26963 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK   UINT32_C(0x4)
26971 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
26973 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
26975 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
26987 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX		UINT32_C(0x1)
26992 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX		UINT32_C(0x2)
27000 	 * flag is set to 0, the pause is forced as indicated in
27005 	 * 1, auto_pause bits should be ignored and should be set to 0.
27007 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE	UINT32_C(0x4)
27020 	 * When set to 0, management firmware is using the given port.
27022 	#define HWRM_PORT_PHY_CFG_INPUT_MGMT_FLAG_LINK_RELEASE	UINT32_C(0x1)
27027 	#define HWRM_PORT_PHY_CFG_INPUT_MGMT_FLAG_MGMT_VALID	UINT32_C(0x80)
27035 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
27037 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB   UINT32_C(0xa)
27039 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB   UINT32_C(0x14)
27041 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
27043 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB  UINT32_C(0x64)
27045 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB  UINT32_C(0xc8)
27047 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB  UINT32_C(0xfa)
27049 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB  UINT32_C(0x190)
27051 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB  UINT32_C(0x1f4)
27053 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
27055 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB  UINT32_C(0xffff)
27064 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD	UINT32_C(0x1)
27066 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB	UINT32_C(0x2)
27068 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD	UINT32_C(0x4)
27070 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB	UINT32_C(0x8)
27072 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB	UINT32_C(0x10)
27074 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB	UINT32_C(0x20)
27076 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB	UINT32_C(0x40)
27078 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB	UINT32_C(0x80)
27080 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB	UINT32_C(0x100)
27082 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB	UINT32_C(0x200)
27084 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB	UINT32_C(0x400)
27086 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB	UINT32_C(0x800)
27088 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD	UINT32_C(0x1000)
27090 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB	UINT32_C(0x2000)
27094 	#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
27096 	#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON  UINT32_C(0x1)
27101 	#define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE	UINT32_C(0x0)
27106 	#define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL	UINT32_C(0x1)
27112 	#define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE   UINT32_C(0x2)
27119 	#define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
27130 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX	UINT32_C(0x1)
27135 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX	UINT32_C(0x2)
27140 	 * enable.preemphasis = 0) unless driver is sure of setting.
27155 	#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1	UINT32_C(0x1)
27157 	#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB	UINT32_C(0x2)
27159 	#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2	UINT32_C(0x4)
27161 	#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB	UINT32_C(0x8)
27163 	#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3	UINT32_C(0x10)
27165 	#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4	UINT32_C(0x20)
27167 	#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB	UINT32_C(0x40)
27175 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB  UINT32_C(0x1f4)
27177 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB UINT32_C(0x3e8)
27179 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB UINT32_C(0x7d0)
27187 	#define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
27188 	#define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
27191 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G	UINT32_C(0x1)
27192 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G	UINT32_C(0x2)
27193 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G	UINT32_C(0x4)
27201 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_1GB		UINT32_C(0xa)
27203 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_10GB	UINT32_C(0x64)
27205 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_25GB	UINT32_C(0xfa)
27207 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_40GB	UINT32_C(0x190)
27209 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB	UINT32_C(0x1f4)
27211 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB	UINT32_C(0x3e8)
27213 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56   UINT32_C(0x1f5)
27215 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56  UINT32_C(0x3e9)
27217 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56  UINT32_C(0x7d1)
27219 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56  UINT32_C(0xfa1)
27221 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x3ea)
27223 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x7d2)
27225 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0xfa2)
27227 	#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x1f42)
27236 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_1GB		UINT32_C(0x1)
27238 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_10GB		UINT32_C(0x2)
27240 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_25GB		UINT32_C(0x4)
27242 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_40GB		UINT32_C(0x8)
27244 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB		UINT32_C(0x10)
27246 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB		UINT32_C(0x20)
27248 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56	UINT32_C(0x40)
27250 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56	UINT32_C(0x80)
27252 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56	UINT32_C(0x100)
27254 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56	UINT32_C(0x200)
27256 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112	UINT32_C(0x400)
27258 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112	UINT32_C(0x800)
27260 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112	UINT32_C(0x1000)
27262 	#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112	UINT32_C(0x2000)
27297 	#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN	UINT32_C(0x0)
27299 	#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
27305 	 * but if a 0 is returned at any time then this should
27312 	#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY	UINT32_C(0x2)
27340 	 * * 0x0-0xFFF8 - The function ID
27341 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27342 	 * * 0xFFFD - Reserved for user-space HWRM interface
27343 	 * * 0xFFFF - HWRM
27372 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
27374 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL  UINT32_C(0x1)
27376 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK	UINT32_C(0x2)
27383 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK		UINT32_C(0xf)
27384 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT		0
27386 		#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ		UINT32_C(0x0)
27388 		#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4		UINT32_C(0x1)
27390 		#define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112		UINT32_C(0x2)
27393 	#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK		UINT32_C(0xf0)
27396 		#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE	(UINT32_C(0x0) << 4)
27398 		#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE	(UINT32_C(0x1) << 4)
27400 		#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE	(UINT32_C(0x2) << 4)
27402 		#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE   (UINT32_C(0x3) << 4)
27404 		#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE  (UINT32_C(0x4) << 4)
27406 		#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE   (UINT32_C(0x5) << 4)
27408 		#define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE  (UINT32_C(0x6) << 4)
27417 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
27419 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB   UINT32_C(0xa)
27421 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB   UINT32_C(0x14)
27423 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
27425 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB  UINT32_C(0x64)
27427 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB  UINT32_C(0xc8)
27429 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB  UINT32_C(0xfa)
27431 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB  UINT32_C(0x190)
27433 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB  UINT32_C(0x1f4)
27435 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
27437 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
27439 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_400GB UINT32_C(0xfa0)
27441 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_800GB UINT32_C(0x1f40)
27443 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB  UINT32_C(0xffff)
27451 	#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
27453 	#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
27465 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX	UINT32_C(0x1)
27470 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX	UINT32_C(0x2)
27478 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD	UINT32_C(0x1)
27480 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB	UINT32_C(0x2)
27482 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD	UINT32_C(0x4)
27484 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB	UINT32_C(0x8)
27486 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB	UINT32_C(0x10)
27488 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB	UINT32_C(0x20)
27490 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB	UINT32_C(0x40)
27492 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB	UINT32_C(0x80)
27494 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB	UINT32_C(0x100)
27496 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB	UINT32_C(0x200)
27498 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB	UINT32_C(0x400)
27500 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB	UINT32_C(0x800)
27502 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD	UINT32_C(0x1000)
27504 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB	UINT32_C(0x2000)
27508 	 * value shall be set to 0.
27512 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
27514 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB   UINT32_C(0xa)
27516 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB   UINT32_C(0x14)
27518 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
27520 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB  UINT32_C(0x64)
27522 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB  UINT32_C(0xc8)
27524 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB  UINT32_C(0xfa)
27526 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB  UINT32_C(0x190)
27528 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB  UINT32_C(0x1f4)
27530 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
27532 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB  UINT32_C(0xffff)
27537 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE	UINT32_C(0x0)
27539 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS   UINT32_C(0x1)
27544 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED	UINT32_C(0x2)
27550 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
27555 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK   UINT32_C(0x4)
27566 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX		UINT32_C(0x1)
27571 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX		UINT32_C(0x2)
27579 	 * flag is set to 0, the pause is forced as indicated in
27584 	 * 1, auto_pause bits should be ignored and should be set to 0.
27586 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE	UINT32_C(0x4)
27593 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
27595 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB   UINT32_C(0xa)
27597 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB   UINT32_C(0x14)
27599 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
27601 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB  UINT32_C(0x64)
27603 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB  UINT32_C(0xc8)
27605 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB  UINT32_C(0xfa)
27607 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB  UINT32_C(0x190)
27609 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB  UINT32_C(0x1f4)
27611 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
27613 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB  UINT32_C(0xffff)
27624 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD	UINT32_C(0x1)
27626 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB	UINT32_C(0x2)
27628 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD	UINT32_C(0x4)
27630 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB	UINT32_C(0x8)
27632 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB	UINT32_C(0x10)
27634 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB	UINT32_C(0x20)
27636 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB	UINT32_C(0x40)
27638 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB	UINT32_C(0x80)
27640 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB	UINT32_C(0x100)
27642 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB	UINT32_C(0x200)
27644 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB	UINT32_C(0x400)
27646 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB	UINT32_C(0x800)
27648 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD	UINT32_C(0x1000)
27650 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB	UINT32_C(0x2000)
27654 	#define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
27656 	#define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON  UINT32_C(0x1)
27661 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE	UINT32_C(0x0)
27666 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL	UINT32_C(0x1)
27672 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE   UINT32_C(0x2)
27679 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
27684 	 * this value shall be set to 0.
27691 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX	UINT32_C(0x1)
27696 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX	UINT32_C(0x2)
27703 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE	UINT32_C(0x0)
27705 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX	UINT32_C(0x1)
27707 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG	UINT32_C(0x2)
27709 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN	UINT32_C(0x3)
27711 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED   UINT32_C(0x4)
27713 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT  UINT32_C(0x5)
27715 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_OVERHEATED	UINT32_C(0x6)
27717 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE UINT32_C(0xff)
27730 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN	UINT32_C(0x0)
27732 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR	UINT32_C(0x1)
27734 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4	UINT32_C(0x2)
27736 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR	UINT32_C(0x3)
27738 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR	UINT32_C(0x4)
27740 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2	UINT32_C(0x5)
27742 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX	UINT32_C(0x6)
27744 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR	UINT32_C(0x7)
27746 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET		UINT32_C(0x8)
27748 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE	UINT32_C(0x9)
27750 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY	UINT32_C(0xa)
27752 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L  UINT32_C(0xb)
27754 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S  UINT32_C(0xc)
27756 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N  UINT32_C(0xd)
27758 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR	UINT32_C(0xe)
27760 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4	UINT32_C(0xf)
27762 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4	UINT32_C(0x10)
27764 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4	UINT32_C(0x11)
27766 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4	UINT32_C(0x12)
27768 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10	UINT32_C(0x13)
27770 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4	UINT32_C(0x14)
27772 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4	UINT32_C(0x15)
27774 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4	UINT32_C(0x16)
27776 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4	UINT32_C(0x17)
27778 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE UINT32_C(0x18)
27780 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET	UINT32_C(0x19)
27782 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX	UINT32_C(0x1a)
27784 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX	UINT32_C(0x1b)
27786 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4	UINT32_C(0x1c)
27788 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4	UINT32_C(0x1d)
27790 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4	UINT32_C(0x1e)
27792 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4	UINT32_C(0x1f)
27794 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR	UINT32_C(0x20)
27796 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR	UINT32_C(0x21)
27798 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR	UINT32_C(0x22)
27800 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER	UINT32_C(0x23)
27802 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2	UINT32_C(0x24)
27804 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2	UINT32_C(0x25)
27806 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2	UINT32_C(0x26)
27808 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2	UINT32_C(0x27)
27810 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR	UINT32_C(0x28)
27812 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR	UINT32_C(0x29)
27814 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR	UINT32_C(0x2a)
27816 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER	UINT32_C(0x2b)
27818 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR2	UINT32_C(0x2c)
27820 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR2	UINT32_C(0x2d)
27822 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR2	UINT32_C(0x2e)
27824 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER2	UINT32_C(0x2f)
27826 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR8	UINT32_C(0x30)
27828 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR8	UINT32_C(0x31)
27830 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR8	UINT32_C(0x32)
27832 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER8	UINT32_C(0x33)
27834 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR4	UINT32_C(0x34)
27836 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR4	UINT32_C(0x35)
27838 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR4	UINT32_C(0x36)
27840 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER4	UINT32_C(0x37)
27842 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASECR8	UINT32_C(0x38)
27844 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASESR8	UINT32_C(0x39)
27846 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASELR8	UINT32_C(0x3a)
27848 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEER8	UINT32_C(0x3b)
27850 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEFR8	UINT32_C(0x3c)
27852 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEDR8	UINT32_C(0x3d)
27857 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
27859 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP	UINT32_C(0x1)
27861 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC	UINT32_C(0x2)
27863 	#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE   UINT32_C(0x3)
27868 	#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL UINT32_C(0x1)
27870 	#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL UINT32_C(0x2)
27874 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK		UINT32_C(0x1f)
27875 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT		0
27882 	#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK		UINT32_C(0xe0)
27889 	#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED	UINT32_C(0x20)
27893 	 * # If eee_enabled is set to 0, then EEE mode is disabled
27898 	 * # If eee_enabled is set to 1 and this flag is set to 0,
27902 	#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE	UINT32_C(0x40)
27906 	 * # If eee_enabled is set to 0, then EEE mode is disabled
27911 	 * # If eee_enabled is set to 1 and this flag is set to 0,
27915 	#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI	UINT32_C(0x80)
27933 	#define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT	UINT32_C(0x1)
27940 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD	UINT32_C(0x1)
27942 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB	UINT32_C(0x2)
27944 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD	UINT32_C(0x4)
27946 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB	UINT32_C(0x8)
27948 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB	UINT32_C(0x10)
27950 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB	UINT32_C(0x20)
27952 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB	UINT32_C(0x40)
27954 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB	UINT32_C(0x80)
27956 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB	UINT32_C(0x100)
27958 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB	UINT32_C(0x200)
27960 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB	UINT32_C(0x400)
27962 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB	UINT32_C(0x800)
27964 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD	UINT32_C(0x1000)
27966 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB	UINT32_C(0x2000)
27969 	 * This field is deprecated and should be set to 0.
27973 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE	UINT32_C(0x0)
27975 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS   UINT32_C(0x1)
27980 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED	UINT32_C(0x2)
27986 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
27991 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK   UINT32_C(0x4)
27999 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX	UINT32_C(0x1)
28004 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX	UINT32_C(0x2)
28014 	#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1	UINT32_C(0x1)
28016 	#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB	UINT32_C(0x2)
28018 	#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2	UINT32_C(0x4)
28020 	#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB	UINT32_C(0x8)
28022 	#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3	UINT32_C(0x10)
28024 	#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4	UINT32_C(0x20)
28026 	#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB	UINT32_C(0x40)
28034 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1	UINT32_C(0x1)
28036 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB	UINT32_C(0x2)
28038 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2	UINT32_C(0x4)
28040 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB	UINT32_C(0x8)
28042 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3	UINT32_C(0x10)
28044 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4	UINT32_C(0x20)
28046 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB	UINT32_C(0x40)
28053 	#define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK		UINT32_C(0xffffff)
28054 	#define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT		0
28056 	#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK	UINT32_C(0xff000000)
28059 		#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN   (UINT32_C(0x0) << 24)
28061 		#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP	(UINT32_C(0x3) << 24)
28063 		#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP	(UINT32_C(0xc) << 24)
28065 		#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS  (UINT32_C(0xd) << 24)
28067 		#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28	(UINT32_C(0x11) << 24)
28069 		#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPDD	(UINT32_C(0x18) << 24)
28071 		#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP112   (UINT32_C(0x1e) << 24)
28073 		#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFPDD	(UINT32_C(0x1f) << 24)
28075 		#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_CSFP	(UINT32_C(0x20) << 24)
28085 	 * ignored. When set to 0, then FEC is supported as indicated by
28088 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED	UINT32_C(0x1)
28091 	 * When set to 0, then FEC autonegotiation is not supported on this
28094 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED	UINT32_C(0x2)
28097 	 * When set to 0, then FEC autonegotiation is disabled if supported.
28101 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED	UINT32_C(0x4)
28104 	 * port. When set to 0, then FEC CLAUSE 74 (Fire Code) is not
28107 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED	UINT32_C(0x8)
28112 	 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if
28116 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED	UINT32_C(0x10)
28120 	 * When set to 0, then FEC RS(528,418) is not supported on this port.
28122 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED	UINT32_C(0x20)
28127 	 * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514)
28132 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED	UINT32_C(0x40)
28135 	 * When set to 0, then FEC RS544_1XN is not supported on this port.
28137 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED	UINT32_C(0x80)
28142 	 * When set to 0, then FEC RS544_1XN is disabled if supported.
28146 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED	UINT32_C(0x100)
28149 	 * When set to 0, then FEC RS(544,514) is not supported on this port.
28151 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED	UINT32_C(0x200)
28156 	 * enabled. When set to 0, then FEC RS(544,514) is disabled if
28160 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED	UINT32_C(0x400)
28163 	 * When set to 0, then FEC RS272_1XN is not supported on this port.
28165 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED	UINT32_C(0x800)
28170 	 * enabled. When set to 0, then FEC RS272_1XN is disabled if
28175 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED	UINT32_C(0x1000)
28178 	 * When set to 0, then FEC RS(272,514) is not supported on this port.
28180 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED	UINT32_C(0x2000)
28185 	 * enabled. When set to 0, then FEC RS(272,257) is disabled if
28190 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED	UINT32_C(0x4000)
28197 	#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
28199 	#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
28204 	#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT	UINT32_C(0x1)
28209 	#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN	UINT32_C(0x2)
28214 	#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SPEEDS2_SUPPORTED	UINT32_C(0x4)
28235 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G	UINT32_C(0x1)
28236 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G	UINT32_C(0x2)
28237 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G	UINT32_C(0x4)
28241 	 * value shall be set to 0.
28245 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB  UINT32_C(0x1f4)
28247 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB UINT32_C(0x3e8)
28249 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB UINT32_C(0x7d0)
28259 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G	UINT32_C(0x1)
28260 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G	UINT32_C(0x2)
28261 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G	UINT32_C(0x4)
28268 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB	UINT32_C(0x1)
28270 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB	UINT32_C(0x2)
28272 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB	UINT32_C(0x4)
28275 	 * This field is set to 0, if the link down reason is unknown.
28279 	#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF	UINT32_C(0x1)
28288 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_1GB		UINT32_C(0x1)
28290 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_10GB		UINT32_C(0x2)
28292 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_25GB		UINT32_C(0x4)
28294 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_40GB		UINT32_C(0x8)
28296 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB		UINT32_C(0x10)
28298 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB		UINT32_C(0x20)
28300 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB_PAM4_56	UINT32_C(0x40)
28302 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_56	UINT32_C(0x80)
28304 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_56	UINT32_C(0x100)
28306 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_56	UINT32_C(0x200)
28308 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_112	UINT32_C(0x400)
28310 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_112	UINT32_C(0x800)
28312 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_112	UINT32_C(0x1000)
28314 	#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_800GB_PAM4_112	UINT32_C(0x2000)
28317 	 * being forced, this value shall be set to 0.
28323 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_1GB		UINT32_C(0xa)
28325 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_10GB	UINT32_C(0x64)
28327 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_25GB	UINT32_C(0xfa)
28329 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_40GB	UINT32_C(0x190)
28331 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB	UINT32_C(0x1f4)
28333 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB	UINT32_C(0x3e8)
28335 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56   UINT32_C(0x1f5)
28337 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56  UINT32_C(0x3e9)
28339 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56  UINT32_C(0x7d1)
28341 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56  UINT32_C(0xfa1)
28343 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x3ea)
28345 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x7d2)
28347 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0xfa2)
28349 	#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x1f42)
28361 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_1GB		UINT32_C(0x1)
28363 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_10GB		UINT32_C(0x2)
28365 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_25GB		UINT32_C(0x4)
28367 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_40GB		UINT32_C(0x8)
28369 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB		UINT32_C(0x10)
28371 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB		UINT32_C(0x20)
28373 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB_PAM4_56	UINT32_C(0x40)
28375 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_56	UINT32_C(0x80)
28377 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_56	UINT32_C(0x100)
28379 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_56	UINT32_C(0x200)
28381 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_112	UINT32_C(0x400)
28383 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_112	UINT32_C(0x800)
28385 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_112	UINT32_C(0x1000)
28387 	#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_800GB_PAM4_112	UINT32_C(0x2000)
28427 	 * * 0x0-0xFFF8 - The function ID
28428 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28429 	 * * 0xFFFD - Reserved for user-space HWRM interface
28430 	 * * 0xFFFF - HWRM
28471 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK			UINT32_C(0x1)
28476 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE	UINT32_C(0x2)
28481 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE	UINT32_C(0x4)
28486 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE		UINT32_C(0x8)
28492 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE	UINT32_C(0x10)
28498 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE	UINT32_C(0x20)
28504 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE	UINT32_C(0x40)
28510 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE	UINT32_C(0x80)
28515 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE		UINT32_C(0x100)
28520 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE		UINT32_C(0x200)
28525 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE	UINT32_C(0x400)
28530 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE	UINT32_C(0x800)
28535 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE	UINT32_C(0x1000)
28541 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS		UINT32_C(0x2000)
28547 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_ENABLE	UINT32_C(0x4000)
28553 	#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_DISABLE	UINT32_C(0x8000)
28559 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG				UINT32_C(0x1)
28564 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK			UINT32_C(0x2)
28569 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI	UINT32_C(0x4)
28574 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI	UINT32_C(0x10)
28579 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI		UINT32_C(0x20)
28584 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE	UINT32_C(0x40)
28589 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE	UINT32_C(0x80)
28594 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG		UINT32_C(0x100)
28599 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB		UINT32_C(0x200)
28604 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE		UINT32_C(0x400)
28609 	#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_LOAD_CONTROL		UINT32_C(0x800)
28620 	#define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE   UINT32_C(0x0)
28625 	#define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL  UINT32_C(0x1)
28631 	#define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
28642 	 * For example, a value of 0-3 is returned where 0 is being
28658 	 * For example, a value of 0-3 is returned where 0 is being
28671 	 * For example, a value of 0-3 is returned where 0 is being
28702 	#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1			UINT32_C(0x1)
28713 	#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK	UINT32_C(0x6)
28719 		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST	(UINT32_C(0x0) << 1)
28727 		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER	(UINT32_C(0x1) << 1)
28732 		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST	(UINT32_C(0x2) << 1)
28734 		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED	(UINT32_C(0x3) << 1)
28745 	#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK	UINT32_C(0x18)
28751 		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST	(UINT32_C(0x0) << 3)
28759 		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER	(UINT32_C(0x1) << 3)
28764 		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST	(UINT32_C(0x2) << 3)
28766 		#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED  (UINT32_C(0x3) << 3)
28776 	#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK	UINT32_C(0xe0)
28791 	#define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_NONE	UINT32_C(0x0)
28796 	#define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_IMMEDIATE UINT32_C(0x1)
28801 	#define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_PPS_EVENT UINT32_C(0x2)
28841 	#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE   UINT32_C(0x0)
28846 	#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL  UINT32_C(0x1)
28852 	#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
28888 	 * * 0x0-0xFFF8 - The function ID
28889 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28890 	 * * 0xFFFD - Reserved for user-space HWRM interface
28891 	 * * 0xFFFF - HWRM
28939 	#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE   UINT32_C(0x0)
28944 	#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL  UINT32_C(0x1)
28950 	#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
28958 	 * For example, a value of 0-3 is returned where 0 is being
28975 	#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE	UINT32_C(0x1)
28980 	#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE	UINT32_C(0x2)
28985 	#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE	UINT32_C(0x4)
28990 	#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE		UINT32_C(0x8)
28992 	#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE	UINT32_C(0x10)
28994 	#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE	UINT32_C(0x20)
29001 	 * For example, a value of 0-3 is returned where 0 is being
29015 	 * For example, a value of 0-3 is returned where 0 is being
29031 	 * If all bits are set to 0 (i.e. field value set 0),
29047 	 * If all bits are set to 0 (i.e. field value set 0),
29058 	#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD			UINT32_C(0x1)
29065 	#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK	UINT32_C(0x6)
29071 		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST	(UINT32_C(0x0) << 1)
29079 		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER	(UINT32_C(0x1) << 1)
29084 		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST	(UINT32_C(0x2) << 1)
29086 		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED	(UINT32_C(0x3) << 1)
29094 	#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK	UINT32_C(0x18)
29100 		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST	(UINT32_C(0x0) << 3)
29108 		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER	(UINT32_C(0x1) << 3)
29113 		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST	(UINT32_C(0x2) << 3)
29115 		#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED  (UINT32_C(0x3) << 3)
29121 	#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK	UINT32_C(0xe0)
29130 	#define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK	UINT32_C(0x7fff)
29131 	#define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT	0
29133 	#define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID	UINT32_C(0x8000)
29140 	#define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_NONE	UINT32_C(0x0)
29142 	#define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_IMMEDIATE UINT32_C(0x1)
29147 	#define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_PPS_EVENT UINT32_C(0x2)
29183 	 * * 0x0-0xFFF8 - The function ID
29184 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29185 	 * * 0xFFFD - Reserved for user-space HWRM interface
29186 	 * * 0xFFFF - HWRM
29221 	#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS			UINT32_C(0x1)
29226 	#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS			UINT32_C(0x4)
29231 	#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS			UINT32_C(0x8)
29237 	#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK	UINT32_C(0x10)
29242 	#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_RTC_CONFIGURED			UINT32_C(0x20)
29247 	#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_64B_PHC_TIME			UINT32_C(0x40)
29387 	 * Pri 0 transmitted
29515 	 * and RXD is 0xE. The event is reported along with the
29546 	 * XON to XOFF on Pri 0
29586 	 * bit for Pri 0
29687 	 * * 0x0-0xFFF8 - The function ID
29688 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29689 	 * * 0xFFFD - Reserved for user-space HWRM interface
29690 	 * * 0xFFFF - HWRM
29708 	#define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK	UINT32_C(0x1)
29752 	/* Total number of tx bytes count on cos queue 0 */
29768 	/* Total number of tx packets count on cos queue 0 */
29786 	 * -> XON for priority 0
29791 	 * priority 0
29883 	/* Total number of rx bytes count on cos queue 0 */
29899 	/* Total number of rx packets count on cos queue 0 */
29917 	 * priority 0
29922 	 * priority 0
30007 	/* Total number of rx discard bytes count on cos queue 0 */
30023 	/* Total number of rx discard packets count on cos queue 0 */
30082 	 * for Pri 0
30122 	 * for Pri 0
30162 	 * for pri 0
30202 	 * for pri 0
30242 	 * for pri 0
30282 	 * for pri 0
30322 	 * for pri 0
30362 	 * for pri 0
30402 	 * for pri 0
30442 	 * for pri 0
30505 	 * * 0x0-0xFFF8 - The function ID
30506 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30507 	 * * 0xFFFD - Reserved for user-space HWRM interface
30508 	 * * 0xFFFF - HWRM
30536 	#define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK	UINT32_C(0x1)
30572 	#define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED	UINT32_C(0x1)
30606 	 * * 0x0-0xFFF8 - The function ID
30607 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30608 	 * * 0xFFFD - Reserved for user-space HWRM interface
30609 	 * * 0xFFFF - HWRM
30684 	 * * 0x0-0xFFF8 - The function ID
30685 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30686 	 * * 0xFFFD - Reserved for user-space HWRM interface
30687 	 * * 0xFFFF - HWRM
30711 	#define HWRM_PORT_LPBK_QSTATS_INPUT_FLAGS_COUNTER_MASK	UINT32_C(0x1)
30799 	 * * 0x0-0xFFF8 - The function ID
30800 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30801 	 * * 0xFFFD - Reserved for user-space HWRM interface
30802 	 * * 0xFFFF - HWRM
30828 	#define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK	UINT32_C(0x1)
30871 	 * Number of packets marked in CoS queue 0.
30943 	 * * 0x0-0xFFF8 - The function ID
30944 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30945 	 * * 0xFFFD - Reserved for user-space HWRM interface
30946 	 * * 0xFFFF - HWRM
30969 	#define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS	UINT32_C(0x1)
31018 	 * * 0x0-0xFFF8 - The function ID
31019 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31020 	 * * 0xFFFD - Reserved for user-space HWRM interface
31021 	 * * 0xFFFF - HWRM
31081 	 * * 0x0-0xFFF8 - The function ID
31082 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31083 	 * * 0xFFFD - Reserved for user-space HWRM interface
31084 	 * * 0xFFFF - HWRM
31100 	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH		UINT32_C(0x1)
31102 		#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX		UINT32_C(0x0)
31104 		#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX		UINT32_C(0x1)
31110 	#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME	UINT32_C(0x2)
31119 	#define HWRM_PORT_TS_QUERY_INPUT_ENABLES_TS_REQ_TIMEOUT	UINT32_C(0x1)
31124 	#define HWRM_PORT_TS_QUERY_INPUT_ENABLES_PTP_SEQ_ID	UINT32_C(0x2)
31129 	#define HWRM_PORT_TS_QUERY_INPUT_ENABLES_PTP_HDR_OFFSET	UINT32_C(0x4)
31207 	 * * 0x0-0xFFF8 - The function ID
31208 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31209 	 * * 0xFFFD - Reserved for user-space HWRM interface
31210 	 * * 0xFFFF - HWRM
31242 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED			UINT32_C(0x1)
31247 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED	UINT32_C(0x2)
31252 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED	UINT32_C(0x4)
31260 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED	UINT32_C(0x8)
31266 	 * If set to 0, the state of the counters is unspecified when
31269 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET	UINT32_C(0x10)
31274 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED	UINT32_C(0x20)
31284 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN		UINT32_C(0x40)
31290 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS			UINT32_C(0x80)
31294 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
31296 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1	UINT32_C(0x1)
31298 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2	UINT32_C(0x2)
31300 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3	UINT32_C(0x3)
31302 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4	UINT32_C(0x4)
31304 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12	UINT32_C(0xc)
31314 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD	UINT32_C(0x1)
31316 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB	UINT32_C(0x2)
31318 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD	UINT32_C(0x4)
31320 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB	UINT32_C(0x8)
31322 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB	UINT32_C(0x10)
31324 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB	UINT32_C(0x20)
31326 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB	UINT32_C(0x40)
31328 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB	UINT32_C(0x80)
31330 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB	UINT32_C(0x100)
31332 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB	UINT32_C(0x200)
31334 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB	UINT32_C(0x400)
31336 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB	UINT32_C(0x800)
31338 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD	UINT32_C(0x1000)
31340 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB	UINT32_C(0x2000)
31349 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD	UINT32_C(0x1)
31351 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB	UINT32_C(0x2)
31353 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD	UINT32_C(0x4)
31355 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB	UINT32_C(0x8)
31357 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB	UINT32_C(0x10)
31359 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB	UINT32_C(0x20)
31361 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB	UINT32_C(0x40)
31363 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB	UINT32_C(0x80)
31365 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB	UINT32_C(0x100)
31367 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB	UINT32_C(0x200)
31369 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB	UINT32_C(0x400)
31371 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB	UINT32_C(0x800)
31373 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD	UINT32_C(0x1000)
31375 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB	UINT32_C(0x2000)
31385 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1	UINT32_C(0x1)
31387 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB	UINT32_C(0x2)
31389 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2	UINT32_C(0x4)
31391 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB	UINT32_C(0x8)
31393 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3	UINT32_C(0x10)
31395 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4	UINT32_C(0x20)
31397 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB	UINT32_C(0x40)
31404 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK UINT32_C(0xffffff)
31405 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
31407 	 * Reserved field. The HWRM shall set this field to 0.
31410 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK	UINT32_C(0xff000000)
31418 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK UINT32_C(0xffffff)
31419 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
31421 	 * Reserved field. The HWRM shall set this field to 0.
31424 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK		UINT32_C(0xff000000)
31431 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G	UINT32_C(0x1)
31432 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G	UINT32_C(0x2)
31433 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G	UINT32_C(0x4)
31439 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G	UINT32_C(0x1)
31440 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G	UINT32_C(0x2)
31441 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G	UINT32_C(0x4)
31448 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED	UINT32_C(0x1)
31453 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED		UINT32_C(0x2)
31458 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED	UINT32_C(0x4)
31464 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_SPEEDS2_SUPPORTED	UINT32_C(0x8)
31469 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_REMOTE_LPBK_UNSUPPORTED	UINT32_C(0x10)
31474 	 * the PRBS test run on them. This field always return 0 unless NVM
31488 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_1GB		UINT32_C(0x1)
31490 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_10GB		UINT32_C(0x2)
31492 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_25GB		UINT32_C(0x4)
31494 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_40GB		UINT32_C(0x8)
31496 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB		UINT32_C(0x10)
31498 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB		UINT32_C(0x20)
31500 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56	UINT32_C(0x40)
31502 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56	UINT32_C(0x80)
31504 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56	UINT32_C(0x100)
31506 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56	UINT32_C(0x200)
31508 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112	UINT32_C(0x400)
31510 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112	UINT32_C(0x800)
31512 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112	UINT32_C(0x1000)
31514 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112	UINT32_C(0x2000)
31524 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_1GB		UINT32_C(0x1)
31526 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_10GB		UINT32_C(0x2)
31528 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_25GB		UINT32_C(0x4)
31530 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_40GB		UINT32_C(0x8)
31532 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB		UINT32_C(0x10)
31534 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB		UINT32_C(0x20)
31536 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56	UINT32_C(0x40)
31538 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56	UINT32_C(0x80)
31540 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56	UINT32_C(0x100)
31542 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56	UINT32_C(0x200)
31544 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112	UINT32_C(0x400)
31546 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112	UINT32_C(0x800)
31548 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112	UINT32_C(0x1000)
31550 	#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112	UINT32_C(0x2000)
31585 	 * * 0x0-0xFFF8 - The function ID
31586 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31587 	 * * 0xFFFD - Reserved for user-space HWRM interface
31588 	 * * 0xFFFF - HWRM
31604 	#define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET	UINT32_C(0x1)
31609 	#define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_BANK_NUMBER	UINT32_C(0x2)
31676 	 * * 0x0-0xFFF8 - The function ID
31677 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31678 	 * * 0xFFFD - Reserved for user-space HWRM interface
31679 	 * * 0xFFFF - HWRM
31695 	#define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET	UINT32_C(0x1)
31700 	#define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_BANK_NUMBER	UINT32_C(0x2)
31767 	 * * 0x0-0xFFF8 - The function ID
31768 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31769 	 * * 0xFFFD - Reserved for user-space HWRM interface
31770 	 * * 0xFFFF - HWRM
31784 	/* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
31794 	 * when this bit is set to 0 a Clause 22 mdio access is done.
31846 	 * * 0x0-0xFFF8 - The function ID
31847 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31848 	 * * 0xFFFD - Reserved for user-space HWRM interface
31849 	 * * 0xFFFF - HWRM
31863 	/* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
31871 	 * when this bit is set to 0 a Clause 22 mdio access is done.
31925 	 * * 0x0-0xFFF8 - The function ID
31926 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31927 	 * * 0xFFFD - Reserved for user-space HWRM interface
31928 	 * * 0xFFFF - HWRM
31943 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID		UINT32_C(0x1)
31948 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE	UINT32_C(0x2)
31953 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR	UINT32_C(0x4)
31958 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON	UINT32_C(0x8)
31963 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF	UINT32_C(0x10)
31968 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID	UINT32_C(0x20)
31973 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID		UINT32_C(0x40)
31978 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE	UINT32_C(0x80)
31983 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR	UINT32_C(0x100)
31988 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON	UINT32_C(0x200)
31993 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF	UINT32_C(0x400)
31998 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID	UINT32_C(0x800)
32003 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID		UINT32_C(0x1000)
32008 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE	UINT32_C(0x2000)
32013 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR	UINT32_C(0x4000)
32018 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON	UINT32_C(0x8000)
32023 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF	UINT32_C(0x10000)
32028 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID	UINT32_C(0x20000)
32033 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID		UINT32_C(0x40000)
32038 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE	UINT32_C(0x80000)
32043 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR	UINT32_C(0x100000)
32048 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON	UINT32_C(0x200000)
32053 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF	UINT32_C(0x400000)
32058 	#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID	UINT32_C(0x800000)
32068 	/* An identifier for the LED #0. */
32070 	/* The requested state of the LED #0. */
32073 	#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT  UINT32_C(0x0)
32075 	#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF	UINT32_C(0x1)
32077 	#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON	UINT32_C(0x2)
32079 	#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK	UINT32_C(0x3)
32081 	#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
32083 	/* The requested color of LED #0. */
32086 	#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT	UINT32_C(0x0)
32088 	#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER	UINT32_C(0x1)
32090 	#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN	UINT32_C(0x2)
32092 	#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
32096 	 * If the LED #0 state is "blink" or "blinkalt", then
32102 	 * If the LED #0 state is "blink" or "blinkalt", then
32108 	 * An identifier for the group of LEDs that LED #0 belongs
32110 	 * If set to 0, then the LED #0 shall not be grouped and
32112 	 * For all other non-zero values of this field, LED #0 shall
32124 	#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT  UINT32_C(0x0)
32126 	#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF	UINT32_C(0x1)
32128 	#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON	UINT32_C(0x2)
32130 	#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK	UINT32_C(0x3)
32132 	#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
32137 	#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT	UINT32_C(0x0)
32139 	#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER	UINT32_C(0x1)
32141 	#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN	UINT32_C(0x2)
32143 	#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
32161 	 * If set to 0, then the LED #1 shall not be grouped and
32175 	#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT  UINT32_C(0x0)
32177 	#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF	UINT32_C(0x1)
32179 	#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON	UINT32_C(0x2)
32181 	#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK	UINT32_C(0x3)
32183 	#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
32188 	#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT	UINT32_C(0x0)
32190 	#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER	UINT32_C(0x1)
32192 	#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN	UINT32_C(0x2)
32194 	#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
32212 	 * If set to 0, then the LED #2 shall not be grouped and
32226 	#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT  UINT32_C(0x0)
32228 	#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF	UINT32_C(0x1)
32230 	#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON	UINT32_C(0x2)
32232 	#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK	UINT32_C(0x3)
32234 	#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
32239 	#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT	UINT32_C(0x0)
32241 	#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER	UINT32_C(0x1)
32243 	#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN	UINT32_C(0x2)
32245 	#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
32263 	 * If set to 0, then the LED #3 shall not be grouped and
32319 	 * * 0x0-0xFFF8 - The function ID
32320 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32321 	 * * 0xFFFD - Reserved for user-space HWRM interface
32322 	 * * 0xFFFF - HWRM
32353 	/* An identifier for the LED #0. */
32355 	/* The type of LED #0. */
32358 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED	UINT32_C(0x0)
32360 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
32362 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID  UINT32_C(0xff)
32364 	/* The current state of the LED #0. */
32367 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT  UINT32_C(0x0)
32369 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF	UINT32_C(0x1)
32371 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON	UINT32_C(0x2)
32373 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK	UINT32_C(0x3)
32375 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
32377 	/* The color of LED #0. */
32380 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT	UINT32_C(0x0)
32382 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER	UINT32_C(0x1)
32384 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN	UINT32_C(0x2)
32386 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
32390 	 * If the LED #0 state is "blink" or "blinkalt", then
32396 	 * If the LED #0 state is "blink" or "blinkalt", then
32402 	 * An identifier for the group of LEDs that LED #0 belongs
32404 	 * If set to 0, then the LED #0 is not grouped.
32405 	 * For all other non-zero values of this field, LED #0 is
32415 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED	UINT32_C(0x0)
32417 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
32419 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID  UINT32_C(0xff)
32424 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT  UINT32_C(0x0)
32426 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF	UINT32_C(0x1)
32428 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON	UINT32_C(0x2)
32430 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK	UINT32_C(0x3)
32432 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
32437 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT	UINT32_C(0x0)
32439 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER	UINT32_C(0x1)
32441 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN	UINT32_C(0x2)
32443 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
32461 	 * If set to 0, then the LED #1 is not grouped.
32472 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED	UINT32_C(0x0)
32474 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
32476 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID  UINT32_C(0xff)
32481 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT  UINT32_C(0x0)
32483 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF	UINT32_C(0x1)
32485 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON	UINT32_C(0x2)
32487 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK	UINT32_C(0x3)
32489 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
32494 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT	UINT32_C(0x0)
32496 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER	UINT32_C(0x1)
32498 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN	UINT32_C(0x2)
32500 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
32518 	 * If set to 0, then the LED #2 is not grouped.
32529 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED	UINT32_C(0x0)
32531 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
32533 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID  UINT32_C(0xff)
32538 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT  UINT32_C(0x0)
32540 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF	UINT32_C(0x1)
32542 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON	UINT32_C(0x2)
32544 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK	UINT32_C(0x3)
32546 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
32551 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT	UINT32_C(0x0)
32553 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER	UINT32_C(0x1)
32555 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN	UINT32_C(0x2)
32557 	#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
32575 	 * If set to 0, then the LED #3 is not grouped.
32615 	 * * 0x0-0xFFF8 - The function ID
32616 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32617 	 * * 0xFFFD - Reserved for user-space HWRM interface
32618 	 * * 0xFFFF - HWRM
32651 	/* An identifier for the LED #0. */
32653 	/* The type of LED #0. */
32656 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED	UINT32_C(0x0)
32658 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
32660 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID  UINT32_C(0xff)
32663 	 * An identifier for the group of LEDs that LED #0 belongs
32665 	 * If set to 0, then the LED #0 cannot be grouped.
32666 	 * For all other non-zero values of this field, LED #0 is
32672 	/* The states supported by LED #0. */
32676 	 * If set to 0, this LED is disabled.
32678 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED		UINT32_C(0x1)
32681 	 * If set to 0, off state is not supported on this LED.
32683 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED	UINT32_C(0x2)
32686 	 * If set to 0, on state is not supported on this LED.
32688 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED		UINT32_C(0x4)
32691 	 * If set to 0, blink state is not supported on this LED.
32693 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED	UINT32_C(0x8)
32696 	 * If set to 0, blink_alt state is not supported on this LED.
32698 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED	UINT32_C(0x10)
32699 	/* The colors supported by LED #0. */
32702 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD		UINT32_C(0x1)
32705 	 * If set to 0, Amber color is not supported on this LED.
32707 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED	UINT32_C(0x2)
32710 	 * If set to 0, Green color is not supported on this LED.
32712 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED	UINT32_C(0x4)
32718 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED	UINT32_C(0x0)
32720 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
32722 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID  UINT32_C(0xff)
32727 	 * If set to 0, then the LED #0 cannot be grouped.
32728 	 * For all other non-zero values of this field, LED #0 is
32738 	 * If set to 0, this LED is disabled.
32740 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED		UINT32_C(0x1)
32743 	 * If set to 0, off state is not supported on this LED.
32745 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED	UINT32_C(0x2)
32748 	 * If set to 0, on state is not supported on this LED.
32750 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED		UINT32_C(0x4)
32753 	 * If set to 0, blink state is not supported on this LED.
32755 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED	UINT32_C(0x8)
32758 	 * If set to 0, blink_alt state is not supported on this LED.
32760 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED	UINT32_C(0x10)
32764 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD		UINT32_C(0x1)
32767 	 * If set to 0, Amber color is not supported on this LED.
32769 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED	UINT32_C(0x2)
32772 	 * If set to 0, Green color is not supported on this LED.
32774 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED	UINT32_C(0x4)
32780 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED	UINT32_C(0x0)
32782 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
32784 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID  UINT32_C(0xff)
32787 	 * An identifier for the group of LEDs that LED #0 belongs
32789 	 * If set to 0, then the LED #0 cannot be grouped.
32790 	 * For all other non-zero values of this field, LED #0 is
32800 	 * If set to 0, this LED is disabled.
32802 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED		UINT32_C(0x1)
32805 	 * If set to 0, off state is not supported on this LED.
32807 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED	UINT32_C(0x2)
32810 	 * If set to 0, on state is not supported on this LED.
32812 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED		UINT32_C(0x4)
32815 	 * If set to 0, blink state is not supported on this LED.
32817 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED	UINT32_C(0x8)
32820 	 * If set to 0, blink_alt state is not supported on this LED.
32822 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED	UINT32_C(0x10)
32826 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD		UINT32_C(0x1)
32829 	 * If set to 0, Amber color is not supported on this LED.
32831 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED	UINT32_C(0x2)
32834 	 * If set to 0, Green color is not supported on this LED.
32836 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED	UINT32_C(0x4)
32842 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED	UINT32_C(0x0)
32844 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
32846 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID  UINT32_C(0xff)
32851 	 * If set to 0, then the LED #0 cannot be grouped.
32852 	 * For all other non-zero values of this field, LED #0 is
32862 	 * If set to 0, this LED is disabled.
32864 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED		UINT32_C(0x1)
32867 	 * If set to 0, off state is not supported on this LED.
32869 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED	UINT32_C(0x2)
32872 	 * If set to 0, on state is not supported on this LED.
32874 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED		UINT32_C(0x4)
32877 	 * If set to 0, blink state is not supported on this LED.
32879 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED	UINT32_C(0x8)
32882 	 * If set to 0, blink_alt state is not supported on this LED.
32884 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED	UINT32_C(0x10)
32888 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD		UINT32_C(0x1)
32891 	 * If set to 0, Amber color is not supported on this LED.
32893 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED	UINT32_C(0x2)
32896 	 * If set to 0, Green color is not supported on this LED.
32898 	#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED	UINT32_C(0x4)
32933 	 * * 0x0-0xFFF8 - The function ID
32934 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32935 	 * * 0xFFFD - Reserved for user-space HWRM interface
32936 	 * * 0xFFFF - HWRM
32960 	#define HWRM_PORT_PRBS_TEST_INPUT_FLAGS_INTERNAL	UINT32_C(0x1)
32967 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7   UINT32_C(0x0)
32969 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9   UINT32_C(0x1)
32971 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11  UINT32_C(0x2)
32973 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15  UINT32_C(0x3)
32975 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23  UINT32_C(0x4)
32977 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31  UINT32_C(0x5)
32979 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58  UINT32_C(0x6)
32981 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS49  UINT32_C(0x7)
32983 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS10  UINT32_C(0x8)
32985 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS20  UINT32_C(0x9)
32987 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS13  UINT32_C(0xa)
32989 	#define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
32995 	 * if set to 0 test will be run on all lanes.
32999 	 * Set 0 to stop test currently in progress
33002 	#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP		UINT32_C(0x1)
33005 	 * If set to 0, test will be run on all lanes for this port.
33007 	#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID	UINT32_C(0x2)
33010 	 * If set to 0, test will be run on all lanes for this port.
33012 	#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID	UINT32_C(0x4)
33013 	/* If set to 1, FEC stat t-code 0-7 registers are enabled. */
33014 	#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T0_T7	UINT32_C(0x8)
33019 	#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T8_T15	UINT32_C(0x10)
33021 	#define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_T_CODE		UINT32_C(0x20)
33054 	#define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_PRBS UINT32_C(0x0)
33056 	#define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC  UINT32_C(0x1)
33093 	 * * 0x0-0xFFF8 - The function ID
33094 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33095 	 * * 0xFFFD - Reserved for user-space HWRM interface
33096 	 * * 0xFFFF - HWRM
33128 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE	UINT32_C(0x0)
33130 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE	UINT32_C(0x1)
33132 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT	UINT32_C(0x2)
33134 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE	UINT32_C(0x3)
33136 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE   UINT32_C(0x4)
33138 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE   UINT32_C(0x5)
33140 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE	UINT32_C(0x6)
33142 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE	UINT32_C(0x7)
33144 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG UINT32_C(0x8)
33146 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT   UINT32_C(0x9)
33148 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ   UINT32_C(0xa)
33150 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE UINT32_C(0xb)
33152 	#define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP  UINT32_C(0xc)
33156 	 * If this is 0xFFFF, the dsc dump will be collected for all lanes,
33163 	 * Set 0 to retrieve the dsc dump
33169 	#define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE	UINT32_C(0x1)
33171 	 * Set 0 to limit the report size to 65535 bytes.
33174 	 * If this is set 0 in the start operation, the firmware will
33184 	#define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_BIG_BUFFER	UINT32_C(0x2)
33186 	 * Set 0 on the last 'retrieve' to release the firmware buffer
33196 	#define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_DEFER_CLOSE	UINT32_C(0x4)
33247 	#define HWRM_PORT_DSC_DUMP_OUTPUT_FLAGS_BIG_BUFFER	UINT32_C(0x1)
33281 	 * * 0x0-0xFFF8 - The function ID
33282 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33283 	 * * 0xFFFD - Reserved for user-space HWRM interface
33284 	 * * 0xFFFF - HWRM
33303 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0	UINT32_C(0x1)
33305 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1	UINT32_C(0x2)
33307 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS	UINT32_C(0x4)
33312 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL	UINT32_C(0x8)
33314 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L	UINT32_C(0x10)
33316 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE	UINT32_C(0x20)
33318 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS	UINT32_C(0x40)
33330 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0	UINT32_C(0x1)
33336 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1	UINT32_C(0x2)
33342 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS	UINT32_C(0x4)
33347 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL	UINT32_C(0x8)
33349 	 * If reset_l is set to 0, Module will be taken out of reset
33354 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L	UINT32_C(0x10)
33360 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE	UINT32_C(0x20)
33362 	#define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS	UINT32_C(0x40)
33410 	 * * 0x0-0xFFF8 - The function ID
33411 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33412 	 * * 0xFFFD - Reserved for user-space HWRM interface
33413 	 * * 0xFFFF - HWRM
33446 	#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS	UINT32_C(0x1)
33451 	#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS	UINT32_C(0x2)
33457 	#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0	UINT32_C(0x4)
33463 	#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1	UINT32_C(0x8)
33469 	#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS	UINT32_C(0x10)
33471 	#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT	UINT32_C(0x20)
33476 	#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL	UINT32_C(0x40)
33478 	 * When this bit is set to '0', the module is held in reset.
33483 	#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L	UINT32_C(0x80)
33488 	#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE	UINT32_C(0x100)
33490 	#define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS	UINT32_C(0x200)
33525 	 * * 0x0-0xFFF8 - The function ID
33526 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33527 	 * * 0xFFFD - Reserved for user-space HWRM interface
33528 	 * * 0xFFFF - HWRM
33542 	 * Any value from 0x10 to 0xFFFF can be used.
33545 	 * 0-0xF are reserved for internal use.
33552 	 * A 0xFFFF will hold the bus until this bus is released.
33572 	 * 0-0xF are reserved for internal use.
33609 	 * * 0x0-0xFFF8 - The function ID
33610 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33611 	 * * 0xFFFD - Reserved for user-space HWRM interface
33612 	 * * 0xFFFF - HWRM
33680 	 * * 0x0-0xFFF8 - The function ID
33681 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33682 	 * * 0xFFFD - Reserved for user-space HWRM interface
33683 	 * * 0xFFFF - HWRM
33696 	#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ	UINT32_C(0x0)
33698 	#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4	UINT32_C(0x1)
33700 	#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_NRZ	UINT32_C(0x2)
33702 	#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_PAM4	UINT32_C(0x3)
33704 	#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4_112	UINT32_C(0x4)
33706 	#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_PAM4_112G UINT32_C(0x5)
33708 	#define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LPO_PAM4_112G UINT32_C(0x6)
33769 	 * * 0x0-0xFFF8 - The function ID
33770 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33771 	 * * 0xFFFD - Reserved for user-space HWRM interface
33772 	 * * 0xFFFF - HWRM
33785 	#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ	UINT32_C(0x0)
33787 	#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4	UINT32_C(0x1)
33789 	#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_NRZ	UINT32_C(0x2)
33791 	#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_PAM4	UINT32_C(0x3)
33793 	#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4_112	UINT32_C(0x4)
33795 	#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_PAM4_112 UINT32_C(0x5)
33797 	#define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LPO_PAM4_112 UINT32_C(0x6)
33857 	 * * 0x0-0xFFF8 - The function ID
33858 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33859 	 * * 0xFFFD - Reserved for user-space HWRM interface
33860 	 * * 0xFFFF - HWRM
33872 	#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW	UINT32_C(0x1)
33874 	#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW	UINT32_C(0x2)
33876 	#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW	UINT32_C(0x4)
33878 	#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW	UINT32_C(0x8)
33880 	#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW	UINT32_C(0x10)
33882 	#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW	UINT32_C(0x20)
33884 	#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW	UINT32_C(0x40)
33886 	#define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW	UINT32_C(0x80)
33887 	/* A port index, from 0 to the number of front panel ports, minus 1. */
33892 	 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
33893 	 * the specified port. The range is 0 to 100. A value of 0 indicates no
33901 	 * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
33902 	 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33909 	 * the specified port. The range is 0 to 100. A value of 0 indicates no
33918 	 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33925 	 * the specified port. The range is 0 to 100. A value of 0 indicates no
33934 	 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33941 	 * the specified port. The range is 0 to 100. A value of 0 indicates no
33950 	 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33989 	#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN		UINT32_C(0x0)
33991 	#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID	UINT32_C(0x1)
33993 	#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE	UINT32_C(0x2)
33995 	#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE	UINT32_C(0x3)
34000 	#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX  UINT32_C(0x4)
34002 	#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM	UINT32_C(0x5)
34007 	#define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED UINT32_C(0x6)
34035 	 * * 0x0-0xFFF8 - The function ID
34036 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34037 	 * * 0xFFFD - Reserved for user-space HWRM interface
34038 	 * * 0xFFFF - HWRM
34066 	 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
34067 	 * the specified port. The range is 0 to 100. A value of 0 indicates no
34075 	 * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
34076 	 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
34083 	 * the specified port. The range is 0 to 100. A value of 0 indicates no
34092 	 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
34099 	 * the specified port. The range is 0 to 100. A value of 0 indicates no
34108 	 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
34115 	 * the specified port. The range is 0 to 100. A value of 0 indicates no
34124 	 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
34163 	 * * 0x0-0xFFF8 - The function ID
34164 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34165 	 * * 0xFFFD - Reserved for user-space HWRM interface
34166 	 * * 0xFFFF - HWRM
34182 	#define HWRM_PORT_CFG_INPUT_ENABLES_TX_RATE_LIMIT	UINT32_C(0x1)
34188 	 * tx_rate_limit = 0 will cancel the rate limit if any.
34240 	 * * 0x0-0xFFF8 - The function ID
34241 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34242 	 * * 0xFFFD - Reserved for user-space HWRM interface
34243 	 * * 0xFFFF - HWRM
34274 	#define HWRM_PORT_QCFG_OUTPUT_SUPPORTED_TX_RATE_LIMIT	UINT32_C(0x1)
34280 	#define HWRM_PORT_QCFG_OUTPUT_ENABLED_TX_RATE_LIMIT	UINT32_C(0x1)
34321 	 * * 0x0-0xFFF8 - The function ID
34322 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34323 	 * * 0xFFFD - Reserved for user-space HWRM interface
34324 	 * * 0xFFFF - HWRM
34356 	#define HWRM_PORT_MAC_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED	UINT32_C(0x1)
34361 	#define HWRM_PORT_MAC_QCAPS_OUTPUT_FLAGS_REMOTE_LPBK_SUPPORTED	UINT32_C(0x2)
34396 	 * * 0x0-0xFFF8 - The function ID
34397 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34398 	 * * 0xFFFD - Reserved for user-space HWRM interface
34399 	 * * 0xFFFF - HWRM
34414 	#define HWRM_PORT_POE_CFG_INPUT_FLAGS_ENABLE_POE	UINT32_C(0x1)
34463 	 * * 0x0-0xFFF8 - The function ID
34464 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34465 	 * * 0xFFFD - Reserved for user-space HWRM interface
34466 	 * * 0xFFFF - HWRM
34495 	#define HWRM_PORT_POE_QCFG_OUTPUT_STATUS_POE_ENABLED	UINT32_C(0x1)
34530 	 * * 0x0-0xFFF8 - The function ID
34531 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34532 	 * * 0xFFFD - Reserved for user-space HWRM interface
34533 	 * * 0xFFFF - HWRM
34549 	#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH	UINT32_C(0x1)
34551 		#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
34553 		#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
34566 	#define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
34568 	#define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED  UINT32_C(0x1)
34593 	 * Valid values range from 0 through 8.
34600 	 * Each bit represents a specific queue where bit 0 represents
34601 	 * queue 0 and bit 7 represents queue 7.
34602 	 * # A value of 0 indicates that the queue is not configurable
34614 	 * If this flag is set to '0', then the queues are
34621 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG		UINT32_C(0x1)
34627 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE	UINT32_C(0x2)
34632 	 * Each bit represents a specific priority where bit 0 represents
34633 	 * priority 0 and bit 7 represents priority 7.
34634 	 * # A value of 0 indicates that the priority is not configurable by
34645 	 * Each bit represents a specific queue where bit 0 represents
34646 	 * queue 0 and bit 7 represents queue 7.
34647 	 * # A value of 0 indicates that the queue is not configurable
34658 	 * Each bit represents a specific queue where bit 0 represents
34659 	 * queue 0 and bit 7 represents queue 7.
34660 	 * # A value of 0 indicates that the queue is not configurable
34668 	 * ID of CoS Queue 0.
34676 	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
34679 	 * # A value of 0xff indicates that the queue is not available.
34686 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY	UINT32_C(0x0)
34688 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS	UINT32_C(0x1)
34690 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE  UINT32_C(0x1)
34692 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
34694 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC   UINT32_C(0x3)
34695 	/* Set to 0xFF... (All Fs) if there is no service profile specified */
34696 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN	UINT32_C(0xff)
34707 	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
34710 	 * # A value of 0xff indicates that the queue is not available.
34717 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY	UINT32_C(0x0)
34719 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS	UINT32_C(0x1)
34721 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE  UINT32_C(0x1)
34723 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
34725 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC   UINT32_C(0x3)
34726 	/* Set to 0xFF... (All Fs) if there is no service profile specified */
34727 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN	UINT32_C(0xff)
34738 	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
34741 	 * # A value of 0xff indicates that the queue is not available.
34748 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY	UINT32_C(0x0)
34750 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS	UINT32_C(0x1)
34752 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE  UINT32_C(0x1)
34754 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
34756 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC   UINT32_C(0x3)
34757 	/* Set to 0xFF... (All Fs) if there is no service profile specified */
34758 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN	UINT32_C(0xff)
34769 	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
34772 	 * # A value of 0xff indicates that the queue is not available.
34779 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY	UINT32_C(0x0)
34781 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS	UINT32_C(0x1)
34783 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE  UINT32_C(0x1)
34785 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
34787 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC   UINT32_C(0x3)
34788 	/* Set to 0xFF... (All Fs) if there is no service profile specified */
34789 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN	UINT32_C(0xff)
34800 	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
34803 	 * # A value of 0xff indicates that the queue is not available.
34810 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY	UINT32_C(0x0)
34812 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS	UINT32_C(0x1)
34814 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE  UINT32_C(0x1)
34816 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
34818 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC   UINT32_C(0x3)
34819 	/* Set to 0xFF... (All Fs) if there is no service profile specified */
34820 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN	UINT32_C(0xff)
34831 	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
34834 	 * # A value of 0xff indicates that the queue is not available.
34841 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY	UINT32_C(0x0)
34843 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS	UINT32_C(0x1)
34845 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE  UINT32_C(0x1)
34847 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
34849 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC   UINT32_C(0x3)
34850 	/* Set to 0xFF... (All Fs) if there is no service profile specified */
34851 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN	UINT32_C(0xff)
34862 	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
34865 	 * # A value of 0xff indicates that the queue is not available.
34872 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY	UINT32_C(0x0)
34874 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS	UINT32_C(0x1)
34876 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE  UINT32_C(0x1)
34878 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
34880 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC   UINT32_C(0x3)
34881 	/* Set to 0xFF... (All Fs) if there is no service profile specified */
34882 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN	UINT32_C(0xff)
34893 	 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
34896 	 * # A value of 0xff indicates that the queue is not available.
34903 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY	UINT32_C(0x0)
34905 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS	UINT32_C(0x1)
34907 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE  UINT32_C(0x1)
34909 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
34911 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC   UINT32_C(0x3)
34912 	/* Set to 0xFF... (All Fs) if there is no service profile specified */
34913 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN	UINT32_C(0xff)
34918 	 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34923 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE	UINT32_C(0x1)
34925 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC	UINT32_C(0x2)
34927 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP	UINT32_C(0x4)
34951 	 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34956 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE	UINT32_C(0x1)
34958 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC	UINT32_C(0x2)
34960 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP	UINT32_C(0x4)
34964 	 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34969 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE	UINT32_C(0x1)
34971 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC	UINT32_C(0x2)
34973 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP	UINT32_C(0x4)
34977 	 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34982 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE	UINT32_C(0x1)
34984 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC	UINT32_C(0x2)
34986 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP	UINT32_C(0x4)
34990 	 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34995 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE	UINT32_C(0x1)
34997 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC	UINT32_C(0x2)
34999 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP	UINT32_C(0x4)
35003 	 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
35008 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE	UINT32_C(0x1)
35010 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC	UINT32_C(0x2)
35012 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP	UINT32_C(0x4)
35016 	 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
35021 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE	UINT32_C(0x1)
35023 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC	UINT32_C(0x2)
35025 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP	UINT32_C(0x4)
35029 	 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
35034 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE	UINT32_C(0x1)
35036 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC	UINT32_C(0x2)
35038 	#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP	UINT32_C(0x4)
35072 	 * * 0x0-0xFFF8 - The function ID
35073 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35074 	 * * 0xFFFD - Reserved for user-space HWRM interface
35075 	 * * 0xFFFF - HWRM
35091 	#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH	UINT32_C(0x1)
35093 		#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
35095 		#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
35120 	#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY	UINT32_C(0x0)
35122 	#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
35123 	/* Set to 0xFF... (All Fs) if there is no service profile specified */
35124 	#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN  UINT32_C(0xff)
35131 	 * If this flag is set to '0', then this queue is
35134 	#define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG	UINT32_C(0x1)
35169 	 * * 0x0-0xFFF8 - The function ID
35170 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35171 	 * * 0xFFFD - Reserved for user-space HWRM interface
35172 	 * * 0xFFFF - HWRM
35188 	#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
35189 	#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT  0
35191 		#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
35193 		#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
35195 		#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR  UINT32_C(0x2)
35202 	#define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN		UINT32_C(0x1)
35207 	#define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE	UINT32_C(0x2)
35213 	 * Set to 0xFF... (All Fs) to not adjust this value.
35219 	#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY	UINT32_C(0x0)
35221 	#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
35222 	/* Set to 0xFF... (All Fs) if there is no service profile specified */
35223 	#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN  UINT32_C(0xff)
35273 	 * * 0x0-0xFFF8 - The function ID
35274 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35275 	 * * 0xFFFD - Reserved for user-space HWRM interface
35276 	 * * 0xFFFF - HWRM
35307 	/* If set to 1, then PFC is enabled on PRI 0. */
35308 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED		UINT32_C(0x1)
35310 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED		UINT32_C(0x2)
35312 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED		UINT32_C(0x4)
35314 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED		UINT32_C(0x8)
35316 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED		UINT32_C(0x10)
35318 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED		UINT32_C(0x20)
35320 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED		UINT32_C(0x40)
35322 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED		UINT32_C(0x80)
35324 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED	UINT32_C(0x100)
35326 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED	UINT32_C(0x200)
35328 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED	UINT32_C(0x400)
35330 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED	UINT32_C(0x800)
35332 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED	UINT32_C(0x1000)
35334 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED	UINT32_C(0x2000)
35336 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED	UINT32_C(0x4000)
35338 	#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED	UINT32_C(0x8000)
35373 	 * * 0x0-0xFFF8 - The function ID
35374 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35375 	 * * 0xFFFD - Reserved for user-space HWRM interface
35376 	 * * 0xFFFF - HWRM
35387 	/* If set to 1, then PFC is requested to be enabled on PRI 0. */
35388 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED		UINT32_C(0x1)
35390 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED		UINT32_C(0x2)
35392 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED		UINT32_C(0x4)
35394 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED		UINT32_C(0x8)
35396 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED		UINT32_C(0x10)
35398 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED		UINT32_C(0x20)
35400 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED		UINT32_C(0x40)
35402 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED		UINT32_C(0x80)
35404 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED	UINT32_C(0x100)
35406 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED	UINT32_C(0x200)
35408 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED	UINT32_C(0x400)
35410 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED	UINT32_C(0x800)
35412 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED	UINT32_C(0x1000)
35414 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED	UINT32_C(0x2000)
35416 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED	UINT32_C(0x4000)
35418 	#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED	UINT32_C(0x8000)
35473 	 * * 0x0-0xFFF8 - The function ID
35474 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35475 	 * * 0xFFFD - Reserved for user-space HWRM interface
35476 	 * * 0xFFFF - HWRM
35492 	#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH	UINT32_C(0x1)
35494 		#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
35496 		#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
35499 	 * When this bit is set to '0', the query is
35504 	#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN	UINT32_C(0x2)
35526 	 * CoS Queue assigned to priority 0. This value can only
35528 	 * A value of 0xff indicates that no CoS queue is assigned to the
35535 	 * A value of 0xff indicates that no CoS queue is assigned to the
35542 	 * A value of 0xff indicates that no CoS queue is assigned to the
35549 	 * A value of 0xff indicates that no CoS queue is assigned to the
35556 	 * A value of 0xff indicates that no CoS queue is assigned to the
35563 	 * A value of 0xff indicates that no CoS queue is assigned to the
35570 	 * A value of 0xff indicates that no CoS queue is assigned to the
35577 	 * A value of 0xff indicates that no CoS queue is assigned to the
35586 	 * If this flag is set to '0', then PRI to CoS configuration
35589 	#define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG	UINT32_C(0x1)
35624 	 * * 0x0-0xFFF8 - The function ID
35625 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35626 	 * * 0xFFFD - Reserved for user-space HWRM interface
35627 	 * * 0xFFFF - HWRM
35643 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
35644 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT  0
35646 		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
35648 		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
35650 		#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR  UINT32_C(0x2)
35653 	 * When this bit is set to '0', the mapping is requested
35658 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN	UINT32_C(0x4)
35664 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID	UINT32_C(0x1)
35669 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID	UINT32_C(0x2)
35674 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID	UINT32_C(0x4)
35679 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID	UINT32_C(0x8)
35684 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID	UINT32_C(0x10)
35689 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID	UINT32_C(0x20)
35694 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID	UINT32_C(0x40)
35699 	#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID	UINT32_C(0x80)
35707 	 * CoS Queue assigned to priority 0. This value can only
35794 	 * * 0x0-0xFFF8 - The function ID
35795 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35796 	 * * 0xFFFD - Reserved for user-space HWRM interface
35797 	 * * 0xFFFF - HWRM
35827 	/* ID of CoS Queue 0. */
35838 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
35839 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT		0
35841 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE			UINT32_C(0x10000000)
35843 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
35845 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
35848 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
35851 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
35853 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
35855 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
35857 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
35859 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
35861 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
35870 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
35871 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT		0
35873 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE			UINT32_C(0x10000000)
35875 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
35877 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
35880 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
35883 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
35885 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
35887 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
35889 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
35891 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
35893 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
35898 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP		UINT32_C(0x0)
35900 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS		UINT32_C(0x1)
35902 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35904 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
35907 	 * tsa_assign is 0 - Strict Priority (SP)
35908 	 * 0..7 - Valid values.
35926 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
35927 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT		0
35929 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE			UINT32_C(0x10000000)
35931 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
35933 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
35936 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
35939 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
35941 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
35943 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
35945 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
35947 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
35949 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
35958 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
35959 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT		0
35961 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE			UINT32_C(0x10000000)
35963 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
35965 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
35968 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
35971 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
35973 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
35975 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
35977 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
35979 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
35981 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
35986 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP		UINT32_C(0x0)
35988 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS		UINT32_C(0x1)
35990 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35992 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
35995 	 * tsa_assign is 0 - Strict Priority (SP)
35996 	 * 0..7 - Valid values.
36014 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36015 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT		0
36017 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE			UINT32_C(0x10000000)
36019 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36021 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36024 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36027 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36029 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36031 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36033 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36035 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36037 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36046 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36047 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT		0
36049 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE			UINT32_C(0x10000000)
36051 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36053 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36056 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36059 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36061 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36063 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36065 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36067 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36069 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36074 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP		UINT32_C(0x0)
36076 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS		UINT32_C(0x1)
36078 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36080 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
36083 	 * tsa_assign is 0 - Strict Priority (SP)
36084 	 * 0..7 - Valid values.
36102 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36103 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT		0
36105 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE			UINT32_C(0x10000000)
36107 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36109 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36112 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36115 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36117 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36119 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36121 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36123 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36125 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36134 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36135 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT		0
36137 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE			UINT32_C(0x10000000)
36139 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36141 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36144 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36147 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36149 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36151 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36153 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36155 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36157 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36162 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP		UINT32_C(0x0)
36164 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS		UINT32_C(0x1)
36166 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36168 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
36171 	 * tsa_assign is 0 - Strict Priority (SP)
36172 	 * 0..7 - Valid values.
36190 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36191 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT		0
36193 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE			UINT32_C(0x10000000)
36195 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36197 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36200 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36203 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36205 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36207 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36209 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36211 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36213 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36222 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36223 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT		0
36225 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE			UINT32_C(0x10000000)
36227 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36229 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36232 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36235 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36237 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36239 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36241 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36243 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36245 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36250 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP		UINT32_C(0x0)
36252 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS		UINT32_C(0x1)
36254 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36256 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
36259 	 * tsa_assign is 0 - Strict Priority (SP)
36260 	 * 0..7 - Valid values.
36278 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36279 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT		0
36281 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE			UINT32_C(0x10000000)
36283 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36285 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36288 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36291 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36293 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36295 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36297 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36299 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36301 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36310 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36311 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT		0
36313 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE			UINT32_C(0x10000000)
36315 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36317 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36320 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36323 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36325 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36327 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36329 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36331 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36333 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36338 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP		UINT32_C(0x0)
36340 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS		UINT32_C(0x1)
36342 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36344 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
36347 	 * tsa_assign is 0 - Strict Priority (SP)
36348 	 * 0..7 - Valid values.
36366 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36367 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT		0
36369 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE			UINT32_C(0x10000000)
36371 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36373 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36376 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36379 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36381 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36383 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36385 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36387 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36389 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36398 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36399 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT		0
36401 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE			UINT32_C(0x10000000)
36403 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36405 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36408 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36411 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36413 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36415 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36417 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36419 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36421 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36426 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP		UINT32_C(0x0)
36428 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS		UINT32_C(0x1)
36430 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36432 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
36435 	 * tsa_assign is 0 - Strict Priority (SP)
36436 	 * 0..7 - Valid values.
36454 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36455 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT		0
36457 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE			UINT32_C(0x10000000)
36459 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36461 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36464 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36467 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36469 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36471 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36473 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36475 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36477 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36486 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36487 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT		0
36489 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE			UINT32_C(0x10000000)
36491 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36493 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36496 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36499 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36501 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36503 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36505 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36507 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
36509 		#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36514 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP		UINT32_C(0x0)
36516 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS		UINT32_C(0x1)
36518 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36520 	#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
36523 	 * tsa_assign is 0 - Strict Priority (SP)
36524 	 * 0..7 - Valid values.
36567 	 * * 0x0-0xFFF8 - The function ID
36568 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36569 	 * * 0xFFFD - Reserved for user-space HWRM interface
36570 	 * * 0xFFFF - HWRM
36586 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID	UINT32_C(0x1)
36591 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID	UINT32_C(0x2)
36596 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID	UINT32_C(0x4)
36601 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID	UINT32_C(0x8)
36606 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID	UINT32_C(0x10)
36611 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID	UINT32_C(0x20)
36616 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID	UINT32_C(0x40)
36621 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID	UINT32_C(0x80)
36628 	/* ID of CoS Queue 0. */
36638 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36639 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT		0
36641 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE			UINT32_C(0x10000000)
36643 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36645 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36648 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36651 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36653 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36655 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36657 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36659 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
36661 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36670 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36671 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT		0
36673 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE			UINT32_C(0x10000000)
36675 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36677 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36680 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36683 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36685 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36687 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36689 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36691 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
36693 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36698 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP		UINT32_C(0x0)
36700 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS		UINT32_C(0x1)
36702 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36704 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
36707 	 * tsa_assign is 0 - Strict Priority (SP)
36708 	 * 0..7 - Valid values.
36726 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36727 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT		0
36729 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE			UINT32_C(0x10000000)
36731 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36733 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36736 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36739 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36741 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36743 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36745 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36747 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
36749 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36758 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36759 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT		0
36761 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE			UINT32_C(0x10000000)
36763 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36765 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36768 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36771 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36773 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36775 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36777 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36779 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
36781 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36786 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP		UINT32_C(0x0)
36788 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS		UINT32_C(0x1)
36790 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36792 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
36795 	 * tsa_assign is 0 - Strict Priority (SP)
36796 	 * 0..7 - Valid values.
36814 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36815 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT		0
36817 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE			UINT32_C(0x10000000)
36819 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36821 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36824 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36827 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36829 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36831 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36833 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36835 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
36837 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36846 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36847 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT		0
36849 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE			UINT32_C(0x10000000)
36851 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36853 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36856 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36859 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36861 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36863 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36865 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36867 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
36869 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36874 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP		UINT32_C(0x0)
36876 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS		UINT32_C(0x1)
36878 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36880 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
36883 	 * tsa_assign is 0 - Strict Priority (SP)
36884 	 * 0..7 - Valid values.
36902 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36903 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT		0
36905 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE			UINT32_C(0x10000000)
36907 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36909 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36912 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36915 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36917 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36919 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36921 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36923 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
36925 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36934 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36935 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT		0
36937 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE			UINT32_C(0x10000000)
36939 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36941 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
36944 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
36947 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
36949 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
36951 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
36953 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
36955 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
36957 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
36962 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP		UINT32_C(0x0)
36964 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS		UINT32_C(0x1)
36966 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36968 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
36971 	 * tsa_assign is 0 - Strict Priority (SP)
36972 	 * 0..7 - Valid values.
36990 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
36991 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT		0
36993 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE			UINT32_C(0x10000000)
36995 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
36997 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
37000 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
37003 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
37005 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
37007 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
37009 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
37011 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
37013 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
37022 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
37023 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT		0
37025 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE			UINT32_C(0x10000000)
37027 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
37029 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
37032 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
37035 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
37037 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
37039 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
37041 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
37043 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
37045 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
37050 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP		UINT32_C(0x0)
37052 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS		UINT32_C(0x1)
37054 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
37056 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
37059 	 * tsa_assign is 0 - Strict Priority (SP)
37060 	 * 0..7 - Valid values.
37078 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
37079 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT		0
37081 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE			UINT32_C(0x10000000)
37083 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
37085 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
37088 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
37091 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
37093 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
37095 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
37097 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
37099 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
37101 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
37110 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
37111 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT		0
37113 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE			UINT32_C(0x10000000)
37115 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
37117 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
37120 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
37123 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
37125 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
37127 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
37129 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
37131 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
37133 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
37138 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP		UINT32_C(0x0)
37140 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS		UINT32_C(0x1)
37142 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
37144 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
37147 	 * tsa_assign is 0 - Strict Priority (SP)
37148 	 * 0..7 - Valid values.
37166 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
37167 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT		0
37169 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE			UINT32_C(0x10000000)
37171 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
37173 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
37176 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
37179 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
37181 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
37183 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
37185 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
37187 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
37189 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
37198 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
37199 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT		0
37201 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE			UINT32_C(0x10000000)
37203 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
37205 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
37208 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
37211 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
37213 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
37215 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
37217 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
37219 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
37221 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
37226 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP		UINT32_C(0x0)
37228 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS		UINT32_C(0x1)
37230 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
37232 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
37235 	 * tsa_assign is 0 - Strict Priority (SP)
37236 	 * 0..7 - Valid values.
37254 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
37255 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT		0
37257 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE			UINT32_C(0x10000000)
37259 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
37261 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
37264 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
37267 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
37269 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
37271 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
37273 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
37275 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
37277 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
37286 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
37287 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT		0
37289 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE			UINT32_C(0x10000000)
37291 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
37293 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
37296 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
37299 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
37301 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
37303 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
37305 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
37307 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
37309 		#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
37314 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP		UINT32_C(0x0)
37316 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS		UINT32_C(0x1)
37318 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
37320 	#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST  UINT32_C(0xff)
37323 	 * tsa_assign is 0 - Strict Priority (SP)
37324 	 * 0..7 - Valid values.
37381 	 * * 0x0-0xFFF8 - The function ID
37382 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37383 	 * * 0xFFFD - Reserved for user-space HWRM interface
37384 	 * * 0xFFFF - HWRM
37453 	 * * 0x0-0xFFF8 - The function ID
37454 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37455 	 * * 0xFFFD - Reserved for user-space HWRM interface
37456 	 * * 0xFFFF - HWRM
37538 	 * * 0x0-0xFFF8 - The function ID
37539 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37540 	 * * 0xFFFD - Reserved for user-space HWRM interface
37541 	 * * 0xFFFF - HWRM
37554 	 * a mask equal to 0 triggers the firmware to remove a tuple.
37556 	 * prior to Thor a mask can be 0 - 0x3f, while on Thor it can
37557 	 * be 0 or 0x3f.
37562 	#define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI	UINT32_C(0x1)
37568 	#define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI	UINT32_C(0x1)
37633 	 * * 0x0-0xFFF8 - The function ID
37634 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37635 	 * * 0xFFFD - Reserved for user-space HWRM interface
37636 	 * * 0xFFFF - HWRM
37670 	 * Each bit represents a specific pri where bit 0 represents
37671 	 * pri 0 and bit 7 represents pri 7.
37672 	 * # A value of 0 indicates that the pri is not configurable
37718 	 * * 0x0-0xFFF8 - The function ID
37719 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37720 	 * * 0xFFFD - Reserved for user-space HWRM interface
37721 	 * * 0xFFFF - HWRM
37752 	 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
37754 	 * A value of 0xff indicates that no pri is assigned to the
37755 	 * MPLS TC(EXP) 0.
37761 	 * A value of 0xff indicates that no pri is assigned to the
37768 	 * A value of 0xff indicates that no pri is assigned to the
37775 	 * A value of 0xff indicates that no pri is assigned to the
37782 	 * A value of 0xff indicates that no pri is assigned to the
37789 	 * A value of 0xff indicates that no pri is assigned to the
37796 	 * A value of 0xff indicates that no pri is assigned to the
37803 	 * A value of 0xff indicates that no pri is assigned to the
37841 	 * * 0x0-0xFFF8 - The function ID
37842 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37843 	 * * 0xFFFD - Reserved for user-space HWRM interface
37844 	 * * 0xFFFF - HWRM
37859 	#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID	UINT32_C(0x1)
37864 	#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID	UINT32_C(0x2)
37869 	#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID	UINT32_C(0x4)
37874 	#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID	UINT32_C(0x8)
37879 	#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID	UINT32_C(0x10)
37884 	#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID	UINT32_C(0x20)
37889 	#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID	UINT32_C(0x40)
37894 	#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID	UINT32_C(0x80)
37903 	 * pri assigned to MPLS TC(EXP) 0. This value can only
37989 	 * * 0x0-0xFFF8 - The function ID
37990 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37991 	 * * 0xFFFD - Reserved for user-space HWRM interface
37992 	 * * 0xFFFF - HWRM
38061 	 * * 0x0-0xFFF8 - The function ID
38062 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38063 	 * * 0xFFFD - Reserved for user-space HWRM interface
38064 	 * * 0xFFFF - HWRM
38095 	 * User priority assigned to VLAN priority 0. A value of 0xff
38101 	 * User priority assigned to VLAN priority 1. A value of 0xff
38107 	 * User priority assigned to VLAN priority 2. A value of 0xff
38113 	 * User priority assigned to VLAN priority 3. A value of 0xff
38119 	 * User priority assigned to VLAN priority 4. A value of 0xff
38125 	 * User priority assigned to VLAN priority 5. A value of 0xff
38131 	 * User priority assigned to VLAN priority 6. A value of 0xff
38137 	 * User priority assigned to VLAN priority 7. A value of 0xff
38176 	 * * 0x0-0xFFF8 - The function ID
38177 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38178 	 * * 0xFFFD - Reserved for user-space HWRM interface
38179 	 * * 0xFFFF - HWRM
38194 	#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID	UINT32_C(0x1)
38199 	#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID	UINT32_C(0x2)
38204 	#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID	UINT32_C(0x4)
38209 	#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID	UINT32_C(0x8)
38214 	#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID	UINT32_C(0x10)
38219 	#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID	UINT32_C(0x20)
38224 	#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID	UINT32_C(0x40)
38229 	#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID	UINT32_C(0x80)
38238 	 * User priority assigned to VLAN priority 0. This value can only
38324 	 * * 0x0-0xFFF8 - The function ID
38325 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38326 	 * * 0xFFFD - Reserved for user-space HWRM interface
38327 	 * * 0xFFFF - HWRM
38344 	#define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED	UINT32_C(0x0)
38349 	#define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1)
38354 	#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE	UINT32_C(0x1)
38356 	 * This bit must be '1' when the maximum bandwidth for queue group 0
38359 	#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW	UINT32_C(0x2)
38364 	#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW	UINT32_C(0x4)
38369 	#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW	UINT32_C(0x8)
38374 	#define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW	UINT32_C(0x10)
38377 	 * bandwidth, of the receive traffic through queue group 0. A value
38378 	 * of 0 indicates no rate limit.
38383 	 * through port 0. In multi-root or multi-host mode, each PCIe endpoint
38386 	 * endpoints, in this case endpoint 0.
38393 	 * value of 0 indicates no rate limit.
38400 	 * value of 0 indicates no rate limit.
38405 	 * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0
38456 	 * * 0x0-0xFFF8 - The function ID
38457 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38458 	 * * 0xFFFD - Reserved for user-space HWRM interface
38459 	 * * 0xFFFF - HWRM
38482 	/* Port or PCIe endpoint id to be mapped for buffer pool 0. */
38490 	/* Size of buffer pool 0 (KBytes). */
38503 	#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING			UINT32_C(0x1)
38505 	 * The buffer_pool_id[0-3]_map field represents mapping of rx
38508 		#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT	UINT32_C(0x0)
38510 	 * The buffer_pool_id[0-3]_map field represents mapping of rx
38513 		#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT  UINT32_C(0x1)
38522 	#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED	UINT32_C(0x0)
38527 	#define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1)
38532 	 * group 0. The rate limit is a percentage of total link bandwidth. A
38533 	 * value of 0 indicates no rate limit.
38538 	 * through port 0. In multi-root or multi-host mode, each PCIe endpoint
38541 	 * endpoints, in this case endpoint 0.
38547 	 * percentage of total link bandwidth. A value of 0 indicates no rate
38554 	 * percentage of total link bandwidth. A value of 0 indicates no rate
38561 	 * percentage of total link bandwidth. A value of 0 indicates no rate
38599 	 * * 0x0-0xFFF8 - The function ID
38600 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38601 	 * * 0xFFFD - Reserved for user-space HWRM interface
38602 	 * * 0xFFFF - HWRM
38628 	 * Each bit represents a specific queue where bit 0 represents
38629 	 * queue 0 and bit 7 represents queue 7.
38630 	 * A value of 0 indicates that the queue is not enabled.
38635 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE	UINT32_C(0x1)
38637 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED  UINT32_C(0x…
38639 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED   UINT32_C(0x…
38642 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE	UINT32_C(0x2)
38644 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED  (UINT32_C(0x0) << 1)
38646 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED   (UINT32_C(0x1) << 1)
38649 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE	UINT32_C(0x4)
38651 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED  (UINT32_C(0x0) << 2)
38653 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED   (UINT32_C(0x1) << 2)
38656 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE	UINT32_C(0x8)
38658 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED  (UINT32_C(0x0) << 3)
38660 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED   (UINT32_C(0x1) << 3)
38663 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE	UINT32_C(0x10)
38665 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED  (UINT32_C(0x0) << 4)
38667 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED   (UINT32_C(0x1) << 4)
38670 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE	UINT32_C(0x20)
38672 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED  (UINT32_C(0x0) << 5)
38674 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED   (UINT32_C(0x1) << 5)
38677 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE	UINT32_C(0x40)
38679 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED  (UINT32_C(0x0) << 6)
38681 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED   (UINT32_C(0x1) << 6)
38684 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE	UINT32_C(0x80)
38686 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED  (UINT32_C(0x0) << 7)
38688 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED   (UINT32_C(0x1) << 7)
38694 	 * where bit 0 represents queue 0 and bit 7 represents queue 7.
38695 	 * A value of 0 indicates that the queue is lossy.
38699 	/* If set to 0, then the queue is lossy, else lossless. */
38700 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE	UINT32_C(0x1)
38702 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSY	UINT32_C(0x0)
38704 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSLESS  UINT32_C(0x1)
38706 	/* If set to 0, then the queue is lossy, else lossless. */
38707 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE	UINT32_C(0x2)
38709 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSY	(UINT32_C(0x0) << 1)
38711 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSLESS  (UINT32_C(0x1) …
38713 	/* If set to 0, then the queue is lossy, else lossless. */
38714 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE	UINT32_C(0x4)
38716 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSY	(UINT32_C(0x0) << 2)
38718 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSLESS  (UINT32_C(0x1) …
38720 	/* If set to 0, then the queue is lossy, else lossless. */
38721 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE	UINT32_C(0x8)
38723 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSY	(UINT32_C(0x0) << 3)
38725 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSLESS  (UINT32_C(0x1) …
38727 	/* If set to 0, then the queue is lossy, else lossless. */
38728 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE	UINT32_C(0x10)
38730 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSY	(UINT32_C(0x0) << 4)
38732 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSLESS  (UINT32_C(0x1) …
38734 	/* If set to 0, then the queue is lossy, else lossless. */
38735 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE	UINT32_C(0x20)
38737 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSY	(UINT32_C(0x0) << 5)
38739 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSLESS  (UINT32_C(0x1) …
38741 	/* If set to 0, then the queue is lossy, else lossless. */
38742 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE	UINT32_C(0x40)
38744 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSY	(UINT32_C(0x0) << 6)
38746 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSLESS  (UINT32_C(0x1) …
38748 	/* If set to 0, then the queue is lossy, else lossless. */
38749 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE	UINT32_C(0x80)
38751 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSY	(UINT32_C(0x0) << 7)
38753 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSLESS  (UINT32_C(0x1) …
38789 	 * * 0x0-0xFFF8 - The function ID
38790 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38791 	 * * 0xFFFD - Reserved for user-space HWRM interface
38792 	 * * 0xFFFF - HWRM
38804 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_ENABLES_QUEUE_ENABLE	UINT32_C(0x1)
38806 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_ENABLES_QUEUE_MODE	UINT32_C(0x2)
38810 	 * Each bit represents a specific queue where bit 0 represents
38811 	 * queue 0 and bit 7 represents queue 7.
38812 	 * A value of 0 indicates that the queue is not enabled.
38817 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE	UINT32_C(0x1)
38819 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED  UINT32_C(0x0)
38821 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED   UINT32_C(0x1)
38824 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE	UINT32_C(0x2)
38826 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED  (UINT32_C(0x0…
38828 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED   (UINT32_C(0x1…
38831 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE	UINT32_C(0x4)
38833 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED  (UINT32_C(0x0…
38835 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED   (UINT32_C(0x1…
38838 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE	UINT32_C(0x8)
38840 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED  (UINT32_C(0x0…
38842 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED   (UINT32_C(0x1…
38845 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE	UINT32_C(0x10)
38847 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED  (UINT32_C(0x0…
38849 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED   (UINT32_C(0x1…
38852 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE	UINT32_C(0x20)
38854 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED  (UINT32_C(0x0…
38856 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED   (UINT32_C(0x1…
38859 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE	UINT32_C(0x40)
38861 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED  (UINT32_C(0x0…
38863 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED   (UINT32_C(0x1…
38866 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE	UINT32_C(0x80)
38868 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED  (UINT32_C(0x0…
38870 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED   (UINT32_C(0x1…
38875 	 * Each bit represents a specific queue where bit 0 represents
38876 	 * queue 0 and bit 7 represents queue 7.
38877 	 * A value of 0 indicates that the queue is lossy.
38881 	/* If set to 0, then the queue is lossy, else lossless. */
38882 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE	UINT32_C(0x1)
38884 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSY	UINT32_C(0x0)
38886 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSLESS  UINT32_C(0x1)
38888 	/* If set to 0, then the queue is lossy, else lossless. */
38889 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE	UINT32_C(0x2)
38891 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSY	(UINT32_C(0x0) << 1)
38893 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSLESS  (UINT32_C(0x1) <<…
38895 	/* If set to 0, then the queue is lossy, else lossless. */
38896 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE	UINT32_C(0x4)
38898 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSY	(UINT32_C(0x0) << 2)
38900 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSLESS  (UINT32_C(0x1) <<…
38902 	/* If set to 0, then the queue is lossy, else lossless. */
38903 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE	UINT32_C(0x8)
38905 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSY	(UINT32_C(0x0) << 3)
38907 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSLESS  (UINT32_C(0x1) <<…
38909 	/* If set to 0, then the queue is lossy, else lossless. */
38910 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE	UINT32_C(0x10)
38912 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSY	(UINT32_C(0x0) << 4)
38914 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSLESS  (UINT32_C(0x1) <<…
38916 	/* If set to 0, then the queue is lossy, else lossless. */
38917 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE	UINT32_C(0x20)
38919 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSY	(UINT32_C(0x0) << 5)
38921 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSLESS  (UINT32_C(0x1) <<…
38923 	/* If set to 0, then the queue is lossy, else lossless. */
38924 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE	UINT32_C(0x40)
38926 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSY	(UINT32_C(0x0) << 6)
38928 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSLESS  (UINT32_C(0x1) <<…
38930 	/* If set to 0, then the queue is lossy, else lossless. */
38931 	#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE	UINT32_C(0x80)
38933 		#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSY	(UINT32_C(0x0) << 7)
38935 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSLESS  (UINT32_C(0x1) <<…
38985 	 * * 0x0-0xFFF8 - The function ID
38986 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38987 	 * * 0xFFFD - Reserved for user-space HWRM interface
38988 	 * * 0xFFFF - HWRM
39014 	 * Each bit represents a specific queue where bit 0 represents
39015 	 * queue 0 and bit 7 represents queue 7.
39016 	 * A value of 0 indicates that the queue is not enabled.
39021 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE	UINT32_C(0x1)
39023 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED  UINT32_C(0x…
39025 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED   UINT32_C(0x…
39028 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE	UINT32_C(0x2)
39030 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED  (UINT32_C(0x0) << 1)
39032 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED   (UINT32_C(0x1) << 1)
39035 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE	UINT32_C(0x4)
39037 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED  (UINT32_C(0x0) << 2)
39039 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED   (UINT32_C(0x1) << 2)
39042 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE	UINT32_C(0x8)
39044 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED  (UINT32_C(0x0) << 3)
39046 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED   (UINT32_C(0x1) << 3)
39049 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE	UINT32_C(0x10)
39051 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED  (UINT32_C(0x0) << 4)
39053 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED   (UINT32_C(0x1) << 4)
39056 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE	UINT32_C(0x20)
39058 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED  (UINT32_C(0x0) << 5)
39060 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED   (UINT32_C(0x1) << 5)
39063 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE	UINT32_C(0x40)
39065 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED  (UINT32_C(0x0) << 6)
39067 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED   (UINT32_C(0x1) << 6)
39070 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE	UINT32_C(0x80)
39072 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED  (UINT32_C(0x0) << 7)
39074 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED   (UINT32_C(0x1) << 7)
39110 	 * * 0x0-0xFFF8 - The function ID
39111 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39112 	 * * 0xFFFD - Reserved for user-space HWRM interface
39113 	 * * 0xFFFF - HWRM
39125 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_ENABLES_QUEUE_ENABLE	UINT32_C(0x1)
39129 	 * Each bit represents a specific queue where bit 0 represents
39130 	 * queue 0 and bit 7 represents queue 7.
39131 	 * A value of 0 indicates that the queue is not enabled.
39136 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE	UINT32_C(0x1)
39138 		#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED  UINT32_C(0x0)
39140 		#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED   UINT32_C(0x1)
39143 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE	UINT32_C(0x2)
39145 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED  (UINT32_C(0x0…
39147 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED   (UINT32_C(0x1…
39150 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE	UINT32_C(0x4)
39152 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED  (UINT32_C(0x0…
39154 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED   (UINT32_C(0x1…
39157 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE	UINT32_C(0x8)
39159 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED  (UINT32_C(0x0…
39161 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED   (UINT32_C(0x1…
39164 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE	UINT32_C(0x10)
39166 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED  (UINT32_C(0x0…
39168 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED   (UINT32_C(0x1…
39171 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE	UINT32_C(0x20)
39173 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED  (UINT32_C(0x0…
39175 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED   (UINT32_C(0x1…
39178 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE	UINT32_C(0x40)
39180 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED  (UINT32_C(0x0…
39182 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED   (UINT32_C(0x1…
39185 	#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE	UINT32_C(0x80)
39187 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED  (UINT32_C(0x0…
39189 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED   (UINT32_C(0x1…
39239 	 * * 0x0-0xFFF8 - The function ID
39240 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39241 	 * * 0xFFFD - Reserved for user-space HWRM interface
39242 	 * * 0xFFFF - HWRM
39270 	 * If set to '0', then the capability to configure queue_enable
39273 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_FEATURE_PARAMS_QUEUE_ENABLE_CAP	UINT32_C(0x1)
39277 	 * If set to '0', then the capability to configure queue_mode
39280 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_FEATURE_PARAMS_QUEUE_MODE_CAP	UINT32_C(0x2)
39286 	 * If set to '0', then the capability to configure queue_enable
39289 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_FEATURE_PARAMS_QUEUE_ENABLE_CAP	UINT32_C(0x1)
39301 	 * If set to '0', then the capability to configure the option
39304 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_WFQ_COST_CAP			UINT32_C(0x1)
39308 	 * If set to '0', then the capability to configure the option
39311 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_WFQ_UPPER_FACTOR_CAP		UINT32_C(0x2)
39315 	 * If set to '0', then the capability to configure the option
39318 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_HYST_WINDOW_SIZE_FACTOR_CAP	UINT32_C(0x4)
39322 	 * If set to '0', then the capability to configure the option
39325 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_PCIE_BW_EFF_CAP		UINT32_C(0x8)
39329 	 * If set to '0', then the capability to configure the option
39332 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_XOFF_HEADROOM_FACTOR_CAP	UINT32_C(0x10)
39336 	 * If set to '0', then the capability to configure the option
39339 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_MIN_LATENCY_CAP		UINT32_C(0x20)
39343 	 * If set to '0', then the capability to configure the option
39346 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_MAX_LATENCY_CAP		UINT32_C(0x40)
39350 	 * If set to '0', then the capability to configure the option
39353 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_MIN_LATENCY_CAP		UINT32_C(0x80)
39357 	 * If set to '0', then the capability to configure the option
39360 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_MAX_LATENCY_CAP		UINT32_C(0x100)
39364 	 * If set to '0', then the capability to configure the option
39367 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_PIPE_COS_LATENCY_CAP	UINT32_C(0x200)
39371 	 * If set to '0', then the capability to configure the option
39374 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_PIPE_COS_LATENCY_CAP	UINT32_C(0x400)
39378 	 * If set to '0', then the capability to configure the option
39381 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_COS_SHARED_MIN_RATIO_CAP	UINT32_C(0x800)
39385 	 * If set to '0', then the capability to configure the option
39388 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_RSVD_CELLS_LIMIT_RATIO_CAP	UINT32_C(0x1000)
39392 	 * If set to '0', then the capability to configure the option
39395 	#define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_SHAPER_REFILL_TIMER_CAP	UINT32_C(0x2000)
39401 	 * If set to '0', then the capability to configure the option
39404 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_WFQ_COST_CAP			UINT32_C(0x1)
39408 	 * If set to '0', then the capability to configure the option
39411 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_WFQ_UPPER_FACTOR_CAP		UINT32_C(0x2)
39415 	 * If set to '0', then the capability to configure the option
39418 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_HYST_WINDOW_SIZE_FACTOR_CAP	UINT32_C(0x4)
39422 	 * If set to '0', then the capability to configure the option
39425 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_RSVD_CELLS_LIMIT_RATIO_CAP	UINT32_C(0x8)
39429 	 * If set to '0', then the capability to configure the option
39432 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_L2_MIN_LATENCY_CAP		UINT32_C(0x10)
39436 	 * If set to '0', then the capability to configure the option
39439 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_L2_MAX_LATENCY_CAP		UINT32_C(0x20)
39443 	 * If set to '0', then the capability to configure the option
39446 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_ROCE_MIN_LATENCY_CAP		UINT32_C(0x40)
39450 	 * If set to '0', then the capability to configure the option
39453 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_ROCE_MAX_LATENCY_CAP		UINT32_C(0x80)
39457 	 * If set to '0', then the capability to configure the option
39460 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_MAX_TBM_CELLS_PRERESERVED_CAP	UINT32_C(0x100)
39464 	 * If set to '0', then the capability to configure the option
39467 	#define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_SHAPER_REFILL_TIMER_CAP	UINT32_C(0x200)
39502 	 * * 0x0-0xFFF8 - The function ID
39503 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39504 	 * * 0xFFFD - Reserved for user-space HWRM interface
39505 	 * * 0xFFFF - HWRM
39542 	 * Specifies PCIe BW efficiency in the range of 0-100%. System
39595 	 * value. Its range of values is 0-50%.
39637 	 * * 0x0-0xFFF8 - The function ID
39638 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39639 	 * * 0xFFFD - Reserved for user-space HWRM interface
39640 	 * * 0xFFFF - HWRM
39652 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_WFQ_COST			UINT32_C(0x1)
39654 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_WFQ_UPPER_FACTOR		UINT32_C(0x2)
39656 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_HYST_WINDOW_SIZE_FACTOR	UINT32_C(0x4)
39658 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_PCIE_BW_EFF		UINT32_C(0x8)
39660 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_XOFF_HEADROOM_FACTOR	UINT32_C(0x10)
39662 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_MIN_LATENCY		UINT32_C(0x20)
39664 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_MAX_LATENCY		UINT32_C(0x40)
39666 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_MIN_LATENCY		UINT32_C(0x80)
39668 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_MAX_LATENCY		UINT32_C(0x100)
39670 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_PIPE_COS_LATENCY	UINT32_C(0x200)
39672 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_PIPE_COS_LATENCY	UINT32_C(0x400)
39674 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_COS_SHARED_MIN_RATIO	UINT32_C(0x800)
39676 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_RSVD_CELLS_LIMIT_RATIO	UINT32_C(0x1000)
39678 	#define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_SHAPER_REFILL_TIMER	UINT32_C(0x2000)
39693 	 * Specifies PCIe BW efficiency in the range of 0-100%. System
39746 	 * value. Its range of values is 0-50%.
39802 	 * * 0x0-0xFFF8 - The function ID
39803 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39804 	 * * 0xFFFD - Reserved for user-space HWRM interface
39805 	 * * 0xFFFF - HWRM
39845 	 * value. Its range of values is 0-50%.
39913 	 * * 0x0-0xFFF8 - The function ID
39914 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39915 	 * * 0xFFFD - Reserved for user-space HWRM interface
39916 	 * * 0xFFFF - HWRM
39928 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_WFQ_COST			UINT32_C(0x1)
39930 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_WFQ_UPPER_FACTOR		UINT32_C(0x2)
39932 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_HYST_WINDOW_SIZE_FACTOR	UINT32_C(0x4)
39934 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_RSVD_CELLS_LIMIT_RATIO	UINT32_C(0x8)
39936 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_L2_MIN_LATENCY		UINT32_C(0x10)
39938 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_L2_MAX_LATENCY		UINT32_C(0x20)
39940 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_ROCE_MIN_LATENCY		UINT32_C(0x40)
39942 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_ROCE_MAX_LATENCY		UINT32_C(0x80)
39944 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_MAX_TBM_CELLS_PRERESERVED	UINT32_C(0x100)
39946 	#define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_SHAPER_REFILL_TIMER	UINT32_C(0x200)
39964 	 * value. Its range of values is 0-50%.
40046 	 * * 0x0-0xFFF8 - The function ID
40047 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40048 	 * * 0xFFFD - Reserved for user-space HWRM interface
40049 	 * * 0xFFFF - HWRM
40108 	 * * 0x0-0xFFF8 - The function ID
40109 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40110 	 * * 0xFFFD - Reserved for user-space HWRM interface
40111 	 * * 0xFFFF - HWRM
40123 	 * A value of 0 means firmware will disable the PFC watchdog.
40124 	 * A value of 0xffff means firmware will reset the timeout
40125 	 * value to Hardware defaults. Anywhere between 0 to 0xffff is
40178 	 * * 0x0-0xFFF8 - The function ID
40179 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40180 	 * * 0xFFFD - Reserved for user-space HWRM interface
40181 	 * * 0xFFFF - HWRM
40206 	 * A value of 0 means PFC watchdog functionality is disabled.
40243 	 * * 0x0-0xFFF8 - The function ID
40244 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40245 	 * * 0xFFFD - Reserved for user-space HWRM interface
40246 	 * * 0xFFFF - HWRM
40261 	#define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT		UINT32_C(0x1)
40267 	#define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID	UINT32_C(0x2)
40324 	 * * 0x0-0xFFF8 - The function ID
40325 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40326 	 * * 0xFFFD - Reserved for user-space HWRM interface
40327 	 * * 0xFFFF - HWRM
40344 	#define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID		UINT32_C(0x1)
40349 	#define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID			UINT32_C(0x2)
40354 	#define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID	UINT32_C(0x4)
40361 	#define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
40363 	#define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP   UINT32_C(0x1)
40373 	#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)
40374 	#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)
40375 	#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)
40376 	#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)
40377 	#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)
40437 	 * * 0x0-0xFFF8 - The function ID
40438 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40439 	 * * 0xFFFD - Reserved for user-space HWRM interface
40440 	 * * 0xFFFF - HWRM
40500 	 * * 0x0-0xFFF8 - The function ID
40501 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40502 	 * * 0xFFFD - Reserved for user-space HWRM interface
40503 	 * * 0xFFFF - HWRM
40518 	#define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT				UINT32_C(0x1)
40522 	 * If set to '0', then VLAN stripping is disabled on
40525 	#define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE			UINT32_C(0x2)
40530 	 * If set to '0', then bd_stall is being configured to be
40533 	#define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE			UINT32_C(0x4)
40537 	 * If set to '0', then this VNIC is not configured to be
40540 	#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE		UINT32_C(0x8)
40544 	 * If this flag is set to '0', then this flag shall be
40550 	#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE		UINT32_C(0x10)
40568 	#define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE			UINT32_C(0x20)
40575 	#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE	UINT32_C(0x40)
40580 	#define HWRM_VNIC_CFG_INPUT_FLAGS_PORTCOS_MAPPING_MODE		UINT32_C(0x80)
40586 	#define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP		UINT32_C(0x1)
40591 	#define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE		UINT32_C(0x2)
40596 	#define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE		UINT32_C(0x4)
40601 	#define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE		UINT32_C(0x8)
40606 	#define HWRM_VNIC_CFG_INPUT_ENABLES_MRU			UINT32_C(0x10)
40611 	#define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID	UINT32_C(0x20)
40616 	#define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID	UINT32_C(0x40)
40618 	#define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID		UINT32_C(0x80)
40623 	#define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE	UINT32_C(0x100)
40625 	#define HWRM_VNIC_CFG_INPUT_ENABLES_L2_CQE_MODE		UINT32_C(0x200)
40635 	 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
40640 	 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
40646 	 * 0xFF... (All Fs) if there is no LB rule.
40700 	#define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
40710 	#define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK  UINT32_C(0x1)
40715 	#define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX	UINT32_C(0x2)
40727 	#define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_DEFAULT	UINT32_C(0x0)
40737 	#define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1)
40744 	#define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED	UINT32_C(0x2)
40794 	 * * 0x0-0xFFF8 - The function ID
40795 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40796 	 * * 0xFFFD - Reserved for user-space HWRM interface
40797 	 * * 0xFFFF - HWRM
40812 	#define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID	UINT32_C(0x1)
40834 	 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
40839 	 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
40845 	 * 0xFF... (All Fs) if there is no LB rule.
40856 	#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT				UINT32_C(0x1)
40860 	 * If set to '0', then VLAN stripping is disabled on
40863 	#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE			UINT32_C(0x2)
40868 	 * If set to '0', then bd_stall is disabled on
40871 	#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE			UINT32_C(0x4)
40875 	 * If set to '0', then this VNIC is not configured to
40878 	#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE		UINT32_C(0x8)
40882 	 * When this flag is set to '0', the VNIC is not configured
40889 	#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE		UINT32_C(0x10)
40903 	#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE			UINT32_C(0x20)
40910 	#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE	UINT32_C(0x40)
40912 	 * When this bit is '0', VNIC is in normal operation state.
40915 	#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE			UINT32_C(0x80)
40917 	#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE		UINT32_C(0x100)
40920 	 * association is valid. Otherwise it will return 0xFFFF to indicate no
40936 	#define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
40942 	#define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK  UINT32_C(0x1)
40947 	#define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX	UINT32_C(0x2)
40959 	#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_DEFAULT	UINT32_C(0x0)
40964 	#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1)
40970 	#define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED	UINT32_C(0x2)
40980 	#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)
40981 	#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)
40982 	#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)
40983 	#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)
40984 	#define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)
40989 	#define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
40991 	#define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP   UINT32_C(0x1)
41027 	 * * 0x0-0xFFF8 - The function ID
41028 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41029 	 * * 0xFFFD - Reserved for user-space HWRM interface
41030 	 * * 0xFFFF - HWRM
41060 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED				UINT32_C(0x1)
41064 	 * If set to '0', then VLAN stripping capability is
41067 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP			UINT32_C(0x2)
41072 	 * If set to '0', then bd_stall capability is not supported
41075 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP				UINT32_C(0x4)
41080 	 * If set to '0', then the capability to receive
41084 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP			UINT32_C(0x8)
41088 	 * When this flag is set to '0', the VNIC capability to
41091 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP			UINT32_C(0x10)
41096 	 * When this bit is set to '0', then a VNIC can not be configured
41100 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP			UINT32_C(0x20)
41104 	 * If set to '0', then the capability to mirror the
41107 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP	UINT32_C(0x40)
41110 	 * is supported. If set to '0', then the outermost RSS hashing
41113 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP			UINT32_C(0x80)
41120 	 * to 1. If set to '0', firmware does not support this feature.
41122 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP			UINT32_C(0x100)
41129 	 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
41132 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP			UINT32_C(0x200)
41136 	 * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not
41139 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP			UINT32_C(0x400)
41144 	 * This capability is available only on Proxy VEE PF. If set to '0',
41147 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP		UINT32_C(0x800)
41151 	 * When this bit is set to '0', then the capability to configure
41155 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP			UINT32_C(0x1000)
41161 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP		UINT32_C(0x2000)
41166 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP		UINT32_C(0x4000)
41175 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP	UINT32_C(0x8000)
41184 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_XOR_CAP		UINT32_C(0x10000)
41196 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP	UINT32_C(0x20000)
41201 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP		UINT32_C(0x40000)
41206 	 * be used for the RX rings of the VNIC. If set to '0', the
41209 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V3_CAP			UINT32_C(0x80000)
41215 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP			UINT32_C(0x100000)
41220 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP		UINT32_C(0x200000)
41225 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP		UINT32_C(0x400000)
41230 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP		UINT32_C(0x800000)
41235 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP		UINT32_C(0x1000000)
41239 	 * When outermost_rss_cap is '1' and this bit is '0', the outermost
41242 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP		UINT32_C(0x2000000)
41247 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE			UINT32_C(0x4000000)
41252 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED		UINT32_C(0x8000000)
41254 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP		UINT32_C(0x10000000)
41256 	#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_HW_TUNNEL_TPA_CAP			UINT32_C(0x20000000)
41260 	 * '0' means that both the TPA v2 and v3 are not supported.
41297 	 * * 0x0-0xFFF8 - The function ID
41298 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41299 	 * * 0xFFFD - Reserved for user-space HWRM interface
41300 	 * * 0xFFFF - HWRM
41316 	#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA			UINT32_C(0x1)
41322 	#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA		UINT32_C(0x2)
41328 	#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE		UINT32_C(0x4)
41334 	#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO			UINT32_C(0x8)
41340 	#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN		UINT32_C(0x10)
41347 	#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ	UINT32_C(0x20)
41358 	#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK		UINT32_C(0x40)
41366 	#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK		UINT32_C(0x80)
41370 	 * When this bit is '0', the VNIC shall DMA payload data
41374 	#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO	UINT32_C(0x100)
41380 	#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS	UINT32_C(0x1)
41385 	#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS	UINT32_C(0x2)
41390 	#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER	UINT32_C(0x4)
41392 	#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN	UINT32_C(0x8)
41397 	#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_TNL_TPA_EN	UINT32_C(0x10)
41404 	 * valid values are > 0 and <= 63.
41408 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1   UINT32_C(0x0)
41410 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2   UINT32_C(0x1)
41412 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4   UINT32_C(0x2)
41414 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8   UINT32_C(0x3)
41416 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
41421 	 * supporting TPA v2, this is in unit of 1 and must be > 0
41427 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1   UINT32_C(0x0)
41429 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2   UINT32_C(0x1)
41431 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4   UINT32_C(0x2)
41433 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8   UINT32_C(0x3)
41435 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16  UINT32_C(0x4)
41437 	#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
41448 	 * should be set to 0. The minimum length is set by firmware
41464 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN	UINT32_C(0x1)
41469 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GENEVE	UINT32_C(0x2)
41474 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_NVGRE	UINT32_C(0x4)
41479 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE		UINT32_C(0x8)
41484 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV4		UINT32_C(0x10)
41489 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV6		UINT32_C(0x20)
41494 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE	UINT32_C(0x40)
41499 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1	UINT32_C(0x80)
41504 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE_CUST1	UINT32_C(0x100)
41509 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR1	UINT32_C(0x200)
41514 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR2	UINT32_C(0x400)
41519 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR3	UINT32_C(0x800)
41524 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR4	UINT32_C(0x1000)
41529 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR5	UINT32_C(0x2000)
41534 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR6	UINT32_C(0x4000)
41539 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR7	UINT32_C(0x8000)
41544 	#define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR8	UINT32_C(0x10000)
41593 	 * * 0x0-0xFFF8 - The function ID
41594 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41595 	 * * 0xFFFD - Reserved for user-space HWRM interface
41596 	 * * 0xFFFF - HWRM
41628 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA			UINT32_C(0x1)
41634 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA		UINT32_C(0x2)
41640 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE		UINT32_C(0x4)
41646 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO			UINT32_C(0x8)
41652 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN		UINT32_C(0x10)
41659 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ	UINT32_C(0x20)
41670 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK		UINT32_C(0x40)
41678 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK		UINT32_C(0x80)
41685 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1   UINT32_C(0x0)
41687 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2   UINT32_C(0x1)
41689 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4   UINT32_C(0x2)
41691 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8   UINT32_C(0x3)
41693 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
41701 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1   UINT32_C(0x0)
41703 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2   UINT32_C(0x1)
41705 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4   UINT32_C(0x2)
41707 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8   UINT32_C(0x3)
41709 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16  UINT32_C(0x4)
41711 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7)
41735 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN	UINT32_C(0x1)
41740 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GENEVE	UINT32_C(0x2)
41745 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_NVGRE	UINT32_C(0x4)
41750 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE		UINT32_C(0x8)
41755 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV4		UINT32_C(0x10)
41760 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV6		UINT32_C(0x20)
41765 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE	UINT32_C(0x40)
41770 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1	UINT32_C(0x80)
41775 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE_CUST1	UINT32_C(0x100)
41780 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR1	UINT32_C(0x200)
41785 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR2	UINT32_C(0x400)
41790 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR3	UINT32_C(0x800)
41795 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR4	UINT32_C(0x1000)
41800 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR5	UINT32_C(0x2000)
41805 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR6	UINT32_C(0x4000)
41810 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR7	UINT32_C(0x8000)
41815 	#define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR8	UINT32_C(0x10000)
41850 	 * * 0x0-0xFFF8 - The function ID
41851 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41852 	 * * 0xFFFD - Reserved for user-space HWRM interface
41853 	 * * 0xFFFF - HWRM
41869 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4		UINT32_C(0x1)
41875 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4		UINT32_C(0x2)
41881 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4		UINT32_C(0x4)
41887 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6		UINT32_C(0x8)
41893 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6		UINT32_C(0x10)
41899 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6		UINT32_C(0x20)
41909 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL	UINT32_C(0x40)
41916 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4	UINT32_C(0x80)
41923 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4	UINT32_C(0x100)
41930 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6	UINT32_C(0x200)
41937 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6	UINT32_C(0x400)
41942 	 * Valid values range from 0 to 7.
41948 	 * 0xffff. Only PF can initiate global RSS hash mode setting changes.
41965 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT	UINT32_C(0x1)
41973 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4	UINT32_C(0x2)
41980 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2	UINT32_C(0x4)
41988 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4	UINT32_C(0x8)
41995 	#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2	UINT32_C(0x10)
42014 	#define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE		UINT32_C(0x1)
42026 	#define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE		UINT32_C(0x2)
42031 	#define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT	UINT32_C(0x4)
42040 	#define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ	UINT32_C(0x0)
42048 	#define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_XOR		UINT32_C(0x1)
42058 	#define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM UINT32_C(0x2)
42094 	#define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN		UINT32_C(0x0)
42099 	#define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY UINT32_C(0x1)
42127 	 * * 0x0-0xFFF8 - The function ID
42128 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42129 	 * * 0xFFFD - Reserved for user-space HWRM interface
42130 	 * * 0xFFFF - HWRM
42170 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4		UINT32_C(0x1)
42176 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4		UINT32_C(0x2)
42182 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4		UINT32_C(0x4)
42188 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6		UINT32_C(0x8)
42194 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6		UINT32_C(0x10)
42200 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6		UINT32_C(0x20)
42207 	 * udp_ipv6 hash types. This bit will be '0' if
42208 	 * rss_ipv6_flow_label_cap is '0'.
42210 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6_FLOW_LABEL	UINT32_C(0x40)
42214 	 * AH/IPv4 packets. This bit will be '0' if rss_ipsec_ah_spi_ipv4_cap
42215 	 * is '0'.
42217 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV4	UINT32_C(0x80)
42221 	 * ESP/IPv4 packets. This bit will be '0' if
42222 	 * rss_ipsec_esp_spi_ipv4_cap is '0'.
42224 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV4	UINT32_C(0x100)
42228 	 * AH/IPv6 packets. This bit will be '0' if
42229 	 * rss_ipsec_ah_spi_ipv6_cap is '0'.
42231 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV6	UINT32_C(0x200)
42235 	 * ESP/IPv6 packets. This bit will be '0' if
42236 	 * rss_ipsec_esp_spi_ipv6_cap is '0'.
42238 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV6	UINT32_C(0x400)
42244 	 * the value of 0xffff implies a global RSS configuration query.
42248 	 * and rss_ctx_idx is 0xffff.
42258 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT	UINT32_C(0x1)
42266 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4	UINT32_C(0x2)
42273 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2	UINT32_C(0x4)
42281 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4	UINT32_C(0x8)
42288 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2	UINT32_C(0x10)
42297 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ	UINT32_C(0x0)
42305 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_XOR		UINT32_C(0x1)
42315 	#define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM UINT32_C(0x2)
42351 	 * * 0x0-0xFFF8 - The function ID
42352 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42353 	 * * 0xFFFD - Reserved for user-space HWRM interface
42354 	 * * 0xFFFF - HWRM
42371 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT	UINT32_C(0x1)
42376 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT	UINT32_C(0x2)
42390 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4		UINT32_C(0x4)
42404 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6		UINT32_C(0x8)
42410 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE		UINT32_C(0x10)
42416 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE		UINT32_C(0x20)
42422 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT	UINT32_C(0x40)
42428 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID	UINT32_C(0x1)
42433 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID	UINT32_C(0x2)
42438 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID	UINT32_C(0x4)
42443 	#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID	UINT32_C(0x8)
42534 	 * * 0x0-0xFFF8 - The function ID
42535 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42536 	 * * 0xFFFD - Reserved for user-space HWRM interface
42537 	 * * 0xFFFF - HWRM
42568 	#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT	UINT32_C(0x1)
42573 	#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT	UINT32_C(0x2)
42578 	#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4		UINT32_C(0x4)
42583 	#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6		UINT32_C(0x8)
42588 	#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE		UINT32_C(0x10)
42593 	#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE		UINT32_C(0x20)
42598 	#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC		UINT32_C(0x40)
42604 	#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT	UINT32_C(0x80)
42679 	 * * 0x0-0xFFF8 - The function ID
42680 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42681 	 * * 0xFFFD - Reserved for user-space HWRM interface
42682 	 * * 0xFFFF - HWRM
42741 	 * * 0x0-0xFFF8 - The function ID
42742 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42743 	 * * 0xFFFD - Reserved for user-space HWRM interface
42744 	 * * 0xFFFF - HWRM
42804 	 * * 0x0-0xFFF8 - The function ID
42805 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42806 	 * * 0xFFFD - Reserved for user-space HWRM interface
42807 	 * * 0xFFFF - HWRM
42822 	#define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG	UINT32_C(0x2)
42827 	#define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID	UINT32_C(0x8)
42832 	#define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID	UINT32_C(0x20)
42837 	#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID	UINT32_C(0x40)
42842 	#define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID	UINT32_C(0x80)
42847 	#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID	UINT32_C(0x100)
42852 	#define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID		UINT32_C(0x200)
42857 	#define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE	UINT32_C(0x400)
42862 	#define HWRM_RING_ALLOC_INPUT_ENABLES_STEERING_TAG_VALID	UINT32_C(0x800)
42866 	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL   UINT32_C(0x0)
42868 	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX	UINT32_C(0x1)
42870 	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX	UINT32_C(0x2)
42872 	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
42874 	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG	UINT32_C(0x4)
42876 	#define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ	UINT32_C(0x5)
42886 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0)
42888 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4   UINT32_C(0x1)
42890 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8   UINT32_C(0x2)
42892 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12  UINT32_C(0x3)
42894 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16  UINT32_C(0x4)
42896 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24  UINT32_C(0x5)
42898 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32  UINT32_C(0x6)
42900 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48  UINT32_C(0x7)
42902 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64  UINT32_C(0x8)
42904 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96  UINT32_C(0x9)
42906 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa)
42908 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb)
42910 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc)
42912 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd)
42914 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe)
42916 	#define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf)
42922 	 * a 0B or 2B offset from the start of the Rx packet buffer. When
42928 	#define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD			UINT32_C(0x1)
42939 	#define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION	UINT32_C(0x2)
42945 	#define HWRM_RING_ALLOC_INPUT_FLAGS_NQ_DBR_PACING			UINT32_C(0x4)
42958 	#define HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE		UINT32_C(0x8)
42987 	 * For this version of the specification, value other than 0 or
42989 	 * When the page_tbl_depth = 0, then it is treated as a
43047 	#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK	UINT32_C(0xf)
43048 	#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT	0
43053 		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP	UINT32_C(0x1)
43058 		#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ	UINT32_C(0x2)
43061 	#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK		UINT32_C(0xf0)
43066 	 * represents a priority value. If set to 0, then the priority
43070 	 * represents a weight value. If set to 0, then the weight
43074 	#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK UINT32_C(0xff00)
43080 	 * It shall be set to 0.
43091 	 * It shall be set to 0.
43102 	#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK		UINT32_C(0xfffffff)
43103 	#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT		0
43105 	#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE			UINT32_C(0x10000000)
43107 		#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS		(UINT32_C(0x0) << 28)
43109 		#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES		(UINT32_C(0x1) << 28)
43112 	#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
43115 		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
43117 		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
43119 		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
43121 		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
43123 		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
43125 		#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
43136 	#define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
43138 	#define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD   UINT32_C(0x1)
43140 	#define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX   UINT32_C(0x2)
43142 	#define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL   UINT32_C(0x3)
43150 	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE	UINT32_C(0x0)
43155 	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE	UINT32_C(0x1)
43160 	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA  UINT32_C(0x2)
43165 	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA  UINT32_C(0x3)
43170 	#define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
43206 	#define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER UINT32_C(0x0)
43208 	#define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER UINT32_C(0x1)
43244 	 * * 0x0-0xFFF8 - The function ID
43245 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43246 	 * * 0xFFFD - Reserved for user-space HWRM interface
43247 	 * * 0xFFFF - HWRM
43260 	#define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL   UINT32_C(0x0)
43262 	#define HWRM_RING_FREE_INPUT_RING_TYPE_TX	UINT32_C(0x1)
43264 	#define HWRM_RING_FREE_INPUT_RING_TYPE_RX	UINT32_C(0x2)
43266 	#define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
43268 	#define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG	UINT32_C(0x4)
43270 	#define HWRM_RING_FREE_INPUT_RING_TYPE_NQ	UINT32_C(0x5)
43282 	 * If this bit is '0', firmware will not treat ring_id as virtio
43287 	#define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1)
43349 	 * * 0x0-0xFFF8 - The function ID
43350 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43351 	 * * 0xFFFD - Reserved for user-space HWRM interface
43352 	 * * 0xFFFF - HWRM
43365 	#define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL	UINT32_C(0x0)
43367 	#define HWRM_RING_RESET_INPUT_RING_TYPE_TX	UINT32_C(0x1)
43369 	#define HWRM_RING_RESET_INPUT_RING_TYPE_RX	UINT32_C(0x2)
43371 	#define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL   UINT32_C(0x3)
43377 	#define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
43405 	#define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER UINT32_C(0x0)
43407 	#define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER UINT32_C(0x1)
43445 	 * * 0x0-0xFFF8 - The function ID
43446 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43447 	 * * 0xFFFD - Reserved for user-space HWRM interface
43448 	 * * 0xFFFF - HWRM
43461 	#define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
43463 	#define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
43472 	 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
43477 	 * When '0', the received packet will not be padded.
43481 	#define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE		UINT32_C(0x1)
43490 	 * When set to '0', the PCI function on which driver issues
43495 	#define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE		UINT32_C(0x2)
43504 	#define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE	UINT32_C(0x4)
43506 	#define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID			UINT32_C(0x8)
43508 	#define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE		UINT32_C(0x10)
43512 	 * QP context field. When set to '0', no change done to metadata.
43517 	#define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA			UINT32_C(0x20)
43601 	 * * 0x0-0xFFF8 - The function ID
43602 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43603 	 * * 0xFFFD - Reserved for user-space HWRM interface
43604 	 * * 0xFFFF - HWRM
43617 	#define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
43619 	#define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
43641 	 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
43646 	 * When '0', the received packet will not be padded.
43650 	#define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE		UINT32_C(0x1)
43659 	 * When set to '0', the PCI function on which driver issues
43664 	#define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE		UINT32_C(0x2)
43673 	#define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE	UINT32_C(0x4)
43741 	 * * 0x0-0xFFF8 - The function ID
43742 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43743 	 * * 0xFFFD - Reserved for user-space HWRM interface
43744 	 * * 0xFFFF - HWRM
43772 	#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN		UINT32_C(0x1)
43777 	#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX		UINT32_C(0x2)
43782 	#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET			UINT32_C(0x4)
43787 	#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE			UINT32_C(0x8)
43792 	#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR		UINT32_C(0x10)
43797 	#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT	UINT32_C(0x20)
43802 	#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR		UINT32_C(0x40)
43807 	#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT	UINT32_C(0x80)
43812 	#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT		UINT32_C(0x100)
43818 	#define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN	UINT32_C(0x1)
43883 	 * * 0x0-0xFFF8 - The function ID
43884 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43885 	 * * 0xFFFD - Reserved for user-space HWRM interface
43886 	 * * 0xFFFF - HWRM
43899 	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK UINT32_C(0x3)
43900 	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
43903 	 * queue. Set this flag to 0 when querying parameters on a
43906 	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ	UINT32_C(0x4)
43926 	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET	UINT32_C(0x1)
43931 	#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE	UINT32_C(0x2)
43999 	 * * 0x0-0xFFF8 - The function ID
44000 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44001 	 * * 0xFFFD - Reserved for user-space HWRM interface
44002 	 * * 0xFFFF - HWRM
44019 	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET	UINT32_C(0x1)
44024 	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE	UINT32_C(0x2)
44027 	 * notification queue. Set this flag to 0 when configuring
44030 	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ	UINT32_C(0x4)
44075 	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR		UINT32_C(0x1)
44080 …fine HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT	UINT32_C(0x2)
44085 	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR		UINT32_C(0x4)
44090 	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN		UINT32_C(0x8)
44095 	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX		UINT32_C(0x10)
44100 	#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT		UINT32_C(0x20)
44149 	 * * 0x0-0xFFF8 - The function ID
44150 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44151 	 * * 0xFFFD - Reserved for user-space HWRM interface
44152 	 * * 0xFFFF - HWRM
44174 	 * the ring group. If this value is 0xFF... (All Fs), then no
44236 	 * * 0x0-0xFFF8 - The function ID
44237 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44238 	 * * 0xFFFD - Reserved for user-space HWRM interface
44239 	 * * 0xFFFF - HWRM
44299 	 * * 0x0-0xFFF8 - The function ID
44300 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44301 	 * * 0xFFFD - Reserved for user-space HWRM interface
44302 	 * * 0xFFFF - HWRM
44317 	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0	UINT32_C(0x1)
44322 	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1	UINT32_C(0x2)
44327 	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2	UINT32_C(0x4)
44332 	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3	UINT32_C(0x8)
44337 	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4	UINT32_C(0x10)
44342 	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5	UINT32_C(0x20)
44347 	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6	UINT32_C(0x40)
44352 	#define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7	UINT32_C(0x80)
44355 	/* TQM ring 0 page size and level. */
44357 	/* TQM ring 0 PBL indirect levels. */
44358 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK	UINT32_C(0xf)
44359 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT	0
44361 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0	UINT32_C(0x0)
44363 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1	UINT32_C(0x1)
44368 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2	UINT32_C(0x2)
44370 	/* TQM ring 0 page size. */
44371 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK  UINT32_C(0xf0)
44374 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
44376 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
44378 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
44380 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
44382 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
44384 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
44389 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK	UINT32_C(0xf)
44390 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT	0
44392 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0	UINT32_C(0x0)
44394 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1	UINT32_C(0x1)
44399 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2	UINT32_C(0x2)
44402 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK  UINT32_C(0xf0)
44405 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
44407 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
44409 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
44411 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
44413 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
44415 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
44420 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK	UINT32_C(0xf)
44421 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT	0
44423 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0	UINT32_C(0x0)
44425 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1	UINT32_C(0x1)
44430 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2	UINT32_C(0x2)
44433 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK  UINT32_C(0xf0)
44436 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
44438 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
44440 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
44442 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
44444 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
44446 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
44451 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK	UINT32_C(0xf)
44452 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT	0
44454 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0	UINT32_C(0x0)
44456 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1	UINT32_C(0x1)
44461 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2	UINT32_C(0x2)
44464 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK  UINT32_C(0xf0)
44467 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
44469 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
44471 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
44473 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
44475 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
44477 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
44482 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK	UINT32_C(0xf)
44483 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT	0
44485 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0	UINT32_C(0x0)
44487 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1	UINT32_C(0x1)
44492 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2	UINT32_C(0x2)
44495 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK  UINT32_C(0xf0)
44498 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
44500 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
44502 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
44504 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
44506 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
44508 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
44513 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK	UINT32_C(0xf)
44514 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT	0
44516 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0	UINT32_C(0x0)
44518 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1	UINT32_C(0x1)
44523 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2	UINT32_C(0x2)
44526 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK  UINT32_C(0xf0)
44529 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
44531 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
44533 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
44535 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
44537 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
44539 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
44544 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK	UINT32_C(0xf)
44545 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT	0
44547 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0	UINT32_C(0x0)
44549 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1	UINT32_C(0x1)
44554 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2	UINT32_C(0x2)
44557 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK  UINT32_C(0xf0)
44560 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
44562 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
44564 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
44566 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
44568 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
44570 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
44575 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK	UINT32_C(0xf)
44576 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT	0
44578 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0	UINT32_C(0x0)
44580 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1	UINT32_C(0x1)
44585 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2	UINT32_C(0x2)
44588 	#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK  UINT32_C(0xf0)
44591 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
44593 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
44595 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
44597 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
44599 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
44601 		#define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
44603 	/* TQM ring 0 page directory. */
44620 	 * Number of TQM ring 0 entries.
44771 	 * * 0x0-0xFFF8 - The function ID
44772 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44773 	 * * 0xFFFD - Reserved for user-space HWRM interface
44774 	 * * 0xFFFF - HWRM
44791 	 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
44798 	#define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED	UINT32_C(0x1)
44800 	#define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_RESERVATION_ENABLED	UINT32_C(0x2)
44926 	 * * 0x0-0xFFF8 - The function ID
44927 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44928 	 * * 0xFFFD - Reserved for user-space HWRM interface
44929 	 * * 0xFFFF - HWRM
44970 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
44975 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
44980 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
44985 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
45010 	 * * 0x0-0xFFF8 - The function ID
45011 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45012 	 * * 0xFFFD - Reserved for user-space HWRM interface
45013 	 * * 0xFFFF - HWRM
45029 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH		UINT32_C(0x1)
45031 		#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX		UINT32_C(0x0)
45033 		#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX		UINT32_C(0x1)
45039 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK	UINT32_C(0x2)
45044 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP		UINT32_C(0x4)
45051 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST	UINT32_C(0x8)
45056 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK	UINT32_C(0x30)
45059 		#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2  (UINT32_C(0x0) << 4)
45061 		#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2	(UINT32_C(0x1) << 4)
45063 		#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE	(UINT32_C(0x2) << 4)
45068 	 * 0 - legacy behavior, XDP filter is created with L2 filter
45071 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE	UINT32_C(0x40)
45074 	 * pertain to source fields. Setting this flag to 0 indicate the
45078 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID	UINT32_C(0x80)
45084 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR		UINT32_C(0x1)
45089 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK	UINT32_C(0x2)
45094 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN		UINT32_C(0x4)
45099 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK	UINT32_C(0x8)
45104 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN		UINT32_C(0x10)
45109 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK	UINT32_C(0x20)
45114 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR	UINT32_C(0x40)
45119 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK	UINT32_C(0x80)
45124 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN	UINT32_C(0x100)
45129 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK	UINT32_C(0x200)
45134 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN	UINT32_C(0x400)
45139 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK	UINT32_C(0x800)
45144 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE		UINT32_C(0x1000)
45149 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID		UINT32_C(0x2000)
45154 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE	UINT32_C(0x4000)
45159 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID		UINT32_C(0x8000)
45164 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID	UINT32_C(0x10000)
45169 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS	UINT32_C(0x20000)
45174 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS	UINT32_C(0x40000)
45190 	 * A value of 0 will mask the corresponding bit from
45198 	 * A value of 0 will mask the corresponding bit from
45206 	 * A value of 0 will mask the corresponding bit from
45222 	 * A value of 0 will mask the corresponding bit from
45230 	 * A value of 0 will mask the corresponding bit from
45238 	 * A value of 0 will mask the corresponding bit from
45245 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
45247 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF	UINT32_C(0x1)
45249 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF	UINT32_C(0x2)
45251 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC  UINT32_C(0x3)
45253 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG  UINT32_C(0x4)
45255 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE   UINT32_C(0x5)
45257 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO  UINT32_C(0x6)
45259 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG  UINT32_C(0x7)
45278 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL	UINT32_C(0x0)
45280 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN	UINT32_C(0x1)
45282 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE	UINT32_C(0x2)
45284 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE	UINT32_C(0x3)
45286 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP	UINT32_C(0x4)
45288 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE	UINT32_C(0x5)
45290 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS	UINT32_C(0x6)
45292 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT	UINT32_C(0x7)
45294 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE	UINT32_C(0x8)
45296 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
45301 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
45302 	/* Use fixed layer 2 ether type of 0xFFFF */
45303 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
45308 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
45310 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
45312 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL	UINT32_C(0xff)
45333 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER	UINT32_C(0x0)
45335 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER UINT32_C(0x1)
45337 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER UINT32_C(0x2)
45339 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX	UINT32_C(0x3)
45341 	#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN	UINT32_C(0x4)
45373 	 * The flow id value in bit 0-29 is the actual ID of the flow
45376 	 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
45381 	#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
45382 	#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
45384 	#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE	UINT32_C(0x40000000)
45386 	 * If this bit set to 0, then it indicates that the flow is
45389 		#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT	(UINT32_C(0x0) << 30)
45394 		#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT	(UINT32_C(0x1) << 30)
45397 	#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR	UINT32_C(0x80000000)
45398 	/* If this bit set to 0, then it indicates rx flow. */
45399 		#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX	(UINT32_C(0x0) << 31)
45401 		#define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX	(UINT32_C(0x1) << 31)
45438 	 * * 0x0-0xFFF8 - The function ID
45439 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45440 	 * * 0xFFFD - Reserved for user-space HWRM interface
45441 	 * * 0xFFFF - HWRM
45504 	 * * 0x0-0xFFF8 - The function ID
45505 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45506 	 * * 0xFFFD - Reserved for user-space HWRM interface
45507 	 * * 0xFFFF - HWRM
45523 	#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH		UINT32_C(0x1)
45525 		#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX		UINT32_C(0x0)
45527 		#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX		UINT32_C(0x1)
45533 	#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP		UINT32_C(0x2)
45538 	#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK	UINT32_C(0xc)
45541 		#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2	(UINT32_C(0x0) << 2)
45543 		#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2		(UINT32_C(0x1) << 2)
45545 		#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE		(UINT32_C(0x2) << 2)
45551 	#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_MASK	UINT32_C(0x30)
45554 		#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_NO_UPDATE	(UINT32_C(0x0) << 4)
45556 		#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_BYPASS_LKUP	(UINT32_C(0x1) << 4)
45558 		#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_ENABLE_LKUP	(UINT32_C(0x2) << 4)
45563 		#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_RESTORE_FW_OP  (UINT32_C(0x3) << 4)
45570 	#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID		UINT32_C(0x1)
45575 	#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID	UINT32_C(0x2)
45580 	#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_PROF_FUNC		UINT32_C(0x4)
45585 	#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_L2_CONTEXT_ID	UINT32_C(0x8)
45606 	 * Profile TCAM entry for further classification. A value of 0xFFFFFFFF
45614 	 * Lookup entry for further classification. A value of 0xFFFFFFFF
45667 	 * * 0x0-0xFFF8 - The function ID
45668 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45669 	 * * 0xFFFD - Reserved for user-space HWRM interface
45670 	 * * 0xFFFF - HWRM
45687 	#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST		UINT32_C(0x2)
45692 	#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST	UINT32_C(0x4)
45697 	#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST		UINT32_C(0x8)
45734 	#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS	UINT32_C(0x10)
45741 	#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST	UINT32_C(0x20)
45749 	#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY		UINT32_C(0x40)
45757 	#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN	UINT32_C(0x80)
45774 	#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN	UINT32_C(0x100)
45830 	#define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN			UINT32_C(0x0)
45832 	#define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR UINT32_C(0x1)
45860 	 * * 0x0-0xFFF8 - The function ID
45861 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45862 	 * * 0xFFFD - Reserved for user-space HWRM interface
45863 	 * * 0xFFFF - HWRM
45884 	 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
45886 	 * For an individual VLAN entry, the mask value should be 0xfff
45938 	 * * 0x0-0xFFF8 - The function ID
45939 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45940 	 * * 0xFFFD - Reserved for user-space HWRM interface
45941 	 * * 0xFFFF - HWRM
45965 	 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
45968 	 * the mask value should be 0xfff for the 12-bit VLAN ID.
46021 	 * * 0x0-0xFFF8 - The function ID
46022 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46023 	 * * 0xFFFD - Reserved for user-space HWRM interface
46024 	 * * 0xFFFF - HWRM
46039 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK	UINT32_C(0x1)
46045 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID	UINT32_C(0x1)
46050 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR		UINT32_C(0x2)
46055 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN	UINT32_C(0x4)
46060 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR		UINT32_C(0x8)
46065 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE	UINT32_C(0x10)
46070 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE	UINT32_C(0x20)
46075 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR	UINT32_C(0x40)
46080 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE	UINT32_C(0x80)
46085 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI		UINT32_C(0x100)
46090 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID	UINT32_C(0x200)
46095 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID	UINT32_C(0x400)
46140 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL	UINT32_C(0x0)
46142 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN	UINT32_C(0x1)
46144 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE	UINT32_C(0x2)
46146 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE	UINT32_C(0x3)
46148 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP	UINT32_C(0x4)
46150 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE	UINT32_C(0x5)
46152 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS	UINT32_C(0x6)
46154 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT	UINT32_C(0x7)
46156 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE	UINT32_C(0x8)
46158 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
46163 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
46164 	/* Use fixed layer 2 ether type of 0xFFFF */
46165 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
46170 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
46172 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
46174 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL	UINT32_C(0xff)
46189 …#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR	UINT32_C(0x…
46199 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1	UINT32_C(0x2)
46210 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0	UINT32_C(0x4)
46241 	 * The flow id value in bit 0-29 is the actual ID of the flow
46244 	 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
46249 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
46250 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
46252 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE	UINT32_C(0x40000000)
46254 	 * If this bit set to 0, then it indicates that the flow is
46257 		#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT	(UINT32_C(0x0) << 30)
46262 		#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT	(UINT32_C(0x1) << 30)
46265 	#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR	UINT32_C(0x80000000)
46266 	/* If this bit set to 0, then it indicates rx flow. */
46267 		#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX	(UINT32_C(0x0) << 31)
46269 		#define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX	(UINT32_C(0x1) << 31)
46306 	 * * 0x0-0xFFF8 - The function ID
46307 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46308 	 * * 0xFFFD - Reserved for user-space HWRM interface
46309 	 * * 0xFFFF - HWRM
46369 	 * * 0x0-0xFFF8 - The function ID
46370 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46371 	 * * 0xFFFD - Reserved for user-space HWRM interface
46372 	 * * 0xFFFF - HWRM
46387 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL	UINT32_C(0x0)
46389 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN	UINT32_C(0x1)
46391 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE	UINT32_C(0x2)
46393 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE	UINT32_C(0x3)
46395 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP	UINT32_C(0x4)
46397 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE	UINT32_C(0x5)
46399 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS	UINT32_C(0x6)
46401 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT	UINT32_C(0x7)
46403 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE	UINT32_C(0x8)
46405 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
46410 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
46411 	/* Use fixed layer 2 ether type of 0xFFFF */
46412 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
46417 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
46419 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
46421 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL	UINT32_C(0xff)
46429 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST	UINT32_C(0x1)
46479 	 * * 0x0-0xFFF8 - The function ID
46480 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46481 	 * * 0xFFFD - Reserved for user-space HWRM interface
46482 	 * * 0xFFFF - HWRM
46497 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL	UINT32_C(0x0)
46499 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN	UINT32_C(0x1)
46501 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE	UINT32_C(0x2)
46503 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE	UINT32_C(0x3)
46505 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP	UINT32_C(0x4)
46507 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE	UINT32_C(0x5)
46509 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS	UINT32_C(0x6)
46511 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT	UINT32_C(0x7)
46513 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE	UINT32_C(0x8)
46515 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
46520 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
46521 	/* Use fixed layer 2 ether type of 0xFFFF */
46522 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
46527 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
46529 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
46531 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL	UINT32_C(0xff)
46582 	 * * 0x0-0xFFF8 - The function ID
46583 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46584 	 * * 0xFFFD - Reserved for user-space HWRM interface
46585 	 * * 0xFFFF - HWRM
46600 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL	UINT32_C(0x0)
46602 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN	UINT32_C(0x1)
46604 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE	UINT32_C(0x2)
46606 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE	UINT32_C(0x3)
46608 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP	UINT32_C(0x4)
46610 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE	UINT32_C(0x5)
46612 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS	UINT32_C(0x6)
46614 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT	UINT32_C(0x7)
46616 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE	UINT32_C(0x8)
46618 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
46623 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
46624 	/* Use fixed layer 2 ether type of 0xFFFF */
46625 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
46630 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
46632 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
46634 	#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL	UINT32_C(0xff)
46670 	#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
46671 	#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
46673 	#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK	UINT32_C(0xf0)
46697 	#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT	UINT32_C(0x1c)
46699 	#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK	UINT32_C(0xf0000000)
46701 	#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT	UINT32_C(0x14)
46703 	#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK	UINT32_C(0xff00000)
46705 	#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT  UINT32_C(0x0)
46707 	#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK UINT32_C(0xfffff)
46745 	#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
46747 	#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
46749 	#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
46792 	 * * 0x0-0xFFF8 - The function ID
46793 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46794 	 * * 0xFFFD - Reserved for user-space HWRM interface
46795 	 * * 0xFFFF - HWRM
46810 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK	UINT32_C(0x1)
46816 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL	UINT32_C(0x2)
46820 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN	UINT32_C(0x1)
46822 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE	UINT32_C(0x2)
46824 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE	UINT32_C(0x3)
46826 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP	UINT32_C(0x4)
46828 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE	UINT32_C(0x5)
46830 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS	UINT32_C(0x6)
46832 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN	UINT32_C(0x7)
46834 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE	UINT32_C(0x8)
46836 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4	UINT32_C(0x9)
46841 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1	UINT32_C(0xa)
46842 	/* Use fixed layer 2 ether type of 0xFFFF */
46843 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE	UINT32_C(0xb)
46848 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
46850 	#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE	UINT32_C(0x10)
46905 	 * * 0x0-0xFFF8 - The function ID
46906 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46907 	 * * 0xFFFD - Reserved for user-space HWRM interface
46908 	 * * 0xFFFF - HWRM
46969 	 * * 0x0-0xFFF8 - The function ID
46970 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46971 	 * * 0xFFFD - Reserved for user-space HWRM interface
46972 	 * * 0xFFFF - HWRM
46987 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK		UINT32_C(0x1)
46992 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP		UINT32_C(0x2)
46998 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER		UINT32_C(0x4)
47004 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID		UINT32_C(0x8)
47007 	 * is 0x0806. If this is not set it indicates no specific arp opcode
47010 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY		UINT32_C(0x10)
47020 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX	UINT32_C(0x20)
47027 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT	UINT32_C(0x40)
47033 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID	UINT32_C(0x1)
47038 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE		UINT32_C(0x2)
47043 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE	UINT32_C(0x4)
47048 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR	UINT32_C(0x8)
47053 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE	UINT32_C(0x10)
47058 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR	UINT32_C(0x20)
47063 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK	UINT32_C(0x40)
47068 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR	UINT32_C(0x80)
47073 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK	UINT32_C(0x100)
47078 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL	UINT32_C(0x200)
47083 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT		UINT32_C(0x400)
47088 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK	UINT32_C(0x800)
47093 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT		UINT32_C(0x1000)
47098 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK	UINT32_C(0x2000)
47103 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT		UINT32_C(0x4000)
47108 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID	UINT32_C(0x8000)
47113 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID		UINT32_C(0x10000)
47115 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID	UINT32_C(0x20000)
47120 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR	UINT32_C(0x40000)
47125 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX	UINT32_C(0x80000)
47146 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
47148 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4	UINT32_C(0x4)
47150 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6	UINT32_C(0x6)
47163 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
47165 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP	UINT32_C(0x6)
47167 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP	UINT32_C(0x11)
47169 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMP	UINT32_C(0x1)
47171 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMPV6  UINT32_C(0x3a)
47173 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD	UINT32_C(0xff)
47199 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL	UINT32_C(0x0)
47201 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN	UINT32_C(0x1)
47203 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE	UINT32_C(0x2)
47205 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE	UINT32_C(0x3)
47207 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP	UINT32_C(0x4)
47209 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE	UINT32_C(0x5)
47211 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS	UINT32_C(0x6)
47213 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT	UINT32_C(0x7)
47215 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE	UINT32_C(0x8)
47217 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
47222 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
47223 	/* Use fixed layer 2 ether type of 0xFFFF */
47224 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
47229 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
47231 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
47233 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL	UINT32_C(0xff)
47241 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0)
47243 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE	UINT32_C(0x1)
47245 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW	UINT32_C(0x2)
47247 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST   UINT32_C(0x3)
47249 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST	UINT32_C(0x4)
47315 	 * The flow id value in bit 0-29 is the actual ID of the flow
47318 	 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
47323 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
47324 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
47326 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE	UINT32_C(0x40000000)
47328 	 * If this bit set to 0, then it indicates that the flow is
47331 		#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT	(UINT32_C(0x0) << 30)
47336 		#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT	(UINT32_C(0x1) << 30)
47339 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR	UINT32_C(0x80000000)
47340 	/* If this bit set to 0, then it indicates rx flow. */
47341 		#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX	(UINT32_C(0x0) << 31)
47343 		#define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX	(UINT32_C(0x1) << 31)
47366 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN		UINT32_C(0x0)
47368 	#define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR UINT32_C(0x1)
47396 	 * * 0x0-0xFFF8 - The function ID
47397 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47398 	 * * 0xFFFD - Reserved for user-space HWRM interface
47399 	 * * 0xFFFF - HWRM
47459 	 * * 0x0-0xFFF8 - The function ID
47460 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47461 	 * * 0xFFFD - Reserved for user-space HWRM interface
47462 	 * * 0xFFFF - HWRM
47477 	#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID		UINT32_C(0x1)
47482 	#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID	UINT32_C(0x2)
47487 	#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID	UINT32_C(0x4)
47491 	 * Setting this to 0 indicates that dest_id field contains VNIC or
47494 	#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID		UINT32_C(0x1)
47501 	#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX	UINT32_C(0x2)
47508 	#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT	UINT32_C(0x4)
47530 	 * A value of 0xfff is considered invalid and implies the
47533 	#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
47584 	 * * 0x0-0xFFF8 - The function ID
47585 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47586 	 * * 0xFFFD - Reserved for user-space HWRM interface
47587 	 * * 0xFFFF - HWRM
47603 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH	UINT32_C(0x1)
47605 		#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
47607 		#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
47613 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR	UINT32_C(0x2)
47618 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR	UINT32_C(0x4)
47623 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP	UINT32_C(0x8)
47628 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP	UINT32_C(0x10)
47633 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP	UINT32_C(0x20)
47639 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER	UINT32_C(0x40)
47645 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID	UINT32_C(0x1)
47650 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE	UINT32_C(0x2)
47655 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID		UINT32_C(0x4)
47660 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR	UINT32_C(0x8)
47665 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR	UINT32_C(0x10)
47670 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID		UINT32_C(0x20)
47675 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID		UINT32_C(0x40)
47680 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE		UINT32_C(0x80)
47685 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR		UINT32_C(0x100)
47690 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR		UINT32_C(0x200)
47695 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE	UINT32_C(0x400)
47700 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL	UINT32_C(0x800)
47705 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT		UINT32_C(0x1000)
47710 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT		UINT32_C(0x2000)
47715 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID		UINT32_C(0x4000)
47720 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID	UINT32_C(0x8000)
47725 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID	UINT32_C(0x10000)
47730 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID	UINT32_C(0x20000)
47739 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL	UINT32_C(0x0)
47741 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN	UINT32_C(0x1)
47743 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE	UINT32_C(0x2)
47745 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE	UINT32_C(0x3)
47747 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP	UINT32_C(0x4)
47749 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE	UINT32_C(0x5)
47751 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS	UINT32_C(0x6)
47753 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT	UINT32_C(0x7)
47755 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE	UINT32_C(0x8)
47757 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
47762 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
47763 	/* Use fixed layer 2 ether type of 0xFFFF */
47764 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
47769 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
47771 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
47773 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL	UINT32_C(0xff)
47792 	 * A value of 0xfff is considered invalid and implies the
47795 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
47822 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
47824 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4	UINT32_C(0x4)
47826 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6	UINT32_C(0x6)
47836 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
47838 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP	UINT32_C(0x6)
47840 	#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP	UINT32_C(0x11)
47895 	 * The flow id value in bit 0-29 is the actual ID of the flow
47898 	 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
47903 	#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
47904 	#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
47906 	#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE	UINT32_C(0x40000000)
47908 	 * If this bit set to 0, then it indicates that the flow is
47911 		#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT	(UINT32_C(0x0) << 30)
47916 		#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT	(UINT32_C(0x1) << 30)
47919 	#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR	UINT32_C(0x80000000)
47920 	/* If this bit set to 0, then it indicates rx flow. */
47921 		#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX	(UINT32_C(0x0) << 31)
47923 		#define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX	(UINT32_C(0x1) << 31)
47960 	 * * 0x0-0xFFF8 - The function ID
47961 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47962 	 * * 0xFFFD - Reserved for user-space HWRM interface
47963 	 * * 0xFFFF - HWRM
48023 	 * * 0x0-0xFFF8 - The function ID
48024 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48025 	 * * 0xFFFD - Reserved for user-space HWRM interface
48026 	 * * 0xFFFF - HWRM
48041 	#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID		UINT32_C(0x1)
48046 	#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID	UINT32_C(0x2)
48051 	#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID	UINT32_C(0x4)
48074 	 * A value of 0xfff is considered invalid and implies the
48077 	#define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
48128 	 * * 0x0-0xFFF8 - The function ID
48129 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48130 	 * * 0xFFFD - Reserved for user-space HWRM interface
48131 	 * * 0xFFFF - HWRM
48160 	#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK  UINT32_C(0xf)
48161 	#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT   0
48163 		#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ  UINT32_C(0x0)
48165 		#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ  UINT32_C(0x1)
48243 	 * * 0x0-0xFFF8 - The function ID
48244 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48245 	 * * 0xFFFD - Reserved for user-space HWRM interface
48246 	 * * 0xFFFF - HWRM
48262 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH	UINT32_C(0x1)
48264 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
48266 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
48271 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0)
48273 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1)
48275 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2)
48279 	 * It shall be set to 0.
48284 	 * It shall be set to 0.
48290 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK		UINT32_C(0xfffffff)
48291 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT		0
48293 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE			UINT32_C(0x10000000)
48295 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS		(UINT32_C(0x0) << 28)
48297 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES		(UINT32_C(0x1) << 28)
48300 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
48303 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
48305 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
48307 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
48309 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
48311 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) …
48313 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW	(UINT32_C(0x7) << 29)
48318 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK		UINT32_C(0xfffffff)
48319 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT		0
48321 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE			UINT32_C(0x10000000)
48323 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS		(UINT32_C(0x0) << 28)
48325 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES		(UINT32_C(0x1) << 28)
48328 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
48331 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
48333 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
48335 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
48337 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
48339 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1)…
48341 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
48346 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK		UINT32_C(0xfffffff)
48347 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT		0
48349 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE			UINT32_C(0x10000000)
48351 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS		(UINT32_C(0x0) << 28)
48353 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES		(UINT32_C(0x1) << 28)
48356 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
48359 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 2…
48361 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 2…
48363 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 2…
48365 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 2…
48367 …RM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
48369 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW	(UINT32_C(0x7) << 29)
48374 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK		UINT32_C(0xfffffff)
48375 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT		0
48377 	#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE			UINT32_C(0x10000000)
48379 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS		(UINT32_C(0x0) << 28)
48381 		#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES		(UINT32_C(0x1) << 28)
48384 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK	UINT32_C(0xe000000…
48387 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << …
48389 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << …
48391 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << …
48393 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << …
48395 …M_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
48397 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) …
48415 	 * A value of 0xfff is considered invalid and implies the
48418 	#define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
48455 	 * * 0x0-0xFFF8 - The function ID
48456 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48457 	 * * 0xFFFD - Reserved for user-space HWRM interface
48458 	 * * 0xFFFF - HWRM
48474 	#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH	UINT32_C(0x1)
48476 		#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
48478 		#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
48484 	 * A value of 0xfff is considered invalid and implies the
48487 	#define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
48538 	 * * 0x0-0xFFF8 - The function ID
48539 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48540 	 * * 0xFFFD - Reserved for user-space HWRM interface
48541 	 * * 0xFFFF - HWRM
48557 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH	UINT32_C(0x1)
48559 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
48561 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
48566 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0)
48568 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1)
48570 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2)
48575 	 * A value of 0xfff is considered invalid and implies the
48578 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
48582 	 * It shall be set to 0.
48588 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK		UINT32_C(0xfffffff)
48589 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT		0
48591 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE			UINT32_C(0x10000000)
48593 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS		(UINT32_C(0x0) << 28)
48595 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES		(UINT32_C(0x1) << 28)
48598 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
48601 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
48603 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
48605 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
48607 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
48609 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <<…
48611 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW	(UINT32_C(0x7) << 29)
48616 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK		UINT32_C(0xfffffff)
48617 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT		0
48619 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE			UINT32_C(0x10000000)
48621 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS		(UINT32_C(0x0) << 28)
48623 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES		(UINT32_C(0x1) << 28)
48626 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
48629 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
48631 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
48633 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
48635 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
48637 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) <…
48639 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) << 29)
48644 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK		UINT32_C(0xfffffff)
48645 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT		0
48647 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE			UINT32_C(0x10000000)
48649 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS		(UINT32_C(0x0) << 28)
48651 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES		(UINT32_C(0x1) << 28)
48654 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
48657 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
48659 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
48661 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
48663 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
48665 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x…
48667 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW	(UINT32_C(0x7) << 29)
48672 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK		UINT32_C(0xfffffff)
48673 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT		0
48675 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE			UINT32_C(0x10000000)
48677 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS		(UINT32_C(0x0) << 28)
48679 		#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES		(UINT32_C(0x1) << 28)
48682 	#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK	UINT32_C(0xe0000000)
48685 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA	(UINT32_C(0x0) << 29)
48687 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO	(UINT32_C(0x2) << 29)
48689 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE	(UINT32_C(0x4) << 29)
48691 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA	(UINT32_C(0x6) << 29)
48693 …WRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100  (UINT32_C(0x1) << 29)
48695 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID	(UINT32_C(0x7) <<…
48745 	 * * 0x0-0xFFF8 - The function ID
48746 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48747 	 * * 0xFFFD - Reserved for user-space HWRM interface
48748 	 * * 0xFFFF - HWRM
48764 	#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH	UINT32_C(0x1)
48766 		#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
48768 		#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
48774 	 * A value of 0xffff is considered invalid and implies the
48777 	#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
48796 	 * A value of 0xffff is considered invalid and implies the
48799 	#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
48836 	 * * 0x0-0xFFF8 - The function ID
48837 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48838 	 * * 0xFFFD - Reserved for user-space HWRM interface
48839 	 * * 0xFFFF - HWRM
48855 	#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH	UINT32_C(0x1)
48857 		#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
48859 		#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
48868 	 * A value of 0xffff is considered invalid and implies the
48871 	#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
48927 	 * * 0x0-0xFFF8 - The function ID
48928 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48929 	 * * 0xFFFD - Reserved for user-space HWRM interface
48930 	 * * 0xFFFF - HWRM
48946 	#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH	UINT32_C(0x1)
48948 		#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
48950 		#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
48956 	 * A value of 0xfff is considered invalid and implies the
48959 	#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
49010 	 * * 0x0-0xFFF8 - The function ID
49011 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49012 	 * * 0xFFFD - Reserved for user-space HWRM interface
49013 	 * * 0xFFFF - HWRM
49025 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL	UINT32_C(0x1)
49031 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE	UINT32_C(0x1)
49036 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID	UINT32_C(0x2)
49041 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR	UINT32_C(0x4)
49046 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR	UINT32_C(0x8)
49051 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID	UINT32_C(0x10)
49056 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID	UINT32_C(0x20)
49061 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID	UINT32_C(0x40)
49066 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID	UINT32_C(0x80)
49071 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE	UINT32_C(0x100)
49076 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR	UINT32_C(0x200)
49081 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR	UINT32_C(0x400)
49086 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE	UINT32_C(0x800)
49091 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL	UINT32_C(0x1000)
49096 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT	UINT32_C(0x2000)
49101 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT	UINT32_C(0x4000)
49106 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID		UINT32_C(0x8000)
49111 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID	UINT32_C(0x10000)
49123 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL	UINT32_C(0x0)
49125 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN	UINT32_C(0x1)
49127 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE	UINT32_C(0x2)
49129 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE	UINT32_C(0x3)
49131 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP	UINT32_C(0x4)
49133 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE	UINT32_C(0x5)
49135 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS	UINT32_C(0x6)
49137 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT	UINT32_C(0x7)
49139 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE	UINT32_C(0x8)
49141 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
49146 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
49147 	/* Use fixed layer 2 ether type of 0xFFFF */
49148 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
49153 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
49155 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
49157 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL	UINT32_C(0xff)
49202 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
49204 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4	UINT32_C(0x4)
49206 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6	UINT32_C(0x6)
49216 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
49218 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP	UINT32_C(0x6)
49220 	#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP	UINT32_C(0x11)
49305 	 * * 0x0-0xFFF8 - The function ID
49306 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49307 	 * * 0xFFFD - Reserved for user-space HWRM interface
49308 	 * * 0xFFFF - HWRM
49369 	 * * 0x0-0xFFF8 - The function ID
49370 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49371 	 * * 0xFFFD - Reserved for user-space HWRM interface
49372 	 * * 0xFFFF - HWRM
49384 	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL		UINT32_C(0x1)
49386 	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK	UINT32_C(0x6)
49389 		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE		(UINT32_C(0x0) << 1)
49391 		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE		(UINT32_C(0x1) << 1)
49393 		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO		(UINT32_C(0x2) << 1)
49396 	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK	UINT32_C(0x38)
49399 		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2		(UINT32_C(0x0) << 3)
49401 		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4		(UINT32_C(0x1) << 3)
49403 		#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6		(UINT32_C(0x2) << 3)
49415 	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX		UINT32_C(0x40)
49420 	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX		UINT32_C(0x80)
49427 	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI	UINT32_C(0x100)
49432 	#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN	UINT32_C(0x200)
49445 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD			UINT32_C(0x1)
49447 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE		UINT32_C(0x2)
49452 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP			UINT32_C(0x4)
49454 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER			UINT32_C(0x8)
49456 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL			UINT32_C(0x10)
49458 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC		UINT32_C(0x20)
49460 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST		UINT32_C(0x40)
49462 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS	UINT32_C(0x80)
49464 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE	UINT32_C(0x100)
49466 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT		UINT32_C(0x200)
49473 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP		UINT32_C(0x400)
49475 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED	UINT32_C(0x800)
49478 	 * to the most optimal flow table resource. If set to 0, the flow
49481 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT		UINT32_C(0x1000)
49484 	 * to offload this flow. If set to 0, which will keep compatibility
49490 	#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC	UINT32_C(0x2000)
49544 	 * 0 values are ignored.
49552 	 * 0 values are ignored.
49562 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL	UINT32_C(0x0)
49564 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN	UINT32_C(0x1)
49566 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE	UINT32_C(0x2)
49568 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE	UINT32_C(0x3)
49570 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP	UINT32_C(0x4)
49572 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE	UINT32_C(0x5)
49574 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS	UINT32_C(0x6)
49576 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT	UINT32_C(0x7)
49578 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE	UINT32_C(0x8)
49580 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
49585 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
49586 	/* Use fixed layer 2 ether type of 0xFFFF */
49587 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
49592 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
49594 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
49596 	#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL	UINT32_C(0xff)
49615 	 * The flow id value in bit 0-29 is the actual ID of the flow
49618 	 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
49623 	#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
49624 	#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
49626 	#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE	UINT32_C(0x40000000)
49628 	 * If this bit set to 0, then it indicates that the flow is
49631 		#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT	(UINT32_C(0x0) << 30)
49636 		#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT	(UINT32_C(0x1) << 30)
49639 	#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR	UINT32_C(0x80000000)
49640 	/* If this bit set to 0, then it indicates rx flow. */
49641 		#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX	(UINT32_C(0x0) << 31)
49643 		#define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX	(UINT32_C(0x1) << 31)
49669 	#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN	UINT32_C(0x0)
49671 	#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
49673 	#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD   UINT32_C(0x2)
49675 	#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER	UINT32_C(0x3)
49677 	#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM  UINT32_C(0x4)
49679 	#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION  UINT32_C(0x5)
49681 	#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS	UINT32_C(0x6)
49683 	#define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB	UINT32_C(0x7)
49711 	 * * 0x0-0xFFF8 - The function ID
49712 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49713 	 * * 0xFFFD - Reserved for user-space HWRM interface
49714 	 * * 0xFFFF - HWRM
49765 	#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD			UINT32_C(0x1)
49767 	#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE		UINT32_C(0x2)
49769 	#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP		UINT32_C(0x4)
49771 	#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER		UINT32_C(0x8)
49773 	#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL		UINT32_C(0x10)
49779 	#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP		UINT32_C(0x20)
49781 	#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT	UINT32_C(0x40)
49783 	#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED	UINT32_C(0x80)
49785 	#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP		UINT32_C(0x100)
49787 	#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP		UINT32_C(0x200)
49802 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN	UINT32_C(0x1)
49804 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE	UINT32_C(0x2)
49806 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE	UINT32_C(0x3)
49808 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP	UINT32_C(0x4)
49810 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE	UINT32_C(0x5)
49812 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS	UINT32_C(0x6)
49814 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN	UINT32_C(0x7)
49816 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE	UINT32_C(0x8)
49818 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4	UINT32_C(0x9)
49823 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1	UINT32_C(0xa)
49824 	/* Use fixed layer 2 ether type of 0xFFFF */
49825 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE	UINT32_C(0xb)
49830 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
49832 	#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE	UINT32_C(0x10)
49845 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL	UINT32_C(0x0)
49847 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN	UINT32_C(0x1)
49849 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE	UINT32_C(0x2)
49851 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE	UINT32_C(0x3)
49853 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP	UINT32_C(0x4)
49855 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE	UINT32_C(0x5)
49857 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS	UINT32_C(0x6)
49859 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT	UINT32_C(0x7)
49861 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE	UINT32_C(0x8)
49863 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
49868 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
49869 	/* Use fixed layer 2 ether type of 0xFFFF */
49870 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
49875 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
49877 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
49879 	#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL	UINT32_C(0xff)
50002 	 * * 0x0-0xFFF8 - The function ID
50003 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50004 	 * * 0xFFFD - Reserved for user-space HWRM interface
50005 	 * * 0xFFFF - HWRM
50018 	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK	UINT32_C(0xfff)
50020 	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT	UINT32_C(0x1000)
50022 	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT	UINT32_C(0x2000)
50024 	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_TX	UINT32_C(0x3000)
50026 	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT	UINT32_C(0x4000)
50028 	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX	UINT32_C(0x8000)
50030 	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT_RX	UINT32_C(0x9000)
50032 	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT_RX UINT32_C(0xa000)
50034 	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_RX	UINT32_C(0xb000)
50036 	#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX UINT32_C(0xc000)
50056 	#define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX	UINT32_C(0x1)
50058 	#define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX	UINT32_C(0x2)
50121 	 * * 0x0-0xFFF8 - The function ID
50122 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50123 	 * * 0xFFFD - Reserved for user-space HWRM interface
50124 	 * * 0xFFFF - HWRM
50140 	 * specified. This flag is set to 0 by older driver. For older
50143 	#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID			UINT32_C(0x1)
50147 	 * 0 by older driver. For older firmware, setting this flag has no
50150 	#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL			UINT32_C(0x2)
50153 	 * flows by the caller. This flag is set to 0 by older driver. For
50156 	#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT			UINT32_C(0x4)
50161 	#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC		UINT32_C(0x8000000)
50167 	#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK	UINT32_C(0xc0000000)
50170 …#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT  (UINT32_C(0x0) << 3…
50172 …#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT  (UINT32_C(0x1) << 3…
50177 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K   UINT32_C(0x0)
50179 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K   UINT32_C(0x1)
50181 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K  UINT32_C(0x4)
50183 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
50185 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M   UINT32_C(0x8)
50187 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M   UINT32_C(0x9)
50189 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M   UINT32_C(0xa)
50191 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G   UINT32_C(0x12)
50196 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
50198 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
50203 	#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
50257 	 * * 0x0-0xFFF8 - The function ID
50258 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50259 	 * * 0xFFFD - Reserved for user-space HWRM interface
50260 	 * * 0xFFFF - HWRM
50409 	 * will be 0. Mapping will match flow numbers where bitX is for flowX
50410 	 * (ex: bit 0 is flow0). This only applies for NIC flows. Upon
50450 	 * * 0x0-0xFFF8 - The function ID
50451 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50452 	 * * 0xFFFD - Reserved for user-space HWRM interface
50453 	 * * 0xFFFF - HWRM
50521 	 * * 0x0-0xFFF8 - The function ID
50522 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50523 	 * * 0xFFFD - Reserved for user-space HWRM interface
50524 	 * * 0xFFFF - HWRM
50540 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER	UINT32_C(0x1)
50545 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER	UINT32_C(0x2)
50550 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER	UINT32_C(0x4)
50555 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL	UINT32_C(0x8)
50560 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL	UINT32_C(0x10)
50565 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES	UINT32_C(0x20)
50570 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID		UINT32_C(0x40)
50575 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE	UINT32_C(0x80)
50578 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH	UINT32_C(0x1)
50580 		#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
50582 		#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
50588 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM	UINT32_C(0x2)
50590 		#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE  (UINT32_C(0x0) << 1)
50592 		#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE   (UINT32_C(0x1) << 1)
50629 	#define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA UINT32_C(0x0)
50680 	 * * 0x0-0xFFF8 - The function ID
50681 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50682 	 * * 0xFFFD - Reserved for user-space HWRM interface
50683 	 * * 0xFFFF - HWRM
50699 	#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH	UINT32_C(0x1)
50701 		#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
50703 		#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
50785 	 * * 0x0-0xFFF8 - The function ID
50786 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50787 	 * * 0xFFFD - Reserved for user-space HWRM interface
50788 	 * * 0xFFFF - HWRM
50804 	#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH	UINT32_C(0x1)
50806 		#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
50808 		#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
50876 	 * * 0x0-0xFFF8 - The function ID
50877 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50878 	 * * 0xFFFD - Reserved for user-space HWRM interface
50879 	 * * 0xFFFF - HWRM
50902 	/* The port 0 RX mirror action record ID. */
50907 	 * The port 0 RX action record ID for TX TCP flag packets from
50951 	 * * 0x0-0xFFF8 - The function ID
50952 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50953 	 * * 0xFFFD - Reserved for user-space HWRM interface
50954 	 * * 0xFFFF - HWRM
50964 	/* Logical VF number (range: 0 -> MAX_VFS -1). */
50966 	/* Logical VF number (range: 0 -> MAX_VFS -1). */
51019 	 * * 0x0-0xFFF8 - The function ID
51020 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51021 	 * * 0xFFFD - Reserved for user-space HWRM interface
51022 	 * * 0xFFFF - HWRM
51082 	 * * 0x0-0xFFF8 - The function ID
51083 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51084 	 * * 0xFFFD - Reserved for user-space HWRM interface
51085 	 * * 0xFFFF - HWRM
51097 	#define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE	UINT32_C(0x1)
51129 	#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
51131 	#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE	UINT32_C(0x2)
51171 	 * * 0x0-0xFFF8 - The function ID
51172 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51173 	 * * 0xFFFD - Reserved for user-space HWRM interface
51174 	 * * 0xFFFF - HWRM
51185 	 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
51193 	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN	UINT32_C(0x0)
51198 	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN	UINT32_C(0x1)
51203 	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP	UINT32_C(0x2)
51205 	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY	UINT32_C(0x3)
51207 	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR	UINT32_C(0x4)
51209 	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD	UINT32_C(0x5)
51214 	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL  UINT32_C(0x6)
51219 	#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
51221 	/* Logical VF number (range: 0 -> MAX_VFS -1). */
51223 	/* Logical Host (0xff-local host). */
51225 	/* Logical PF (0xff-PF for command channel). */
51227 	/* Logical VF number (range: 0 -> MAX_VFS -1). */
51229 	/* Loopback port (0xff-internal loopback), valid for mode-3. */
51240 	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID	UINT32_C(0x1)
51245 	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID	UINT32_C(0x2)
51250 	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID	UINT32_C(0x4)
51255 	#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID	UINT32_C(0x8)
51261 	 * the interface pair. The default value is 0.
51271 	 * Specifies whether RX ring flow control is disabled (0) or enabled
51272 	 * (1) in the A to B direction. The default value is 0, meaning that
51277 	 * Specifies whether RX ring flow control is disabled (0) or enabled
51340 	 * * 0x0-0xFFF8 - The function ID
51341 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51342 	 * * 0xFFFD - Reserved for user-space HWRM interface
51343 	 * * 0xFFFF - HWRM
51355 	/* Logical PF (0xff-PF for command channel). */
51358 	/* Logical VF number (range: 0 -> MAX_VFS -1). */
51361 	 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
51369 	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN	UINT32_C(0x0)
51374 	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN	UINT32_C(0x1)
51379 	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP	UINT32_C(0x2)
51381 	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY	UINT32_C(0x3)
51383 	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR	UINT32_C(0x4)
51385 	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD	UINT32_C(0x5)
51390 	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL  UINT32_C(0x6)
51395 	#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
51445 	 * * 0x0-0xFFF8 - The function ID
51446 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51447 	 * * 0xFFFD - Reserved for user-space HWRM interface
51448 	 * * 0xFFFF - HWRM
51460 	#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE	UINT32_C(0x1)
51462 	#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE	UINT32_C(0x2)
51510 	/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
51516 	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN   UINT32_C(0x0)
51521 	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN  UINT32_C(0x1)
51526 	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
51528 	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY   UINT32_C(0x3)
51530 	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR  UINT32_C(0x4)
51535 	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
51537 	#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE	UINT32_C(0x2)
51576 	 * * 0x0-0xFFF8 - The function ID
51577 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51578 	 * * 0xFFFD - Reserved for user-space HWRM interface
51579 	 * * 0xFFFF - HWRM
51589 	/* Logical VF number (range: 0 -> MAX_VFS -1). */
51593 	 * It shall be set to 0.
51651 	 * * 0x0-0xFFF8 - The function ID
51652 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51653 	 * * 0xFFFD - Reserved for user-space HWRM interface
51654 	 * * 0xFFFF - HWRM
51666 	/* Logical VF number (range: 0 -> MAX_VFS -1). */
51670 	 * It shall be set to 0.
51722 	 * * 0x0-0xFFF8 - The function ID
51723 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51724 	 * * 0xFFFD - Reserved for user-space HWRM interface
51725 	 * * 0xFFFF - HWRM
51754 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL	UINT32_C(0x1)
51756 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN		UINT32_C(0x2)
51758 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE		UINT32_C(0x4)
51760 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE		UINT32_C(0x8)
51762 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP		UINT32_C(0x10)
51764 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE	UINT32_C(0x20)
51766 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS		UINT32_C(0x40)
51768 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT		UINT32_C(0x80)
51770 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE		UINT32_C(0x100)
51772 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4	UINT32_C(0x200)
51777 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1	UINT32_C(0x400)
51779 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL	UINT32_C(0x800)
51780 	/* Use fixed layer 2 ether type of 0xFFFF */
51781 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE	UINT32_C(0x1000)
51786 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6	UINT32_C(0x2000)
51788 	#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE	UINT32_C(0x4000)
51824 	 * * 0x0-0xFFF8 - The function ID
51825 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51826 	 * * 0xFFFD - Reserved for user-space HWRM interface
51827 	 * * 0xFFFF - HWRM
51841 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
51843 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
51848 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
51853 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K   UINT32_C(0x0)
51855 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K   UINT32_C(0x1)
51857 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K  UINT32_C(0x4)
51859 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
51861 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M   UINT32_C(0x8)
51863 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M   UINT32_C(0x9)
51865 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M   UINT32_C(0xa)
51867 	#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G   UINT32_C(0x12)
51925 	 * * 0x0-0xFFF8 - The function ID
51926 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51927 	 * * 0xFFFD - Reserved for user-space HWRM interface
51928 	 * * 0xFFFF - HWRM
51992 	 * * 0x0-0xFFF8 - The function ID
51993 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51994 	 * * 0xFFFD - Reserved for user-space HWRM interface
51995 	 * * 0xFFFF - HWRM
52028 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
52030 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
52035 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
52040 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K   UINT32_C(0x0)
52042 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K   UINT32_C(0x1)
52044 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K  UINT32_C(0x4)
52046 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
52048 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M   UINT32_C(0x8)
52050 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M   UINT32_C(0x9)
52052 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M   UINT32_C(0xa)
52054 	#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G   UINT32_C(0x12)
52094 	 * * 0x0-0xFFF8 - The function ID
52095 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52096 	 * * 0xFFFD - Reserved for user-space HWRM interface
52097 	 * * 0xFFFF - HWRM
52160 	 * * 0x0-0xFFF8 - The function ID
52161 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52162 	 * * 0xFFFD - Reserved for user-space HWRM interface
52163 	 * * 0xFFFF - HWRM
52188 	#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT	UINT32_C(0x1)
52190 		#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE	UINT32_C(0x0)
52192 		#define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT  UINT32_C(0x1)
52295 	 * * 0x0-0xFFF8 - The function ID
52296 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52297 	 * * 0xFFFD - Reserved for user-space HWRM interface
52298 	 * * 0xFFFF - HWRM
52310 	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE			UINT32_C(0x1)
52312 		#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE		UINT32_C(0x0)
52314 		#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE		UINT32_C(0x1)
52317 	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH			UINT32_C(0x2)
52319 		#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX			(UINT32_C(0x0) << 1)
52321 		#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX			(UINT32_C(0x1) << 1)
52324 	#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK	UINT32_C(0xc)
52327 		#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH	(UINT32_C(0x0) << 2)
52329 		#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL	(UINT32_C(0x1) << 2)
52331 		#define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC  (UINT32_C(0x2) << 2)
52335 	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC  UINT32_C(0x0)
52337 	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
52339 	#define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
52396 	 * * 0x0-0xFFF8 - The function ID
52397 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52398 	 * * 0xFFFD - Reserved for user-space HWRM interface
52399 	 * * 0xFFFF - HWRM
52411 	#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH			UINT32_C(0x1)
52413 		#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_TX			UINT32_C(0x0)
52415 		#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_RX			UINT32_C(0x1)
52418 	#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK	UINT32_C(0x6)
52421 		#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH	(UINT32_C(0x0) << 1)
52423 		#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL	(UINT32_C(0x1) << 1)
52425 		#define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC  (UINT32_C(0x2) << 1)
52480 	 * * 0x0-0xFFF8 - The function ID
52481 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52482 	 * * 0xFFFD - Reserved for user-space HWRM interface
52483 	 * * 0xFFFF - HWRM
52495 	#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH	UINT32_C(0x1)
52497 		#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX	UINT32_C(0x0)
52499 		#define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX	UINT32_C(0x1)
52557 	 * * 0x0-0xFFF8 - The function ID
52558 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52559 	 * * 0xFFFD - Reserved for user-space HWRM interface
52560 	 * * 0xFFFF - HWRM
52576 	#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX		UINT32_C(0x1)
52582 	#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX		UINT32_C(0x2)
52584 	#define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD	UINT32_C(0x4)
52605 	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX					UINT32_C(0x1)
52611 	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX					UINT32_C(0x2)
52617 	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED		UINT32_C(0x4)
52625 	#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED	UINT32_C(0x8)
52630 	 * If set to 0, EEM KEY0 table is not supported.
52632 	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE			UINT32_C(0x1)
52635 	 * If set to 0, EEM KEY1 table is not supported.
52637 	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE			UINT32_C(0x2)
52640 	 * If set to 0, EEM External Record table is not supported.
52643 	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE		UINT32_C(0x4)
52646 	 * If set to 0, EEM External Flow Counters table is not supported.
52648 	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE	UINT32_C(0x8)
52652 	 * If set to 0, then FID table used for implicit flow flush is
52655 	#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE			UINT32_C(0x10)
52709 	 * * 0x0-0xFFF8 - The function ID
52710 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52711 	 * * 0xFFFD - Reserved for user-space HWRM interface
52712 	 * * 0xFFFF - HWRM
52728 	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX		UINT32_C(0x1)
52734 	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX		UINT32_C(0x2)
52736 	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD	UINT32_C(0x4)
52737 	/* When set to 1, secondary, 0 means primary. */
52738 	#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF	UINT32_C(0x8)
52813 	 * * 0x0-0xFFF8 - The function ID
52814 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52815 	 * * 0xFFFD - Reserved for user-space HWRM interface
52816 	 * * 0xFFFF - HWRM
52828 	#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX	UINT32_C(0x1)
52830 	#define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX	UINT32_C(0x2)
52847 	#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX		UINT32_C(0x1)
52849 	#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX		UINT32_C(0x2)
52851 	#define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD	UINT32_C(0x4)
52899 	 * * 0x0-0xFFF8 - The function ID
52900 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52901 	 * * 0xFFFD - Reserved for user-space HWRM interface
52902 	 * * 0xFFFF - HWRM
52918 	#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX	UINT32_C(0x1)
52924 	#define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX	UINT32_C(0x2)
52929 	#define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED	UINT32_C(0x0)
52936 	#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
52943 	#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE  UINT32_C(0x2)
52948 	#define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
52998 	 * * 0x0-0xFFF8 - The function ID
52999 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53000 	 * * 0xFFFD - Reserved for user-space HWRM interface
53001 	 * * 0xFFFF - HWRM
53028 	 * Value of 0 to indicate firmware not support 16-bit flow handle.
53030 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED			UINT32_C(0x1)
53033 	 * Value of 0 to indicate firmware not support 64-bit flow handle.
53035 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED			UINT32_C(0x2)
53039 	 * Value of 0 to indicate that the firmware does not support flow
53042 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED		UINT32_C(0x4)
53046 	 * Value of 0 indicates firmware does not support flow reset all
53049 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED			UINT32_C(0x8)
53053 	 * Value of 0 indicates firmware does not support use of FID as
53056 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED		UINT32_C(0x10)
53059 	 * Value of 0 indicates firmware does not support TX EEM flows.
53062 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED			UINT32_C(0x20)
53065 	 * Value of 0 indicates firmware does not support RX EEM flows.
53068 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED			UINT32_C(0x40)
53072 	 * flows. Value of 0 indicates firmware does not support the dynamic
53076 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED		UINT32_C(0x80)
53080 	 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
53082 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED		UINT32_C(0x100)
53085 	 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
53088 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED			UINT32_C(0x200)
53091 	 * of 0 indicates firmware does not support XDP filter.
53093 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED				UINT32_C(0x400)
53097 	 * Value of 0 indicates firmware does not support L2 header source
53100 …#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED		UINT32_C(0x80…
53104 	 * RX direction. By default, this flag should be 0 for older version
53107 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED		UINT32_C(0x1000)
53111 	 * command. Value of 0 indicates firmware does not support
53114 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED		UINT32_C(0x2000)
53118 	 * direction. By default, this flag should be 0 for older version
53121 …#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED	UINT32_C(0…
53127 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE				UINT32_C(0x8000)
53131 	 * By default, this flag should be 0 for older version of firmware.
53133 …WRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED	UINT32_C(0x10000)
53138 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED				UINT32_C(0x20000)
53143 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED		UINT32_C(0x40000)
53146 	 * in cfa_flow_stats command where flow_handle value 0xF000.
53148 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED			UINT32_C(0x80000)
53152 	 * this flag should be 0 for older version of firmware.
53154 …#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED	UINT32_C(0…
53158 	 * Value of 0 indicates ring tbl idx should be passed using dst_id.
53160 	#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED		UINT32_C(0x200000)
53196 	 * * 0x0-0xFFF8 - The function ID
53197 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53198 	 * * 0xFFFD - Reserved for user-space HWRM interface
53199 	 * * 0xFFFF - HWRM
53274 	 * * 0x0-0xFFF8 - The function ID
53275 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53276 	 * * 0xFFFD - Reserved for user-space HWRM interface
53277 	 * * 0xFFFF - HWRM
53292 	#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP UINT32_C(0x1)
53303 	#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR   UINT32_C(0x2)
53305 	#define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST	UINT32_C(0x3)
53308 	 * Supports up to 5 ports. bit0 = port 0, bit1 = port 1,
53365 	 * * 0x0-0xFFF8 - The function ID
53366 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53367 	 * * 0xFFFD - Reserved for user-space HWRM interface
53368 	 * * 0xFFFF - HWRM
53429 	 * * 0x0-0xFFF8 - The function ID
53430 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53431 	 * * 0xFFFD - Reserved for user-space HWRM interface
53432 	 * * 0xFFFF - HWRM
53448 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID		UINT32_C(0x1)
53453 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE		UINT32_C(0x2)
53458 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE		UINT32_C(0x4)
53463 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR		UINT32_C(0x8)
53468 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR		UINT32_C(0x10)
53473 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL		UINT32_C(0x20)
53478 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT		UINT32_C(0x40)
53483 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_PORT		UINT32_C(0x80)
53488 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_KID			UINT32_C(0x100)
53493 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_ID		UINT32_C(0x200)
53498 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID	UINT32_C(0x400)
53503 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_QUIC_DST_CONNECT_ID	UINT32_C(0x800)
53520 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
53522 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4	UINT32_C(0x4)
53524 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6	UINT32_C(0x6)
53534 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
53536 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP	UINT32_C(0x6)
53538 	#define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP	UINT32_C(0x11)
53596 	 * The flow id value in bit 0-29 is the actual ID of the flow
53599 	 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
53604 	#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
53605 	#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
53607 	#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE	UINT32_C(0x40000000)
53609 	 * If this bit set to 0, then it indicates that the flow is
53612 		#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT	(UINT32_C(0x0) << 30)
53617 		#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT	(UINT32_C(0x1) << 30)
53620 	#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR	UINT32_C(0x80000000)
53621 	/* If this bit set to 0, then it indicates rx flow. */
53622 		#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX	(UINT32_C(0x0) << 31)
53624 		#define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX	(UINT32_C(0x1) << 31)
53661 	 * * 0x0-0xFFF8 - The function ID
53662 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53663 	 * * 0xFFFD - Reserved for user-space HWRM interface
53664 	 * * 0xFFFF - HWRM
53724 	 * * 0x0-0xFFF8 - The function ID
53725 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53726 	 * * 0xFFFD - Reserved for user-space HWRM interface
53727 	 * * 0xFFFF - HWRM
53744 	#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_EFID UINT32_C(0x1)
53746 	#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_RFID UINT32_C(0x2)
53748 	#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_DFID UINT32_C(0x3)
53757 	#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_BC_REM	UINT32_C(0x1)
53759 	#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_MC_REM	UINT32_C(0x2)
53761 	#define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_PROMISC_REM	UINT32_C(0x4)
53811 	 * * 0x0-0xFFF8 - The function ID
53812 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53813 	 * * 0xFFFD - Reserved for user-space HWRM interface
53814 	 * * 0xFFFF - HWRM
53889 	 * * 0x0-0xFFF8 - The function ID
53890 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53891 	 * * 0xFFFD - Reserved for user-space HWRM interface
53892 	 * * 0xFFFF - HWRM
53964 	 * * 0x0-0xFFF8 - The function ID
53965 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53966 	 * * 0xFFFD - Reserved for user-space HWRM interface
53967 	 * * 0xFFFF - HWRM
54007 	 * should be 1. The AFM session's fw_rm_client_id is 0.
54009 	#define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION		UINT32_C(0x1)
54011 	 * If this bit set to 0, then it indicates the shared session
54014 		#define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR  UINT32_C(0x0)
54019 		#define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR	UINT32_C(0x1)
54057 	 * * 0x0-0xFFF8 - The function ID
54058 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54059 	 * * 0xFFFD - Reserved for user-space HWRM interface
54060 	 * * 0xFFFF - HWRM
54138 	 * * 0x0-0xFFF8 - The function ID
54139 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54140 	 * * 0xFFFD - Reserved for user-space HWRM interface
54141 	 * * 0xFFFF - HWRM
54210 	 * * 0x0-0xFFF8 - The function ID
54211 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54212 	 * * 0xFFFD - Reserved for user-space HWRM interface
54213 	 * * 0xFFFF - HWRM
54276 	 * * 0x0-0xFFF8 - The function ID
54277 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54278 	 * * 0xFFFD - Reserved for user-space HWRM interface
54279 	 * * 0xFFFF - HWRM
54312 	#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN		UINT32_C(0x1)
54318 	#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH	UINT32_C(0x2)
54324 	#define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2	UINT32_C(0x4)
54328 	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN	UINT32_C(0x1)
54333 	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K	UINT32_C(0x2)
54340 	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH	UINT32_C(0x4)
54346 	#define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH	UINT32_C(0x8)
54383 	 * * 0x0-0xFFF8 - The function ID
54384 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54385 	 * * 0xFFFD - Reserved for user-space HWRM interface
54386 	 * * 0xFFFF - HWRM
54401 	#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR	UINT32_C(0x1)
54402 	/* If this bit set to 0, then it indicates rx flow. */
54403 		#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
54405 		#define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
54437 	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK  UINT32_C(0x3)
54438 	#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT   0
54440 		#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC  UINT32_C(0x0)
54442 		#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1	UINT32_C(0x1)
54444 		#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2	UINT32_C(0x2)
54446 		#define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3	UINT32_C(0x3)
54497 	 * * 0x0-0xFFF8 - The function ID
54498 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54499 	 * * 0xFFFD - Reserved for user-space HWRM interface
54500 	 * * 0xFFFF - HWRM
54515 	#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR	UINT32_C(0x1)
54516 	/* If this bit set to 0, then it indicates rx flow. */
54517 		#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
54519 		#define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
54597 	 * * 0x0-0xFFF8 - The function ID
54598 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54599 	 * * 0xFFFD - Reserved for user-space HWRM interface
54600 	 * * 0xFFFF - HWRM
54615 	#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR	UINT32_C(0x1)
54616 	/* If this bit set to 0, then it indicates rx flow. */
54617 		#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
54619 		#define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
54682 	 * * 0x0-0xFFF8 - The function ID
54683 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54684 	 * * 0xFFFD - Reserved for user-space HWRM interface
54685 	 * * 0xFFFF - HWRM
54700 	#define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR	UINT32_C(0x1)
54701 	/* If this bit set to 0, then it indicates rx flow. */
54702 		#define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
54704 		#define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
54806 	 * * 0x0-0xFFF8 - The function ID
54807 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54808 	 * * 0xFFFD - Reserved for user-space HWRM interface
54809 	 * * 0xFFFF - HWRM
54824 	#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR	UINT32_C(0x1)
54825 	/* If this bit set to 0, then it indicates rx flow. */
54826 		#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
54828 		#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
54833 	#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_CFA	UINT32_C(0x0)
54835 	#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_RXP	UINT32_C(0x1)
54837 	#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
54839 	#define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
54903 	 * * 0x0-0xFFF8 - The function ID
54904 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54905 	 * * 0xFFFD - Reserved for user-space HWRM interface
54906 	 * * 0xFFFF - HWRM
54921 	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR		UINT32_C(0x1)
54922 	/* If this bit set to 0, then it indicates rx flow. */
54923 		#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX		UINT32_C(0x0)
54925 		#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX		UINT32_C(0x1)
54931 	#define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ	UINT32_C(0x2)
54935 	#define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_CFA	UINT32_C(0x0)
54937 	#define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_RXP	UINT32_C(0x1)
54939 	#define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
54941 	#define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
55009 	 * * 0x0-0xFFF8 - The function ID
55010 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55011 	 * * 0xFFFD - Reserved for user-space HWRM interface
55012 	 * * 0xFFFF - HWRM
55027 	#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
55028 	/* If this bit set to 0, then it indicates rx flow. */
55029 		#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55031 		#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55034 	#define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA	UINT32_C(0x2)
55038 	#define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_CFA	UINT32_C(0x0)
55040 	#define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_RXP	UINT32_C(0x1)
55042 	#define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
55044 	#define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
55110 	 * * 0x0-0xFFF8 - The function ID
55111 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55112 	 * * 0xFFFD - Reserved for user-space HWRM interface
55113 	 * * 0xFFFF - HWRM
55128 	#define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR	UINT32_C(0x1)
55129 	/* If this bit set to 0, then it indicates rx flow. */
55130 		#define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55132 		#define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55137 	#define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_CFA	UINT32_C(0x0)
55139 	#define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_RXP	UINT32_C(0x1)
55141 	#define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
55143 	#define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
55205 	 * * 0x0-0xFFF8 - The function ID
55206 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55207 	 * * 0xFFFD - Reserved for user-space HWRM interface
55208 	 * * 0xFFFF - HWRM
55223 	#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR	UINT32_C(0x1)
55224 	/* If this bit set to 0, then it indicates rx flow. */
55225 		#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55227 		#define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55256 	/* EM record offset 0~3. */
55296 	 * * 0x0-0xFFF8 - The function ID
55297 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55298 	 * * 0xFFFD - Reserved for user-space HWRM interface
55299 	 * * 0xFFFF - HWRM
55314 	#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR	UINT32_C(0x1)
55315 	/* If this bit set to 0, then it indicates rx flow. */
55316 		#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55318 		#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55321 	#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DMA	UINT32_C(0x2)
55349 	/* EM record offset 0~3. */
55389 	 * * 0x0-0xFFF8 - The function ID
55390 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55391 	 * * 0xFFFD - Reserved for user-space HWRM interface
55392 	 * * 0xFFFF - HWRM
55407 	#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR	UINT32_C(0x1)
55408 	/* If this bit set to 0, then it indicates rx flow. */
55409 		#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55411 		#define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55474 	 * * 0x0-0xFFF8 - The function ID
55475 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55476 	 * * 0xFFFD - Reserved for user-space HWRM interface
55477 	 * * 0xFFFF - HWRM
55492 	#define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR	UINT32_C(0x1)
55493 	/* If this bit set to 0, then it indicates rx flow. */
55494 		#define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55496 		#define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55557 	 * * 0x0-0xFFF8 - The function ID
55558 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55559 	 * * 0xFFFD - Reserved for user-space HWRM interface
55560 	 * * 0xFFFF - HWRM
55575 	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
55576 	/* If this bit set to 0, then it indicates rx flow. */
55577 		#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55579 		#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55585 	#define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA	UINT32_C(0x2)
55599 	 * array, key offset is always 0.
55607 	 * TCAM key located at offset 0, mask located at mask_offset
55660 	 * * 0x0-0xFFF8 - The function ID
55661 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55662 	 * * 0xFFFD - Reserved for user-space HWRM interface
55663 	 * * 0xFFFF - HWRM
55678 	#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR	UINT32_C(0x1)
55679 	/* If this bit set to 0, then it indicates rx flow. */
55680 		#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55682 		#define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55717 	 * TCAM key located at offset 0, mask located at mask_offset
55757 	 * * 0x0-0xFFF8 - The function ID
55758 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55759 	 * * 0xFFFD - Reserved for user-space HWRM interface
55760 	 * * 0xFFFF - HWRM
55775 	#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR	UINT32_C(0x1)
55776 	/* If this bit set to 0, then it indicates rx flow. */
55777 		#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55779 		#define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55841 	 * * 0x0-0xFFF8 - The function ID
55842 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55843 	 * * 0xFFFD - Reserved for user-space HWRM interface
55844 	 * * 0xFFFF - HWRM
55859 	#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR	UINT32_C(0x1)
55860 	/* If this bit set to 0, then it indicates rx flow. */
55861 		#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55863 		#define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55925 	 * * 0x0-0xFFF8 - The function ID
55926 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55927 	 * * 0xFFFD - Reserved for user-space HWRM interface
55928 	 * * 0xFFFF - HWRM
55943 	#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
55944 	/* If this bit set to 0, then it indicates rx flow. */
55945 		#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
55947 		#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
55950 	#define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DMA	UINT32_C(0x2)
55961 	/* Mask of data to set, 0 indicates no mask */
56012 	 * * 0x0-0xFFF8 - The function ID
56013 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56014 	 * * 0xFFFD - Reserved for user-space HWRM interface
56015 	 * * 0xFFFF - HWRM
56030 	#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR	UINT32_C(0x1)
56031 	/* If this bit set to 0, then it indicates rx flow. */
56032 		#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
56034 		#define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
56099 	 * * 0x0-0xFFF8 - The function ID
56100 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56101 	 * * 0xFFFD - Reserved for user-space HWRM interface
56102 	 * * 0xFFFF - HWRM
56117 	#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR	UINT32_C(0x1)
56118 	/* If this bit set to 0, then it indicates rx flow. */
56119 		#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
56121 		#define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
56189 	 * * 0x0-0xFFF8 - The function ID
56190 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56191 	 * * 0xFFFD - Reserved for user-space HWRM interface
56192 	 * * 0xFFFF - HWRM
56207 	#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
56208 	/* If this bit set to 0, then it indicates rx flow. */
56209 		#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
56211 		#define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
56277 	 * * 0x0-0xFFF8 - The function ID
56278 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56279 	 * * 0xFFFD - Reserved for user-space HWRM interface
56280 	 * * 0xFFFF - HWRM
56295 	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR		UINT32_C(0x1)
56296 	/* If this bit set to 0, then it indicates rx flow. */
56297 		#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX		UINT32_C(0x0)
56299 		#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX		UINT32_C(0x1)
56305 	#define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ	UINT32_C(0x2)
56374 	 * * 0x0-0xFFF8 - The function ID
56375 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56376 	 * * 0xFFFD - Reserved for user-space HWRM interface
56377 	 * * 0xFFFF - HWRM
56394 	#define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
56395 	/* If this bit set to 0, then it indicates rx flow. */
56396 		#define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
56398 		#define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
56449 	 * * 0x0-0xFFF8 - The function ID
56450 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56451 	 * * 0xFFFD - Reserved for user-space HWRM interface
56452 	 * * 0xFFFF - HWRM
56467 	#define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR	UINT32_C(0x1)
56468 	/* If this bit set to 0, then it indicates rx flow. */
56469 		#define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
56471 		#define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
56528 	 * * 0x0-0xFFF8 - The function ID
56529 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56530 	 * * 0xFFFD - Reserved for user-space HWRM interface
56531 	 * * 0xFFFF - HWRM
56546 	#define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
56547 	/* If this bit set to 0, then it indicates rx flow. */
56548 		#define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
56550 		#define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
56553 	#define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DMA	UINT32_C(0x2)
56557 	#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_WC_TCAM	UINT32_C(0x1)
56559 	#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_EM		UINT32_C(0x2)
56561 	#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_METER		UINT32_C(0x4)
56563 	#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_COUNTER	UINT32_C(0x8)
56565 	#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACTION		UINT32_C(0x10)
56567 	#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACT_MOD_ENCAP	UINT32_C(0x20)
56569 	#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_SP_SMAC	UINT32_C(0x40)
56571 	#define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ALL		UINT32_C(0x80)
56627 	 * * 0x0-0xFFF8 - The function ID
56628 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56629 	 * * 0xFFFD - Reserved for user-space HWRM interface
56630 	 * * 0xFFFF - HWRM
56645 	#define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR	UINT32_C(0x1)
56646 	/* If this bit set to 0, then it indicates rx flow. */
56647 		#define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
56649 		#define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
56656 	#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_WC_TCAM	UINT32_C(0x1)
56658 	#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_EM		UINT32_C(0x2)
56660 	#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_METER		UINT32_C(0x4)
56662 	#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_COUNTER	UINT32_C(0x8)
56664 	#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACTION		UINT32_C(0x10)
56666 	#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACT_MOD_ENCAP	UINT32_C(0x20)
56668 	#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_SP_SMAC	UINT32_C(0x40)
56670 	#define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ALL		UINT32_C(0x80)
56734 	 * * 0x0-0xFFF8 - The function ID
56735 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56736 	 * * 0xFFFD - Reserved for user-space HWRM interface
56737 	 * * 0xFFFF - HWRM
56801  * a fid_cnt of 0 that also means that the table scope ID has
56822 	 * * 0x0-0xFFF8 - The function ID
56823 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56824 	 * * 0xFFFD - Reserved for user-space HWRM interface
56825 	 * * 0xFFFF - HWRM
56840 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
56862 	/* Application type. 0 (AFM), 1 (TF) */
56923 	 * * 0x0-0xFFF8 - The function ID
56924 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56925 	 * * 0xFFFD - Reserved for user-space HWRM interface
56926 	 * * 0xFFFF - HWRM
57034 	 * * 0x0-0xFFF8 - The function ID
57035 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57036 	 * * 0xFFFD - Reserved for user-space HWRM interface
57037 	 * * 0xFFFF - HWRM
57101 	 * * 0x0-0xFFF8 - The function ID
57102 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57103 	 * * 0xFFFD - Reserved for user-space HWRM interface
57104 	 * * 0xFFFF - HWRM
57119 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57179 	 * * 0x0-0xFFF8 - The function ID
57180 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57181 	 * * 0xFFFD - Reserved for user-space HWRM interface
57182 	 * * 0xFFFF - HWRM
57197 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57243  * to 0), will result in this session id being freed automatically.
57263 	 * * 0x0-0xFFF8 - The function ID
57264 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57265 	 * * 0xFFFD - Reserved for user-space HWRM interface
57266 	 * * 0xFFFF - HWRM
57281 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57345 	 * * 0x0-0xFFF8 - The function ID
57346 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57347 	 * * 0xFFFD - Reserved for user-space HWRM interface
57348 	 * * 0xFFFF - HWRM
57363 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57411  * (fid_cnt goes to 0), will result in this session id being freed
57432 	 * * 0x0-0xFFF8 - The function ID
57433 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57434 	 * * 0xFFFD - Reserved for user-space HWRM interface
57435 	 * * 0xFFFF - HWRM
57450 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57519 	 * * 0x0-0xFFF8 - The function ID
57520 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57521 	 * * 0xFFFD - Reserved for user-space HWRM interface
57522 	 * * 0xFFFF - HWRM
57537 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57549 	#define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR	UINT32_C(0x1)
57550 	/* If this bit set to 0, then it indicates rx flow. */
57551 		#define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
57553 		#define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
57563 	#define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
57565 	#define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID	UINT32_C(0x1)
57567 	#define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID	UINT32_C(0x2)
57631 	 * * 0x0-0xFFF8 - The function ID
57632 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57633 	 * * 0xFFFD - Reserved for user-space HWRM interface
57634 	 * * 0xFFFF - HWRM
57649 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57666 	#define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR	UINT32_C(0x1)
57667 	/* If this bit set to 0, then it indicates rx flow. */
57668 		#define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
57670 		#define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
57723 	 * * 0x0-0xFFF8 - The function ID
57724 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57725 	 * * 0xFFFD - Reserved for user-space HWRM interface
57726 	 * * 0xFFFF - HWRM
57741 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57754 	#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR	UINT32_C(0x1)
57755 	/* If this bit set to 0, then it indicates rx flow. */
57756 		#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
57758 		#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
57773 	#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
57775 	#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID	UINT32_C(0x1)
57777 	#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID	UINT32_C(0x2)
57782 	#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_CFA	UINT32_C(0x0)
57784 	#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_RXP	UINT32_C(0x1)
57786 	#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
57788 	#define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
57844 	 * * 0x0-0xFFF8 - The function ID
57845 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57846 	 * * 0xFFFD - Reserved for user-space HWRM interface
57847 	 * * 0xFFFF - HWRM
57862 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57875 	#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
57876 	/* If this bit set to 0, then it indicates rx flow. */
57877 		#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
57879 		#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
57885 	#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA	UINT32_C(0x2)
57899 	#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
57901 	#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID	UINT32_C(0x1)
57903 	#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID	UINT32_C(0x2)
57908 	#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_CFA	UINT32_C(0x0)
57910 	#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_RXP	UINT32_C(0x1)
57912 	#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
57914 	#define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
57923 	 * Index table data located at offset 0. If dma bit is set,
57981 	 * * 0x0-0xFFF8 - The function ID
57982 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57983 	 * * 0xFFFD - Reserved for user-space HWRM interface
57984 	 * * 0xFFFF - HWRM
57997 	#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
57998 	/* If this bit set to 0, then it indicates rx flow. */
57999 		#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
58001 		#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
58007 	#define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DMA	UINT32_C(0x2)
58018 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
58037 	#define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_CFA	UINT32_C(0x0)
58039 	#define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_RXP	UINT32_C(0x1)
58041 	#define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
58043 	#define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
58050 	 * Index table data located at offset 0. If dma bit is set,
58103 	 * * 0x0-0xFFF8 - The function ID
58104 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58105 	 * * 0xFFFD - Reserved for user-space HWRM interface
58106 	 * * 0xFFFF - HWRM
58119 	#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR		UINT32_C(0x1)
58120 	/* If this bit set to 0, then it indicates rx flow. */
58121 		#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_RX		UINT32_C(0x0)
58123 		#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX		UINT32_C(0x1)
58129 	#define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_CLEAR_ON_READ	UINT32_C(0x2)
58140 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
58159 	#define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_CFA	UINT32_C(0x0)
58161 	#define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_RXP	UINT32_C(0x1)
58163 	#define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
58165 	#define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
58222 	 * * 0x0-0xFFF8 - The function ID
58223 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58224 	 * * 0xFFFD - Reserved for user-space HWRM interface
58225 	 * * 0xFFFF - HWRM
58238 	#define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR	UINT32_C(0x1)
58239 	/* If this bit set to 0, then it indicates rx flow. */
58240 		#define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
58242 		#define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
58254 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
58268 	#define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_CFA	UINT32_C(0x0)
58270 	#define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_RXP	UINT32_C(0x1)
58272 	#define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
58274 	#define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
58355 	 * * 0x0-0xFFF8 - The function ID
58356 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58357 	 * * 0xFFFD - Reserved for user-space HWRM interface
58358 	 * * 0xFFFF - HWRM
58373 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
58459 	 * * 0x0-0xFFF8 - The function ID
58460 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58461 	 * * 0xFFFD - Reserved for user-space HWRM interface
58462 	 * * 0xFFFF - HWRM
58477 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
58495 	#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
58496 	/* If this bit set to 0, then it indicates rx flow. */
58497 		#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
58499 		#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
58502 	#define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DMA	UINT32_C(0x2)
58513 	 * TCAM key located at offset 0, mask located at mask_offset
58566 	 * * 0x0-0xFFF8 - The function ID
58567 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58568 	 * * 0xFFFD - Reserved for user-space HWRM interface
58569 	 * * 0xFFFF - HWRM
58582 	#define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR	UINT32_C(0x1)
58583 	/* If this bit set to 0, then it indicates rx flow. */
58584 		#define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
58586 		#define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
58598 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
58629 	 * TCAM key located at offset 0, mask located at key_size
58669 	 * * 0x0-0xFFF8 - The function ID
58670 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58671 	 * * 0xFFFD - Reserved for user-space HWRM interface
58672 	 * * 0xFFFF - HWRM
58685 	#define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR	UINT32_C(0x1)
58686 	/* If this bit set to 0, then it indicates rx flow. */
58687 		#define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
58689 		#define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
58701 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
58718 	#define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
58720 	#define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID	UINT32_C(0x1)
58722 	#define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID	UINT32_C(0x2)
58780 	 * * 0x0-0xFFF8 - The function ID
58781 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58782 	 * * 0xFFFD - Reserved for user-space HWRM interface
58783 	 * * 0xFFFF - HWRM
58796 	#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
58797 	/* If this bit set to 0, then it indicates rx flow. */
58798 		#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
58800 		#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
58803 	#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DMA	UINT32_C(0x2)
58814 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
58833 	#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
58835 	#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID	UINT32_C(0x1)
58837 	#define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID	UINT32_C(0x2)
58844 	 * Index table data located at offset 0. If dma bit is set,
58899 	 * * 0x0-0xFFF8 - The function ID
58900 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58901 	 * * 0xFFFD - Reserved for user-space HWRM interface
58902 	 * * 0xFFFF - HWRM
58915 	#define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR	UINT32_C(0x1)
58916 	/* If this bit set to 0, then it indicates rx flow. */
58917 		#define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
58919 		#define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
58931 	 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
58991 	 * * 0x0-0xFFF8 - The function ID
58992 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58993 	 * * 0xFFFD - Reserved for user-space HWRM interface
58994 	 * * 0xFFFF - HWRM
59016 	#define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR	UINT32_C(0x1)
59017 	/* If this bit set to 0, then it indicates rx flow. */
59018 		#define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
59020 		#define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
59079 	 * * 0x0-0xFFF8 - The function ID
59080 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59081 	 * * 0xFFFD - Reserved for user-space HWRM interface
59082 	 * * 0xFFFF - HWRM
59104 	#define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR	UINT32_C(0x1)
59105 	/* If this bit set to 0, then it indicates rx flow. */
59106 		#define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
59108 		#define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
59141 	#define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR	UINT32_C(0x1)
59142 	/* If this bit set to 0, then it indicates rx flow. */
59143 		#define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_RX	UINT32_C(0x0)
59145 		#define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_TX	UINT32_C(0x1)
59192 	 * * 0x0-0xFFF8 - The function ID
59193 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59194 	 * * 0xFFFD - Reserved for user-space HWRM interface
59195 	 * * 0xFFFF - HWRM
59260 	 * * 0x0-0xFFF8 - The function ID
59261 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59262 	 * * 0xFFFD - Reserved for user-space HWRM interface
59263 	 * * 0xFFFF - HWRM
59280 	#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR	UINT32_C(0x1)
59281 	/* If this bit set to 0, then it indicates rx flow. */
59282 		#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX	UINT32_C(0x0)
59284 		#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX	UINT32_C(0x1)
59289 	#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
59291 	#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_SID	UINT32_C(0x1)
59293 	#define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_FID	UINT32_C(0x2)
59356 	 * * 0x0-0xFFF8 - The function ID
59357 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59358 	 * * 0xFFFD - Reserved for user-space HWRM interface
59359 	 * * 0xFFFF - HWRM
59372 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN		UINT32_C(0x1)
59374 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE		UINT32_C(0x5)
59376 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
59381 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
59382 	/* Use fixed layer 2 ether type of 0xFFFF */
59383 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
59388 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6	UINT32_C(0xc)
59390 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE	UINT32_C(0xd)
59392 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI		UINT32_C(0xe)
59394 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6		UINT32_C(0xf)
59396 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
59398 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GRE		UINT32_C(0x11)
59400 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR	UINT32_C(0x12)
59402 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13)
59404 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14)
59406 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15)
59408 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16)
59410 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17)
59412 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18)
59414 	#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19)
59449 	 * A value of 0 means that the destination port is not
59461 	#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR0	UINT32_C(0x1)
59463 	#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR1	UINT32_C(0x2)
59465 	#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR2	UINT32_C(0x4)
59467 	#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR3	UINT32_C(0x8)
59469 	#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR4	UINT32_C(0x10)
59471 	#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR5	UINT32_C(0x20)
59473 	#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6	UINT32_C(0x40)
59475 	#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7	UINT32_C(0x80)
59482 	#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_CHIP_LEVEL	UINT32_C(0x1)
59487 	#define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_FUNC_LEVEL	UINT32_C(0x2)
59522 	 * * 0x0-0xFFF8 - The function ID
59523 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59524 	 * * 0xFFFD - Reserved for user-space HWRM interface
59525 	 * * 0xFFFF - HWRM
59538 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN		UINT32_C(0x1)
59540 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE		UINT32_C(0x5)
59542 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
59547 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
59548 	/* Use fixed layer 2 ether type of 0xFFFF */
59549 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
59554 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6	UINT32_C(0xc)
59559 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE	UINT32_C(0xd)
59561 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI		UINT32_C(0xe)
59563 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6		UINT32_C(0xf)
59565 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
59567 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GRE		UINT32_C(0x11)
59569 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR	UINT32_C(0x12)
59571 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13)
59573 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14)
59575 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15)
59577 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16)
59579 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17)
59581 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18)
59583 	#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19)
59598 	 * A value of 0 shall fail the command.
59623 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_SUCCESS	UINT32_C(0x0)
59625 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED   UINT32_C(0x1)
59627 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE UINT32_C(0x2)
59629 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ENABLED	UINT32_C(0x3)
59639 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR0	UINT32_C(0x1)
59641 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR1	UINT32_C(0x2)
59643 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR2	UINT32_C(0x4)
59645 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR3	UINT32_C(0x8)
59647 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR4	UINT32_C(0x10)
59649 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR5	UINT32_C(0x20)
59651 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR6	UINT32_C(0x40)
59653 	#define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR7	UINT32_C(0x80)
59688 	 * * 0x0-0xFFF8 - The function ID
59689 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59690 	 * * 0xFFFD - Reserved for user-space HWRM interface
59691 	 * * 0xFFFF - HWRM
59704 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN		UINT32_C(0x1)
59706 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE		UINT32_C(0x5)
59708 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4	UINT32_C(0x9)
59713 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1	UINT32_C(0xa)
59714 	/* Use fixed layer 2 ether type of 0xFFFF */
59715 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE	UINT32_C(0xb)
59720 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6	UINT32_C(0xc)
59725 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE	UINT32_C(0xd)
59727 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI		UINT32_C(0xe)
59729 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6		UINT32_C(0xf)
59731 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE	UINT32_C(0x10)
59733 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GRE		UINT32_C(0x11)
59735 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR	UINT32_C(0x12)
59737 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13)
59739 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14)
59741 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15)
59743 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16)
59745 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17)
59747 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18)
59749 	#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19)
59778 	#define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_SUCCESS	UINT32_C(0x0)
59780 	#define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_OWNER	UINT32_C(0x1)
59782 	#define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED UINT32_C(0x2)
59965 	 * * 0x0-0xFFF8 - The function ID
59966 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59967 	 * * 0xFFFD - Reserved for user-space HWRM interface
59968 	 * * 0xFFFF - HWRM
59987 	 * If update_period_ms is 0, then the stats update
59992 	 *   if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
60008 	 * When this bit is set to '0', the statistics context shall be
60011 	#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE		UINT32_C(0x1)
60023 	#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_DUP_HOST_BUF	UINT32_C(0x2)
60033 	#define HWRM_STAT_CTX_ALLOC_INPUT_FLAGS_STEERING_TAG_VALID	UINT32_C(0x1)
60101 	 * * 0x0-0xFFF8 - The function ID
60102 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60103 	 * * 0xFFFD - Reserved for user-space HWRM interface
60104 	 * * 0xFFFF - HWRM
60166 	 * * 0x0-0xFFF8 - The function ID
60167 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60168 	 * * 0xFFFD - Reserved for user-space HWRM interface
60169 	 * * 0xFFFF - HWRM
60187 	#define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK	UINT32_C(0x1)
60276 	 * * 0x0-0xFFF8 - The function ID
60277 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60278 	 * * 0xFFFD - Reserved for user-space HWRM interface
60279 	 * * 0xFFFF - HWRM
60297 	#define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK	UINT32_C(0x1)
60390 	 * * 0x0-0xFFF8 - The function ID
60391 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60392 	 * * 0xFFFD - Reserved for user-space HWRM interface
60393 	 * * 0xFFFF - HWRM
60494 	 * * 0x0-0xFFF8 - The function ID
60495 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60496 	 * * 0xFFFD - Reserved for user-space HWRM interface
60497 	 * * 0xFFFF - HWRM
60557 	 * * 0x0-0xFFF8 - The function ID
60558 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60559 	 * * 0xFFFD - Reserved for user-space HWRM interface
60560 	 * * 0xFFFF - HWRM
60668 	 * * 0x0-0xFFF8 - The function ID
60669 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60670 	 * * 0xFFFD - Reserved for user-space HWRM interface
60671 	 * * 0xFFFF - HWRM
60695 	#define HWRM_STAT_GENERIC_QSTATS_INPUT_FLAGS_COUNTER_MASK	UINT32_C(0x1)
60855 	 * * 0x0-0xFFF8 - The function ID
60856 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60857 	 * * 0xFFFD - Reserved for user-space HWRM interface
60858 	 * * 0xFFFF - HWRM
60948 	 * * 0x0-0xFFF8 - The function ID
60949 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60950 	 * * 0xFFFD - Reserved for user-space HWRM interface
60951 	 * * 0xFFFF - HWRM
60964 	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT		UINT32_C(0x0)
60966 	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT		UINT32_C(0x1)
60968 	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL		UINT32_C(0x2)
60970 	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE		UINT32_C(0x3)
60975 	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST		UINT32_C(0x4)
60980 	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP			UINT32_C(0x5)
60982 	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP		UINT32_C(0x6)
60987 	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT  UINT32_C(0x7)
60993 	 * status is set to a non-0x8000 value to disambiguate reset pending
60997 	#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION UINT32_C(0x8)
61002 	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE	UINT32_C(0x0)
61004 	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP	UINT32_C(0x1)
61006 	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST   UINT32_C(0x2)
61008 	#define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE UINT32_C(0x3)
61011 	 * Indicate which host is being reset. 0 means first host.
61023 	#define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL	UINT32_C(0x1)
61030 	#define HWRM_FW_RESET_INPUT_FLAGS_FW_ACTIVATION	UINT32_C(0x2)
61048 	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE	UINT32_C(0x0)
61050 	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP	UINT32_C(0x1)
61052 	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST   UINT32_C(0x2)
61054 	#define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE UINT32_C(0x3)
61090 	 * * 0x0-0xFFF8 - The function ID
61091 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61092 	 * * 0xFFFD - Reserved for user-space HWRM interface
61093 	 * * 0xFFFF - HWRM
61106 	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_BOOT	UINT32_C(0x0)
61108 	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_MGMT	UINT32_C(0x1)
61110 	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)
61112 	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_ROCE	UINT32_C(0x3)
61117 	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_HOST	UINT32_C(0x4)
61122 	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_AP	UINT32_C(0x5)
61124 	#define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_CHIP	UINT32_C(0x6)
61143 	#define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTNONE	UINT32_C(0x0)
61145 	#define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTASAP	UINT32_C(0x1)
61147 	#define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
61149 	#define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPOWER   UINT32_C(0x3)
61158 	#define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE	UINT32_C(0x0)
61160 	#define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET UINT32_C(0x1)
61162 	#define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT UINT32_C(0x2)
61164 	#define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT UINT32_C(0x3)
61200 	 * * 0x0-0xFFF8 - The function ID
61201 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61202 	 * * 0xFFFD - Reserved for user-space HWRM interface
61203 	 * * 0xFFFF - HWRM
61216 	#define HWRM_FW_SET_TIME_INPUT_YEAR_UNKNOWN UINT32_C(0x0)
61222 	/* Current hour (0-23) */
61224 	/* Current minute (0-59) */
61226 	/* Current second (0-59) */
61229 	/* Current millisecond (0-999) */
61231 	/* Minutes east of UTC, 0xffff if TZ is not known */
61234 	#define HWRM_FW_SET_TIME_INPUT_ZONE_UTC	0
61286 	 * * 0x0-0xFFF8 - The function ID
61287 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61288 	 * * 0xFFFD - Reserved for user-space HWRM interface
61289 	 * * 0xFFFF - HWRM
61315 	#define HWRM_FW_GET_TIME_OUTPUT_YEAR_UNKNOWN UINT32_C(0x0)
61321 	/* Current hour (0-23) */
61323 	/* Current minute (0-59) */
61325 	/* Current second (0-59) */
61328 	/* Current millisecond (0-999) */
61330 	/* Minutes east of UTC, 0xffff if TZ is not known */
61333 	#define HWRM_FW_GET_TIME_OUTPUT_ZONE_UTC	0
61354 	#define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_CFG	UINT32_C(0x41b)
61356 	#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_ETS	UINT32_C(0x41d)
61358 	#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_PFC	UINT32_C(0x41f)
61360 	#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_APP	UINT32_C(0x421)
61362 	#define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE UINT32_C(0x422)
61367 	#define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_GENERIC	UINT32_C(0x424)
61372 	#define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_DEVICE	UINT32_C(0x426)
61374 	#define HWRM_STRUCT_HDR_STRUCT_ID_POWER_BKUP	UINT32_C(0x427)
61376 	#define HWRM_STRUCT_HDR_STRUCT_ID_PEER_MMAP	UINT32_C(0x429)
61378 	#define HWRM_STRUCT_HDR_STRUCT_ID_AFM_OPAQUE	UINT32_C(0x1)
61380 	#define HWRM_STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION   UINT32_C(0xa)
61382 	#define HWRM_STRUCT_HDR_STRUCT_ID_RSS_V2		UINT32_C(0x64)
61384 	#define HWRM_STRUCT_HDR_STRUCT_ID_MSIX_PER_VF	UINT32_C(0xc8)
61396 	 * header. A value of 0 means that this is the last element. The value is
61401 	#define HWRM_STRUCT_HDR_NEXT_OFFSET_LAST UINT32_C(0x0)
61415 	#define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION   UINT32_C(0x1)
61417 	#define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION UINT32_C(0x2)
61423 	/* ETS priority 0 to TC map. */
61439 	/* ETS TC 0 to bandwidth map. */
61455 	/* ETS TC 0 to TSA map. */
61458 	#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP		UINT32_C(0x0)
61460 	#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS		UINT32_C(0x1)
61462 	#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS		UINT32_C(0x2)
61464 	#define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC UINT32_C(0xff)
61487 	 * This field indicates PFC priority bit map. A value of '0' indicates
61499 	 * of '1' indicates MBC is enabled. A value of '0' indicates MBC is
61520 	#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE   UINT32_C(0x1)
61522 	#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT	UINT32_C(0x2)
61524 	#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT	UINT32_C(0x3)
61526 	#define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT UINT32_C(0x4)
61541 	#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED UINT32_C(0x0)
61543 	#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE	UINT32_C(0x1)
61545 	#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE	UINT32_C(0x2)
61554 	#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS	UINT32_C(0x7)
61556 	#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS   UINT32_C(0x6)
61558 	#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS UINT32_C(0x5)
61568 	#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS   UINT32_C(0x1)
61570 	#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC   UINT32_C(0x2)
61572 	#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP   UINT32_C(0x4)
61574 	#define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE UINT32_C(0x8)
61584 	#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE UINT32_C(0x0)
61586 	#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_TX	UINT32_C(0x1)
61588 	#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_RX	UINT32_C(0x2)
61590 	#define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE  UINT32_C(0x3)
61592 	/* Port description TLV transmit state (enable(1)/disable(0)). */
61595 	#define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE UINT32_C(0x0)
61597 	#define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE  UINT32_C(0x1)
61599 	/* System name TLV transmit state (enable(1)/disable(0)). */
61602 	#define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE UINT32_C(0x0)
61604 	#define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE  UINT32_C(0x1)
61606 	/* System description TLV transmit state (enable(1)/disable(0)). */
61609 	#define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE UINT32_C(0x0)
61611 	#define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE  UINT32_C(0x1)
61613 	/* System capabilities TLV transmit state (enable(1)/disable(0)). */
61616 	#define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE UINT32_C(0x0)
61618 	#define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE  UINT32_C(0x1)
61620 	/* Management address TLV transmit state (enable(1)/disable(0)). */
61623 	#define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE UINT32_C(0x0)
61625 	#define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE  UINT32_C(0x1)
61627 	/* Async event notification state (enable(1)/disable(0)). */
61630 	#define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE UINT32_C(0x0)
61632 	#define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE  UINT32_C(0x1)
61643 	#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS		UINT32_C(0x1)
61645 	#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT		UINT32_C(0x2)
61647 	#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME	UINT32_C(0x3)
61649 	#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION UINT32_C(0x4)
61651 	#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME	UINT32_C(0x5)
61653 	#define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION   UINT32_C(0x6)
61695 	 * Port #. Port number starts at 0 and anything greater than number of
61707 	#define HWRM_STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID	UINT32_C(0x1)
61718 	#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4	UINT32_C(0x1)
61724 	#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4	UINT32_C(0x2)
61730 	#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4	UINT32_C(0x4)
61736 	#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6	UINT32_C(0x8)
61742 	#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6	UINT32_C(0x10)
61748 	#define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6	UINT32_C(0x20)
61781 	 * be 0xffff for current PF or a valid VF fid for child
61787 	 * be > 0 and <= 8. Maximum of 8 mappings are supported.
61791 	/* Host Physical Address for mapping 0. */
61793 	/* Guest Physical Address for mapping 0. */
61795 	/* Size in Kilobytes for mapping 0. */
61849 	/* Starting VF for row 0 */
61851 	/* MSI-X vectors per VF for row 0 */
61906 	 * * 0x0-0xFFF8 - The function ID
61907 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61908 	 * * 0xFFFD - Reserved for user-space HWRM interface
61909 	 * * 0xFFFF - HWRM
61965 	#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN	UINT32_C(0x0)
61967 	#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT UINT32_C(0x1)
61969 	#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT	UINT32_C(0x2)
61971 	#define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID	UINT32_C(0x3)
61999 	 * * 0x0-0xFFF8 - The function ID
62000 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62001 	 * * 0xFFFD - Reserved for user-space HWRM interface
62002 	 * * 0xFFFF - HWRM
62039 	#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_UNUSED		UINT32_C(0x0)
62040 	#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_ALL			UINT32_C(0xffff)
62041 	#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_ADMIN	UINT32_C(0x100)
62042 	#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_PEER	UINT32_C(0x101)
62043 	#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_OPERATIONAL UINT32_C(0x102)
62044 	#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_ADMIN	UINT32_C(0x200)
62045 	#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_PEER	UINT32_C(0x201)
62046 	#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_OPERATIONAL	UINT32_C(0x202)
62047 	#define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL	UINT32_C(0x300)
62090 	#define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
62092 	#define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID  UINT32_C(0x3)
62120 	 * * 0x0-0xFFF8 - The function ID
62121 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62122 	 * * 0xFFFD - Reserved for user-space HWRM interface
62123 	 * * 0xFFFF - HWRM
62138 	#define HWRM_FW_IPC_MSG_INPUT_ENABLES_COMMAND_ID	UINT32_C(0x1)
62143 	#define HWRM_FW_IPC_MSG_INPUT_ENABLES_SRC_PROCESSOR	UINT32_C(0x2)
62148 	#define HWRM_FW_IPC_MSG_INPUT_ENABLES_DATA_OFFSET	UINT32_C(0x4)
62153 	#define HWRM_FW_IPC_MSG_INPUT_ENABLES_LENGTH		UINT32_C(0x8)
62157 	#define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_LAG	UINT32_C(0x1)
62159 	#define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_MHB_HOST	UINT32_C(0x2)
62161 	#define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_DRVR_VERSION UINT32_C(0x3)
62166 	#define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_CFW  UINT32_C(0x1)
62168 	#define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_BONO UINT32_C(0x2)
62170 	#define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_APE  UINT32_C(0x3)
62172 	#define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_KONG UINT32_C(0x4)
62232 	 * * 0x0-0xFFF8 - The function ID
62233 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62234 	 * * 0xFFFD - Reserved for user-space HWRM interface
62235 	 * * 0xFFFF - HWRM
62290 	#define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
62292 	#define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID  UINT32_C(0x3)
62320 	 * * 0x0-0xFFF8 - The function ID
62321 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62322 	 * * 0xFFFD - Reserved for user-space HWRM interface
62323 	 * * 0xFFFF - HWRM
62343 	 * Setting this bit to '0' disables ECN immediately.
62345 	#define HWRM_FW_ECN_CFG_INPUT_FLAGS_ENABLE_ECN	UINT32_C(0x1)
62394 	 * * 0x0-0xFFF8 - The function ID
62395 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62396 	 * * 0xFFFD - Reserved for user-space HWRM interface
62397 	 * * 0xFFFF - HWRM
62422 	#define HWRM_FW_ECN_QCFG_OUTPUT_FLAGS_ENABLE_ECN	UINT32_C(0x1)
62457 	 * * 0x0-0xFFF8 - The function ID
62458 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62459 	 * * 0xFFFD - Reserved for user-space HWRM interface
62460 	 * * 0xFFFF - HWRM
62485 	 * This bit is '0' if the primary SBI was used this boot,
62488 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SBI_BOOTED	UINT32_C(0x1)
62490 	 * This bit is '0' if the primary and secondary SBI images
62493 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SBI_MISMATCH	UINT32_C(0x2)
62495 	 * This bit is '0' if the primary SRT was used this boot,
62498 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT_BOOTED	UINT32_C(0x4)
62500 	 * This bit is '0' if the primary and secondary SRT images
62503 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT_MISMATCH	UINT32_C(0x8)
62505 	 * This bit is '0' if the primary CRT (or second stage SRT)
62509 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT_BOOTED	UINT32_C(0x10)
62511 	 * This bit is '0' if the primary and secondary CRT images
62515 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT_MISMATCH	UINT32_C(0x20)
62517 	 * This bit is '0' if the second stage RT image is a CRT,
62520 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SECOND_RT		UINT32_C(0x40)
62522 	 * This bit is '0' if the image was loaded from flash,
62525 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FASTBOOTED	UINT32_C(0x80)
62527 	 * This bit is '0' if the primary dir_hdr was used to locate
62530 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_DIR_HDR_BOOTED	UINT32_C(0x100)
62532 	 * This bit is '0' if the primary and secondary dir_hdr match,
62535 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_DIR_HDR_MISMATCH	UINT32_C(0x200)
62537 	 * This bit is '0' if the Master Boot Record is in good condition,
62540 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_MBR_CORRUPT	UINT32_C(0x400)
62542 	 * This bit is '0' if the configuration is in good condition,
62545 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CFG_MISMATCH	UINT32_C(0x800)
62547 	 * This bit is '0' if both FRU entries match,
62550 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FRU_MISMATCH	UINT32_C(0x1000)
62552 	 * This bit is '0' if the primary CRT2 was used this boot,
62555 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT2_BOOTED	UINT32_C(0x2000)
62557 	 * This bit is '0' if the primary and secondary CRT2 images
62560 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT2_MISMATCH	UINT32_C(0x4000)
62562 	 * This bit is '0' if the primary GXRT was used this boot,
62565 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_GXRT_BOOTED	UINT32_C(0x8000)
62567 	 * This bit is '0' if the primary and secondary GXRT images
62570 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_GXRT_MISMATCH	UINT32_C(0x10000)
62572 	 * This bit is '0' if the primary SRT2 was used this boot,
62575 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT2_BOOTED	UINT32_C(0x20000)
62577 	 * This bit is '0' if the primary and secondary SRT2 images
62580 	#define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT2_MISMATCH	UINT32_C(0x40000)
62615 	 * * 0x0-0xFFF8 - The function ID
62616 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62617 	 * * 0xFFFD - Reserved for user-space HWRM interface
62618 	 * * 0xFFFF - HWRM
62631 	#define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_COMMON_FW UINT32_C(0x1)
62633 	#define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_SECURE_FW UINT32_C(0x2)
62661 	#define HWRM_FW_LIVEPATCH_QUERY_OUTPUT_STATUS_FLAGS_INSTALL	UINT32_C(0x1)
62663 	#define HWRM_FW_LIVEPATCH_QUERY_OUTPUT_STATUS_FLAGS_ACTIVE	UINT32_C(0x2)
62698 	 * * 0x0-0xFFF8 - The function ID
62699 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62700 	 * * 0xFFFD - Reserved for user-space HWRM interface
62701 	 * * 0xFFFF - HWRM
62719 	#define HWRM_FW_LIVEPATCH_INPUT_OPCODE_ACTIVATE   UINT32_C(0x1)
62724 	#define HWRM_FW_LIVEPATCH_INPUT_OPCODE_DEACTIVATE UINT32_C(0x2)
62729 	#define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_COMMON_FW UINT32_C(0x1)
62731 	#define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_SECURE_FW UINT32_C(0x2)
62736 	#define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_NVM_INSTALL   UINT32_C(0x1)
62741 	#define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_MEMORY_DIRECT UINT32_C(0x2)
62782 	#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN	UINT32_C(0x0)
62784 	#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE  UINT32_C(0x1)
62786 	#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET  UINT32_C(0x2)
62788 	#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED   UINT32_C(0x3)
62790 	#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED   UINT32_C(0x4)
62792 	#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED	UINT32_C(0x5)
62794 	#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL	UINT32_C(0x6)
62796 	#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER  UINT32_C(0x7)
62798 	#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE	UINT32_C(0x8)
62803 	#define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED UINT32_C(0x9)
62831 	 * * 0x0-0xFFF8 - The function ID
62832 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62833 	 * * 0xFFFD - Reserved for user-space HWRM interface
62834 	 * * 0xFFFF - HWRM
62851 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SBI	UINT32_C(0x1)
62858 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SRT	UINT32_C(0x2)
62866 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CRT	UINT32_C(0x4)
62873 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_DIR_HDR	UINT32_C(0x8)
62878 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_WRITE_MBR	UINT32_C(0x10)
62883 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CFG	UINT32_C(0x20)
62889 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_FRU	UINT32_C(0x40)
62896 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CRT2	UINT32_C(0x80)
62903 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_GXRT	UINT32_C(0x100)
62910 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SRT2	UINT32_C(0x200)
62915 	 * A value of '0' just requests the status for the previously
62918 	#define HWRM_FW_SYNC_INPUT_SYNC_ACTION_ACTION	UINT32_C(0x80000000)
62935 	#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_MASK	UINT32_C(0xff)
62936 	#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_SFT	0
62938 		#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_SUCCESS	UINT32_C(0x0)
62943 		#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_IN_PROGRESS  UINT32_C(0x1)
62945 		#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_TIMEOUT	UINT32_C(0x2)
62947 		#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_GENERAL	UINT32_C(0x3)
62954 	#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_SYNC_ERR		UINT32_C(0x40000000)
62956 	 * This bit is '0' if the previously requested synchronization
62962 	#define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_SYNC_COMPLETE	UINT32_C(0x80000000)
62997 	 * * 0x0-0xFFF8 - The function ID
62998 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62999 	 * * 0xFFFD - Reserved for user-space HWRM interface
63000 	 * * 0xFFFF - HWRM
63053 	 * for status 0x8000.
63058 	 * 0x8000 before assuming a reset failure occurred. This time does
63098 	 * * 0x0-0xFFF8 - The function ID
63099 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63100 	 * * 0xFFFD - Reserved for user-space HWRM interface
63101 	 * * 0xFFFF - HWRM
63125 	#define HWRM_FW_STATE_QUIESCE_INPUT_FLAGS_ERROR_RECOVERY	UINT32_C(0x1)
63145 	#define HWRM_FW_STATE_QUIESCE_OUTPUT_QUIESCE_STATUS_INITIATED	UINT32_C(0x80000000)
63182 	 * * 0x0-0xFFF8 - The function ID
63183 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63184 	 * * 0xFFFD - Reserved for user-space HWRM interface
63185 	 * * 0xFFFF - HWRM
63210 	#define HWRM_FW_STATE_UNQUIESCE_OUTPUT_UNQUIESCE_STATUS_COMPLETE	UINT32_C(0x80000000)
63246 	 * * 0x0-0xFFF8 - The function ID
63247 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63248 	 * * 0xFFFD - Reserved for user-space HWRM interface
63249 	 * * 0xFFFF - HWRM
63262 	#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_MASK	UINT32_C(0xf)
63263 	#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_SFT	0
63265 		#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_0	UINT32_C(0x0)
63267 		#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_1	UINT32_C(0x1)
63272 		#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_2	UINT32_C(0x2)
63275 	#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_MASK  UINT32_C(0xf0)
63278 		#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
63280 		#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
63282 		#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
63284 		#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
63286 		#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
63288 		#define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
63311 	#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_MASK	UINT32_C(0xff)
63312 	#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_SFT	0
63314 		#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_SUCCESS	UINT32_C(0x0)
63316 		#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_QUIESCE_ERROR  UINT32_C(0x1)
63318 		#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_GENERAL	UINT32_C(0x3)
63321 	 * This bit is '0' if the backout was done in a way that firmware
63329 	#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_RESET_REQUIRED	UINT32_C(0x40000000)
63331 	#define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_COMPLETE		UINT32_C(0x80000000)
63367 	 * * 0x0-0xFFF8 - The function ID
63368 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63369 	 * * 0xFFFD - Reserved for user-space HWRM interface
63370 	 * * 0xFFFF - HWRM
63383 	#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_MASK	UINT32_C(0xf)
63384 	#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_SFT	0
63386 		#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_0	UINT32_C(0x0)
63388 		#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_1	UINT32_C(0x1)
63393 		#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_2	UINT32_C(0x2)
63396 	#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_MASK  UINT32_C(0xf0)
63399 		#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
63401 		#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
63403 		#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
63405 		#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
63407 		#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
63409 		#define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
63432 	#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_MASK		UINT32_C(0xff)
63433 	#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_SFT		0
63435 		#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_SUCCESS		UINT32_C(0x0)
63437 		#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_GENERAL		UINT32_C(0x1)
63439 		#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_FORMAT_PARSE		UINT32_C(0x2)
63441 		#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_INTEGRITY_CHECK	UINT32_C(0x3)
63444 	 * If a failure occurs (complete is 0), restore attempts to
63449 	#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_FAILURE_ROLLBACK_COMPLETED	UINT32_C(0x40000000)
63451 	#define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_COMPLETE			UINT32_C(0x80000000)
63486 	 * * 0x0-0xFFF8 - The function ID
63487 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63488 	 * * 0xFFFD - Reserved for user-space HWRM interface
63489 	 * * 0xFFFF - HWRM
63502 	#define HWRM_FW_SECURE_CFG_INPUT_ENABLE_NVRAM UINT32_C(0x1)
63504 	#define HWRM_FW_SECURE_CFG_INPUT_ENABLE_GRC   UINT32_C(0x2)
63506 	#define HWRM_FW_SECURE_CFG_INPUT_ENABLE_UART  UINT32_C(0x3)
63514 	#define HWRM_FW_SECURE_CFG_INPUT_CONFIG_MODE_PERSISTENT	UINT32_C(0x1)
63516 	#define HWRM_FW_SECURE_CFG_INPUT_CONFIG_MODE_RUNTIME	UINT32_C(0x2)
63523 	#define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_NONE	UINT32_C(0x0)
63528 	#define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_PARTIAL UINT32_C(0x1)
63533 	#define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_FULL	UINT32_C(0x2)
63539 	#define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_CHIP	UINT32_C(0x3)
63547 	#define HWRM_FW_SECURE_CFG_INPUT_NVM_PARTIAL_LOCK_MASK_EXE	UINT32_C(0x1)
63549 	#define HWRM_FW_SECURE_CFG_INPUT_NVM_PARTIAL_LOCK_MASK_CFG	UINT32_C(0x2)
63553 	#define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RO UINT32_C(0x0)
63555 	#define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RW UINT32_C(0x1)
63560 	#define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_DISABLE UINT32_C(0x0)
63562 	#define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_ENABLE  UINT32_C(0x1)
63614 	 * * 0x0-0xFFF8 - The function ID
63615 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63616 	 * * 0xFFFD - Reserved for user-space HWRM interface
63617 	 * * 0xFFFF - HWRM
63637 	 * 0x0 - 0xFFF8 - Used for function ids
63638 	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
63639 	 * 0xFFFF - HWRM
63690 	 * * 0x0-0xFFF8 - The function ID
63691 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63692 	 * * 0xFFFD - Reserved for user-space HWRM interface
63693 	 * * 0xFFFF - HWRM
63713 	 * 0x0 - 0xFFF8 - Used for function ids
63714 	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
63715 	 * 0xFFFF - HWRM
63766 	 * * 0x0-0xFFF8 - The function ID
63767 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63768 	 * * 0xFFFD - Reserved for user-space HWRM interface
63769 	 * * 0xFFFF - HWRM
63782 	 * 0x0 - 0xFFF8 - Used for function ids
63783 	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
63784 	 * 0xFFFF - HWRM
63857 	 * * 0x0-0xFFF8 - The function ID
63858 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63859 	 * * 0xFFFD - Reserved for user-space HWRM interface
63860 	 * * 0xFFFF - HWRM
63873 	 * 0x0 - 0xFFF8 - Used for function ids
63874 	 * 0xFFF8 - 0xFFFE - Reserved for internal processors
63875 	 * 0xFFFF - Broadcast to all children VFs (only applicable when
63929 	 * * 0x0-0xFFF8 - The function ID
63930 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63931 	 * * 0xFFFD - Reserved for user-space HWRM interface
63932 	 * * 0xFFFF - HWRM
63977 	#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_TEMP_NOT_AVAILABLE		UINT32_C(0x1)
63982 	#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_PHY_TEMP_NOT_AVAILABLE	UINT32_C(0x2)
63984 	#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_OM_NOT_PRESENT		UINT32_C(0x4)
63989 	#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_OM_TEMP_NOT_AVAILABLE	UINT32_C(0x8)
63994 	#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_EXT_TEMP_FIELDS_AVAILABLE	UINT32_C(0x10)
63999 	#define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_THRESHOLD_VALUES_AVAILABLE	UINT32_C(0x20)
64002 	 * This field is unsigned and the value range of 0 to 255 is used to
64005 	 * Example: A value of 0 represents a temperature of -64, a value of
64011 	 * field is unsigned and the value range of 0 to 255 is used to
64014 	 * Example: A value of 0 represents a temperature of -64, a value of
64020 	 * This field is unsigned and the value range of 0 to 255 is used to
64023 	 * Example: A value of 0 represents a temperature of -64, a value of
64083 	 * * 0x0-0xFFF8 - The function ID
64084 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64085 	 * * 0xFFFD - Reserved for user-space HWRM interface
64086 	 * * 0xFFFF - HWRM
64112 	#define HWRM_REG_POWER_QUERY_OUTPUT_FLAGS_IN_POWER_AVAILABLE	UINT32_C(0x1)
64114 	#define HWRM_REG_POWER_QUERY_OUTPUT_FLAGS_OUT_POWER_AVAILABLE	UINT32_C(0x2)
64159 	 * * 0x0-0xFFF8 - The function ID
64160 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64161 	 * * 0xFFFD - Reserved for user-space HWRM interface
64162 	 * * 0xFFFF - HWRM
64221 	 * * 0x0-0xFFF8 - The function ID
64222 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64223 	 * * 0xFFFD - Reserved for user-space HWRM interface
64224 	 * * 0xFFFF - HWRM
64240 	#define HWRM_REG_POWER_HISTOGRAM_INPUT_FLAGS_CLEAR_HISTOGRAM	UINT32_C(0x1)
64264 	#define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT	UINT32_C(0x1)
64269 		#define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_INPUT   UINT32_C(0x0)
64274 		#define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_OUTPUT  UINT32_C(0x1)
64298 	 * value, 0xFFFFFFFF, and do not roll over. Clients should use the
64323 #define BUCKET_NO_DATA_FOR_SAMPLE UINT32_C(0x0)
64325 #define BUCKET_RANGE_8W_OR_LESS   UINT32_C(0x1)
64327 #define BUCKET_RANGE_8W_TO_9W	UINT32_C(0x2)
64329 #define BUCKET_RANGE_9W_TO_10W	UINT32_C(0x3)
64331 #define BUCKET_RANGE_10W_TO_11W   UINT32_C(0x4)
64333 #define BUCKET_RANGE_11W_TO_12W   UINT32_C(0x5)
64335 #define BUCKET_RANGE_12W_TO_13W   UINT32_C(0x6)
64337 #define BUCKET_RANGE_13W_TO_14W   UINT32_C(0x7)
64339 #define BUCKET_RANGE_14W_TO_15W   UINT32_C(0x8)
64341 #define BUCKET_RANGE_15W_TO_16W   UINT32_C(0x9)
64343 #define BUCKET_RANGE_16W_TO_18W   UINT32_C(0xa)
64345 #define BUCKET_RANGE_18W_TO_20W   UINT32_C(0xb)
64347 #define BUCKET_RANGE_20W_TO_22W   UINT32_C(0xc)
64349 #define BUCKET_RANGE_22W_TO_24W   UINT32_C(0xd)
64351 #define BUCKET_RANGE_24W_TO_26W   UINT32_C(0xe)
64353 #define BUCKET_RANGE_26W_TO_28W   UINT32_C(0xf)
64355 #define BUCKET_RANGE_28W_TO_30W   UINT32_C(0x10)
64357 #define BUCKET_RANGE_30W_TO_32W   UINT32_C(0x11)
64359 #define BUCKET_RANGE_32W_TO_34W   UINT32_C(0x12)
64361 #define BUCKET_RANGE_34W_TO_36W   UINT32_C(0x13)
64363 #define BUCKET_RANGE_36W_TO_38W   UINT32_C(0x14)
64365 #define BUCKET_RANGE_38W_TO_40W   UINT32_C(0x15)
64367 #define BUCKET_RANGE_40W_TO_42W   UINT32_C(0x16)
64369 #define BUCKET_RANGE_42W_TO_44W   UINT32_C(0x17)
64371 #define BUCKET_RANGE_44W_TO_50W   UINT32_C(0x18)
64373 #define BUCKET_RANGE_OVER_50W	UINT32_C(0x19)
64400 	 * * 0x0-0xFFF8 - The function ID
64401 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64402 	 * * 0xFFFD - Reserved for user-space HWRM interface
64403 	 * * 0xFFFF - HWRM
64419 	#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_MAC_ADDRESS	UINT32_C(0x1)
64424 	#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_OFFSET	UINT32_C(0x2)
64429 	#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_SIZE	UINT32_C(0x4)
64434 	#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_ADDR	UINT32_C(0x8)
64439 	#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_ADDR	UINT32_C(0x10)
64444 	#define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_SIZE	UINT32_C(0x20)
64450 	#define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0)
64452 	#define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_BMP	UINT32_C(0x1)
64454 	#define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_INVALID  UINT32_C(0xff)
64464 	 * 0xFF in this command, then the HWRM
64469 	 * 0xFF in this command, then the HWRM
64549 	 * * 0x0-0xFFF8 - The function ID
64550 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64551 	 * * 0xFFFD - Reserved for user-space HWRM interface
64552 	 * * 0xFFFF - HWRM
64570 	#define HWRM_WOL_FILTER_FREE_INPUT_FLAGS_FREE_ALL_WOL_FILTERS	UINT32_C(0x1)
64576 	#define HWRM_WOL_FILTER_FREE_INPUT_ENABLES_WOL_FILTER_ID	UINT32_C(0x1)
64632 	 * * 0x0-0xFFF8 - The function ID
64633 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64634 	 * * 0xFFFD - Reserved for user-space HWRM interface
64635 	 * * 0xFFFF - HWRM
64649 	 * # The HWRM client shall set this field to 0x0000 to begin
64660 	 * # Value of 0 indicates an invalid buffer address.
64661 	 * If this field is set to 0, then HWRM shall ignore
64678 	 * # Value of 0 indicates an invalid pattern mask address.
64679 	 * If this field is set to 0, then HWRM shall ignore
64708 	 * # If this field is set to 0x0000, then no WoL filters are
64711 	 * # If this field is set to neither 0x0000 nor 0xFFFF, then the
64714 	 * # If this field is set to 0xFFFF, then there are no remaining
64731 	#define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0)
64733 	#define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_BMP	UINT32_C(0x1)
64735 	#define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_INVALID  UINT32_C(0xff)
64793 	 * * 0x0-0xFFF8 - The function ID
64794 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64795 	 * * 0xFFFD - Reserved for user-space HWRM interface
64796 	 * * 0xFFFF - HWRM
64845 	#define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_MAGICPKT UINT32_C(0x0)
64847 	#define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_BMP	UINT32_C(0x1)
64849 	#define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID  UINT32_C(0xff)
64887 	 * * 0x0-0xFFF8 - The function ID
64888 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64889 	 * * 0xFFFD - Reserved for user-space HWRM interface
64890 	 * * 0xFFFF - HWRM
64962 	 * * 0x0-0xFFF8 - The function ID
64963 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64964 	 * * 0xFFFD - Reserved for user-space HWRM interface
64965 	 * * 0xFFFF - HWRM
65028 	 * * 0x0-0xFFF8 - The function ID
65029 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65030 	 * * 0xFFFD - Reserved for user-space HWRM interface
65031 	 * * 0xFFFF - HWRM
65051 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2	UINT32_C(0x0)
65053 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4	UINT32_C(0x1)
65055 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2	UINT32_C(0x2)
65057 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4	UINT32_C(0x3)
65059 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS		UINT32_C(0x4)
65061 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM		UINT32_C(0x5)
65063 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM		UINT32_C(0x6)
65065 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM	UINT32_C(0x7)
65067 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM	UINT32_C(0x8)
65069 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9)
65071 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa)
65073 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM	UINT32_C(0xb)
65075 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc)
65077 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd)
65079 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM	UINT32_C(0xe)
65081 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM	UINT32_C(0xf)
65083 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB			UINT32_C(0x10)
65085 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL		UINT32_C(0x11)
65087 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC		UINT32_C(0x12)
65089 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_PRIVATE		UINT32_C(0x13)
65091 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_HOST_DMA		UINT32_C(0x14)
65095 	 * in the opaque[0] field.
65096 	 * 1) sub-type CHECK(0) if ELOG is available in media.
65102 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_SOC_ELOG		UINT32_C(0x15)
65104 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CTX			UINT32_C(0x16)
65106 	#define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS			UINT32_C(0x17)
65165 	 * * 0x0-0xFFF8 - The function ID
65166 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65167 	 * * 0xFFFD - Reserved for user-space HWRM interface
65168 	 * * 0xFFFF - HWRM
65181 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2	UINT32_C(0x0)
65183 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4	UINT32_C(0x1)
65185 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2	UINT32_C(0x2)
65187 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4	UINT32_C(0x3)
65189 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS		UINT32_C(0x4)
65191 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM		UINT32_C(0x5)
65193 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM		UINT32_C(0x6)
65195 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM	UINT32_C(0x7)
65197 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM	UINT32_C(0x8)
65199 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9)
65201 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa)
65203 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM	UINT32_C(0xb)
65205 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc)
65207 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd)
65209 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM	UINT32_C(0xe)
65211 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM	UINT32_C(0xf)
65213 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB			UINT32_C(0x10)
65215 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL		UINT32_C(0x11)
65217 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC		UINT32_C(0x12)
65219 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_PRIVATE		UINT32_C(0x13)
65221 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_HOST_DMA		UINT32_C(0x14)
65223 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_SOC_ELOG		UINT32_C(0x15)
65225 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CTX			UINT32_C(0x16)
65227 	#define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS			UINT32_C(0x17)
65286 	 * * 0x0-0xFFF8 - The function ID
65287 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65288 	 * * 0xFFFD - Reserved for user-space HWRM interface
65289 	 * * 0xFFFF - HWRM
65301 	 * handle = 0 indicates the beginning of the dump.
65302 	 * handle != 0 indicates the request to dump the next part.
65329 	 * nexthandle = 0 indicates that there is no more debug data
65331 	 * nexthandle != 0 indicates the handle value that should be used
65374 	 * * 0x0-0xFFF8 - The function ID
65375 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65376 	 * * 0xFFFD - Reserved for user-space HWRM interface
65377 	 * * 0xFFFF - HWRM
65389 	#define HWRM_DBG_ERASE_NVM_INPUT_FLAGS_ERASE_ALL		UINT32_C(0x1)
65397 	#define HWRM_DBG_ERASE_NVM_INPUT_FLAGS_SECURITY_SOC_NVM	UINT32_C(0x2)
65446 	 * * 0x0-0xFFF8 - The function ID
65447 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65448 	 * * 0xFFFD - Reserved for user-space HWRM interface
65449 	 * * 0xFFFF - HWRM
65464 	#define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG		UINT32_C(0x1)
65470 	#define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG_SECONDARY	UINT32_C(0x2)
65475 	#define HWRM_DBG_CFG_INPUT_FLAGS_FW_TRACE		UINT32_C(0x4)
65480 	#define HWRM_DBG_CFG_INPUT_FLAGS_FW_TRACE_SECONDARY	UINT32_C(0x8)
65485 	#define HWRM_DBG_CFG_INPUT_FLAGS_DEBUG_NOTIFY	UINT32_C(0x10)
65492 	#define HWRM_DBG_CFG_INPUT_FLAGS_JTAG_DEBUG		UINT32_C(0x20)
65547 	 * * 0x0-0xFFF8 - The function ID
65548 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65549 	 * * 0xFFFD - Reserved for user-space HWRM interface
65550 	 * * 0xFFFF - HWRM
65592 	#define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_UTC				0
65650 	 * have '\0' character.
65692 	 * * 0x0-0xFFF8 - The function ID
65693 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65694 	 * * 0xFFFD - Reserved for user-space HWRM interface
65695 	 * * 0xFFFF - HWRM
65711 	#define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_INVALIDATE UINT32_C(0x0)
65719 	#define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_REINIT	UINT32_C(0x1)
65770 	 * * 0x0-0xFFF8 - The function ID
65771 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65772 	 * * 0xFFFD - Reserved for user-space HWRM interface
65773 	 * * 0xFFFF - HWRM
65785 	 * 0xFF... (All Fs) if the query is for the requesting
65818 	#define HWRM_DBG_QCAPS_OUTPUT_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM	UINT32_C(0x1)
65821 	#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_NVM		UINT32_C(0x1)
65823 	#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_HOST_DDR	UINT32_C(0x2)
65825 	#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_SOC_DDR	UINT32_C(0x4)
65827 	#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_USEQ			UINT32_C(0x8)
65833 	#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_COREDUMP_HOST_DDR	UINT32_C(0x10)
65840 	#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_COREDUMP_HOST_CAPTURE	UINT32_C(0x20)
65847 	#define HWRM_DBG_QCAPS_OUTPUT_FLAGS_PTRACE			UINT32_C(0x40)
65882 	 * * 0x0-0xFFF8 - The function ID
65883 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65884 	 * * 0xFFFD - Reserved for user-space HWRM interface
65885 	 * * 0xFFFF - HWRM
65897 	 * 0xFF... (All Fs) if the query is for the requesting
65906 	#define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK	UINT32_C(0x3)
65907 	#define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT	0
65909 		#define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM	UINT32_C(0x0)
65911 		#define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR  UINT32_C(0x1)
65913 		#define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR   UINT32_C(0x2)
65924 	#define HWRM_DBG_QCFG_INPUT_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM	UINT32_C(0x1)
65955 	#define HWRM_DBG_QCFG_OUTPUT_FLAGS_UART_LOG		UINT32_C(0x1)
65960 	#define HWRM_DBG_QCFG_OUTPUT_FLAGS_UART_LOG_SECONDARY	UINT32_C(0x2)
65965 	#define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE		UINT32_C(0x4)
65970 	#define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE_SECONDARY	UINT32_C(0x8)
65975 	#define HWRM_DBG_QCFG_OUTPUT_FLAGS_DEBUG_NOTIFY	UINT32_C(0x10)
65982 	#define HWRM_DBG_QCFG_OUTPUT_FLAGS_JTAG_DEBUG		UINT32_C(0x20)
66029 	 * * 0x0-0xFFF8 - The function ID
66030 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66031 	 * * 0xFFFD - Reserved for user-space HWRM interface
66032 	 * * 0xFFFF - HWRM
66044 	#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_TYPE_DDR	UINT32_C(0x1)
66047 	#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_MASK	UINT32_C(0x3)
66048 	#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_SFT	0
66050 		#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_0	UINT32_C(0x0)
66052 		#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_1	UINT32_C(0x1)
66057 		#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_2	UINT32_C(0x2)
66060 	#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_MASK  UINT32_C(0x1c)
66063 		#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_4K   (UINT32_C(0x0) << 2)
66065 		#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_8K   (UINT32_C(0x1) << 2)
66067 		#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_64K  (UINT32_C(0x2) << 2)
66069 		#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_2M   (UINT32_C(0x3) << 2)
66071 		#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_8M   (UINT32_C(0x4) << 2)
66073 		#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_1G   (UINT32_C(0x5) << 2)
66076 	#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_UNUSED11_MASK UINT32_C(0xffe0)
66089 	#define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_NVRAM	UINT32_C(0x1)
66131 	 * bit 0: live data
66141 	#define SFLAG_COMPRESSED_ZLIB	UINT32_C(0x1)
66173 	 * * 0x0-0xFFF8 - The function ID
66174 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66175 	 * * 0xFFFD - Reserved for user-space HWRM interface
66176 	 * * 0xFFFF - HWRM
66193 	/* Sequence number of the request. Starts at 0. */
66199 	 * If set to 0, both live core and crash dump are requested.
66201 	#define HWRM_DBG_COREDUMP_LIST_INPUT_FLAGS_CRASHDUMP	UINT32_C(0x1)
66221 	#define HWRM_DBG_COREDUMP_LIST_OUTPUT_FLAGS_MORE	UINT32_C(0x1)
66261 	 * * 0x0-0xFFF8 - The function ID
66262 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66263 	 * * 0xFFFD - Reserved for user-space HWRM interface
66264 	 * * 0xFFFF - HWRM
66283 	 * bit 0: live data
66289 	#define HWRM_DBG_COREDUMP_INITIATE_INPUT_SEG_FLAGS_LIVE_DATA		UINT32_C(0x1)
66291 	#define HWRM_DBG_COREDUMP_INITIATE_INPUT_SEG_FLAGS_CRASH_DATA		UINT32_C(0x2)
66296 	#define HWRM_DBG_COREDUMP_INITIATE_INPUT_SEG_FLAGS_COLLECT_CTX_L1_CACHE	UINT32_C(0x4)
66329 	 * length: 0 - 23 bits represents the actual data without the pad.
66335 	#define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK	UINT32_C(0xffffff)
66336 	#define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT	0
66338 	#define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS	UINT32_C(0x1000000)
66368 	 * * 0x0-0xFFF8 - The function ID
66369 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66370 	 * * 0xFFFD - Reserved for user-space HWRM interface
66371 	 * * 0xFFFF - HWRM
66399 	 * bit 0: live data
66407 	/* Sequence number is used per segment request. Starts at 0. */
66428 	#define HWRM_DBG_COREDUMP_RETRIEVE_OUTPUT_FLAGS_MORE	UINT32_C(0x1)
66466 	 * * 0x0-0xFFF8 - The function ID
66467 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66468 	 * * 0xFFFD - Reserved for user-space HWRM interface
66469 	 * * 0xFFFF - HWRM
66506 	#define HWRM_DBG_I2C_CMD_INPUT_OPTIONS_10_BIT_ADDRESSING	UINT32_C(0x1)
66511 	#define HWRM_DBG_I2C_CMD_INPUT_OPTIONS_FAST_MODE		UINT32_C(0x2)
66517 	#define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_READ	UINT32_C(0x0)
66519 	#define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE	UINT32_C(0x1)
66521 	#define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE_READ UINT32_C(0x2)
66571 	 * * 0x0-0xFFF8 - The function ID
66572 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66573 	 * * 0xFFFD - Reserved for user-space HWRM interface
66574 	 * * 0xFFFF - HWRM
66645 	 * * 0x0-0xFFF8 - The function ID
66646 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66647 	 * * 0xFFFD - Reserved for user-space HWRM interface
66648 	 * * 0xFFFF - HWRM
66661 	#define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
66663 	#define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_TX	UINT32_C(0x1)
66665 	#define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_RX	UINT32_C(0x2)
66667 	#define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_NQ	UINT32_C(0x3)
66734 	 * * 0x0-0xFFF8 - The function ID
66735 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66736 	 * * 0xFFFD - Reserved for user-space HWRM interface
66737 	 * * 0xFFFF - HWRM
66750 	#define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_FATAL   UINT32_C(0x0)
66752 	#define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_ERROR   UINT32_C(0x1)
66754 	#define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_WARNING UINT32_C(0x2)
66756 	#define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_INFO	UINT32_C(0x3)
66758 	#define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_DEBUG   UINT32_C(0x4)
66815 	 * * 0x0-0xFFF8 - The function ID
66816 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66817 	 * * 0xFFFD - Reserved for user-space HWRM interface
66818 	 * * 0xFFFF - HWRM
66862 	#define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL	UINT32_C(0x1)
66864 	#define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
66907 	 * * 0x0-0xFFF8 - The function ID
66908 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66909 	 * * 0xFFFD - Reserved for user-space HWRM interface
66910 	 * * 0xFFFF - HWRM
66946 	#define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL	UINT32_C(0x1)
66948 	#define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
66989 	 * * 0x0-0xFFF8 - The function ID
66990 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66991 	 * * 0xFFFD - Reserved for user-space HWRM interface
66992 	 * * 0xFFFF - HWRM
67005 	#define HWRM_DBG_USEQ_FLUSH_INPUT_USEQ_CODE_WORDS UINT32_C(0x1)
67007 	#define HWRM_DBG_USEQ_FLUSH_INPUT_BUFFERS	UINT32_C(0x2)
67033 	#define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL	UINT32_C(0x1)
67035 	#define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
67076 	 * * 0x0-0xFFF8 - The function ID
67077 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67078 	 * * 0xFFFD - Reserved for user-space HWRM interface
67079 	 * * 0xFFFF - HWRM
67116 	#define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USID_CTRL_PRESENT UINT32_C(0x1)
67122 	#define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USE_DMA	UINT32_C(0x2)
67127 	#define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_END		UINT32_C(0x8000)
67153 	#define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL	UINT32_C(0x1)
67155 	#define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
67186 	 * * 0x0-0xFFF8 - The function ID
67187 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67188 	 * * 0xFFFD - Reserved for user-space HWRM interface
67189 	 * * 0xFFFF - HWRM
67221 	#define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL	UINT32_C(0x1)
67223 	#define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
67272 	 * * 0x0-0xFFF8 - The function ID
67273 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67274 	 * * 0xFFFD - Reserved for user-space HWRM interface
67275 	 * * 0xFFFF - HWRM
67288 	#define HWRM_DBG_USEQ_SCHED_CFG_INPUT_NO_CHANGE UINT32_C(0x0)
67293 	#define HWRM_DBG_USEQ_SCHED_CFG_INPUT_DISABLE   UINT32_C(0x1)
67298 	#define HWRM_DBG_USEQ_SCHED_CFG_INPUT_ENABLE	UINT32_C(0x2)
67331 	#define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL	UINT32_C(0x1)
67333 …#define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x…
67374 	 * * 0x0-0xFFF8 - The function ID
67375 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67376 	 * * 0xFFFD - Reserved for user-space HWRM interface
67377 	 * * 0xFFFF - HWRM
67392 	#define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_SINGLE   UINT32_C(0x0)
67398 	#define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_CNT	UINT32_C(0x1)
67405 	#define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_FILL_BUF UINT32_C(0x2)
67454 	#define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL	UINT32_C(0x1)
67456 	#define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
67501 	 * * 0x0-0xFFF8 - The function ID
67502 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67503 	 * * 0xFFFD - Reserved for user-space HWRM interface
67504 	 * * 0xFFFF - HWRM
67516 	 * deliver USEQ output details. A value of 0x0 for the address can be
67548 …#define HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL	UINT32_C(0x…
67550 …ine HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
67597 	 * * 0x0-0xFFF8 - The function ID
67598 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67599 	 * * 0xFFFD - Reserved for user-space HWRM interface
67600 	 * * 0xFFFF - HWRM
67613 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT_TRACE	UINT32_C(0x0)
67615 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT2_TRACE	UINT32_C(0x1)
67617 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT_TRACE	UINT32_C(0x2)
67619 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT2_TRACE	UINT32_C(0x3)
67621 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_RIGP0_TRACE	UINT32_C(0x4)
67623 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_L2_HWRM_TRACE   UINT32_C(0x5)
67625 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6)
67626 	/* Context Accelerator CPU 0 trace. */
67627 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CA0_TRACE	UINT32_C(0x7)
67629 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CA1_TRACE	UINT32_C(0x8)
67631 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CA2_TRACE	UINT32_C(0x9)
67633 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_RIGP1_TRACE	UINT32_C(0xa)
67642 	#define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_FLAGS_FLUSH_ALL_BUFFERS	UINT32_C(0x1)
67698 	 * * 0x0-0xFFF8 - The function ID
67699 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67700 	 * * 0xFFFD - Reserved for user-space HWRM interface
67701 	 * * 0xFFFF - HWRM
67715 	 * copying the data to the host from. This should be set to 0 on the
67731 	#define HWRM_DBG_SERDES_TEST_INPUT_FLAGS_UNUSED_TEST_MASK	UINT32_C(0x7)
67732 	#define HWRM_DBG_SERDES_TEST_INPUT_FLAGS_UNUSED_TEST_SFT	0
67734 	#define HWRM_DBG_SERDES_TEST_INPUT_FLAGS_EYE_PROJECTION	UINT32_C(0x8)
67736 	#define HWRM_DBG_SERDES_TEST_INPUT_FLAGS_PCIE_SERDES_TEST	UINT32_C(0x10)
67738 	#define HWRM_DBG_SERDES_TEST_INPUT_FLAGS_ETHERNET_SERDES_TEST	UINT32_C(0x20)
67746 	 * the network port minus 1. Valid values from 0 to 16.
67748 	#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_LANE_NO_MASK	UINT32_C(0xf)
67749 	#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_LANE_NO_SFT	0
67751 	#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_DIRECTION		UINT32_C(0x10)
67752 	/* Value 0 indicates Horizontal plot request. */
67753 		#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_DIRECTION_HORIZONTAL	(UINT32_C(0x0) << 4)
67755 		#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_DIRECTION_VERTICAL	(UINT32_C(0x1) << 4)
67758 	#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_PROJ_TYPE		UINT32_C(0x20)
67760 	 * Value 0 indicates left/top projection in horizontal/vertical
67763 		#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_PROJ_TYPE_LEFT_TOP	(UINT32_C(0x0) << 5)
67769 		#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM  (UINT32_C(0x1) << 5)
67772 	#define HWRM_DBG_SERDES_TEST_INPUT_OPTIONS_RSVD_MASK		UINT32_C(0xc0)
67780 	#define HWRM_DBG_SERDES_TEST_INPUT_TARGETBER_BER_1E8  UINT32_C(0x0)
67782 	#define HWRM_DBG_SERDES_TEST_INPUT_TARGETBER_BER_1E9  UINT32_C(0x1)
67784 	#define HWRM_DBG_SERDES_TEST_INPUT_TARGETBER_BER_1E10 UINT32_C(0x2)
67786 	#define HWRM_DBG_SERDES_TEST_INPUT_TARGETBER_BER_1E11 UINT32_C(0x3)
67788 	#define HWRM_DBG_SERDES_TEST_INPUT_TARGETBER_BER_1E12 UINT32_C(0x4)
67796 	 * Value 0 indicates that collection of the eyescope should be
67800 	#define HWRM_DBG_SERDES_TEST_INPUT_ACTION_SYNCHRONOUS UINT32_C(0x0)
67805 	#define HWRM_DBG_SERDES_TEST_INPUT_ACTION_START	UINT32_C(0x1)
67810 	#define HWRM_DBG_SERDES_TEST_INPUT_ACTION_PROGRESS	UINT32_C(0x2)
67816 	#define HWRM_DBG_SERDES_TEST_INPUT_ACTION_STOP	UINT32_C(0x3)
67844 	 * current eyescope operation in tenths of a percentage. 0 (0.0) to
67855 	#define HWRM_DBG_SERDES_TEST_OUTPUT_FLAGS_BIT_COUNT_TYPE		UINT32_C(0x1)
67857 	 * Value 0 indicates that bit_count value is a raw total
67860 		#define HWRM_DBG_SERDES_TEST_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_TOTAL  UINT32_C(0x0)
67866 		#define HWRM_DBG_SERDES_TEST_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_POW2   UINT32_C(0x1)
67869 	#define HWRM_DBG_SERDES_TEST_OUTPUT_FLAGS_RSVD_MASK			UINT32_C(0xfe)
67912 	 * * 0x0-0xFFF8 - The function ID
67913 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67914 	 * * 0xFFFD - Reserved for user-space HWRM interface
67915 	 * * 0xFFFF - HWRM
67972 	 * * 0x0-0xFFF8 - The function ID
67973 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67974 	 * * 0xFFFD - Reserved for user-space HWRM interface
67975 	 * * 0xFFFF - HWRM
67987 	/* Value 0 indicates to the firmware to insert the cable. */
67988 	#define HWRM_DBG_SIM_CABLE_STATE_INPUT_ACTION_INSERT UINT32_C(0x0)
67990 	#define HWRM_DBG_SIM_CABLE_STATE_INPUT_ACTION_REMOVE UINT32_C(0x1)
68040 	 * * 0x0-0xFFF8 - The function ID
68041 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68042 	 * * 0xFFFD - Reserved for user-space HWRM interface
68043 	 * * 0xFFFF - HWRM
68075 	#define HWRM_DBG_PTRACE_INPUT_FLAGS_SELECT_IN	UINT32_C(0x1)
68080 	#define HWRM_DBG_PTRACE_INPUT_FLAGS_SELECT_OUT	UINT32_C(0x2)
68085 	#define HWRM_DBG_PTRACE_INPUT_FLAGS_GLOBAL_START	UINT32_C(0x4)
68090 	#define HWRM_DBG_PTRACE_INPUT_FLAGS_GLOBAL_STOP	UINT32_C(0x8)
68110 	#define HWRM_DBG_PTRACE_OUTPUT_FLAGS_MORE	UINT32_C(0x1)
68146 	 * * 0x0-0xFFF8 - The function ID
68147 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68148 	 * * 0xFFFD - Reserved for user-space HWRM interface
68149 	 * * 0xFFFF - HWRM
68180 	#define HWRM_NVM_RAW_WRITE_BLK_INPUT_FLAGS_SECURITY_SOC_NVM	UINT32_C(0x1)
68229 	 * * 0x0-0xFFF8 - The function ID
68230 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68231 	 * * 0xFFFD - Reserved for user-space HWRM interface
68232 	 * * 0xFFFF - HWRM
68247 	/* The 0-based index of the directory entry. */
68302 	 * * 0x0-0xFFF8 - The function ID
68303 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68304 	 * * 0xFFFD - Reserved for user-space HWRM interface
68305 	 * * 0xFFFF - HWRM
68332 	#define HWRM_NVM_RAW_DUMP_INPUT_FLAGS_SECURITY_SOC_NVM	UINT32_C(0x1)
68381 	 * * 0x0-0xFFF8 - The function ID
68382 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68383 	 * * 0xFFFD - Reserved for user-space HWRM interface
68384 	 * * 0xFFFF - HWRM
68446 	 * * 0x0-0xFFF8 - The function ID
68447 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68448 	 * * 0xFFFD - Reserved for user-space HWRM interface
68449 	 * * 0xFFFF - HWRM
68510 	 * * 0x0-0xFFF8 - The function ID
68511 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68512 	 * * 0xFFFD - Reserved for user-space HWRM interface
68513 	 * * 0xFFFF - HWRM
68535 	 * The 0-based instance of the combined Directory Entry Type and
68563 	#define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG	UINT32_C(0x1)
68574 	#define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE		UINT32_C(0x2)
68579 	#define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST		UINT32_C(0x4)
68648 	#define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN  UINT32_C(0x0)
68650 	#define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
68652 	#define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
68680 	 * * 0x0-0xFFF8 - The function ID
68681 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68682 	 * * 0xFFFD - Reserved for user-space HWRM interface
68683 	 * * 0xFFFF - HWRM
68711 	#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE	UINT32_C(0x1)
68716 	#define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST	UINT32_C(0x2)
68772 	 * * 0x0-0xFFF8 - The function ID
68773 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68774 	 * * 0xFFFD - Reserved for user-space HWRM interface
68775 	 * * 0xFFFF - HWRM
68790 	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID	UINT32_C(0x1)
68805 	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
68806 	#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
68808 		#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ	UINT32_C(0x0)
68810 		#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE	UINT32_C(0x1)
68812 		#define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT	UINT32_C(0x2)
68876 	 * * 0x0-0xFFF8 - The function ID
68877 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68878 	 * * 0xFFFD - Reserved for user-space HWRM interface
68879 	 * * 0xFFFF - HWRM
68939 	 * * 0x0-0xFFF8 - The function ID
68940 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68941 	 * * 0xFFFD - Reserved for user-space HWRM interface
68942 	 * * 0xFFFF - HWRM
68961 	#define HWRM_NVM_GET_DEV_INFO_INPUT_FLAGS_SECURITY_SOC_NVM	UINT32_C(0x1)
69001 	#define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID	UINT32_C(0x1)
69146 	 * * 0x0-0xFFF8 - The function ID
69147 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
69148 	 * * 0xFFFD - Reserved for user-space HWRM interface
69149 	 * * 0xFFFF - HWRM
69164 	#define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM	UINT32_C(0x1)
69169 	 * The (0-based) instance of this Directory Type.
69234 	 * * 0x0-0xFFF8 - The function ID
69235 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
69236 	 * * 0xFFFD - Reserved for user-space HWRM interface
69237 	 * * 0xFFFF - HWRM
69312 	 * * 0x0-0xFFF8 - The function ID
69313 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
69314 	 * * 0xFFFD - Reserved for user-space HWRM interface
69315 	 * * 0xFFFF - HWRM
69326 	 * Installation type. If the value 3 through 0xffff is used,
69338 	#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
69344 	#define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL	UINT32_C(0xffffffff)
69351 	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE	UINT32_C(0x1)
69358 	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG	UINT32_C(0x2)
69365 	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG	UINT32_C(0x4)
69371 	#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY		UINT32_C(0x8)
69388 	 * Bit-0 corresponding to the first packaged item, Bit-1 for the second
69389 	 * item, etc. A value of 0 indicates that no items were successfully
69396 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS			UINT32_C(0x0)
69398 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE			UINT32_C(0xff)
69400 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE		UINT32_C(0xfd)
69402 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER	UINT32_C(0xfb)
69404 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER	UINT32_C(0xf3)
69406 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE	UINT32_C(0xf2)
69408 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER	UINT32_C(0xec)
69410 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE		UINT32_C(0xeb)
69412 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM	UINT32_C(0xea)
69414 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH	UINT32_C(0xe9)
69416 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST		UINT32_C(0xe8)
69418 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER		UINT32_C(0xe7)
69420 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM		UINT32_C(0xe6)
69422 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM	UINT32_C(0xe5)
69424 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH	UINT32_C(0xe4)
69426 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE		UINT32_C(0xe1)
69428 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV	UINT32_C(0xce)
69430 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID	UINT32_C(0xcd)
69432 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR	UINT32_C(0xcc)
69434 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID	UINT32_C(0xcb)
69436 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM	UINT32_C(0xc5)
69438 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM		UINT32_C(0xc4)
69440 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM		UINT32_C(0xc3)
69442 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR	UINT32_C(0xb9)
69444 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR	UINT32_C(0xb8)
69446 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR UINT32_C(0xb7)
69448 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND		UINT32_C(0xb0)
69450 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED		UINT32_C(0xa7)
69455 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE	UINT32_C(0x0)
69457 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE UINT32_C(0xff)
69465 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE  UINT32_C(0x0)
69471 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI   UINT32_C(0x1)
69479 	#define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER UINT32_C(0x2)
69501 	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN		UINT32_C(0x0)
69503 	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR	UINT32_C(0x1)
69505 	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE	UINT32_C(0x2)
69507 	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK	UINT32_C(0x3)
69509 	#define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT UINT32_C(0x4)
69537 	 * * 0x0-0xFFF8 - The function ID
69538 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
69539 	 * * 0xFFFD - Reserved for user-space HWRM interface
69540 	 * * 0xFFFF - HWRM
69583 	#define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
69585 	#define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL	UINT32_C(0x1)
69613 	 * * 0x0-0xFFF8 - The function ID
69614 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
69615 	 * * 0xFFFD - Reserved for user-space HWRM interface
69616 	 * * 0xFFFF - HWRM
69636 	#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0	UINT32_C(0x0)
69638 	#define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
69643 	 * A value of 0 means that none of the indexN values are valid.
69659 	 * returned, 0 returns the operational value.
69661 	#define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT	UINT32_C(0x1)
69689 	#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0	UINT32_C(0x0)
69691 	#define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
69713 	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN	UINT32_C(0x0)
69715 	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
69717 	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   UINT32_C(0x2)
69719 	#define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
69747 	 * * 0x0-0xFFF8 - The function ID
69748 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
69749 	 * * 0xFFFD - Reserved for user-space HWRM interface
69750 	 * * 0xFFFF - HWRM
69770 	#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0	UINT32_C(0x0)
69772 	#define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
69777 	 * A value of 0 means that none of the indexN values are valid.
69795 	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH		UINT32_C(0x1)
69797 	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK	UINT32_C(0xe)
69800 		#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE		(UINT32_C(0x0) << 1)
69802 		#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1	(UINT32_C(0x1) << 1)
69804 		#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256	(UINT32_C(0x2) << 1)
69806 		#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH  (UINT32_C(0x3) << 1)
69808 	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK	UINT32_C(0x70)
69811 	#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT		UINT32_C(0x80)
69846 	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN	UINT32_C(0x0)
69848 	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
69850 	#define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR   UINT32_C(0x2)
69878 	 * * 0x0-0xFFF8 - The function ID
69879 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
69880 	 * * 0xFFFD - Reserved for user-space HWRM interface
69881 	 * * 0xFFFF - HWRM
69901 	#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0	UINT32_C(0x0)
69903 	#define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
69908 	 * A value of 0 means that none of the indexN values are valid.
69940 	#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
69945 	#define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH	UINT32_C(0x1)
69967 	#define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
69995 	 * * 0x0-0xFFF8 - The function ID
69996 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
69997 	 * * 0xFFFD - Reserved for user-space HWRM interface
69998 	 * * 0xFFFF - HWRM
70016 	#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0)
70023 	#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE  UINT32_C(0x1)
70028 	 * If it is '0', the operation applies to all data. If it is not '0',
70033 	#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_SELECTION_CFG_OPTION	UINT32_C(0x1)
70035 	#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_SELECTION_CRASHDUMP	UINT32_C(0x2)
70052 	#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK	UINT32_C(0x0)
70054 	#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK	UINT32_C(0x1)
70056 	#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY UINT32_C(0x2)
70078 	#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN	UINT32_C(0x0)
70080 	#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG UINT32_C(0x1)
70082 	#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG UINT32_C(0x2)
70110 	 * * 0x0-0xFFF8 - The function ID
70111 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
70112 	 * * 0xFFFD - Reserved for user-space HWRM interface
70113 	 * * 0xFFFF - HWRM
70126 	#define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_STATUS  UINT32_C(0x0)
70128 	#define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_ACQUIRE UINT32_C(0x1)
70130 	#define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_RELEASE UINT32_C(0x2)
70182 	 * * 0x0-0xFFF8 - The function ID
70183 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
70184 	 * * 0xFFFD - Reserved for user-space HWRM interface
70185 	 * * 0xFFFF - HWRM
70197 	#define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG	UINT32_C(0x1)
70232 	#define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
70234 	#define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL	UINT32_C(0x1)
70262 	 * * 0x0-0xFFF8 - The function ID
70263 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
70264 	 * * 0xFFFD - Reserved for user-space HWRM interface
70265 	 * * 0xFFFF - HWRM
70277 	 * a value of [0x00, 0x82] should be used. All other fields
70280 	 * in tag_id[0] and the next letter in tag_id[1].
70335 	 * * 0x0-0xFFF8 - The function ID
70336 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
70337 	 * * 0xFFFD - Reserved for user-space HWRM interface
70338 	 * * 0xFFFF - HWRM
70355 	 * a value of [0x00, 0x82] should be used. All other fields
70358 	 * in tag_id[0] and the next letter in tag_id[1].
70406 	#define CMDQ_INIT_CMDQ_LVL_MASK UINT32_C(0x3)
70407 	#define CMDQ_INIT_CMDQ_LVL_SFT  0
70409 	#define CMDQ_INIT_CMDQ_SIZE_MASK UINT32_C(0xfffc)
70437 	#define CMDQ_BASE_OPCODE_CREATE_QP			UINT32_C(0x1)
70442 	#define CMDQ_BASE_OPCODE_DESTROY_QP			UINT32_C(0x2)
70447 	#define CMDQ_BASE_OPCODE_MODIFY_QP			UINT32_C(0x3)
70449 	#define CMDQ_BASE_OPCODE_QUERY_QP			UINT32_C(0x4)
70451 	#define CMDQ_BASE_OPCODE_CREATE_SRQ			UINT32_C(0x5)
70453 	#define CMDQ_BASE_OPCODE_DESTROY_SRQ			UINT32_C(0x6)
70455 	#define CMDQ_BASE_OPCODE_QUERY_SRQ			UINT32_C(0x8)
70457 	#define CMDQ_BASE_OPCODE_CREATE_CQ			UINT32_C(0x9)
70459 	#define CMDQ_BASE_OPCODE_DESTROY_CQ			UINT32_C(0xa)
70461 	#define CMDQ_BASE_OPCODE_RESIZE_CQ			UINT32_C(0xc)
70466 	#define CMDQ_BASE_OPCODE_ALLOCATE_MRW			UINT32_C(0xd)
70471 	#define CMDQ_BASE_OPCODE_DEALLOCATE_KEY		UINT32_C(0xe)
70473 	#define CMDQ_BASE_OPCODE_REGISTER_MR			UINT32_C(0xf)
70475 	#define CMDQ_BASE_OPCODE_DEREGISTER_MR		UINT32_C(0x10)
70477 	#define CMDQ_BASE_OPCODE_ADD_GID			UINT32_C(0x11)
70479 	#define CMDQ_BASE_OPCODE_DELETE_GID			UINT32_C(0x12)
70481 	#define CMDQ_BASE_OPCODE_MODIFY_GID			UINT32_C(0x17)
70483 	#define CMDQ_BASE_OPCODE_QUERY_GID			UINT32_C(0x18)
70485 	#define CMDQ_BASE_OPCODE_CREATE_QP1			UINT32_C(0x13)
70487 	#define CMDQ_BASE_OPCODE_DESTROY_QP1			UINT32_C(0x14)
70489 	#define CMDQ_BASE_OPCODE_CREATE_AH			UINT32_C(0x15)
70491 	#define CMDQ_BASE_OPCODE_DESTROY_AH			UINT32_C(0x16)
70496 	#define CMDQ_BASE_OPCODE_INITIALIZE_FW		UINT32_C(0x80)
70498 	#define CMDQ_BASE_OPCODE_DEINITIALIZE_FW		UINT32_C(0x81)
70500 	#define CMDQ_BASE_OPCODE_STOP_FUNC			UINT32_C(0x82)
70502 	#define CMDQ_BASE_OPCODE_QUERY_FUNC			UINT32_C(0x83)
70508 	#define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES		UINT32_C(0x84)
70513 	#define CMDQ_BASE_OPCODE_READ_CONTEXT			UINT32_C(0x85)
70518 	#define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST	UINT32_C(0x86)
70523 	#define CMDQ_BASE_OPCODE_READ_VF_MEMORY		UINT32_C(0x87)
70529 	#define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST		UINT32_C(0x88)
70535 	#define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRAY_DEPRECATED UINT32_C(0x89)
70537 	#define CMDQ_BASE_OPCODE_MAP_TC_TO_COS		UINT32_C(0x8a)
70539 	#define CMDQ_BASE_OPCODE_QUERY_VERSION		UINT32_C(0x8b)
70541 	#define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC		UINT32_C(0x8c)
70543 	#define CMDQ_BASE_OPCODE_QUERY_ROCE_CC		UINT32_C(0x8d)
70545 	#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS		UINT32_C(0x8e)
70547 	#define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE		UINT32_C(0x8f)
70549 	#define CMDQ_BASE_OPCODE_MODIFY_CQ			UINT32_C(0x90)
70554 	#define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND		UINT32_C(0x91)
70556 	#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT		UINT32_C(0x92)
70563 	#define CMDQ_BASE_OPCODE_ORCHESTRATE_QID_MIGRATION	UINT32_C(0x93)
70568 	#define CMDQ_BASE_OPCODE_CREATE_QP_BATCH		UINT32_C(0x94)
70574 	#define CMDQ_BASE_OPCODE_DESTROY_QP_BATCH		UINT32_C(0x95)
70583 	#define CMDQ_BASE_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX	UINT32_C(0x96)
70585 	#define CMDQ_BASE_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX   UINT32_C(0x97)
70590 	#define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT_V2	UINT32_C(0x98)
70616 	#define CREQ_BASE_TYPE_MASK	UINT32_C(0x3f)
70617 	#define CREQ_BASE_TYPE_SFT	0
70619 		#define CREQ_BASE_TYPE_QP_EVENT	UINT32_C(0x38)
70621 		#define CREQ_BASE_TYPE_FUNC_EVENT  UINT32_C(0x3a)
70628 	 * will write 1. The odd passes will write 0.
70630 	#define CREQ_BASE_V	UINT32_C(0x1)
70642 	#define CREQ_RESP_SB_HDR_OPCODE_QUERY_QP		UINT32_C(0x4)
70644 	#define CREQ_RESP_SB_HDR_OPCODE_QUERY_SRQ		UINT32_C(0x8)
70646 	#define CREQ_RESP_SB_HDR_OPCODE_QUERY_GID		UINT32_C(0x18)
70648 	#define CREQ_RESP_SB_HDR_OPCODE_QUERY_FUNC		UINT32_C(0x83)
70650 	#define CREQ_RESP_SB_HDR_OPCODE_QUERY_VERSION	UINT32_C(0x8b)
70652 	#define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_CC	UINT32_C(0x8d)
70654 	#define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS	UINT32_C(0x8e)
70656 	#define CREQ_RESP_SB_HDR_OPCODE_QUERY_QP_EXTEND	UINT32_C(0x91)
70658 	#define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT	UINT32_C(0x92)
70660 	#define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
70688 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_SRQ_USED		UINT32_C(0x1)
70690 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_FORCE_COMPLETION	UINT32_C(0x2)
70692 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_RESERVED_LKEY_ENABLE	UINT32_C(0x4)
70694 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_FR_PMR_ENABLED		UINT32_C(0x8)
70696 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED UINT32_C(0x10)
70703 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x20)
70709 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA  UINT32_C(0x40)
70714 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_EXT_STATS_ENABLED	UINT32_C(0x80)
70716 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_EXPRESS_MODE_ENABLED	UINT32_C(0x100)
70718 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_STEERING_TAG_VALID	UINT32_C(0x200)
70724 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED  UINT32_C(0x400)
70729 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_EXT_STATS_CTX_VALID	UINT32_C(0x800)
70731 	#define CREATE_QP_BATCH_DATA_QP_FLAGS_SCHQ_ID_VALID		UINT32_C(0x1000)
70736 	#define CREATE_QP_BATCH_DATA_TYPE_RC		UINT32_C(0x2)
70738 	#define CREATE_QP_BATCH_DATA_TYPE_UD		UINT32_C(0x4)
70740 	#define CREATE_QP_BATCH_DATA_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
70742 	#define CREATE_QP_BATCH_DATA_TYPE_GSI	UINT32_C(0x7)
70749 	#define CREATE_QP_BATCH_DATA_SQ_LVL_MASK	UINT32_C(0xf)
70750 	#define CREATE_QP_BATCH_DATA_SQ_LVL_SFT	0
70752 		#define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_0	UINT32_C(0x0)
70754 		#define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_1	UINT32_C(0x1)
70759 		#define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_2	UINT32_C(0x2)
70765 	#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_MASK  UINT32_C(0xf0)
70768 		#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
70770 		#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
70772 		#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
70774 		#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
70776 		#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
70778 		#define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
70785 	#define CREATE_QP_BATCH_DATA_RQ_LVL_MASK	UINT32_C(0xf)
70786 	#define CREATE_QP_BATCH_DATA_RQ_LVL_SFT	0
70788 		#define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_0	UINT32_C(0x0)
70790 		#define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_1	UINT32_C(0x1)
70795 		#define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_2	UINT32_C(0x2)
70801 	#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_MASK  UINT32_C(0xf0)
70804 		#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
70806 		#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
70808 		#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
70810 		#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
70812 		#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
70814 		#define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
70832 	#define CREATE_QP_BATCH_DATA_SQ_SGE_MASK UINT32_C(0xf)
70833 	#define CREATE_QP_BATCH_DATA_SQ_SGE_SFT 0
70838 	#define CREATE_QP_BATCH_DATA_SQ_FWO_MASK UINT32_C(0xfff0)
70846 	#define CREATE_QP_BATCH_DATA_RQ_SGE_MASK UINT32_C(0xf)
70847 	#define CREATE_QP_BATCH_DATA_RQ_SGE_SFT 0
70852 	#define CREATE_QP_BATCH_DATA_RQ_FWO_MASK UINT32_C(0xfff0)
71031 	#define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION UINT32_C(0x8b)
71057 	#define CREQ_QUERY_VERSION_RESP_TYPE_MASK	UINT32_C(0x3f)
71058 	#define CREQ_QUERY_VERSION_RESP_TYPE_SFT	0
71060 		#define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
71078 	 * will write 1. The odd passes will write 0.
71080 	#define CREQ_QUERY_VERSION_RESP_V	UINT32_C(0x1)
71084 	#define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION UINT32_C(0x8b)
71111 	#define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW UINT32_C(0x80)
71121 	#define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT	UINT32_C(0x1)
71126 	#define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED	UINT32_C(0x2)
71128 	#define CMDQ_INITIALIZE_FW_FLAGS_DRV_VERSION			UINT32_C(0x4)
71130 	#define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED	UINT32_C(0x8)
71135 	#define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT		UINT32_C(0x10)
71145 	#define CMDQ_INITIALIZE_FW_QPC_LVL_MASK	UINT32_C(0xf)
71146 	#define CMDQ_INITIALIZE_FW_QPC_LVL_SFT	0
71148 		#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0	UINT32_C(0x0)
71150 		#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1	UINT32_C(0x1)
71155 		#define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2	UINT32_C(0x2)
71158 	#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK  UINT32_C(0xf0)
71161 		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
71163 		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
71165 		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
71167 		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
71169 		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
71171 		#define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
71175 	#define CMDQ_INITIALIZE_FW_MRW_LVL_MASK	UINT32_C(0xf)
71176 	#define CMDQ_INITIALIZE_FW_MRW_LVL_SFT	0
71178 		#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0	UINT32_C(0x0)
71180 		#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1	UINT32_C(0x1)
71185 		#define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2	UINT32_C(0x2)
71188 	#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK  UINT32_C(0xf0)
71191 		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
71193 		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
71195 		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
71197 		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
71199 		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
71201 		#define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
71205 	#define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK	UINT32_C(0xf)
71206 	#define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT	0
71208 		#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0	UINT32_C(0x0)
71210 		#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1	UINT32_C(0x1)
71215 		#define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2	UINT32_C(0x2)
71218 	#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK  UINT32_C(0xf0)
71221 		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
71223 		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
71225 		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
71227 		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
71229 		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
71231 		#define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
71235 	#define CMDQ_INITIALIZE_FW_CQ_LVL_MASK	UINT32_C(0xf)
71236 	#define CMDQ_INITIALIZE_FW_CQ_LVL_SFT	0
71238 		#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0	UINT32_C(0x0)
71240 		#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1	UINT32_C(0x1)
71245 		#define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2	UINT32_C(0x2)
71248 	#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK  UINT32_C(0xf0)
71251 		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
71253 		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
71255 		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
71257 		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
71259 		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
71261 		#define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
71265 	#define CMDQ_INITIALIZE_FW_TQM_LVL_MASK	UINT32_C(0xf)
71266 	#define CMDQ_INITIALIZE_FW_TQM_LVL_SFT	0
71268 		#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0	UINT32_C(0x0)
71270 		#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1	UINT32_C(0x1)
71275 		#define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2	UINT32_C(0x2)
71278 	#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK  UINT32_C(0xf0)
71281 		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
71283 		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
71285 		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
71287 		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
71289 		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
71291 		#define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
71295 	#define CMDQ_INITIALIZE_FW_TIM_LVL_MASK	UINT32_C(0xf)
71296 	#define CMDQ_INITIALIZE_FW_TIM_LVL_SFT	0
71298 		#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0	UINT32_C(0x0)
71300 		#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1	UINT32_C(0x1)
71305 		#define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2	UINT32_C(0x2)
71308 	#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK  UINT32_C(0xf0)
71311 		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
71313 		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
71315 		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
71317 		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
71319 		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
71321 		#define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
71325 	 * Log base 2 of DBR page size - 12. 0 for 4KB. HW supported values
71328 	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK   UINT32_C(0xf)
71329 	#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT	0
71331 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K	UINT32_C(0x0)
71333 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K	UINT32_C(0x1)
71335 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K   UINT32_C(0x2)
71337 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K   UINT32_C(0x3)
71339 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K   UINT32_C(0x4)
71341 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K  UINT32_C(0x5)
71343 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K  UINT32_C(0x6)
71345 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K  UINT32_C(0x7)
71347 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M	UINT32_C(0x8)
71349 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M	UINT32_C(0x9)
71351 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M	UINT32_C(0xa)
71353 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M	UINT32_C(0xb)
71355 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M   UINT32_C(0xc)
71357 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M   UINT32_C(0xd)
71359 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M   UINT32_C(0xe)
71361 		#define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M  UINT32_C(0xf)
71364 	#define CMDQ_INITIALIZE_FW_RSVD_MASK		UINT32_C(0xfff0)
71412 	 * represents the `max_mr_per_vf` and bits `[15:0]` represents
71467 	#define CREQ_INITIALIZE_FW_RESP_TYPE_MASK	UINT32_C(0x3f)
71468 	#define CREQ_INITIALIZE_FW_RESP_TYPE_SFT	0
71470 		#define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
71481 	 * will write 1. The odd passes will write 0.
71483 	#define CREQ_INITIALIZE_FW_RESP_V	UINT32_C(0x1)
71487 	#define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW UINT32_C(0x80)
71503 	#define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW UINT32_C(0x81)
71529 	#define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK	UINT32_C(0x3f)
71530 	#define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT	0
71532 		#define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
71543 	 * will write 1. The odd passes will write 0.
71545 	#define CREQ_DEINITIALIZE_FW_RESP_V	UINT32_C(0x1)
71549 	#define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW UINT32_C(0x81)
71568 	#define CMDQ_CREATE_QP_OPCODE_CREATE_QP UINT32_C(0x1)
71589 	#define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED		UINT32_C(0x1)
71591 	#define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION	UINT32_C(0x2)
71593 	#define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE	UINT32_C(0x4)
71595 	#define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED		UINT32_C(0x8)
71597 	#define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED UINT32_C(0x10)
71604 	#define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x20)
71610 	#define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA  UINT32_C(0x40)
71615 	#define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED	UINT32_C(0x80)
71617 	#define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED	UINT32_C(0x100)
71619 	#define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID	UINT32_C(0x200)
71625 	#define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED  UINT32_C(0x400)
71630 	#define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_CTX_VALID	UINT32_C(0x800)
71632 	#define CMDQ_CREATE_QP_QP_FLAGS_SCHQ_ID_VALID		UINT32_C(0x1000)
71637 	#define CMDQ_CREATE_QP_TYPE_RC		UINT32_C(0x2)
71639 	#define CMDQ_CREATE_QP_TYPE_UD		UINT32_C(0x4)
71641 	#define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
71643 	#define CMDQ_CREATE_QP_TYPE_GSI	UINT32_C(0x7)
71650 	#define CMDQ_CREATE_QP_SQ_LVL_MASK	UINT32_C(0xf)
71651 	#define CMDQ_CREATE_QP_SQ_LVL_SFT	0
71653 		#define CMDQ_CREATE_QP_SQ_LVL_LVL_0	UINT32_C(0x0)
71655 		#define CMDQ_CREATE_QP_SQ_LVL_LVL_1	UINT32_C(0x1)
71660 		#define CMDQ_CREATE_QP_SQ_LVL_LVL_2	UINT32_C(0x2)
71666 	#define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK  UINT32_C(0xf0)
71669 		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
71671 		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
71673 		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
71675 		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
71677 		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
71679 		#define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
71686 	#define CMDQ_CREATE_QP_RQ_LVL_MASK	UINT32_C(0xf)
71687 	#define CMDQ_CREATE_QP_RQ_LVL_SFT	0
71689 		#define CMDQ_CREATE_QP_RQ_LVL_LVL_0	UINT32_C(0x0)
71691 		#define CMDQ_CREATE_QP_RQ_LVL_LVL_1	UINT32_C(0x1)
71696 		#define CMDQ_CREATE_QP_RQ_LVL_LVL_2	UINT32_C(0x2)
71702 	#define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK  UINT32_C(0xf0)
71705 		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
71707 		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
71709 		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
71711 		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
71713 		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
71715 		#define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
71733 	#define CMDQ_CREATE_QP_SQ_SGE_MASK UINT32_C(0xf)
71734 	#define CMDQ_CREATE_QP_SQ_SGE_SFT 0
71739 	#define CMDQ_CREATE_QP_SQ_FWO_MASK UINT32_C(0xfff0)
71747 	#define CMDQ_CREATE_QP_RQ_SGE_MASK UINT32_C(0xf)
71748 	#define CMDQ_CREATE_QP_RQ_SGE_SFT 0
71753 	#define CMDQ_CREATE_QP_RQ_FWO_MASK UINT32_C(0xfff0)
71833 	#define CREQ_CREATE_QP_RESP_TYPE_MASK	UINT32_C(0x3f)
71834 	#define CREQ_CREATE_QP_RESP_TYPE_SFT	0
71836 		#define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
71848 	 * will write 1. The odd passes will write 0.
71850 	#define CREQ_CREATE_QP_RESP_V	UINT32_C(0x1)
71854 	#define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP UINT32_C(0x1)
71878 	#define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP UINT32_C(0x2)
71907 	#define CREQ_DESTROY_QP_RESP_TYPE_MASK	UINT32_C(0x3f)
71908 	#define CREQ_DESTROY_QP_RESP_TYPE_SFT	0
71910 		#define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
71922 	 * will write 1. The odd passes will write 0.
71924 	#define CREQ_DESTROY_QP_RESP_V	UINT32_C(0x1)
71928 	#define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP UINT32_C(0x2)
71947 	#define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP UINT32_C(0x3)
71959 	#define CMDQ_MODIFY_QP_FLAGS_SRQ_USED		UINT32_C(0x1)
71964 	#define CMDQ_MODIFY_QP_FLAGS_EXCLUDE_QP_UDCC	UINT32_C(0x2)
71976 	#define CMDQ_MODIFY_QP_QP_TYPE_RC		UINT32_C(0x2)
71978 	#define CMDQ_MODIFY_QP_QP_TYPE_UD		UINT32_C(0x4)
71980 	#define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
71982 	#define CMDQ_MODIFY_QP_QP_TYPE_GSI	UINT32_C(0x7)
71989 	#define CMDQ_MODIFY_QP_MODIFY_MASK_STATE		UINT32_C(0x1)
71991 	#define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY	UINT32_C(0x2)
71993 	#define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS		UINT32_C(0x4)
71995 	#define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY			UINT32_C(0x8)
71997 	#define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY			UINT32_C(0x10)
71999 	#define CMDQ_MODIFY_QP_MODIFY_MASK_DGID			UINT32_C(0x20)
72001 	#define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL		UINT32_C(0x40)
72003 	#define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX		UINT32_C(0x80)
72005 	#define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT		UINT32_C(0x100)
72007 	#define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS	UINT32_C(0x200)
72009 	#define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC		UINT32_C(0x400)
72011 	#define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE	UINT32_C(0x800)
72013 	#define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU		UINT32_C(0x1000)
72015 	#define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT		UINT32_C(0x2000)
72017 	#define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT		UINT32_C(0x4000)
72019 	#define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY		UINT32_C(0x8000)
72021 	#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN		UINT32_C(0x10000)
72023 	#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC	UINT32_C(0x20000)
72025 	#define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER	UINT32_C(0x40000)
72027 	#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN		UINT32_C(0x80000)
72029 	#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC	UINT32_C(0x100000)
72031 	#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE		UINT32_C(0x200000)
72033 	#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE		UINT32_C(0x400000)
72035 	#define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE		UINT32_C(0x800000)
72037 	#define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE		UINT32_C(0x1000000)
72039 	#define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA	UINT32_C(0x2000000)
72041 	#define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID		UINT32_C(0x4000000)
72043 	#define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC		UINT32_C(0x8000000)
72045 	#define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID		UINT32_C(0x10000000)
72047 	#define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC		UINT32_C(0x20000000)
72049 	#define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN		UINT32_C(0x40000000)
72051 	#define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP		UINT32_C(0x80000000)
72056 	#define CMDQ_MODIFY_QP_NEW_STATE_MASK	UINT32_C(0xf)
72057 	#define CMDQ_MODIFY_QP_NEW_STATE_SFT	0
72059 		#define CMDQ_MODIFY_QP_NEW_STATE_RESET	UINT32_C(0x0)
72061 		#define CMDQ_MODIFY_QP_NEW_STATE_INIT		UINT32_C(0x1)
72063 		#define CMDQ_MODIFY_QP_NEW_STATE_RTR		UINT32_C(0x2)
72065 		#define CMDQ_MODIFY_QP_NEW_STATE_RTS		UINT32_C(0x3)
72067 		#define CMDQ_MODIFY_QP_NEW_STATE_SQD		UINT32_C(0x4)
72069 		#define CMDQ_MODIFY_QP_NEW_STATE_SQE		UINT32_C(0x5)
72071 		#define CMDQ_MODIFY_QP_NEW_STATE_ERR		UINT32_C(0x6)
72074 	#define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY	UINT32_C(0x10)
72076 	#define CMDQ_MODIFY_QP_UNUSED1		UINT32_C(0x20)
72078 	#define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK	UINT32_C(0xc0)
72081 		#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1	(UINT32_C(0x0) << 6)
72083 		#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4  (UINT32_C(0x2) << 6)
72085 		#define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6  (UINT32_C(0x3) << 6)
72089 …#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK		UINT32_C(0x…
72090 	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT		0
72092 	#define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE							UINT32_C(0x1)
72094 	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE							UINT32_C(0x2)
72096 	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ							UINT32_C(0x4)
72101 	#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC							UINT32_C(0x8)
72120 	#define CMDQ_MODIFY_QP_TOS_ECN_MASK UINT32_C(0x3)
72121 	#define CMDQ_MODIFY_QP_TOS_ECN_SFT  0
72123 	#define CMDQ_MODIFY_QP_TOS_DSCP_MASK UINT32_C(0xfc)
72131 	#define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE	UINT32_C(0x1)
72133 	#define CMDQ_MODIFY_QP_UNUSED3_MASK		UINT32_C(0xe)
72136 	#define CMDQ_MODIFY_QP_PATH_MTU_MASK		UINT32_C(0xf0)
72139 		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_256	(UINT32_C(0x0) << 4)
72141 		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_512	(UINT32_C(0x1) << 4)
72143 		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024	(UINT32_C(0x2) << 4)
72145 		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048	(UINT32_C(0x3) << 4)
72147 		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096	(UINT32_C(0x4) << 4)
72149 		#define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192	(UINT32_C(0x5) << 4)
72169 	#define CMDQ_MODIFY_QP_ENABLE_CC	UINT32_C(0x1)
72171 	#define CMDQ_MODIFY_QP_UNUSED15_MASK UINT32_C(0xfffe)
72191 	#define CMDQ_MODIFY_QP_VLAN_ID_MASK UINT32_C(0xfff)
72192 	#define CMDQ_MODIFY_QP_VLAN_ID_SFT  0
72194 	#define CMDQ_MODIFY_QP_VLAN_DEI	UINT32_C(0x1000)
72196 	#define CMDQ_MODIFY_QP_VLAN_PCP_MASK UINT32_C(0xe000)
72208 	#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX	UINT32_C(0x1)
72210 	#define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID	UINT32_C(0x2)
72238 	#define CREQ_MODIFY_QP_RESP_TYPE_MASK	UINT32_C(0x3f)
72239 	#define CREQ_MODIFY_QP_RESP_TYPE_SFT	0
72241 		#define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
72253 	 * will write 1. The odd passes will write 0.
72255 	#define CREQ_MODIFY_QP_RESP_V	UINT32_C(0x1)
72259 	#define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP UINT32_C(0x3)
72266 	#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED	UINT32_C(0x1)
72271 	#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK  UINT32_C(0xe)
72275 	 * for first push operation. 0 - ping buffer, 1 - pong buffer.
72277 	#define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE	UINT32_C(0x10)
72294 	#define CMDQ_QUERY_QP_OPCODE_QUERY_QP UINT32_C(0x4)
72323 	#define CREQ_QUERY_QP_RESP_TYPE_MASK	UINT32_C(0x3f)
72324 	#define CREQ_QUERY_QP_RESP_TYPE_SFT	0
72326 		#define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
72338 	 * will write 1. The odd passes will write 0.
72340 	#define CREQ_QUERY_QP_RESP_V	UINT32_C(0x1)
72344 	#define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP UINT32_C(0x4)
72356 	#define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP UINT32_C(0x4)
72371 	#define CREQ_QUERY_QP_RESP_SB_STATE_MASK		UINT32_C(0xf)
72372 	#define CREQ_QUERY_QP_RESP_SB_STATE_SFT		0
72374 		#define CREQ_QUERY_QP_RESP_SB_STATE_RESET		UINT32_C(0x0)
72376 		#define CREQ_QUERY_QP_RESP_SB_STATE_INIT		UINT32_C(0x1)
72378 		#define CREQ_QUERY_QP_RESP_SB_STATE_RTR		UINT32_C(0x2)
72380 		#define CREQ_QUERY_QP_RESP_SB_STATE_RTS		UINT32_C(0x3)
72382 		#define CREQ_QUERY_QP_RESP_SB_STATE_SQD		UINT32_C(0x4)
72384 		#define CREQ_QUERY_QP_RESP_SB_STATE_SQE		UINT32_C(0x5)
72386 		#define CREQ_QUERY_QP_RESP_SB_STATE_ERR		UINT32_C(0x6)
72389 	#define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY	UINT32_C(0x10)
72391 	#define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK		UINT32_C(0xe0)
72395 …REQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK		UINT32_C(0xff)
72396 	#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT		0
72398 	#define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE							UINT32_C(0x1)
72400 	#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE							UINT32_C(0x2)
72402 	#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ							UINT32_C(0x4)
72404 	#define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC							UINT32_C(0x8)
72429 	#define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK UINT32_C(0xfff)
72430 	#define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0
72432 	#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK	UINT32_C(0xf000)
72435 		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256   (UINT32_C(0x0) << 12)
72437 		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512   (UINT32_C(0x1) << 12)
72439 		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024  (UINT32_C(0x2) << 12)
72441 		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048  (UINT32_C(0x3) << 12)
72443 		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096  (UINT32_C(0x4) << 12)
72445 		#define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192  (UINT32_C(0x5) << 12)
72465 	#define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK UINT32_C(0x3)
72466 	#define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT  0
72468 	#define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc)
72472 	#define CREQ_QUERY_QP_RESP_SB_ENABLE_CC	UINT32_C(0x1)
72494 	#define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK UINT32_C(0xfff)
72495 	#define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT  0
72497 	#define CREQ_QUERY_QP_RESP_SB_VLAN_DEI	UINT32_C(0x1000)
72499 	#define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK UINT32_C(0xe000)
72517 	#define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
72537 	#define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK  UINT32_C(0xff)
72538 	#define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT   0
72540 	#define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK  UINT32_C(0xffff00)
72543 	#define CMDQ_QUERY_QP_EXTEND_VF_VALID	UINT32_C(0x1000000)
72562 	#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK	UINT32_C(0x3f)
72563 	#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT	0
72565 		#define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
72577 	 * will write 1. The odd passes will write 0.
72579 	#define CREQ_QUERY_QP_EXTEND_RESP_V	UINT32_C(0x1)
72583 	#define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND UINT32_C(0x91)
72600 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
72615 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK  UINT32_C(0xf)
72616 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT   0
72618 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET   UINT32_C(0x0)
72620 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT	UINT32_C(0x1)
72622 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR	UINT32_C(0x2)
72624 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS	UINT32_C(0x3)
72626 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD	UINT32_C(0x4)
72628 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE	UINT32_C(0x5)
72630 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR	UINT32_C(0x6)
72633 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK UINT32_C(0xf0)
72645 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1	UINT32_C(0x0)
72647 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 UINT32_C(0x2)
72649 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 UINT32_C(0x3)
72674 	 * For TLV encapsulated messages this field must be 0x8000.
72683 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE	UINT32_C(0x1)
72685 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST	UINT32_C(0x0)
72687 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST  UINT32_C(0x1)
72694 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED	UINT32_C(0x2)
72696 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO	(UINT32_C(0x0) << 1)
72698 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES   (UINT32_C(0x1) << 1)
72709 	 * Global TLV range: `0 - (63k-1)`
72729 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
72744 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK  UINT32_C(0xf)
72745 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT   0
72747 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET   UINT32_C(0x0)
72749 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT	UINT32_C(0x1)
72751 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR	UINT32_C(0x2)
72753 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS	UINT32_C(0x3)
72755 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD	UINT32_C(0x4)
72757 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE	UINT32_C(0x5)
72759 		#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR	UINT32_C(0x6)
72762 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK UINT32_C(0xf0)
72774 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1	UINT32_C(0x0)
72776 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 UINT32_C(0x2)
72778 	#define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 UINT32_C(0x3)
72802 	#define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ UINT32_C(0x5)
72809 	#define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID	UINT32_C(0x1)
72821 	#define CMDQ_CREATE_SRQ_LVL_MASK	UINT32_C(0x3)
72822 	#define CMDQ_CREATE_SRQ_LVL_SFT	0
72824 		#define CMDQ_CREATE_SRQ_LVL_LVL_0	UINT32_C(0x0)
72826 		#define CMDQ_CREATE_SRQ_LVL_LVL_1	UINT32_C(0x1)
72831 		#define CMDQ_CREATE_SRQ_LVL_LVL_2	UINT32_C(0x2)
72834 	#define CMDQ_CREATE_SRQ_PG_SIZE_MASK  UINT32_C(0x1c)
72837 		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 2)
72839 		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 2)
72841 		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 2)
72843 		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 2)
72845 		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 2)
72847 		#define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 2)
72850 	#define CMDQ_CREATE_SRQ_UNUSED11_MASK UINT32_C(0xffe0)
72854 	#define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK UINT32_C(0xfff)
72855 	#define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0
72857 	#define CMDQ_CREATE_SRQ_UNUSED4_MASK  UINT32_C(0xf000)
72863 	#define CMDQ_CREATE_SRQ_SRQ_FWO_MASK UINT32_C(0xfff)
72864 	#define CMDQ_CREATE_SRQ_SRQ_FWO_SFT 0
72869 	#define CMDQ_CREATE_SRQ_SRQ_SGE_MASK UINT32_C(0xf000)
72895 	#define CREQ_CREATE_SRQ_RESP_TYPE_MASK	UINT32_C(0x3f)
72896 	#define CREQ_CREATE_SRQ_RESP_TYPE_SFT	0
72898 		#define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
72910 	 * will write 1. The odd passes will write 0.
72912 	#define CREQ_CREATE_SRQ_RESP_V	UINT32_C(0x1)
72916 	#define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ UINT32_C(0x5)
72932 	#define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ UINT32_C(0x6)
72961 	#define CREQ_DESTROY_SRQ_RESP_TYPE_MASK	UINT32_C(0x3f)
72962 	#define CREQ_DESTROY_SRQ_RESP_TYPE_SFT	0
72964 		#define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
72976 	 * will write 1. The odd passes will write 0.
72978 	#define CREQ_DESTROY_SRQ_RESP_V	UINT32_C(0x1)
72982 	#define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ UINT32_C(0x6)
72985 	#define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK	UINT32_C(0xffff)
72986 	#define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT	0
72991 	#define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK UINT32_C(0x30000)
73006 	#define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ UINT32_C(0x8)
73035 	#define CREQ_QUERY_SRQ_RESP_TYPE_MASK	UINT32_C(0x3f)
73036 	#define CREQ_QUERY_SRQ_RESP_TYPE_SFT	0
73038 		#define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
73050 	 * will write 1. The odd passes will write 0.
73052 	#define CREQ_QUERY_SRQ_RESP_V	UINT32_C(0x1)
73056 	#define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ UINT32_C(0x8)
73068 	#define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ UINT32_C(0x8)
73099 	#define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ UINT32_C(0x9)
73115 	#define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION	UINT32_C(0x1)
73117 	#define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID		UINT32_C(0x2)
73129 	#define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE		UINT32_C(0x4)
73134 	#define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID		UINT32_C(0x8)
73146 	#define CMDQ_CREATE_CQ_LVL_MASK	UINT32_C(0x3)
73147 	#define CMDQ_CREATE_CQ_LVL_SFT	0
73149 		#define CMDQ_CREATE_CQ_LVL_LVL_0	UINT32_C(0x0)
73151 		#define CMDQ_CREATE_CQ_LVL_LVL_1	UINT32_C(0x1)
73156 		#define CMDQ_CREATE_CQ_LVL_LVL_2	UINT32_C(0x2)
73159 	#define CMDQ_CREATE_CQ_PG_SIZE_MASK  UINT32_C(0x1c)
73162 		#define CMDQ_CREATE_CQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 2)
73164 		#define CMDQ_CREATE_CQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 2)
73166 		#define CMDQ_CREATE_CQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 2)
73168 		#define CMDQ_CREATE_CQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 2)
73170 		#define CMDQ_CREATE_CQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 2)
73172 		#define CMDQ_CREATE_CQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 2)
73175 	#define CMDQ_CREATE_CQ_UNUSED27_MASK UINT32_C(0xffffffe0)
73179 	#define CMDQ_CREATE_CQ_CNQ_ID_MASK UINT32_C(0xfff)
73180 	#define CMDQ_CREATE_CQ_CNQ_ID_SFT 0
73182 	#define CMDQ_CREATE_CQ_CQ_FCO_MASK UINT32_C(0xfffff000)
73200 	#define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK	UINT32_C(0x1ff)
73201 	#define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT	0
73207 	#define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK	UINT32_C(0x3e00)
73214 	#define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK	UINT32_C(0x7c000)
73223 	#define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE	UINT32_C(0x80000)
73225 	#define CMDQ_CREATE_CQ_UNUSED12_MASK		UINT32_C(0xfff00000)
73242 	#define CREQ_CREATE_CQ_RESP_TYPE_MASK	UINT32_C(0x3f)
73243 	#define CREQ_CREATE_CQ_RESP_TYPE_SFT	0
73245 		#define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
73257 	 * will write 1. The odd passes will write 0.
73259 	#define CREQ_CREATE_CQ_RESP_V	UINT32_C(0x1)
73263 	#define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ UINT32_C(0x9)
73279 	#define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ UINT32_C(0xa)
73308 	#define CREQ_DESTROY_CQ_RESP_TYPE_MASK	UINT32_C(0x3f)
73309 	#define CREQ_DESTROY_CQ_RESP_TYPE_SFT	0
73311 		#define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
73323 	 * will write 1. The odd passes will write 0.
73325 	#define CREQ_DESTROY_CQ_RESP_V	UINT32_C(0x1)
73329 	#define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ UINT32_C(0xa)
73334 	 * 0 ? Not Armed
73338 	#define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK UINT32_C(0x3)
73339 	#define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0
73360 	#define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ UINT32_C(0xc)
73377 	#define CMDQ_RESIZE_CQ_LVL_MASK	UINT32_C(0x3)
73378 	#define CMDQ_RESIZE_CQ_LVL_SFT	0
73380 		#define CMDQ_RESIZE_CQ_LVL_LVL_0	UINT32_C(0x0)
73382 		#define CMDQ_RESIZE_CQ_LVL_LVL_1	UINT32_C(0x1)
73387 		#define CMDQ_RESIZE_CQ_LVL_LVL_2	UINT32_C(0x2)
73390 	#define CMDQ_RESIZE_CQ_PG_SIZE_MASK	UINT32_C(0x1c)
73393 		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K	(UINT32_C(0x0) << 2)
73395 		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K	(UINT32_C(0x1) << 2)
73397 		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K	(UINT32_C(0x2) << 2)
73399 		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M	(UINT32_C(0x3) << 2)
73401 		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M	(UINT32_C(0x4) << 2)
73403 		#define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G	(UINT32_C(0x5) << 2)
73406 	#define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK UINT32_C(0x1fffffe0)
73426 	#define CREQ_RESIZE_CQ_RESP_TYPE_MASK	UINT32_C(0x3f)
73427 	#define CREQ_RESIZE_CQ_RESP_TYPE_SFT	0
73429 		#define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
73441 	 * will write 1. The odd passes will write 0.
73443 	#define CREQ_RESIZE_CQ_RESP_V	UINT32_C(0x1)
73447 	#define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ UINT32_C(0xc)
73463 	#define CMDQ_MODIFY_CQ_OPCODE_MODIFY_CQ UINT32_C(0x90)
73479 	#define CMDQ_MODIFY_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION	UINT32_C(0x1)
73490 	#define CMDQ_MODIFY_CQ_MODIFY_MASK_CQ_HANDLE	UINT32_C(0x1)
73492 	#define CMDQ_MODIFY_CQ_MODIFY_MASK_CNQ_ID	UINT32_C(0x2)
73494 	#define CMDQ_MODIFY_CQ_MODIFY_MASK_FCO	UINT32_C(0x4)
73496 	#define CMDQ_MODIFY_CQ_MODIFY_MASK_DPI	UINT32_C(0x8)
73498 	#define CMDQ_MODIFY_CQ_MODIFY_MASK_CQ_SIZE	UINT32_C(0x10)
73500 	#define CMDQ_MODIFY_CQ_MODIFY_MASK_PBL	UINT32_C(0x20)
73507 	#define CMDQ_MODIFY_CQ_CNQ_ID_MASK UINT32_C(0xfff)
73508 	#define CMDQ_MODIFY_CQ_CNQ_ID_SFT 0
73510 	#define CMDQ_MODIFY_CQ_CQ_FCO_MASK UINT32_C(0xfffff000)
73535 	#define CREQ_MODIFY_CQ_RESP_TYPE_MASK	UINT32_C(0x3f)
73536 	#define CREQ_MODIFY_CQ_RESP_TYPE_SFT	0
73538 		#define CREQ_MODIFY_CQ_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
73550 	 * will write 1. The odd passes will write 0.
73552 	#define CREQ_MODIFY_CQ_RESP_V	UINT32_C(0x1)
73556 	#define CREQ_MODIFY_CQ_RESP_EVENT_MODIFY_CQ UINT32_C(0x9)
73575 	#define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW UINT32_C(0xd)
73592 	#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK	UINT32_C(0xf)
73593 	#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT	0
73595 		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR		UINT32_C(0x0)
73597 		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR		UINT32_C(0x1)
73599 		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1	UINT32_C(0x2)
73601 		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A	UINT32_C(0x3)
73603 		#define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B	UINT32_C(0x4)
73609 	#define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID	UINT32_C(0x10)
73611 	#define CMDQ_ALLOCATE_MRW_UNUSED3_MASK	UINT32_C(0xe0)
73616 	#define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY	UINT32_C(0x20)
73634 	#define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK	UINT32_C(0x3f)
73635 	#define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT	0
73637 		#define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
73649 	 * will write 1. The odd passes will write 0.
73651 	#define CREQ_ALLOCATE_MRW_RESP_V	UINT32_C(0x1)
73655 	#define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW UINT32_C(0xd)
73674 	#define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY UINT32_C(0xe)
73689 	#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK	UINT32_C(0xf)
73690 	#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT	0
73692 		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR	UINT32_C(0x0)
73694 		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR	UINT32_C(0x1)
73696 		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1   UINT32_C(0x2)
73698 		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A  UINT32_C(0x3)
73700 		#define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B  UINT32_C(0x4)
73703 	#define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK	UINT32_C(0xf0)
73722 	#define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK	UINT32_C(0x3f)
73723 	#define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT	0
73725 		#define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
73737 	 * will write 1. The odd passes will write 0.
73739 	#define CREQ_DEALLOCATE_KEY_RESP_V	UINT32_C(0x1)
73743 	#define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY UINT32_C(0xe)
73772 	#define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR UINT32_C(0xf)
73784 	#define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR		UINT32_C(0x1)
73790 	#define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID	UINT32_C(0x2)
73792 	#define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO		UINT32_C(0x4)
73802 	#define CMDQ_REGISTER_MR_LVL_MASK		UINT32_C(0x3)
73803 	#define CMDQ_REGISTER_MR_LVL_SFT		0
73805 		#define CMDQ_REGISTER_MR_LVL_LVL_0		UINT32_C(0x0)
73807 		#define CMDQ_REGISTER_MR_LVL_LVL_1		UINT32_C(0x1)
73812 		#define CMDQ_REGISTER_MR_LVL_LVL_2		UINT32_C(0x2)
73818 	#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK   UINT32_C(0x7c)
73821 		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K	(UINT32_C(0xc) << 2)
73823 		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K	(UINT32_C(0xd) << 2)
73825 		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K   (UINT32_C(0x10) << 2)
73827 		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K  (UINT32_C(0x12) << 2)
73829 		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M	(UINT32_C(0x14) << 2)
73831 		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M	(UINT32_C(0x15) << 2)
73833 		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M	(UINT32_C(0x16) << 2)
73835 		#define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G	(UINT32_C(0x1e) << 2)
73838 	#define CMDQ_REGISTER_MR_UNUSED1		UINT32_C(0x80)
73842 	#define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE	UINT32_C(0x1)
73844 	#define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ	UINT32_C(0x2)
73846 	#define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE	UINT32_C(0x4)
73848 	#define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC	UINT32_C(0x8)
73850 	#define CMDQ_REGISTER_MR_ACCESS_MW_BIND	UINT32_C(0x10)
73852 	#define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED	UINT32_C(0x20)
73858 	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK   UINT32_C(0x1f)
73859 	#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT	0
73861 		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K	UINT32_C(0xc)
73863 		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K	UINT32_C(0xd)
73865 		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K   UINT32_C(0x10)
73867 		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K  UINT32_C(0x12)
73869 		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M	UINT32_C(0x14)
73871 		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M	UINT32_C(0x15)
73873 		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M	UINT32_C(0x16)
73875 		#define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G	UINT32_C(0x1e)
73878 	#define CMDQ_REGISTER_MR_UNUSED11_MASK	UINT32_C(0xffe0)
73911 	#define CREQ_REGISTER_MR_RESP_TYPE_MASK	UINT32_C(0x3f)
73912 	#define CREQ_REGISTER_MR_RESP_TYPE_SFT	0
73914 		#define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
73926 	 * will write 1. The odd passes will write 0.
73928 	#define CREQ_REGISTER_MR_RESP_V	UINT32_C(0x1)
73932 	#define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR UINT32_C(0xf)
73948 	#define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR UINT32_C(0x10)
73977 	#define CREQ_DEREGISTER_MR_RESP_TYPE_MASK	UINT32_C(0x3f)
73978 	#define CREQ_DEREGISTER_MR_RESP_TYPE_SFT	0
73980 		#define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
73992 	 * will write 1. The odd passes will write 0.
73994 	#define CREQ_DEREGISTER_MR_RESP_V	UINT32_C(0x1)
73998 	#define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR UINT32_C(0x10)
74022 	#define CMDQ_ADD_GID_OPCODE_ADD_GID UINT32_C(0x11)
74041 	#define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK	UINT32_C(0xffff)
74042 	#define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT	0
74044 	#define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK			UINT32_C(0xfff)
74045 	#define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT			0
74047 	#define CMDQ_ADD_GID_VLAN_TPID_MASK			UINT32_C(0x7000)
74049 	/* TPID = 0x88A8. */
74050 		#define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8			(UINT32_C(0x0) << 12)
74051 	/* TPID = 0x8100. */
74052 		#define CMDQ_ADD_GID_VLAN_TPID_TPID_8100			(UINT32_C(0x1) << 12)
74053 	/* TPID = 0x9100. */
74054 		#define CMDQ_ADD_GID_VLAN_TPID_TPID_9100			(UINT32_C(0x2) << 12)
74055 	/* TPID = 0x9200. */
74056 		#define CMDQ_ADD_GID_VLAN_TPID_TPID_9200			(UINT32_C(0x3) << 12)
74057 	/* TPID = 0x9300. */
74058 		#define CMDQ_ADD_GID_VLAN_TPID_TPID_9300			(UINT32_C(0x4) << 12)
74060 		#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1			(UINT32_C(0x5) << 12)
74062 		#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2			(UINT32_C(0x6) << 12)
74064 		#define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3			(UINT32_C(0x7) << 12)
74070 	#define CMDQ_ADD_GID_VLAN_VLAN_EN				UINT32_C(0x8000)
74075 	#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK		UINT32_C(0xffff)
74076 	#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT		0
74078 	#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK				UINT32_C(0x7fff)
74079 	#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT				0
74084 	#define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID				UINT32_C(0x8000)
74099 	#define CREQ_ADD_GID_RESP_TYPE_MASK	UINT32_C(0x3f)
74100 	#define CREQ_ADD_GID_RESP_TYPE_SFT	0
74102 		#define CREQ_ADD_GID_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
74114 	 * will write 1. The odd passes will write 0.
74116 	#define CREQ_ADD_GID_RESP_V	UINT32_C(0x1)
74120 	#define CREQ_ADD_GID_RESP_EVENT_ADD_GID UINT32_C(0x11)
74136 	#define CMDQ_DELETE_GID_OPCODE_DELETE_GID UINT32_C(0x12)
74165 	#define CREQ_DELETE_GID_RESP_TYPE_MASK	UINT32_C(0x3f)
74166 	#define CREQ_DELETE_GID_RESP_TYPE_SFT	0
74168 		#define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
74180 	 * will write 1. The odd passes will write 0.
74182 	#define CREQ_DELETE_GID_RESP_V	UINT32_C(0x1)
74186 	#define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID UINT32_C(0x12)
74202 	#define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID UINT32_C(0x17)
74222 	#define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK  UINT32_C(0xfff)
74223 	#define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT   0
74225 	#define CMDQ_MODIFY_GID_VLAN_TPID_MASK	UINT32_C(0x7000)
74227 	/* TPID = 0x88A8. */
74228 		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8  (UINT32_C(0x0) << 12)
74229 	/* TPID = 0x8100. */
74230 		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100  (UINT32_C(0x1) << 12)
74231 	/* TPID = 0x9100. */
74232 		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100  (UINT32_C(0x2) << 12)
74233 	/* TPID = 0x9200. */
74234 		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200  (UINT32_C(0x3) << 12)
74235 	/* TPID = 0x9300. */
74236 		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300  (UINT32_C(0x4) << 12)
74238 		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1  (UINT32_C(0x5) << 12)
74240 		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2  (UINT32_C(0x6) << 12)
74242 		#define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3  (UINT32_C(0x7) << 12)
74248 	#define CMDQ_MODIFY_GID_VLAN_VLAN_EN	UINT32_C(0x8000)
74256 	#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK   UINT32_C(0x7fff)
74257 	#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT	0
74262 	#define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID	UINT32_C(0x8000)
74277 	#define CREQ_MODIFY_GID_RESP_TYPE_MASK	UINT32_C(0x3f)
74278 	#define CREQ_MODIFY_GID_RESP_TYPE_SFT	0
74280 		#define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
74292 	 * will write 1. The odd passes will write 0.
74294 	#define CREQ_MODIFY_GID_RESP_V	UINT32_C(0x1)
74298 	#define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID UINT32_C(0x11)
74314 	#define CMDQ_QUERY_GID_OPCODE_QUERY_GID UINT32_C(0x18)
74344 	#define CREQ_QUERY_GID_RESP_TYPE_MASK	UINT32_C(0x3f)
74345 	#define CREQ_QUERY_GID_RESP_TYPE_SFT	0
74347 		#define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
74359 	 * will write 1. The odd passes will write 0.
74361 	#define CREQ_QUERY_GID_RESP_V	UINT32_C(0x1)
74365 	#define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID UINT32_C(0x18)
74377 	#define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID UINT32_C(0x18)
74394 	#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK	UINT32_C(0xffff)
74395 	#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT	0
74397 	#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK			UINT32_C(0xfff)
74398 	#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT			0
74400 	#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK			UINT32_C(0x7000)
74402 	/* TPID = 0x88A8. */
74403 		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8			(UINT32_C(0x0) << 12)
74404 	/* TPID = 0x8100. */
74405 		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100			(UINT32_C(0x1) << 12)
74406 	/* TPID = 0x9100. */
74407 		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100			(UINT32_C(0x2) << 12)
74408 	/* TPID = 0x9200. */
74409 		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200			(UINT32_C(0x3) << 12)
74410 	/* TPID = 0x9300. */
74411 		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300			(UINT32_C(0x4) << 12)
74413 		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1			(UINT32_C(0x5) << 12)
74415 		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2			(UINT32_C(0x6) << 12)
74417 		#define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3			(UINT32_C(0x7) << 12)
74423 	#define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN				UINT32_C(0x8000)
74442 	#define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 UINT32_C(0x13)
74460 	#define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED		UINT32_C(0x1)
74462 	#define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION	UINT32_C(0x2)
74464 	#define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
74469 	#define CMDQ_CREATE_QP1_TYPE_GSI UINT32_C(0x1)
74473 	#define CMDQ_CREATE_QP1_SQ_LVL_MASK	UINT32_C(0xf)
74474 	#define CMDQ_CREATE_QP1_SQ_LVL_SFT	0
74476 		#define CMDQ_CREATE_QP1_SQ_LVL_LVL_0	UINT32_C(0x0)
74478 		#define CMDQ_CREATE_QP1_SQ_LVL_LVL_1	UINT32_C(0x1)
74483 		#define CMDQ_CREATE_QP1_SQ_LVL_LVL_2	UINT32_C(0x2)
74486 	#define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK  UINT32_C(0xf0)
74489 		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
74491 		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
74493 		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
74495 		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
74497 		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
74499 		#define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
74503 	#define CMDQ_CREATE_QP1_RQ_LVL_MASK	UINT32_C(0xf)
74504 	#define CMDQ_CREATE_QP1_RQ_LVL_SFT	0
74506 		#define CMDQ_CREATE_QP1_RQ_LVL_LVL_0	UINT32_C(0x0)
74508 		#define CMDQ_CREATE_QP1_RQ_LVL_LVL_1	UINT32_C(0x1)
74513 		#define CMDQ_CREATE_QP1_RQ_LVL_LVL_2	UINT32_C(0x2)
74516 	#define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK  UINT32_C(0xf0)
74519 		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K   (UINT32_C(0x0) << 4)
74521 		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K   (UINT32_C(0x1) << 4)
74523 		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K  (UINT32_C(0x2) << 4)
74525 		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M   (UINT32_C(0x3) << 4)
74527 		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M   (UINT32_C(0x4) << 4)
74529 		#define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G   (UINT32_C(0x5) << 4)
74540 	#define CMDQ_CREATE_QP1_SQ_SGE_MASK UINT32_C(0xf)
74541 	#define CMDQ_CREATE_QP1_SQ_SGE_SFT 0
74543 	#define CMDQ_CREATE_QP1_SQ_FWO_MASK UINT32_C(0xfff0)
74547 	#define CMDQ_CREATE_QP1_RQ_SGE_MASK UINT32_C(0xf)
74548 	#define CMDQ_CREATE_QP1_RQ_SGE_SFT 0
74550 	#define CMDQ_CREATE_QP1_RQ_FWO_MASK UINT32_C(0xfff0)
74577 	#define CREQ_CREATE_QP1_RESP_TYPE_MASK	UINT32_C(0x3f)
74578 	#define CREQ_CREATE_QP1_RESP_TYPE_SFT	0
74580 		#define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
74592 	 * will write 1. The odd passes will write 0.
74594 	#define CREQ_CREATE_QP1_RESP_V	UINT32_C(0x1)
74598 	#define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 UINT32_C(0x13)
74614 	#define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 UINT32_C(0x14)
74643 	#define CREQ_DESTROY_QP1_RESP_TYPE_MASK	UINT32_C(0x3f)
74644 	#define CREQ_DESTROY_QP1_RESP_TYPE_SFT	0
74646 		#define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
74658 	 * will write 1. The odd passes will write 0.
74660 	#define CREQ_DESTROY_QP1_RESP_V	UINT32_C(0x1)
74664 	#define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 UINT32_C(0x14)
74680 	#define CMDQ_CREATE_AH_OPCODE_CREATE_AH UINT32_C(0x15)
74700 	#define CMDQ_CREATE_AH_TYPE_V1	UINT32_C(0x0)
74702 	#define CMDQ_CREATE_AH_TYPE_V2IPV4 UINT32_C(0x2)
74704 	#define CMDQ_CREATE_AH_TYPE_V2IPV6 UINT32_C(0x3)
74712 	#define CMDQ_CREATE_AH_FLOW_LABEL_MASK  UINT32_C(0xfffff)
74713 	#define CMDQ_CREATE_AH_FLOW_LABEL_SFT   0
74715 	#define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK UINT32_C(0xfff00000)
74726 	#define CMDQ_CREATE_AH_ENABLE_CC	UINT32_C(0x1)
74740 	#define CREQ_CREATE_AH_RESP_TYPE_MASK	UINT32_C(0x3f)
74741 	#define CREQ_CREATE_AH_RESP_TYPE_SFT	0
74743 		#define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
74755 	 * will write 1. The odd passes will write 0.
74757 	#define CREQ_CREATE_AH_RESP_V	UINT32_C(0x1)
74761 	#define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH UINT32_C(0x15)
74777 	#define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH UINT32_C(0x16)
74806 	#define CREQ_DESTROY_AH_RESP_TYPE_MASK	UINT32_C(0x3f)
74807 	#define CREQ_DESTROY_AH_RESP_TYPE_SFT	0
74809 		#define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
74821 	 * will write 1. The odd passes will write 0.
74823 	#define CREQ_DESTROY_AH_RESP_V	UINT32_C(0x1)
74827 	#define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH UINT32_C(0x16)
74843 	#define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e)
74855 	#define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID	UINT32_C(0x1)
74862 	#define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID	UINT32_C(0x2)
74874 	#define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK  UINT32_C(0xff)
74875 	#define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT   0
74877 	#define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK  UINT32_C(0xffff00)
74880 	#define CMDQ_QUERY_ROCE_STATS_VF_VALID	UINT32_C(0x1000000)
74895 	#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK	UINT32_C(0x3f)
74896 	#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT	0
74898 		#define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
74910 	 * will write 1. The odd passes will write 0.
74912 	#define CREQ_QUERY_ROCE_STATS_RESP_V	UINT32_C(0x1)
74916 	#define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS UINT32_C(0x8e)
74928 	#define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e)
75044 	#define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS UINT32_C(0x92)
75056 	#define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID	UINT32_C(0x1)
75063 	#define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID	UINT32_C(0x2)
75075 	#define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK  UINT32_C(0xff)
75076 	#define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT   0
75078 	#define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK  UINT32_C(0xffff00)
75081 	#define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID	UINT32_C(0x1000000)
75096 	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK	UINT32_C(0x3f)
75097 	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT	0
75099 		#define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
75111 	 * will write 1. The odd passes will write 0.
75113 	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_V	UINT32_C(0x1)
75117 	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT UINT32_C(0x92)
75129 	#define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92)
75299 	#define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC UINT32_C(0x83)
75325 	#define CREQ_QUERY_FUNC_RESP_TYPE_MASK	UINT32_C(0x3f)
75326 	#define CREQ_QUERY_FUNC_RESP_TYPE_SFT	0
75328 		#define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
75340 	 * will write 1. The odd passes will write 0.
75342 	#define CREQ_QUERY_FUNC_RESP_V	UINT32_C(0x1)
75346 	#define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC UINT32_C(0x83)
75358 	#define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC UINT32_C(0x83)
75387 	#define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP				UINT32_C(0x1)
75389 	#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK		UINT32_C(0xe)
75395 		#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0		(UINT32_C(0x0) << 1)
75404 		#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1		(UINT32_C(0x1) << 1)
75410 		#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT		(UINT32_C(0x2) << 1)
75418 		#define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2		(UINT32_C(0x3) << 1)
75425 	#define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS				UINT32_C(0x10)
75432 	#define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC			UINT32_C(0x20)
75437 	#define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED	UINT32_C(0x40)
75443 	#define CREQ_QUERY_FUNC_RESP_SB_CQE_V2				UINT32_C(0x80)
75445 	#define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE		UINT32_C(0x100)
75447 	#define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED		UINT32_C(0x200)
75449 	#define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED		UINT32_C(0x400)
75451 	#define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED		UINT32_C(0x800)
75453 	#define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED_VALID		UINT32_C(0x1000)
75464 	#define CREQ_QUERY_FUNC_RESP_SB_PSEUDO_STATIC_QP_ALLOC_SUPPORTED	UINT32_C(0x2000)
75471 	#define CREQ_QUERY_FUNC_RESP_SB_EXPRESS_MODE_SUPPORTED		UINT32_C(0x4000)
75476 	#define CREQ_QUERY_FUNC_RESP_SB_INTERNAL_QUEUE_MEMORY		UINT32_C(0x8000)
75528 	 * space: 0x00000000, 0x01000000, 0x02000000, etc.
75544 	#define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED	UINT32_C(0x1)
75546 	#define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED	UINT32_C(0x2)
75548 	#define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED	UINT32_C(0x4)
75550 	#define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED	UINT32_C(0x8)
75562 	#define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED	UINT32_C(0x10)
75567 	#define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED	UINT32_C(0x20)
75569 	#define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED	UINT32_C(0x40)
75571 	#define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED			UINT32_C(0x80)
75593 	#define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED		UINT32_C(0x1)
75598 	#define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED	UINT32_C(0x2)
75600 	#define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED		UINT32_C(0x4)
75605 	#define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED		UINT32_C(0x8)
75607 	#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK	UINT32_C(0x30)
75610 		#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE  (UINT32_C(0x0) << 4)
75612 		#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE  (UINT32_C(0x1) << 4)
75617 		#define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE   (UINT32_C(0x2) << 4)
75654 	#define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84)
75664 	#define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT	UINT32_C(0x1)
75710 	 * represents the `max_mr_per_vf` and bits `[15:0]` represents
75749 	#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK	UINT32_C(0x3f)
75750 	#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT	0
75752 		#define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
75763 	 * will write 1. The odd passes will write 0.
75765 	#define CREQ_SET_FUNC_RESOURCES_RESP_V	UINT32_C(0x1)
75769 	#define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84)
75785 	#define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC UINT32_C(0x82)
75811 	#define CREQ_STOP_FUNC_RESP_TYPE_MASK	UINT32_C(0x3f)
75812 	#define CREQ_STOP_FUNC_RESP_TYPE_SFT	0
75814 		#define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
75825 	 * will write 1. The odd passes will write 0.
75827 	#define CREQ_STOP_FUNC_RESP_V	UINT32_C(0x1)
75831 	#define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC UINT32_C(0x82)
75850 	#define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT UINT32_C(0x85)
75872 	#define CMDQ_READ_CONTEXT_TYPE_QPC UINT32_C(0x0)
75877 	#define CMDQ_READ_CONTEXT_TYPE_CQ  UINT32_C(0x1)
75882 	#define CMDQ_READ_CONTEXT_TYPE_MRW UINT32_C(0x2)
75887 	#define CMDQ_READ_CONTEXT_TYPE_SRQ UINT32_C(0x3)
75903 	#define CREQ_READ_CONTEXT_TYPE_MASK	UINT32_C(0x3f)
75904 	#define CREQ_READ_CONTEXT_TYPE_SFT	0
75906 		#define CREQ_READ_CONTEXT_TYPE_QP_EVENT  UINT32_C(0x38)
75917 	 * will write 1. The odd passes will write 0.
75919 	#define CREQ_READ_CONTEXT_V	UINT32_C(0x1)
75926 	#define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT UINT32_C(0x85)
75943 	#define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a)
75959 	#define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE UINT32_C(0xffff)
75964 	#define CMDQ_MAP_TC_TO_COS_COS1_DISABLE   UINT32_C(0x8000)
75966 	#define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE UINT32_C(0xffff)
75982 	#define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK	UINT32_C(0x3f)
75983 	#define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT	0
75985 		#define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
75996 	 * will write 1. The odd passes will write 0.
75998 	#define CREQ_MAP_TC_TO_COS_RESP_V	UINT32_C(0x1)
76002 	#define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS UINT32_C(0x8a)
76018 	#define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
76044 	#define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK	UINT32_C(0x3f)
76045 	#define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT	0
76047 		#define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
76059 	 * will write 1. The odd passes will write 0.
76061 	#define CREQ_QUERY_ROCE_CC_RESP_V	UINT32_C(0x1)
76065 	#define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC UINT32_C(0x8d)
76077 	#define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
76090 	#define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC	UINT32_C(0x1)
76092 	#define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK  UINT32_C(0xfe)
76096 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK UINT32_C(0x3)
76097 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT  0
76102 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc)
76114 	#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK UINT32_C(0x7)
76115 	#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0
76117 	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK	UINT32_C(0xf8)
76121 	#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
76122 	#define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0
76124 	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK	UINT32_C(0xc0)
76128 	#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP	UINT32_C(0x0)
76130 	 * Probabilistic marking CC algorithm. On chips with CC Gen 0
76133 	#define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC UINT32_C(0x1)
76139 	#define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK  UINT32_C(0x3fff)
76140 	#define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT   0
76142 	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK UINT32_C(0xc000)
76146 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK UINT32_C(0x3ff)
76147 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0
76149 	#define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK UINT32_C(0xfc00)
76173 	 * For TLV encapsulated messages this field must be 0x8000.
76182 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE	UINT32_C(0x1)
76184 		#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST	UINT32_C(0x0)
76186 		#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST  UINT32_C(0x1)
76193 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED	UINT32_C(0x2)
76195 		#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO	(UINT32_C(0x0) << 1)
76197 		#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES   (UINT32_C(0x1) << 1)
76208 	 * Global TLV range: `0 - (63k-1)`
76228 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
76241 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC	UINT32_C(0x1)
76243 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK  UINT32_C(0xfe)
76247 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK UINT32_C(0x3)
76248 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT  0
76253 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK UINT32_C(0xfc)
76265 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK UINT32_C(0x7)
76266 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0
76268 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK	UINT32_C(0xf8)
76272 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
76273 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0
76275 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK	UINT32_C(0xc0)
76279 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP	UINT32_C(0x0)
76281 	 * Probabilistic marking CC algorithm. On chips with CC Gen 0
76284 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC UINT32_C(0x1)
76290 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK  UINT32_C(0x3fff)
76291 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT   0
76293 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK UINT32_C(0xc000)
76297 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK UINT32_C(0x3ff)
76298 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0
76300 	#define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK UINT32_C(0xfc00)
76319 	 * For TLV encapsulated messages this field must be 0x8000.
76328 	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE	UINT32_C(0x1)
76330 		#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST	UINT32_C(0x0)
76332 		#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST  UINT32_C(0x1)
76339 	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED	UINT32_C(0x2)
76341 		#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO	(UINT32_C(0x0) << 1)
76343 		#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES   (UINT32_C(0x1) << 1)
76354 	 * Global TLV range: `0 - (63k-1)`
76375 	 * is 0 - 1023.
76379 	 * In tr_update_mode 0, Target Rate (TR) is updated to
76386 	 * 0: TR is updated when QPC. rtts_with_cnps == 0
76416 	 * as a reduction reference. Values between 0 and 6 represent factor of
76424 	 * 0 for disable, 1 for enable.
76432 	 * 0 for not_ect, 1 for ect_0, 2 for ect_1
76436 	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT UINT32_C(0x0)
76438 	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1   UINT32_C(0x1)
76439 	/* ECN Capable Transport-0 */
76440 	#define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0   UINT32_C(0x2)
76571 	 * For TLV encapsulated messages this field must be 0x8000.
76580 	#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE	UINT32_C(0x1)
76582 		#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_LAST	UINT32_C(0x0)
76584 		#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST  UINT32_C(0x1)
76591 	#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED	UINT32_C(0x2)
76593 		#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO	(UINT32_C(0x0) << 1)
76595 		#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES   (UINT32_C(0x1) << 1)
76606 	 * Global TLV range: `0 - (63k-1)`
76620 	 * level table indices 0 to 7.
76626 	 * DCN queue level table indices 0 to 7.
76630 	#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK	UINT32_C(0x3fff)
76631 	#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT	0
76633 	#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP	UINT32_C(0x4000)
76635 	#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM	UINT32_C(0x8000)
76637 	#define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK	UINT32_C(0x3fff0000)
76652 	#define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
76668 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC		UINT32_C(0x1)
76670 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G			UINT32_C(0x2)
76672 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE	UINT32_C(0x4)
76674 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR		UINT32_C(0x8)
76676 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR		UINT32_C(0x10)
76678 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN		UINT32_C(0x20)
76680 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP		UINT32_C(0x40)
76682 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP	UINT32_C(0x80)
76684 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP	UINT32_C(0x100)
76686 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT		UINT32_C(0x200)
76688 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE		UINT32_C(0x400)
76690 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP		UINT32_C(0x800)
76692 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE		UINT32_C(0x1000)
76694 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP	UINT32_C(0x2000)
76696 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE	UINT32_C(0x4000)
76698 	#define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE	UINT32_C(0x8000)
76701 	#define CMDQ_MODIFY_ROCE_CC_ENABLE_CC	UINT32_C(0x1)
76703 	#define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK	UINT32_C(0xfe)
76723 	#define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK UINT32_C(0x3)
76724 	#define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT  0
76729 	#define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK UINT32_C(0xfc)
76733 	#define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK UINT32_C(0x7)
76734 	#define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0
76736 	#define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK	UINT32_C(0xf8)
76740 	#define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
76741 	#define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0
76743 	#define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK	UINT32_C(0xffc0)
76750 	#define CMDQ_MODIFY_ROCE_CC_RTT_MASK  UINT32_C(0x3fff)
76751 	#define CMDQ_MODIFY_ROCE_CC_RTT_SFT   0
76753 	#define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK UINT32_C(0xc000)
76757 	#define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK UINT32_C(0x3ff)
76758 	#define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0
76760 	#define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK UINT32_C(0xfc00)
76764 	#define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE	UINT32_C(0x0)
76766 	 * Probabilistic marking. On chips with CC Gen 0 support this
76769 	#define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE UINT32_C(0x1)
76773 	 * CC support level 0 support 0 to 3 Tx queues.
76774 	 * CC support level 1 supports 0 to 7 Tx queues.
76801 	 * For TLV encapsulated messages this field must be 0x8000.
76810 	#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE	UINT32_C(0x1)
76812 		#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST	UINT32_C(0x0)
76814 		#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST  UINT32_C(0x1)
76821 	#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED	UINT32_C(0x2)
76823 		#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO	(UINT32_C(0x0) << 1)
76825 		#define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES   (UINT32_C(0x1) << 1)
76836 	 * Global TLV range: `0 - (63k-1)`
76856 	#define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
76872 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC		UINT32_C(0x1)
76874 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G			UINT32_C(0x2)
76876 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE	UINT32_C(0x4)
76878 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR		UINT32_C(0x8)
76880 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR		UINT32_C(0x10)
76882 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN		UINT32_C(0x20)
76884 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP		UINT32_C(0x40)
76886 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP	UINT32_C(0x80)
76888 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP	UINT32_C(0x100)
76890 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT		UINT32_C(0x200)
76892 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE		UINT32_C(0x400)
76894 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP		UINT32_C(0x800)
76896 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE		UINT32_C(0x1000)
76898 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP	UINT32_C(0x2000)
76900 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE	UINT32_C(0x4000)
76902 	#define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE	UINT32_C(0x8000)
76905 	#define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC	UINT32_C(0x1)
76907 	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK	UINT32_C(0xfe)
76927 	#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK UINT32_C(0x3)
76928 	#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT  0
76933 	#define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK UINT32_C(0xfc)
76937 	#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK UINT32_C(0x7)
76938 	#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0
76940 	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK	UINT32_C(0xf8)
76944 	#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
76945 	#define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0
76947 	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK	UINT32_C(0xffc0)
76954 	#define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK  UINT32_C(0x3fff)
76955 	#define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT   0
76957 	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK UINT32_C(0xc000)
76961 	#define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK UINT32_C(0x3ff)
76962 	#define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0
76964 	#define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK UINT32_C(0xfc00)
76968 	#define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE	UINT32_C(0x0)
76970 	 * Probabilistic marking. On chips with CC Gen 0 support this
76973 	#define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE UINT32_C(0x1)
76977 	 * CC support level 0 support 0 to 3 Tx queues.
76978 	 * CC support level 1 supports 0 to 7 Tx queues.
77002 	 * For TLV encapsulated messages this field must be 0x8000.
77011 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE	UINT32_C(0x1)
77013 		#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST	UINT32_C(0x0)
77015 		#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST  UINT32_C(0x1)
77022 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED	UINT32_C(0x2)
77024 		#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO	(UINT32_C(0x0) << 1)
77026 		#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES   (UINT32_C(0x1) << 1)
77037 	 * Global TLV range: `0 - (63k-1)`
77055 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS		UINT32_C(0x1)
77060 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP			UINT32_C(0x2)
77062 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE			UINT32_C(0x4)
77064 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES		UINT32_C(0x8)
77066 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS			UINT32_C(0x10)
77068 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE		UINT32_C(0x20)
77073 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH	UINT32_C(0x40)
77078 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH		UINT32_C(0x80)
77080 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH			UINT32_C(0x100)
77082 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT			UINT32_C(0x200)
77084 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR		UINT32_C(0x400)
77086 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH			UINT32_C(0x800)
77088 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN			UINT32_C(0x1000)
77093 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS			UINT32_C(0x2000)
77095 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN			UINT32_C(0x4000)
77097 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN			UINT32_C(0x8000)
77099 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC		UINT32_C(0x10000)
77104 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH			UINT32_C(0x20000)
77106 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH			UINT32_C(0x40000)
77108 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN		UINT32_C(0x80000)
77110 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX		UINT32_C(0x100000)
77115 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX		UINT32_C(0x200000)
77117 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND			UINT32_C(0x400000)
77122 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR			UINT32_C(0x800000)
77127 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR			UINT32_C(0x1000000)
77132 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH			UINT32_C(0x2000000)
77134 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV			UINT32_C(0x4000000)
77139 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH			UINT32_C(0x8000000)
77144 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS			UINT32_C(0x10000000)
77146 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO		UINT32_C(0x20000000)
77151 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH		UINT32_C(0x40000000)
77156 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1		UINT32_C(0x80000000)
77161 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2		UINT32_C(0x100000000)L
77163 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE			UINT32_C(0x200000000)L
77168 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT		UINT32_C(0x400000000)L
77173 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH	UINT32_C(0x800000000)L
77178 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1		UINT32_C(0x1000000000)L
77183 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2		UINT32_C(0x2000000000)L
77188 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES			UINT32_C(0x4000000000)L
77190 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN			UINT32_C(0x8000000000)L
77195 …#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH	UINT32_C(0x10000000…
77197 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN		UINT32_C(0x20000000000)L
77199 …#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN	UINT32_C(0x40000000…
77201 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN		UINT32_C(0x80000000000)L
77211 	 * is 0 - 1023.
77215 	 * In tr_update_mode 0, Target Rate (TR) is updated to
77222 	 * 0: TR is updated when QPC. rtts_with_cnps == 0
77252 	 * as a reduction reference. Values between 0 and 6 represent factor of
77260 	 * 0 for disable, 1 for enable.
77268 	 * 0 for not_ect, 1 for ect_0, 2 for ect_1
77272 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT UINT32_C(0x0)
77274 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1   UINT32_C(0x1)
77275 	/* ECN Capable Transport-0 */
77276 	#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0   UINT32_C(0x2)
77407 	 * For TLV encapsulated messages this field must be 0x8000.
77416 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE	UINT32_C(0x1)
77418 		#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_LAST	UINT32_C(0x0)
77420 		#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_NOT_LAST  UINT32_C(0x1)
77427 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED	UINT32_C(0x2)
77429 		#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_NO	(UINT32_C(0x0) << 1)
77431 		#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES   (UINT32_C(0x1) << 1)
77442 	 * Global TLV range: `0 - (63k-1)`
77461 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_IDX	UINT32_C(0x1)
77463 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_THR	UINT32_C(0x2)
77465 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_CR	UINT32_C(0x4)
77467 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_INC_CNP	UINT32_C(0x8)
77469 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_UPD_IMM	UINT32_C(0x10)
77471 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_TR	UINT32_C(0x20)
77472 	/* DCN queue level table index. Valid values are from 0 to 7. */
77487 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK	UINT32_C(0x3fff)
77488 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT	0
77490 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP	UINT32_C(0x4000)
77492 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM	UINT32_C(0x8000)
77494 	#define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK	UINT32_C(0x3fff0000)
77509 	#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK	UINT32_C(0x3f)
77510 	#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT	0
77512 		#define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
77523 	 * will write 1. The odd passes will write 0.
77525 	#define CREQ_MODIFY_ROCE_CC_RESP_V	UINT32_C(0x1)
77529 	#define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC UINT32_C(0x8c)
77545 	#define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f)
77561 	#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN		UINT32_C(0x1)
77563 	#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP	UINT32_C(0x2)
77565 	#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP	UINT32_C(0x4)
77567 	#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE	UINT32_C(0x8)
77569 	#define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID	UINT32_C(0x10)
77572 	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE	UINT32_C(0x1)
77574 	#define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK	UINT32_C(0xfe)
77578 	#define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK UINT32_C(0xf)
77579 	#define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0
77581 	#define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK	UINT32_C(0xf0)
77588 	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
77590 	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
77592 	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR   UINT32_C(0x3)
77594 	#define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD	UINT32_C(0x4)
77612 	#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK	UINT32_C(0x3f)
77613 	#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT	0
77615 		#define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
77626 	 * will write 1. The odd passes will write 0.
77628 	#define CREQ_SET_LINK_AGGR_MODE_RESP_V	UINT32_C(0x1)
77632 	#define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE UINT32_C(0x8f)
77647 	#define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86)
77680 	#define CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY UINT32_C(0x87)
77695 	/* VF id, as provided in 0xC0 VF request notification */
77713 	#define CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88)
77733 	/* VF id, as provided in 0xC0 VF request notification */
77758 	#define CMDQ_ORCHESTRATE_QID_MIGRATION_OPCODE_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93)
77773 	#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_MASK			UINT32_C(0xf)
77774 	#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_SFT			0
77776 		#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_ENABLE_NATIVE_QID_RANGE	UINT32_C(0x0)
77778 …#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_ENABLE_EXTENDED_QID_RANGE   UINT32_C(0x…
77780 		#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_NATIVE_QID_RANGE	UINT32_C(0x2)
77782 …#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_EXTENDED_QID_RANGE  UINT32_C(0x…
77785 	#define CMDQ_ORCHESTRATE_QID_MIGRATION_UNUSED4_MASK				UINT32_C(0xf0)
77803 	#define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_MASK	UINT32_C(0x3f)
77804 	#define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_SFT	0
77806 		#define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
77817 	 * will write 1. The odd passes will write 0.
77819 	#define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_V	UINT32_C(0x1)
77823 	#define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_EVENT_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93)
77839 	#define CMDQ_CREATE_QP_BATCH_OPCODE_CREATE_QP_BATCH UINT32_C(0x94)
77881 	#define CREQ_CREATE_QP_BATCH_RESP_TYPE_MASK	UINT32_C(0x3f)
77882 	#define CREQ_CREATE_QP_BATCH_RESP_TYPE_SFT	0
77884 		#define CREQ_CREATE_QP_BATCH_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
77895 	 * will write 1. The odd passes will write 0.
77897 	#define CREQ_CREATE_QP_BATCH_RESP_V	UINT32_C(0x1)
77901 	#define CREQ_CREATE_QP_BATCH_RESP_EVENT_CREATE_QP_BATCH UINT32_C(0x94)
77923 	#define CMDQ_DESTROY_QP_BATCH_OPCODE_DESTROY_QP_BATCH UINT32_C(0x95)
77958 	#define CREQ_DESTROY_QP_BATCH_RESP_TYPE_MASK	UINT32_C(0x3f)
77959 	#define CREQ_DESTROY_QP_BATCH_RESP_TYPE_SFT	0
77961 		#define CREQ_DESTROY_QP_BATCH_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
77972 	 * will write 1. The odd passes will write 0.
77974 	#define CREQ_DESTROY_QP_BATCH_RESP_V	UINT32_C(0x1)
77978 	#define CREQ_DESTROY_QP_BATCH_RESP_EVENT_DESTROY_QP_BATCH UINT32_C(0x95)
78003 	#define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96)
78024 	 * If update_period_ms is 0, then the stats update
78046 	#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK	UINT32_C(0x3f)
78047 	#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT	0
78049 		#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
78061 	 * will write 1. The odd passes will write 0.
78063 	#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_V	UINT32_C(0x1)
78067 	#define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96)
78083 	#define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97)
78114 	#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK	UINT32_C(0x3f)
78115 	#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT	0
78117 		#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
78129 	 * will write 1. The odd passes will write 0.
78131 	#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_V	UINT32_C(0x1)
78135 	#define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97)
78154 	#define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
78185 	#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_MASK	UINT32_C(0x3f)
78186 	#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_SFT	0
78188 		#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT  UINT32_C(0x38)
78200 	 * will write 1. The odd passes will write 0.
78202 	#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_V	UINT32_C(0x1)
78206 	#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
78218 	#define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
78336 	#define CREQ_FUNC_EVENT_TYPE_MASK	UINT32_C(0x3f)
78337 	#define CREQ_FUNC_EVENT_TYPE_SFT	0
78339 		#define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT  UINT32_C(0x3a)
78346 	 * will write 1. The odd passes will write 0.
78348 	#define CREQ_FUNC_EVENT_V	UINT32_C(0x1)
78358 	#define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR	UINT32_C(0x1)
78363 	#define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR	UINT32_C(0x2)
78368 	#define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR	UINT32_C(0x3)
78370 	#define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR	UINT32_C(0x4)
78372 	#define CREQ_FUNC_EVENT_EVENT_CQ_ERROR	UINT32_C(0x5)
78377 	#define CREQ_FUNC_EVENT_EVENT_TQM_ERROR	UINT32_C(0x6)
78379 	#define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR	UINT32_C(0x7)
78381 	#define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR	UINT32_C(0x8)
78383 	#define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR	UINT32_C(0x9)
78385 	#define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR	UINT32_C(0xa)
78391 	#define CREQ_FUNC_EVENT_EVENT_TIM_ERROR	UINT32_C(0xb)
78393 	#define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST	UINT32_C(0x80)
78398 	#define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED UINT32_C(0x81)
78415 	#define CREQ_QP_EVENT_TYPE_MASK	UINT32_C(0x3f)
78416 	#define CREQ_QP_EVENT_TYPE_SFT	0
78418 		#define CREQ_QP_EVENT_TYPE_QP_EVENT  UINT32_C(0x38)
78423 	#define CREQ_QP_EVENT_STATUS_SUCCESS	UINT32_C(0x0)
78425 	#define CREQ_QP_EVENT_STATUS_FAIL		UINT32_C(0x1)
78427 	#define CREQ_QP_EVENT_STATUS_RESOURCES	UINT32_C(0x2)
78429 	#define CREQ_QP_EVENT_STATUS_INVALID_CMD	UINT32_C(0x3)
78431 	#define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED   UINT32_C(0x4)
78433 	#define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER UINT32_C(0x5)
78435 	#define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR	UINT32_C(0x6)
78437 	#define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR	UINT32_C(0x7)
78446 	 * will write 1. The odd passes will write 0.
78448 	#define CREQ_QP_EVENT_V	UINT32_C(0x1)
78452 	#define CREQ_QP_EVENT_EVENT_CREATE_QP		UINT32_C(0x1)
78454 	#define CREQ_QP_EVENT_EVENT_DESTROY_QP		UINT32_C(0x2)
78456 	#define CREQ_QP_EVENT_EVENT_MODIFY_QP		UINT32_C(0x3)
78458 	#define CREQ_QP_EVENT_EVENT_QUERY_QP		UINT32_C(0x4)
78460 	#define CREQ_QP_EVENT_EVENT_CREATE_SRQ		UINT32_C(0x5)
78462 	#define CREQ_QP_EVENT_EVENT_DESTROY_SRQ	UINT32_C(0x6)
78464 	#define CREQ_QP_EVENT_EVENT_QUERY_SRQ		UINT32_C(0x8)
78466 	#define CREQ_QP_EVENT_EVENT_CREATE_CQ		UINT32_C(0x9)
78468 	#define CREQ_QP_EVENT_EVENT_DESTROY_CQ		UINT32_C(0xa)
78470 	#define CREQ_QP_EVENT_EVENT_RESIZE_CQ		UINT32_C(0xc)
78472 	#define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW	UINT32_C(0xd)
78474 	#define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY	UINT32_C(0xe)
78476 	#define CREQ_QP_EVENT_EVENT_REGISTER_MR	UINT32_C(0xf)
78478 	#define CREQ_QP_EVENT_EVENT_DEREGISTER_MR	UINT32_C(0x10)
78480 	#define CREQ_QP_EVENT_EVENT_ADD_GID		UINT32_C(0x11)
78482 	#define CREQ_QP_EVENT_EVENT_DELETE_GID		UINT32_C(0x12)
78484 	#define CREQ_QP_EVENT_EVENT_MODIFY_GID		UINT32_C(0x17)
78486 	#define CREQ_QP_EVENT_EVENT_QUERY_GID		UINT32_C(0x18)
78488 	#define CREQ_QP_EVENT_EVENT_CREATE_QP1		UINT32_C(0x13)
78490 	#define CREQ_QP_EVENT_EVENT_DESTROY_QP1	UINT32_C(0x14)
78492 	#define CREQ_QP_EVENT_EVENT_CREATE_AH		UINT32_C(0x15)
78494 	#define CREQ_QP_EVENT_EVENT_DESTROY_AH		UINT32_C(0x16)
78496 	#define CREQ_QP_EVENT_EVENT_INITIALIZE_FW	UINT32_C(0x80)
78498 	#define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW	UINT32_C(0x81)
78500 	#define CREQ_QP_EVENT_EVENT_STOP_FUNC		UINT32_C(0x82)
78502 	#define CREQ_QP_EVENT_EVENT_QUERY_FUNC		UINT32_C(0x83)
78504 	#define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES	UINT32_C(0x84)
78509 	#define CREQ_QP_EVENT_EVENT_READ_CONTEXT	UINT32_C(0x85)
78511 	#define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS	UINT32_C(0x8a)
78513 	#define CREQ_QP_EVENT_EVENT_QUERY_VERSION	UINT32_C(0x8b)
78515 	#define CREQ_QP_EVENT_EVENT_MODIFY_CC		UINT32_C(0x8c)
78517 	#define CREQ_QP_EVENT_EVENT_QUERY_CC		UINT32_C(0x8d)
78519 	#define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS	UINT32_C(0x8e)
78521 	#define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE	UINT32_C(0x8f)
78526 	#define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND	UINT32_C(0x91)
78528 	#define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0)
78530 	#define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION UINT32_C(0xc1)
78547 	#define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK	UINT32_C(0x3f)
78548 	#define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT	0
78550 		#define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT  UINT32_C(0x38)
78559 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR			UINT32_C(0x0)
78568 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR		UINT32_C(0x1)
78575 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT	UINT32_C(0x2)
78582 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT UINT32_C(0x3)
78587 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1	UINT32_C(0x4)
78592 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2	UINT32_C(0x5)
78597 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3	UINT32_C(0x6)
78602 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4	UINT32_C(0x7)
78608 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR	UINT32_C(0x8)
78614 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR	UINT32_C(0x9)
78621 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH	UINT32_C(0xa)
78628 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP	UINT32_C(0xb)
78646 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND		UINT32_C(0xc)
78664 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG	UINT32_C(0xd)
78678 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE	UINT32_C(0xe)
78684 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR		UINT32_C(0xf)
78690 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR	UINT32_C(0x10)
78695 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR	UINT32_C(0x11)
78700 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR	UINT32_C(0x12)
78705 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR	UINT32_C(0x13)
78711 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR	UINT32_C(0x14)
78716 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR	UINT32_C(0x15)
78723 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR	UINT32_C(0x16)
78731 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR	UINT32_C(0x17)
78738 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR		UINT32_C(0x18)
78745 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR		UINT32_C(0x19)
78754 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR   UINT32_C(0x1a)
78764 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR   UINT32_C(0x1b)
78780 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR	UINT32_C(0x1c)
78786 	#define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW		UINT32_C(0x1d)
78794 	 * will write 1. The odd passes will write 0.
78796 	#define CREQ_QP_ERROR_NOTIFICATION_V	UINT32_C(0x1)
78800 	#define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0)
78806 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR			UINT32_C(0x0)
78813 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX		UINT32_C(0x1)
78821 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH   UINT32_C(0x2)
78828 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE		UINT32_C(0x3)
78836 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR		UINT32_C(0x4)
78844 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT UINT32_C(0x5)
78853 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY	UINT32_C(0x6)
78861 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR	UINT32_C(0x7)
78869 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION	UINT32_C(0x8)
78876 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR		UINT32_C(0x9)
78885 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY	UINT32_C(0xa)
78893 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR	UINT32_C(0xb)
78901 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION	UINT32_C(0xc)
78908 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR		UINT32_C(0xd)
78915 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW		UINT32_C(0xe)
78922 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE	UINT32_C(0xf)
78928 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC		UINT32_C(0x10)
78939 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE		UINT32_C(0x11)
78945 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR		UINT32_C(0x12)
78951 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR		UINT32_C(0x13)
78957 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR		UINT32_C(0x14)
78962 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY	UINT32_C(0x15)
78967 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR	UINT32_C(0x16)
78972 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR	UINT32_C(0x17)
78977 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR		UINT32_C(0x18)
78982 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR		UINT32_C(0x19)
78989 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR		UINT32_C(0x1b)
78996 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR		UINT32_C(0x1c)
79002 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND		UINT32_C(0x1d)
79008 	#define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW		UINT32_C(0x1e)
79034 	#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK	UINT32_C(0x3f)
79035 	#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT	0
79037 		#define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT  UINT32_C(0x38)
79044 	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR  UINT32_C(0x1)
79046 	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR UINT32_C(0x2)
79048 	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR	UINT32_C(0x3)
79050 	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR  UINT32_C(0x4)
79052 	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR UINT32_C(0x5)
79054 	#define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR	UINT32_C(0x6)
79063 	 * will write 1. The odd passes will write 0.
79065 	#define CREQ_CQ_ERROR_NOTIFICATION_V	UINT32_C(0x1)
79069 	#define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION UINT32_C(0xc1)
79080 	#define SQ_BASE_WQE_TYPE_SEND		UINT32_C(0x0)
79087 	#define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD	UINT32_C(0x1)
79093 	#define SQ_BASE_WQE_TYPE_SEND_W_INVALID	UINT32_C(0x2)
79099 	#define SQ_BASE_WQE_TYPE_WRITE_WQE		UINT32_C(0x4)
79105 	#define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD	UINT32_C(0x5)
79111 	#define SQ_BASE_WQE_TYPE_READ_WQE		UINT32_C(0x6)
79117 	#define SQ_BASE_WQE_TYPE_ATOMIC_CS		UINT32_C(0x8)
79123 	#define SQ_BASE_WQE_TYPE_ATOMIC_FA		UINT32_C(0xb)
79129 	#define SQ_BASE_WQE_TYPE_LOCAL_INVALID	UINT32_C(0xc)
79135 	#define SQ_BASE_WQE_TYPE_FR_PMR		UINT32_C(0xd)
79141 	#define SQ_BASE_WQE_TYPE_BIND		UINT32_C(0xe)
79147 	#define SQ_BASE_WQE_TYPE_FR_PPMR		UINT32_C(0xf)
79149 	#define SQ_BASE_WQE_TYPE_SEND_V3		UINT32_C(0x10)
79155 	#define SQ_BASE_WQE_TYPE_SEND_W_IMMED_V3	UINT32_C(0x11)
79161 	#define SQ_BASE_WQE_TYPE_SEND_W_INVALID_V3	UINT32_C(0x12)
79167 	#define SQ_BASE_WQE_TYPE_UDSEND_V3		UINT32_C(0x13)
79173 	#define SQ_BASE_WQE_TYPE_UDSEND_W_IMMED_V3	UINT32_C(0x14)
79179 	#define SQ_BASE_WQE_TYPE_WRITE_WQE_V3	UINT32_C(0x15)
79185 	#define SQ_BASE_WQE_TYPE_WRITE_W_IMMED_V3	UINT32_C(0x16)
79191 	#define SQ_BASE_WQE_TYPE_READ_WQE_V3	UINT32_C(0x17)
79197 	#define SQ_BASE_WQE_TYPE_ATOMIC_CS_V3	UINT32_C(0x18)
79203 	#define SQ_BASE_WQE_TYPE_ATOMIC_FA_V3	UINT32_C(0x19)
79209 	#define SQ_BASE_WQE_TYPE_LOCAL_INVALID_V3	UINT32_C(0x1a)
79215 	#define SQ_BASE_WQE_TYPE_FR_PMR_V3		UINT32_C(0x1b)
79221 	#define SQ_BASE_WQE_TYPE_BIND_V3		UINT32_C(0x1c)
79223 	#define SQ_BASE_WQE_TYPE_RAWQP1SEND_V3	UINT32_C(0x1d)
79225 	#define SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e)
79236  * the mode). In variable-sized WQE mode there can be 0-30 SGE
79272 	#define SQ_PSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff)
79273 	#define SQ_PSN_SEARCH_START_PSN_SFT 0
79275 	#define SQ_PSN_SEARCH_OPCODE_MASK   UINT32_C(0xff000000)
79279 	#define SQ_PSN_SEARCH_NEXT_PSN_MASK UINT32_C(0xffffff)
79280 	#define SQ_PSN_SEARCH_NEXT_PSN_SFT 0
79282 	#define SQ_PSN_SEARCH_FLAGS_MASK   UINT32_C(0xff000000)
79293 	#define SQ_PSN_SEARCH_EXT_START_PSN_MASK UINT32_C(0xffffff)
79294 	#define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0
79296 	#define SQ_PSN_SEARCH_EXT_OPCODE_MASK   UINT32_C(0xff000000)
79300 	#define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK UINT32_C(0xffffff)
79301 	#define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0
79303 	#define SQ_PSN_SEARCH_EXT_FLAGS_MASK   UINT32_C(0xff000000)
79323 	#define SQ_MSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff)
79324 	#define SQ_MSN_SEARCH_START_PSN_SFT 0
79326 	#define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL
79333 	#define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL
79344 	#define SQ_SEND_WQE_TYPE_SEND	UINT32_C(0x0)
79351 	#define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD  UINT32_C(0x1)
79357 	#define SQ_SEND_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
79360 	#define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
79361 	#define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
79364 	 * 0, and the SQ is configured to support Unsignaled completion
79369 	#define SQ_SEND_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
79376 	#define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
79383 	#define SQ_SEND_FLAGS_UC_FENCE								UINT32_C(0x4)
79390 	#define SQ_SEND_FLAGS_SE									UINT32_C(0x8)
79395 	#define SQ_SEND_FLAGS_INLINE								UINT32_C(0x10)
79398 	 * cleared to 0, then TWE provides the timestamp.
79400 	#define SQ_SEND_FLAGS_WQE_TS_EN								UINT32_C(0x20)
79405 	#define SQ_SEND_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
79444 	#define SQ_SEND_DST_QP_MASK UINT32_C(0xffffff)
79445 	#define SQ_SEND_DST_QP_SFT 0
79451 	#define SQ_SEND_AVID_MASK UINT32_C(0xfffff)
79452 	#define SQ_SEND_AVID_SFT 0
79460 	#define SQ_SEND_TIMESTAMP_MASK UINT32_C(0xffffff)
79461 	#define SQ_SEND_TIMESTAMP_SFT 0
79463 	 * When inline=0, then this area is filled with from 1 to 6
79467 	 * send based on the length_or_AVID field. Bits [7:0] of word 0
79480 	#define SQ_SEND_HDR_WQE_TYPE_SEND	UINT32_C(0x0)
79487 	#define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD  UINT32_C(0x1)
79493 	#define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
79496 	#define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
79497 	#define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
79500 	 * 0, and the SQ is configured to support Unsignaled completion
79505 	#define SQ_SEND_HDR_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
79512 	#define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
79519 	#define SQ_SEND_HDR_FLAGS_UC_FENCE								UINT32_C(0x4)
79526 	#define SQ_SEND_HDR_FLAGS_SE									UINT32_C(0x8)
79531 	#define SQ_SEND_HDR_FLAGS_INLINE								UINT32_C(0x10)
79534 	 * cleared to 0, then TWE provides the timestamp.
79536 	#define SQ_SEND_HDR_FLAGS_WQE_TS_EN								UINT32_C(0x20)
79541 	#define SQ_SEND_HDR_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
79580 	#define SQ_SEND_HDR_DST_QP_MASK UINT32_C(0xffffff)
79581 	#define SQ_SEND_HDR_DST_QP_SFT 0
79587 	#define SQ_SEND_HDR_AVID_MASK UINT32_C(0xfffff)
79588 	#define SQ_SEND_HDR_AVID_SFT 0
79596 	#define SQ_SEND_HDR_TIMESTAMP_MASK UINT32_C(0xffffff)
79597 	#define SQ_SEND_HDR_TIMESTAMP_SFT 0
79607 	#define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND UINT32_C(0x0)
79610 …ine SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
79611 	#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
79614 	 * 0, and the SQ is configured to support Unsignaled completion
79619 	#define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
79621 	#define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
79623 	#define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE								UINT32_C(0x4)
79625 	#define SQ_SEND_RAWETH_QP1_FLAGS_SE									UINT32_C(0x8)
79630 	#define SQ_SEND_RAWETH_QP1_FLAGS_INLINE								UINT32_C(0x10)
79633 	 * cleared to 0, then TWE provides the timestamp.
79635 	#define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN								UINT32_C(0x20)
79640 	#define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
79666 	#define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM	UINT32_C(0x1)
79675 	#define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM	UINT32_C(0x2)
79687 	#define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC		UINT32_C(0x4)
79694 	#define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP		UINT32_C(0x8)
79703 	#define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM	UINT32_C(0x10)
79708 	#define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC	UINT32_C(0x100)
79713 	#define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC	UINT32_C(0x200)
79733 	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK	UINT32_C(0xfff)
79734 	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT	0
79736 	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE	UINT32_C(0x1000)
79738 	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK	UINT32_C(0xe000)
79741 	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK	UINT32_C(0x70000)
79743 	/* 0x88a8 */
79744 		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8  (UINT32_C(0x0) << 16)
79745 	/* 0x8100 */
79746 		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100  (UINT32_C(0x1) << 16)
79747 	/* 0x9100 */
79748 		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100  (UINT32_C(0x2) << 16)
79749 	/* 0x9200 */
79750 		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200  (UINT32_C(0x3) << 16)
79751 	/* 0x9300 */
79752 		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300  (UINT32_C(0x4) << 16)
79754 		#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG   (UINT32_C(0x5) << 16)
79757 	#define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
79765 	#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK	UINT32_C(0xf0000000)
79768 		#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE		(UINT32_C(0x0) << 28)
79770 	 * - meta[17:16] - TPID select value (0 = 0x8100).
79772 	 * - meta[11:0] - VID value.
79774 		#define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG	(UINT32_C(0x1) << 28)
79784 	#define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK UINT32_C(0xffffff)
79785 	#define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0
79787 	 * When inline=0, then this area is filled with from 1 to 6
79791 	 * send based on the length_or_AVID field. Bits [7:0] of word 0
79804 	#define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND UINT32_C(0x0)
79807 …SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
79808 	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
79811 	 * 0, and the SQ is configured to support Unsignaled completion
79816 	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
79818 	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
79820 	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE								UINT32_C(0x4)
79822 	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE									UINT32_C(0x8)
79827 	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE								UINT32_C(0x10)
79830 	 * cleared to 0, then TWE provides the timestamp.
79832 	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN								UINT32_C(0x20)
79837 	#define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
79863 	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM	UINT32_C(0x1)
79872 	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM	UINT32_C(0x2)
79884 	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC		UINT32_C(0x4)
79891 	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP		UINT32_C(0x8)
79900 	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM	UINT32_C(0x10)
79905 	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC	UINT32_C(0x100)
79910 	#define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC	UINT32_C(0x200)
79930 	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK	UINT32_C(0xfff)
79931 	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT	0
79933 	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE	UINT32_C(0x1000)
79935 	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK	UINT32_C(0xe000)
79938 	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK	UINT32_C(0x70000)
79940 	/* 0x88a8 */
79941 		#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8  (UINT32_C(0x0) << 16)
79942 	/* 0x8100 */
79943 		#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100  (UINT32_C(0x1) << 16)
79944 	/* 0x9100 */
79945 		#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100  (UINT32_C(0x2) << 16)
79946 	/* 0x9200 */
79947 		#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200  (UINT32_C(0x3) << 16)
79948 	/* 0x9300 */
79949 		#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300  (UINT32_C(0x4) << 16)
79951 		#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG   (UINT32_C(0x5) << 16)
79954 	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
79962 	#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK	UINT32_C(0xf0000000)
79965 		#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE		(UINT32_C(0x0) << 28)
79967 	 * - meta[17:16] - TPID select value (0 = 0x8100).
79969 	 * - meta[11:0] - VID value.
79971 		#define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG	(UINT32_C(0x1) << 28)
79981 	#define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK UINT32_C(0xffffff)
79982 	#define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0
79996 	#define SQ_RDMA_WQE_TYPE_WRITE_WQE	UINT32_C(0x4)
80002 	#define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
80008 	#define SQ_RDMA_WQE_TYPE_READ_WQE	UINT32_C(0x6)
80011 	#define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
80012 	#define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
80015 	 * 0, and the SQ is configured to support Unsignaled
80020 	#define SQ_RDMA_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
80025 	#define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
80030 	#define SQ_RDMA_FLAGS_UC_FENCE								UINT32_C(0x4)
80037 	#define SQ_RDMA_FLAGS_SE									UINT32_C(0x8)
80042 	#define SQ_RDMA_FLAGS_INLINE								UINT32_C(0x10)
80045 	 * cleared to 0, then TWE provides the timestamp.
80047 	#define SQ_RDMA_FLAGS_WQE_TS_EN								UINT32_C(0x20)
80052 	#define SQ_RDMA_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
80086 	#define SQ_RDMA_TIMESTAMP_MASK UINT32_C(0xffffff)
80087 	#define SQ_RDMA_TIMESTAMP_SFT 0
80089 	 * When inline=0, then this area is filled with from 1 to 6
80093 	 * write based on the length field. Bits [7:0] of word 0
80110 	#define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE	UINT32_C(0x4)
80116 	#define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
80122 	#define SQ_RDMA_HDR_WQE_TYPE_READ_WQE	UINT32_C(0x6)
80125 	#define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
80126 	#define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
80129 	 * 0, and the SQ is configured to support Unsignaled
80134 	#define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
80139 	#define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
80144 	#define SQ_RDMA_HDR_FLAGS_UC_FENCE								UINT32_C(0x4)
80151 	#define SQ_RDMA_HDR_FLAGS_SE									UINT32_C(0x8)
80156 	#define SQ_RDMA_HDR_FLAGS_INLINE								UINT32_C(0x10)
80159 	 * cleared to 0, then TWE provides the timestamp.
80161 	#define SQ_RDMA_HDR_FLAGS_WQE_TS_EN								UINT32_C(0x20)
80166 	#define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
80200 	#define SQ_RDMA_HDR_TIMESTAMP_MASK UINT32_C(0xffffff)
80201 	#define SQ_RDMA_HDR_TIMESTAMP_SFT 0
80215 	#define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
80221 	#define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
80224 	#define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
80225 	#define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
80228 	 * 0, and the SQ is configured to support Unsignaled
80233 	#define SQ_ATOMIC_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
80238 	#define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
80243 	#define SQ_ATOMIC_FLAGS_UC_FENCE								UINT32_C(0x4)
80250 	#define SQ_ATOMIC_FLAGS_SE									UINT32_C(0x8)
80252 	#define SQ_ATOMIC_FLAGS_INLINE								UINT32_C(0x10)
80257 	#define SQ_ATOMIC_FLAGS_WQE_TS_EN								UINT32_C(0x20)
80262 	#define SQ_ATOMIC_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
80298 	#define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
80304 	#define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
80307 	#define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
80308 	#define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
80311 	 * 0, and the SQ is configured to support Unsignaled
80316 	#define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
80321 	#define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
80326 	#define SQ_ATOMIC_HDR_FLAGS_UC_FENCE								UINT32_C(0x4)
80333 	#define SQ_ATOMIC_HDR_FLAGS_SE									UINT32_C(0x8)
80335 	#define SQ_ATOMIC_HDR_FLAGS_INLINE								UINT32_C(0x10)
80340 	#define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN								UINT32_C(0x20)
80345 	#define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
80375 	#define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
80378 …ine SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
80379 	#define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
80382 	 * 0, and the SQ is configured to support Unsignaled
80387 	#define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
80392 	#define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
80397 	#define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE								UINT32_C(0x4)
80404 	#define SQ_LOCALINVALIDATE_FLAGS_SE									UINT32_C(0x8)
80406 	#define SQ_LOCALINVALIDATE_FLAGS_INLINE								UINT32_C(0x10)
80408 	 * This flag is not applicable and should be 0 for a local memory
80411 	#define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN								UINT32_C(0x20)
80416 	#define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
80441 	#define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
80444 …SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
80445 	#define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
80448 	 * 0, and the SQ is configured to support Unsignaled
80453 	#define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
80458 	#define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
80463 	#define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE								UINT32_C(0x4)
80470 	#define SQ_LOCALINVALIDATE_HDR_FLAGS_SE									UINT32_C(0x8)
80472 	#define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE								UINT32_C(0x10)
80474 	 * This flag is not applicable and should be 0 for a local memory
80477 	#define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN								UINT32_C(0x20)
80482 	#define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
80505 	#define SQ_FR_PMR_WQE_TYPE_FR_PMR UINT32_C(0xd)
80510 	 * 0, and the SQ is configured to support Unsignaled
80515 	#define SQ_FR_PMR_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
80520 	#define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
80525 	#define SQ_FR_PMR_FLAGS_UC_FENCE		UINT32_C(0x4)
80527 	#define SQ_FR_PMR_FLAGS_SE			UINT32_C(0x8)
80529 	#define SQ_FR_PMR_FLAGS_INLINE		UINT32_C(0x10)
80531 	 * This flag is not applicable and should be 0 for a local memory
80534 	#define SQ_FR_PMR_FLAGS_WQE_TS_EN		UINT32_C(0x20)
80539 	#define SQ_FR_PMR_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
80542 	 * the operation is allowed. '0' means operation is
80547 	#define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE	UINT32_C(0x1)
80549 	#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ	UINT32_C(0x2)
80551 	#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE	UINT32_C(0x4)
80553 	#define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC	UINT32_C(0x8)
80555 	#define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND	UINT32_C(0x10)
80557 	/* Page size. 0 for 4KB page size, ... to 8TB. */
80558 	#define SQ_FR_PMR_PAGE_SIZE_LOG_MASK	UINT32_C(0x1f)
80559 	#define SQ_FR_PMR_PAGE_SIZE_LOG_SFT	0
80561 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K	UINT32_C(0x0)
80563 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K	UINT32_C(0x1)
80565 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K   UINT32_C(0x2)
80567 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K   UINT32_C(0x3)
80569 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K   UINT32_C(0x4)
80571 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K  UINT32_C(0x5)
80573 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K  UINT32_C(0x6)
80575 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K  UINT32_C(0x7)
80577 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M	UINT32_C(0x8)
80579 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M	UINT32_C(0x9)
80581 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M	UINT32_C(0xa)
80583 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M	UINT32_C(0xb)
80585 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M   UINT32_C(0xc)
80587 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M   UINT32_C(0xd)
80589 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M   UINT32_C(0xe)
80591 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M  UINT32_C(0xf)
80593 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M  UINT32_C(0x10)
80595 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M  UINT32_C(0x11)
80597 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G	UINT32_C(0x12)
80599 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G	UINT32_C(0x13)
80601 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G	UINT32_C(0x14)
80603 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G	UINT32_C(0x15)
80605 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G   UINT32_C(0x16)
80607 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G   UINT32_C(0x17)
80609 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G   UINT32_C(0x18)
80611 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G  UINT32_C(0x19)
80613 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G  UINT32_C(0x1a)
80615 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G  UINT32_C(0x1b)
80617 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T	UINT32_C(0x1c)
80619 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T	UINT32_C(0x1d)
80621 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T	UINT32_C(0x1e)
80623 		#define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T	UINT32_C(0x1f)
80626 	#define SQ_FR_PMR_ZERO_BASED		UINT32_C(0x20)
80638 	/* PBL page size. 0 for 4KB page size, ... to 8TB. */
80639 	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK	UINT32_C(0x1f)
80640 	#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT	0
80642 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K	UINT32_C(0x0)
80644 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K	UINT32_C(0x1)
80646 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K   UINT32_C(0x2)
80648 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K   UINT32_C(0x3)
80650 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K   UINT32_C(0x4)
80652 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K  UINT32_C(0x5)
80654 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K  UINT32_C(0x6)
80656 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K  UINT32_C(0x7)
80658 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M	UINT32_C(0x8)
80660 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M	UINT32_C(0x9)
80662 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M	UINT32_C(0xa)
80664 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M	UINT32_C(0xb)
80666 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M   UINT32_C(0xc)
80668 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M   UINT32_C(0xd)
80670 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M   UINT32_C(0xe)
80672 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M  UINT32_C(0xf)
80674 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M  UINT32_C(0x10)
80676 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M  UINT32_C(0x11)
80678 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G	UINT32_C(0x12)
80680 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G	UINT32_C(0x13)
80682 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G	UINT32_C(0x14)
80684 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G	UINT32_C(0x15)
80686 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G   UINT32_C(0x16)
80688 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G   UINT32_C(0x17)
80690 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G   UINT32_C(0x18)
80692 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G  UINT32_C(0x19)
80694 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G  UINT32_C(0x1a)
80696 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G  UINT32_C(0x1b)
80698 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T	UINT32_C(0x1c)
80700 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T	UINT32_C(0x1d)
80702 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T	UINT32_C(0x1e)
80704 		#define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T	UINT32_C(0x1f)
80707 	#define SQ_FR_PMR_NUMLEVELS_MASK		UINT32_C(0xc0)
80713 		#define SQ_FR_PMR_NUMLEVELS_PHYSICAL	(UINT32_C(0x0) << 6)
80719 		#define SQ_FR_PMR_NUMLEVELS_LAYER1		(UINT32_C(0x1) << 6)
80727 		#define SQ_FR_PMR_NUMLEVELS_LAYER2		(UINT32_C(0x2) << 6)
80748 	#define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR UINT32_C(0xd)
80753 	 * 0, and the SQ is configured to support Unsignaled
80758 	#define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
80763 	#define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
80768 	#define SQ_FR_PMR_HDR_FLAGS_UC_FENCE		UINT32_C(0x4)
80770 	#define SQ_FR_PMR_HDR_FLAGS_SE			UINT32_C(0x8)
80772 	#define SQ_FR_PMR_HDR_FLAGS_INLINE		UINT32_C(0x10)
80774 	 * This flag is not applicable and should be 0 for a local memory
80777 	#define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN		UINT32_C(0x20)
80782 	#define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
80785 	 * the operation is allowed. '0' means operation is
80790 	#define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE	UINT32_C(0x1)
80792 	#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ	UINT32_C(0x2)
80794 	#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE	UINT32_C(0x4)
80796 	#define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC	UINT32_C(0x8)
80798 	#define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND	UINT32_C(0x10)
80800 	/* Page size. 0 for 4KB page size, ... to 8TB. */
80801 	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK	UINT32_C(0x1f)
80802 	#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT	0
80804 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K	UINT32_C(0x0)
80806 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K	UINT32_C(0x1)
80808 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K   UINT32_C(0x2)
80810 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K   UINT32_C(0x3)
80812 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K   UINT32_C(0x4)
80814 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K  UINT32_C(0x5)
80816 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K  UINT32_C(0x6)
80818 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K  UINT32_C(0x7)
80820 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M	UINT32_C(0x8)
80822 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M	UINT32_C(0x9)
80824 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M	UINT32_C(0xa)
80826 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M	UINT32_C(0xb)
80828 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M   UINT32_C(0xc)
80830 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M   UINT32_C(0xd)
80832 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M   UINT32_C(0xe)
80834 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M  UINT32_C(0xf)
80836 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M  UINT32_C(0x10)
80838 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M  UINT32_C(0x11)
80840 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G	UINT32_C(0x12)
80842 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G	UINT32_C(0x13)
80844 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G	UINT32_C(0x14)
80846 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G	UINT32_C(0x15)
80848 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G   UINT32_C(0x16)
80850 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G   UINT32_C(0x17)
80852 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G   UINT32_C(0x18)
80854 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G  UINT32_C(0x19)
80856 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G  UINT32_C(0x1a)
80858 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G  UINT32_C(0x1b)
80860 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T	UINT32_C(0x1c)
80862 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T	UINT32_C(0x1d)
80864 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T	UINT32_C(0x1e)
80866 		#define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T	UINT32_C(0x1f)
80869 	#define SQ_FR_PMR_HDR_ZERO_BASED		UINT32_C(0x20)
80881 	/* PBL page size. 0 for 4KB page size, ... to 8TB. */
80882 	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK	UINT32_C(0x1f)
80883 	#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT	0
80885 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K	UINT32_C(0x0)
80887 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K	UINT32_C(0x1)
80889 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K   UINT32_C(0x2)
80891 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K   UINT32_C(0x3)
80893 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K   UINT32_C(0x4)
80895 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K  UINT32_C(0x5)
80897 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K  UINT32_C(0x6)
80899 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K  UINT32_C(0x7)
80901 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M	UINT32_C(0x8)
80903 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M	UINT32_C(0x9)
80905 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M	UINT32_C(0xa)
80907 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M	UINT32_C(0xb)
80909 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M   UINT32_C(0xc)
80911 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M   UINT32_C(0xd)
80913 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M   UINT32_C(0xe)
80915 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M  UINT32_C(0xf)
80917 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M  UINT32_C(0x10)
80919 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M  UINT32_C(0x11)
80921 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G	UINT32_C(0x12)
80923 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G	UINT32_C(0x13)
80925 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G	UINT32_C(0x14)
80927 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G	UINT32_C(0x15)
80929 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G   UINT32_C(0x16)
80931 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G   UINT32_C(0x17)
80933 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G   UINT32_C(0x18)
80935 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G  UINT32_C(0x19)
80937 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G  UINT32_C(0x1a)
80939 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G  UINT32_C(0x1b)
80941 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T	UINT32_C(0x1c)
80943 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T	UINT32_C(0x1d)
80945 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T	UINT32_C(0x1e)
80947 		#define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T	UINT32_C(0x1f)
80950 	#define SQ_FR_PMR_HDR_NUMLEVELS_MASK		UINT32_C(0xc0)
80956 		#define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL	(UINT32_C(0x0) << 6)
80962 		#define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1		(UINT32_C(0x1) << 6)
80970 		#define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2		(UINT32_C(0x2) << 6)
80989 	#define SQ_FR_PPMR_WQE_TYPE_FR_PPMR UINT32_C(0xf)
80994 	 * 0, and the SQ is configured to support Unsignaled
80999 	#define SQ_FR_PPMR_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
81004 	#define SQ_FR_PPMR_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
81009 	#define SQ_FR_PPMR_FLAGS_UC_FENCE		UINT32_C(0x4)
81011 	#define SQ_FR_PPMR_FLAGS_SE			UINT32_C(0x8)
81013 	#define SQ_FR_PPMR_FLAGS_INLINE		UINT32_C(0x10)
81015 	 * This flag is not applicable and should be 0 for a local memory
81018 	#define SQ_FR_PPMR_FLAGS_WQE_TS_EN		UINT32_C(0x20)
81023 	#define SQ_FR_PPMR_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
81026 	 * the operation is allowed. '0' means operation is
81031 	#define SQ_FR_PPMR_ACCESS_CNTL_LOCAL_WRITE	UINT32_C(0x1)
81033 	#define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_READ	UINT32_C(0x2)
81035 	#define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_WRITE	UINT32_C(0x4)
81037 	#define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_ATOMIC	UINT32_C(0x8)
81039 	#define SQ_FR_PPMR_ACCESS_CNTL_WINDOW_BIND	UINT32_C(0x10)
81041 	/* Page size. 0 for 4KB page size, ... to 8TB. */
81042 	#define SQ_FR_PPMR_PAGE_SIZE_LOG_MASK	UINT32_C(0x1f)
81043 	#define SQ_FR_PPMR_PAGE_SIZE_LOG_SFT	0
81045 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4K	UINT32_C(0x0)
81047 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8K	UINT32_C(0x1)
81049 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16K   UINT32_C(0x2)
81051 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32K   UINT32_C(0x3)
81053 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64K   UINT32_C(0x4)
81055 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128K  UINT32_C(0x5)
81057 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256K  UINT32_C(0x6)
81059 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512K  UINT32_C(0x7)
81061 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1M	UINT32_C(0x8)
81063 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2M	UINT32_C(0x9)
81065 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4M	UINT32_C(0xa)
81067 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8M	UINT32_C(0xb)
81069 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16M   UINT32_C(0xc)
81071 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32M   UINT32_C(0xd)
81073 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64M   UINT32_C(0xe)
81075 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128M  UINT32_C(0xf)
81077 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256M  UINT32_C(0x10)
81079 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512M  UINT32_C(0x11)
81081 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1G	UINT32_C(0x12)
81083 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2G	UINT32_C(0x13)
81085 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4G	UINT32_C(0x14)
81087 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8G	UINT32_C(0x15)
81089 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16G   UINT32_C(0x16)
81091 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32G   UINT32_C(0x17)
81093 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64G   UINT32_C(0x18)
81095 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128G  UINT32_C(0x19)
81097 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256G  UINT32_C(0x1a)
81099 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512G  UINT32_C(0x1b)
81101 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1T	UINT32_C(0x1c)
81103 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2T	UINT32_C(0x1d)
81105 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4T	UINT32_C(0x1e)
81107 		#define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8T	UINT32_C(0x1f)
81110 	#define SQ_FR_PPMR_ZERO_BASED		UINT32_C(0x20)
81124 	/* PBL page size. 0 for 4KB page size, ... to 8TB. */
81125 	#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_MASK	UINT32_C(0x1f)
81126 	#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_SFT	0
81128 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4K	UINT32_C(0x0)
81130 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8K	UINT32_C(0x1)
81132 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16K   UINT32_C(0x2)
81134 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32K   UINT32_C(0x3)
81136 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64K   UINT32_C(0x4)
81138 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128K  UINT32_C(0x5)
81140 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256K  UINT32_C(0x6)
81142 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512K  UINT32_C(0x7)
81144 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1M	UINT32_C(0x8)
81146 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2M	UINT32_C(0x9)
81148 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4M	UINT32_C(0xa)
81150 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8M	UINT32_C(0xb)
81152 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16M   UINT32_C(0xc)
81154 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32M   UINT32_C(0xd)
81156 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64M   UINT32_C(0xe)
81158 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128M  UINT32_C(0xf)
81160 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256M  UINT32_C(0x10)
81162 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512M  UINT32_C(0x11)
81164 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1G	UINT32_C(0x12)
81166 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2G	UINT32_C(0x13)
81168 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4G	UINT32_C(0x14)
81170 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8G	UINT32_C(0x15)
81172 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16G   UINT32_C(0x16)
81174 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32G   UINT32_C(0x17)
81176 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64G   UINT32_C(0x18)
81178 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128G  UINT32_C(0x19)
81180 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256G  UINT32_C(0x1a)
81182 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512G  UINT32_C(0x1b)
81184 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1T	UINT32_C(0x1c)
81186 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2T	UINT32_C(0x1d)
81188 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4T	UINT32_C(0x1e)
81190 		#define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8T	UINT32_C(0x1f)
81193 	#define SQ_FR_PPMR_PROXY_VF_VALID		UINT32_C(0x20)
81195 	#define SQ_FR_PPMR_NUMLEVELS_MASK		UINT32_C(0xc0)
81201 		#define SQ_FR_PPMR_NUMLEVELS_PHYSICAL	(UINT32_C(0x0) << 6)
81207 		#define SQ_FR_PPMR_NUMLEVELS_LAYER1		(UINT32_C(0x1) << 6)
81215 		#define SQ_FR_PPMR_NUMLEVELS_LAYER2		(UINT32_C(0x2) << 6)
81236 	#define SQ_FR_PPMR_HDR_WQE_TYPE_FR_PPMR UINT32_C(0xf)
81241 	 * 0, and the SQ is configured to support Unsignaled
81246 	#define SQ_FR_PPMR_HDR_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
81251 	#define SQ_FR_PPMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
81256 	#define SQ_FR_PPMR_HDR_FLAGS_UC_FENCE		UINT32_C(0x4)
81258 	#define SQ_FR_PPMR_HDR_FLAGS_SE			UINT32_C(0x8)
81260 	#define SQ_FR_PPMR_HDR_FLAGS_INLINE		UINT32_C(0x10)
81262 	 * This flag is not applicable and should be 0 for a local memory
81265 	#define SQ_FR_PPMR_HDR_FLAGS_WQE_TS_EN		UINT32_C(0x20)
81270 	#define SQ_FR_PPMR_HDR_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
81273 	 * the operation is allowed. '0' means operation is
81278 	#define SQ_FR_PPMR_HDR_ACCESS_CNTL_LOCAL_WRITE	UINT32_C(0x1)
81280 	#define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_READ	UINT32_C(0x2)
81282 	#define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_WRITE	UINT32_C(0x4)
81284 	#define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC	UINT32_C(0x8)
81286 	#define SQ_FR_PPMR_HDR_ACCESS_CNTL_WINDOW_BIND	UINT32_C(0x10)
81288 	/* Page size. 0 for 4KB page size, ... to 8TB. */
81289 	#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_MASK	UINT32_C(0x1f)
81290 	#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_SFT	0
81292 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4K	UINT32_C(0x0)
81294 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8K	UINT32_C(0x1)
81296 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16K   UINT32_C(0x2)
81298 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32K   UINT32_C(0x3)
81300 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64K   UINT32_C(0x4)
81302 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128K  UINT32_C(0x5)
81304 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256K  UINT32_C(0x6)
81306 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512K  UINT32_C(0x7)
81308 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1M	UINT32_C(0x8)
81310 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2M	UINT32_C(0x9)
81312 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4M	UINT32_C(0xa)
81314 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8M	UINT32_C(0xb)
81316 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16M   UINT32_C(0xc)
81318 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32M   UINT32_C(0xd)
81320 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64M   UINT32_C(0xe)
81322 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128M  UINT32_C(0xf)
81324 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256M  UINT32_C(0x10)
81326 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512M  UINT32_C(0x11)
81328 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1G	UINT32_C(0x12)
81330 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2G	UINT32_C(0x13)
81332 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4G	UINT32_C(0x14)
81334 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8G	UINT32_C(0x15)
81336 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16G   UINT32_C(0x16)
81338 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32G   UINT32_C(0x17)
81340 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64G   UINT32_C(0x18)
81342 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128G  UINT32_C(0x19)
81344 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256G  UINT32_C(0x1a)
81346 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512G  UINT32_C(0x1b)
81348 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1T	UINT32_C(0x1c)
81350 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2T	UINT32_C(0x1d)
81352 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4T	UINT32_C(0x1e)
81354 		#define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8T	UINT32_C(0x1f)
81357 	#define SQ_FR_PPMR_HDR_ZERO_BASED		UINT32_C(0x20)
81371 	/* PBL page size. 0 for 4KB page size, ... to 8TB. */
81372 	#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_MASK	UINT32_C(0x1f)
81373 	#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_SFT	0
81375 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K	UINT32_C(0x0)
81377 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K	UINT32_C(0x1)
81379 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K   UINT32_C(0x2)
81381 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K   UINT32_C(0x3)
81383 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K   UINT32_C(0x4)
81385 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K  UINT32_C(0x5)
81387 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K  UINT32_C(0x6)
81389 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K  UINT32_C(0x7)
81391 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M	UINT32_C(0x8)
81393 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M	UINT32_C(0x9)
81395 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M	UINT32_C(0xa)
81397 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M	UINT32_C(0xb)
81399 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M   UINT32_C(0xc)
81401 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M   UINT32_C(0xd)
81403 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M   UINT32_C(0xe)
81405 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M  UINT32_C(0xf)
81407 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M  UINT32_C(0x10)
81409 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M  UINT32_C(0x11)
81411 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G	UINT32_C(0x12)
81413 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G	UINT32_C(0x13)
81415 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G	UINT32_C(0x14)
81417 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G	UINT32_C(0x15)
81419 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G   UINT32_C(0x16)
81421 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G   UINT32_C(0x17)
81423 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G   UINT32_C(0x18)
81425 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G  UINT32_C(0x19)
81427 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G  UINT32_C(0x1a)
81429 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G  UINT32_C(0x1b)
81431 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T	UINT32_C(0x1c)
81433 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T	UINT32_C(0x1d)
81435 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T	UINT32_C(0x1e)
81437 		#define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T	UINT32_C(0x1f)
81440 	#define SQ_FR_PPMR_HDR_PROXY_VF_VALID		UINT32_C(0x20)
81442 	#define SQ_FR_PPMR_HDR_NUMLEVELS_MASK		UINT32_C(0xc0)
81448 		#define SQ_FR_PPMR_HDR_NUMLEVELS_PHYSICAL	(UINT32_C(0x0) << 6)
81454 		#define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER1		(UINT32_C(0x1) << 6)
81462 		#define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER2		(UINT32_C(0x2) << 6)
81485 	#define SQ_BIND_WQE_TYPE_BIND UINT32_C(0xe)
81488 	#define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
81489 	#define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
81492 	 * 0, and the SQ is configured to support Unsignaled
81497 	#define SQ_BIND_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
81502 	#define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
81507 	#define SQ_BIND_FLAGS_UC_FENCE								UINT32_C(0x4)
81509 	#define SQ_BIND_FLAGS_SE									UINT32_C(0x8)
81511 	#define SQ_BIND_FLAGS_INLINE								UINT32_C(0x10)
81513 	 * This flag is not applicable and should be 0 for a local memory
81516 	#define SQ_BIND_FLAGS_WQE_TS_EN								UINT32_C(0x20)
81521 	#define SQ_BIND_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
81524 	 * the operation is allowed. '0' means operation is
81528 …IND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK		UINT32_C(0xff)
81529 	#define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT		0
81537 	#define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE									UINT32_C(0x1)
81539 	#define SQ_BIND_ACCESS_CNTL_REMOTE_READ									UINT32_C(0x2)
81548 	#define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE									UINT32_C(0x4)
81557 	#define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC									UINT32_C(0x8)
81565 	#define SQ_BIND_ACCESS_CNTL_WINDOW_BIND									UINT32_C(0x10)
81574 	#define SQ_BIND_ZERO_BASED	UINT32_C(0x1)
81594 	#define SQ_BIND_MW_TYPE	UINT32_C(0x2)
81596 		#define SQ_BIND_MW_TYPE_TYPE1	(UINT32_C(0x0) << 1)
81598 		#define SQ_BIND_MW_TYPE_TYPE2	(UINT32_C(0x1) << 1)
81641 	#define SQ_BIND_HDR_WQE_TYPE_BIND UINT32_C(0xe)
81644 	#define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK		UINT32_C(0xff)
81645 	#define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT			0
81648 	 * 0, and the SQ is configured to support Unsignaled
81653 	#define SQ_BIND_HDR_FLAGS_SIGNAL_COMP								UINT32_C(0x1)
81658 	#define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE							UINT32_C(0x2)
81663 	#define SQ_BIND_HDR_FLAGS_UC_FENCE								UINT32_C(0x4)
81665 	#define SQ_BIND_HDR_FLAGS_SE									UINT32_C(0x8)
81667 	#define SQ_BIND_HDR_FLAGS_INLINE								UINT32_C(0x10)
81669 	 * This flag is not applicable and should be 0 for a local memory
81672 	#define SQ_BIND_HDR_FLAGS_WQE_TS_EN								UINT32_C(0x20)
81677 	#define SQ_BIND_HDR_FLAGS_DEBUG_TRACE								UINT32_C(0x40)
81680 	 * the operation is allowed. '0' means operation is
81684 …HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK		UINT32_C(0xff)
81685 …efine SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT		0
81693 	#define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE									UINT32_C(0x1)
81695 	#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ									UINT32_C(0x2)
81704 	#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE									UINT32_C(0x4)
81713 	#define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC									UINT32_C(0x8)
81721 	#define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND									UINT32_C(0x10)
81730 	#define SQ_BIND_HDR_ZERO_BASED	UINT32_C(0x1)
81750 	#define SQ_BIND_HDR_MW_TYPE	UINT32_C(0x2)
81752 		#define SQ_BIND_HDR_MW_TYPE_TYPE1	(UINT32_C(0x0) << 1)
81754 		#define SQ_BIND_HDR_MW_TYPE_TYPE2	(UINT32_C(0x1) << 1)
81789 	#define SQ_MSN_SEARCH_V3_START_PSN_MASK UINT32_C(0xffffff)
81790 	#define SQ_MSN_SEARCH_V3_START_PSN_SFT 0
81792 	#define SQ_MSN_SEARCH_V3_NEXT_PSN_MASK UINT32_C(0xffffff000000)L
81799 	#define SQ_MSN_SEARCH_V3_START_IDX_MASK UINT32_C(0xffff000000000000)L
81810 	#define SQ_MSN_SEARCH_V3_SGNLD			UINT32_C(0x1)
81816 	#define SQ_MSN_SEARCH_V3_PREV_SGNLD_LOCAL_MEM_WQE	UINT32_C(0x2)
81827 	#define SQ_SEND_V3_WQE_TYPE_SEND_V3	UINT32_C(0x10)
81833 	#define SQ_SEND_V3_WQE_TYPE_SEND_W_IMMED_V3   UINT32_C(0x11)
81839 	#define SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12)
81844 	 * 0, and the SQ is configured to support Unsignaled completion
81849 	#define SQ_SEND_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
81856 	#define SQ_SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
81863 	#define SQ_SEND_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
81869 	#define SQ_SEND_V3_FLAGS_SE			UINT32_C(0x8)
81874 	#define SQ_SEND_V3_FLAGS_INLINE		UINT32_C(0x10)
81877 	 * cleared to 0, then TWE provides the timestamp.
81879 	#define SQ_SEND_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
81884 	#define SQ_SEND_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
81897 	#define SQ_SEND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
81898 	#define SQ_SEND_V3_WQE_SIZE_SFT 0
81903 	 * Zero means all 16 bytes are valid. One means only bits 7:0 of
81909 	 * ((inline_length == 0 ) ? 16 : inline_length)
81917 	#define SQ_SEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
81918 	#define SQ_SEND_V3_INLINE_LENGTH_SFT 0
81937 	#define SQ_SEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
81938 	#define SQ_SEND_V3_TIMESTAMP_SFT 0
81940 	 * When inline=0, then this area is filled with from 1 to 30 SGEs
81945 	 * Bits [7:0] of word 0 hold the first byte to go out on the wire.
81957 	#define SQ_SEND_HDR_V3_WQE_TYPE_SEND_V3	UINT32_C(0x10)
81963 	#define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_IMMED_V3   UINT32_C(0x11)
81969 	#define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12)
81974 	 * 0, and the SQ is configured to support Unsignaled completion
81979 	#define SQ_SEND_HDR_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
81986 	#define SQ_SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
81993 	#define SQ_SEND_HDR_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
81999 	#define SQ_SEND_HDR_V3_FLAGS_SE			UINT32_C(0x8)
82004 	#define SQ_SEND_HDR_V3_FLAGS_INLINE		UINT32_C(0x10)
82007 	 * cleared to 0, then TWE provides the timestamp.
82009 	#define SQ_SEND_HDR_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
82014 	#define SQ_SEND_HDR_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
82027 	#define SQ_SEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82028 	#define SQ_SEND_HDR_V3_WQE_SIZE_SFT 0
82033 	 * Zero means all 16 bytes are valid. One means only bits 7:0 of
82039 	 * ((inline_length == 0 ) ? 16 : inline_length)
82047 	#define SQ_SEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
82048 	#define SQ_SEND_HDR_V3_INLINE_LENGTH_SFT 0
82067 	#define SQ_SEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
82068 	#define SQ_SEND_HDR_V3_TIMESTAMP_SFT 0
82078 	#define SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d)
82083 	 * 0, and the SQ is configured to support Unsignaled completion
82088 	#define SQ_RAWQP1SEND_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
82095 	#define SQ_RAWQP1SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
82102 	#define SQ_RAWQP1SEND_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
82110 	#define SQ_RAWQP1SEND_V3_FLAGS_SE			UINT32_C(0x8)
82115 	#define SQ_RAWQP1SEND_V3_FLAGS_INLINE		UINT32_C(0x10)
82118 	 * cleared to 0, then TWE provides the timestamp.
82120 	#define SQ_RAWQP1SEND_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
82125 	#define SQ_RAWQP1SEND_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
82136 	#define SQ_RAWQP1SEND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82137 	#define SQ_RAWQP1SEND_V3_WQE_SIZE_SFT 0
82142 	 * Zero means all 16 bytes are valid. One means only bits 7:0 of
82148 	 * ((inline_length == 0 ) ? 16 : inline_length)
82156 	#define SQ_RAWQP1SEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
82157 	#define SQ_RAWQP1SEND_V3_INLINE_LENGTH_SFT 0
82177 	#define SQ_RAWQP1SEND_V3_LFLAGS_TCP_UDP_CHKSUM	UINT32_C(0x1)
82186 	#define SQ_RAWQP1SEND_V3_LFLAGS_IP_CHKSUM	UINT32_C(0x2)
82198 	#define SQ_RAWQP1SEND_V3_LFLAGS_NOCRC		UINT32_C(0x4)
82207 	#define SQ_RAWQP1SEND_V3_LFLAGS_T_IP_CHKSUM	UINT32_C(0x10)
82217 	 * - If outer UDP checksum is 0, then do not update it.
82221 	#define SQ_RAWQP1SEND_V3_LFLAGS_OT_IP_CHKSUM	UINT32_C(0x20)
82226 	#define SQ_RAWQP1SEND_V3_LFLAGS_ROCE_CRC	UINT32_C(0x100)
82231 	#define SQ_RAWQP1SEND_V3_LFLAGS_FCOE_CRC	UINT32_C(0x200)
82250 	#define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
82251 	#define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_SFT 0
82259 	#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_MASK	UINT32_C(0xfff)
82260 	#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_SFT	0
82262 	#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_DE	UINT32_C(0x1000)
82264 	#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_MASK	UINT32_C(0xe000)
82267 	#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_MASK	UINT32_C(0x70000)
82269 	/* 0x88a8 */
82270 		#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID88A8  (UINT32_C(0x0) << 16)
82271 	/* 0x8100 */
82272 		#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID8100  (UINT32_C(0x1) << 16)
82273 	/* 0x9100 */
82274 		#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9100  (UINT32_C(0x2) << 16)
82275 	/* 0x9200 */
82276 		#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9200  (UINT32_C(0x3) << 16)
82277 	/* 0x9300 */
82278 		#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9300  (UINT32_C(0x4) << 16)
82280 		#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG   (UINT32_C(0x5) << 16)
82283 	#define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
82291 	#define SQ_RAWQP1SEND_V3_CFA_META_KEY_MASK	UINT32_C(0xf0000000)
82294 		#define SQ_RAWQP1SEND_V3_CFA_META_KEY_NONE		(UINT32_C(0x0) << 28)
82296 	 * - meta[17:16] - TPID select value (0 = 0x8100).
82298 	 * - meta[11:0] - VID value.
82300 		#define SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG	(UINT32_C(0x1) << 28)
82308 	#define SQ_RAWQP1SEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
82309 	#define SQ_RAWQP1SEND_V3_TIMESTAMP_SFT 0
82312 	 * When inline=0, then this area is filled with from 1 to 6 SGEs
82317 	 * Bits [7:0] of word 0 hold the first byte to go out on the wire.
82329 	#define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d)
82334 	 * 0, and the SQ is configured to support Unsignaled completion
82339 	#define SQ_RAWQP1SEND_HDR_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
82346 	#define SQ_RAWQP1SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
82353 	#define SQ_RAWQP1SEND_HDR_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
82361 	#define SQ_RAWQP1SEND_HDR_V3_FLAGS_SE			UINT32_C(0x8)
82366 	#define SQ_RAWQP1SEND_HDR_V3_FLAGS_INLINE		UINT32_C(0x10)
82369 	 * cleared to 0, then TWE provides the timestamp.
82371 	#define SQ_RAWQP1SEND_HDR_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
82376 	#define SQ_RAWQP1SEND_HDR_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
82387 	#define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82388 	#define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_SFT 0
82393 	 * Zero means all 16 bytes are valid. One means only bits 7:0 of
82399 	 * ((inline_length == 0 ) ? 16 : inline_length)
82407 	#define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
82408 	#define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_SFT 0
82428 	#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_TCP_UDP_CHKSUM	UINT32_C(0x1)
82437 	#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_IP_CHKSUM	UINT32_C(0x2)
82449 	#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_NOCRC		UINT32_C(0x4)
82458 	#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_T_IP_CHKSUM	UINT32_C(0x10)
82468 	 * - If outer UDP checksum is 0, then do not update it.
82472 	#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_OT_IP_CHKSUM	UINT32_C(0x20)
82477 	#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_ROCE_CRC	UINT32_C(0x100)
82482 	#define SQ_RAWQP1SEND_HDR_V3_LFLAGS_FCOE_CRC	UINT32_C(0x200)
82501 	#define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
82502 	#define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_SFT 0
82510 	#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_MASK	UINT32_C(0xfff)
82511 	#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_SFT	0
82513 	#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_DE	UINT32_C(0x1000)
82515 	#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_MASK	UINT32_C(0xe000)
82518 	#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_MASK	UINT32_C(0x70000)
82520 	/* 0x88a8 */
82521 		#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID88A8  (UINT32_C(0x0) << 16)
82522 	/* 0x8100 */
82523 		#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID8100  (UINT32_C(0x1) << 16)
82524 	/* 0x9100 */
82525 		#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9100  (UINT32_C(0x2) << 16)
82526 	/* 0x9200 */
82527 		#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9200  (UINT32_C(0x3) << 16)
82528 	/* 0x9300 */
82529 		#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9300  (UINT32_C(0x4) << 16)
82531 		#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG   (UINT32_C(0x5) << 16)
82534 	#define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
82542 	#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_MASK	UINT32_C(0xf0000000)
82545 		#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_NONE		(UINT32_C(0x0) << 28)
82547 	 * - meta[17:16] - TPID select value (0 = 0x8100).
82549 	 * - meta[11:0] - VID value.
82551 		#define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG	(UINT32_C(0x1) << 28)
82559 	#define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
82560 	#define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_SFT 0
82575 	#define SQ_UDSEND_V3_WQE_TYPE_UDSEND_V3	UINT32_C(0x13)
82581 	#define SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14)
82586 	 * 0, and the SQ is configured to support Unsignaled completion
82591 	#define SQ_UDSEND_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
82598 	#define SQ_UDSEND_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
82605 	#define SQ_UDSEND_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
82611 	#define SQ_UDSEND_V3_FLAGS_SE			UINT32_C(0x8)
82616 	#define SQ_UDSEND_V3_FLAGS_INLINE		UINT32_C(0x10)
82619 	 * cleared to 0, then TWE provides the timestamp.
82621 	#define SQ_UDSEND_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
82626 	#define SQ_UDSEND_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
82637 	#define SQ_UDSEND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82638 	#define SQ_UDSEND_V3_WQE_SIZE_SFT 0
82643 	 * Zero means all 16 bytes are valid. One means only bits 7:0 of
82649 	 * ((inline_length == 0 ) ? 16 : inline_length)
82657 	#define SQ_UDSEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
82658 	#define SQ_UDSEND_V3_INLINE_LENGTH_SFT 0
82687 	#define SQ_UDSEND_V3_DST_QP_MASK UINT32_C(0xffffff)
82688 	#define SQ_UDSEND_V3_DST_QP_SFT 0
82694 	#define SQ_UDSEND_V3_AVID_MASK UINT32_C(0x3ff)
82695 	#define SQ_UDSEND_V3_AVID_SFT 0
82703 	#define SQ_UDSEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
82704 	#define SQ_UDSEND_V3_TIMESTAMP_SFT 0
82706 	 * When inline=0, then this area is filled with from 1 to 30 SGEs
82711 	 * Bits [7:0] of word 0 hold the first byte to go out on the wire.
82727 	#define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_V3	UINT32_C(0x13)
82733 	#define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14)
82738 	 * 0, and the SQ is configured to support Unsignaled completion
82743 	#define SQ_UDSEND_HDR_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
82750 	#define SQ_UDSEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
82757 	#define SQ_UDSEND_HDR_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
82763 	#define SQ_UDSEND_HDR_V3_FLAGS_SE			UINT32_C(0x8)
82768 	#define SQ_UDSEND_HDR_V3_FLAGS_INLINE		UINT32_C(0x10)
82771 	 * cleared to 0, then TWE provides the timestamp.
82773 	#define SQ_UDSEND_HDR_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
82778 	#define SQ_UDSEND_HDR_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
82789 	#define SQ_UDSEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82790 	#define SQ_UDSEND_HDR_V3_WQE_SIZE_SFT 0
82795 	 * Zero means all 16 bytes are valid. One means only bits 7:0 of
82801 	 * ((inline_length == 0 ) ? 16 : inline_length)
82809 	#define SQ_UDSEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
82810 	#define SQ_UDSEND_HDR_V3_INLINE_LENGTH_SFT 0
82839 	#define SQ_UDSEND_HDR_V3_DST_QP_MASK UINT32_C(0xffffff)
82840 	#define SQ_UDSEND_HDR_V3_DST_QP_SFT 0
82846 	#define SQ_UDSEND_HDR_V3_AVID_MASK UINT32_C(0x3ff)
82847 	#define SQ_UDSEND_HDR_V3_AVID_SFT 0
82855 	#define SQ_UDSEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
82856 	#define SQ_UDSEND_HDR_V3_TIMESTAMP_SFT 0
82870 	#define SQ_RDMA_V3_WQE_TYPE_WRITE_WQE_V3	UINT32_C(0x15)
82876 	#define SQ_RDMA_V3_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16)
82882 	#define SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3	UINT32_C(0x17)
82887 	 * 0, and the SQ is configured to support Unsignaled
82892 	#define SQ_RDMA_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
82897 	#define SQ_RDMA_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
82902 	#define SQ_RDMA_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
82908 	#define SQ_RDMA_V3_FLAGS_SE			UINT32_C(0x8)
82913 	#define SQ_RDMA_V3_FLAGS_INLINE		UINT32_C(0x10)
82916 	 * cleared to 0, then TWE provides the timestamp.
82918 	#define SQ_RDMA_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
82923 	#define SQ_RDMA_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
82934 	#define SQ_RDMA_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82935 	#define SQ_RDMA_V3_WQE_SIZE_SFT 0
82940 	 * Zero means all 16 bytes are valid. One means only bits 7:0 of
82946 	 * ((inline_length == 0 ) ? 16 : inline_length)
82954 	#define SQ_RDMA_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
82955 	#define SQ_RDMA_V3_INLINE_LENGTH_SFT 0
82981 	#define SQ_RDMA_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
82982 	#define SQ_RDMA_V3_TIMESTAMP_SFT 0
82984 	 * When inline=0, then this area is filled with from 1 to 30 SGEs
82988 	 * Length of data is described in the inline_length field. Bits [7:0]
82989 	 * of word 0 hold the first byte to go out on the wire.
83005 	#define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_WQE_V3	UINT32_C(0x15)
83011 	#define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16)
83017 	#define SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3	UINT32_C(0x17)
83022 	 * 0, and the SQ is configured to support Unsignaled
83027 	#define SQ_RDMA_HDR_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
83032 	#define SQ_RDMA_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
83037 	#define SQ_RDMA_HDR_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
83043 	#define SQ_RDMA_HDR_V3_FLAGS_SE			UINT32_C(0x8)
83048 	#define SQ_RDMA_HDR_V3_FLAGS_INLINE		UINT32_C(0x10)
83051 	 * cleared to 0, then TWE provides the timestamp.
83053 	#define SQ_RDMA_HDR_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
83058 	#define SQ_RDMA_HDR_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
83069 	#define SQ_RDMA_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
83070 	#define SQ_RDMA_HDR_V3_WQE_SIZE_SFT 0
83075 	 * Zero means all 16 bytes are valid. One means only bits 7:0 of
83081 	 * ((inline_length == 0 ) ? 16 : inline_length)
83089 	#define SQ_RDMA_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
83090 	#define SQ_RDMA_HDR_V3_INLINE_LENGTH_SFT 0
83116 	#define SQ_RDMA_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
83117 	#define SQ_RDMA_HDR_V3_TIMESTAMP_SFT 0
83131 	#define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18)
83137 	#define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19)
83142 	 * 0, and the SQ is configured to support Unsignaled
83147 	#define SQ_ATOMIC_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
83152 	#define SQ_ATOMIC_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
83157 	#define SQ_ATOMIC_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
83163 	#define SQ_ATOMIC_V3_FLAGS_SE			UINT32_C(0x8)
83165 	#define SQ_ATOMIC_V3_FLAGS_INLINE		UINT32_C(0x10)
83170 	#define SQ_ATOMIC_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
83175 	#define SQ_ATOMIC_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
83183 	#define SQ_ATOMIC_V3_WQE_SIZE_MASK UINT32_C(0x3f)
83184 	#define SQ_ATOMIC_V3_WQE_SIZE_SFT 0
83251 	#define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18)
83257 	#define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19)
83262 	 * 0, and the SQ is configured to support Unsignaled
83267 	#define SQ_ATOMIC_HDR_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
83272 	#define SQ_ATOMIC_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
83277 	#define SQ_ATOMIC_HDR_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
83283 	#define SQ_ATOMIC_HDR_V3_FLAGS_SE			UINT32_C(0x8)
83285 	#define SQ_ATOMIC_HDR_V3_FLAGS_INLINE		UINT32_C(0x10)
83290 	#define SQ_ATOMIC_HDR_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
83295 	#define SQ_ATOMIC_HDR_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
83303 	#define SQ_ATOMIC_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
83304 	#define SQ_ATOMIC_HDR_V3_WQE_SIZE_SFT 0
83348 	#define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a)
83353 	 * 0, and the SQ is configured to support Unsignaled
83358 	#define SQ_LOCALINVALIDATE_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
83363 	#define SQ_LOCALINVALIDATE_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
83368 	#define SQ_LOCALINVALIDATE_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
83370 	 * This flag is not applicable and should be 0 for a local memory
83373 	#define SQ_LOCALINVALIDATE_V3_FLAGS_SE			UINT32_C(0x8)
83375 	 * This flag is not applicable and should be 0 for a local memory
83378 	#define SQ_LOCALINVALIDATE_V3_FLAGS_INLINE		UINT32_C(0x10)
83380 	 * This flag is not applicable and should be 0 for a local memory
83383 	#define SQ_LOCALINVALIDATE_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
83388 	#define SQ_LOCALINVALIDATE_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
83397 	#define SQ_LOCALINVALIDATE_V3_WQE_SIZE_MASK UINT32_C(0x3f)
83398 	#define SQ_LOCALINVALIDATE_V3_WQE_SIZE_SFT 0
83425 	#define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a)
83430 	 * 0, and the SQ is configured to support Unsignaled
83435 	#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
83440 	#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
83445 	#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
83447 	 * This flag is not applicable and should be 0 for a local memory
83450 	#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SE			UINT32_C(0x8)
83452 	 * This flag is not applicable and should be 0 for a local memory
83455 	#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_INLINE		UINT32_C(0x10)
83457 	 * This flag is not applicable and should be 0 for a local memory
83460 	#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
83465 	#define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
83474 	#define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
83475 	#define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_SFT 0
83507 	#define SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b)
83512 	 * 0, and the SQ is configured to support Unsignaled
83517 	#define SQ_FR_PMR_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
83522 	#define SQ_FR_PMR_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
83527 	#define SQ_FR_PMR_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
83529 	 * This flag is not applicable and should be 0 for a local memory
83532 	#define SQ_FR_PMR_V3_FLAGS_SE			UINT32_C(0x8)
83534 	 * This flag is not applicable and should be 0 for a local memory
83537 	#define SQ_FR_PMR_V3_FLAGS_INLINE		UINT32_C(0x10)
83539 	 * This flag is not applicable and should be 0 for a local memory
83542 	#define SQ_FR_PMR_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
83547 	#define SQ_FR_PMR_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
83555 	#define SQ_FR_PMR_V3_WQE_SIZE_MASK  UINT32_C(0x3f)
83556 	#define SQ_FR_PMR_V3_WQE_SIZE_SFT   0
83561 	#define SQ_FR_PMR_V3_ZERO_BASED	UINT32_C(0x40)
83564 	 * the operation is allowed. '0' means operation is
83569 	#define SQ_FR_PMR_V3_ACCESS_CNTL_LOCAL_WRITE	UINT32_C(0x1)
83571 	#define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_READ	UINT32_C(0x2)
83573 	#define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_WRITE	UINT32_C(0x4)
83575 	#define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_ATOMIC	UINT32_C(0x8)
83577 	#define SQ_FR_PMR_V3_ACCESS_CNTL_WINDOW_BIND	UINT32_C(0x10)
83595 	#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_MASK	UINT32_C(0x1f)
83596 	#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_SFT	0
83598 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4K	UINT32_C(0x0)
83600 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8K	UINT32_C(0x1)
83602 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16K	UINT32_C(0x2)
83604 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32K	UINT32_C(0x3)
83606 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64K	UINT32_C(0x4)
83608 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128K	UINT32_C(0x5)
83610 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256K	UINT32_C(0x6)
83612 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512K	UINT32_C(0x7)
83614 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1M	UINT32_C(0x8)
83616 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2M	UINT32_C(0x9)
83618 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4M	UINT32_C(0xa)
83620 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8M	UINT32_C(0xb)
83622 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16M	UINT32_C(0xc)
83624 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32M	UINT32_C(0xd)
83626 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64M	UINT32_C(0xe)
83628 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128M	UINT32_C(0xf)
83630 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256M	UINT32_C(0x10)
83632 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512M	UINT32_C(0x11)
83634 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1G	UINT32_C(0x12)
83636 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2G	UINT32_C(0x13)
83638 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4G	UINT32_C(0x14)
83640 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8G	UINT32_C(0x15)
83642 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16G	UINT32_C(0x16)
83644 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32G	UINT32_C(0x17)
83646 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64G	UINT32_C(0x18)
83648 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128G	UINT32_C(0x19)
83650 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256G	UINT32_C(0x1a)
83652 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512G	UINT32_C(0x1b)
83654 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1T	UINT32_C(0x1c)
83656 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2T	UINT32_C(0x1d)
83658 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4T	UINT32_C(0x1e)
83660 		#define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T	UINT32_C(0x1f)
83667 	#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_MASK	UINT32_C(0x3e0)
83670 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K	(UINT32_C(0x0) << 5)
83672 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K	(UINT32_C(0x1) << 5)
83674 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K   (UINT32_C(0x2) << 5)
83676 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K   (UINT32_C(0x3) << 5)
83678 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K   (UINT32_C(0x4) << 5)
83680 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K  (UINT32_C(0x5) << 5)
83682 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K  (UINT32_C(0x6) << 5)
83684 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K  (UINT32_C(0x7) << 5)
83686 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M	(UINT32_C(0x8) << 5)
83688 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M	(UINT32_C(0x9) << 5)
83690 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M	(UINT32_C(0xa) << 5)
83692 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M	(UINT32_C(0xb) << 5)
83694 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M   (UINT32_C(0xc) << 5)
83696 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M   (UINT32_C(0xd) << 5)
83698 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M   (UINT32_C(0xe) << 5)
83700 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M  (UINT32_C(0xf) << 5)
83702 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M  (UINT32_C(0x10) << 5)
83704 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M  (UINT32_C(0x11) << 5)
83706 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G	(UINT32_C(0x12) << 5)
83708 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G	(UINT32_C(0x13) << 5)
83710 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G	(UINT32_C(0x14) << 5)
83712 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G	(UINT32_C(0x15) << 5)
83714 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G   (UINT32_C(0x16) << 5)
83716 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G   (UINT32_C(0x17) << 5)
83718 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G   (UINT32_C(0x18) << 5)
83720 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G  (UINT32_C(0x19) << 5)
83722 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G  (UINT32_C(0x1a) << 5)
83724 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G  (UINT32_C(0x1b) << 5)
83726 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T	(UINT32_C(0x1c) << 5)
83728 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T	(UINT32_C(0x1d) << 5)
83730 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T	(UINT32_C(0x1e) << 5)
83732 		#define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T	(UINT32_C(0x1f) << 5)
83735 	#define SQ_FR_PMR_V3_NUMLEVELS_MASK		UINT32_C(0xc00)
83741 		#define SQ_FR_PMR_V3_NUMLEVELS_PHYSICAL	(UINT32_C(0x0) << 10)
83748 		#define SQ_FR_PMR_V3_NUMLEVELS_LAYER1		(UINT32_C(0x1) << 10)
83756 		#define SQ_FR_PMR_V3_NUMLEVELS_LAYER2		(UINT32_C(0x2) << 10)
83778 	#define SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b)
83783 	 * 0, and the SQ is configured to support Unsignaled
83788 	#define SQ_FR_PMR_HDR_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
83793 	#define SQ_FR_PMR_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
83798 	#define SQ_FR_PMR_HDR_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
83800 	 * This flag is not applicable and should be 0 for a local memory
83803 	#define SQ_FR_PMR_HDR_V3_FLAGS_SE			UINT32_C(0x8)
83805 	 * This flag is not applicable and should be 0 for a local memory
83808 	#define SQ_FR_PMR_HDR_V3_FLAGS_INLINE		UINT32_C(0x10)
83810 	 * This flag is not applicable and should be 0 for a local memory
83813 	#define SQ_FR_PMR_HDR_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
83818 	#define SQ_FR_PMR_HDR_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
83826 	#define SQ_FR_PMR_HDR_V3_WQE_SIZE_MASK  UINT32_C(0x3f)
83827 	#define SQ_FR_PMR_HDR_V3_WQE_SIZE_SFT   0
83832 	#define SQ_FR_PMR_HDR_V3_ZERO_BASED	UINT32_C(0x40)
83835 	 * the operation is allowed. '0' means operation is
83840 	#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_LOCAL_WRITE	UINT32_C(0x1)
83842 	#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_READ	UINT32_C(0x2)
83844 	#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_WRITE	UINT32_C(0x4)
83846 	#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC	UINT32_C(0x8)
83848 	#define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_WINDOW_BIND	UINT32_C(0x10)
83866 	#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_MASK	UINT32_C(0x1f)
83867 	#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_SFT	0
83869 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4K	UINT32_C(0x0)
83871 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8K	UINT32_C(0x1)
83873 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16K	UINT32_C(0x2)
83875 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32K	UINT32_C(0x3)
83877 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64K	UINT32_C(0x4)
83879 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128K	UINT32_C(0x5)
83881 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256K	UINT32_C(0x6)
83883 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512K	UINT32_C(0x7)
83885 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1M	UINT32_C(0x8)
83887 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2M	UINT32_C(0x9)
83889 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4M	UINT32_C(0xa)
83891 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8M	UINT32_C(0xb)
83893 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16M	UINT32_C(0xc)
83895 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32M	UINT32_C(0xd)
83897 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64M	UINT32_C(0xe)
83899 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128M	UINT32_C(0xf)
83901 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256M	UINT32_C(0x10)
83903 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512M	UINT32_C(0x11)
83905 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1G	UINT32_C(0x12)
83907 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2G	UINT32_C(0x13)
83909 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4G	UINT32_C(0x14)
83911 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8G	UINT32_C(0x15)
83913 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16G	UINT32_C(0x16)
83915 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32G	UINT32_C(0x17)
83917 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64G	UINT32_C(0x18)
83919 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128G	UINT32_C(0x19)
83921 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256G	UINT32_C(0x1a)
83923 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512G	UINT32_C(0x1b)
83925 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1T	UINT32_C(0x1c)
83927 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2T	UINT32_C(0x1d)
83929 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4T	UINT32_C(0x1e)
83931 		#define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T	UINT32_C(0x1f)
83938 	#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_MASK	UINT32_C(0x3e0)
83941 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K	(UINT32_C(0x0) << 5)
83943 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K	(UINT32_C(0x1) << 5)
83945 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K   (UINT32_C(0x2) << 5)
83947 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K   (UINT32_C(0x3) << 5)
83949 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K   (UINT32_C(0x4) << 5)
83951 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K  (UINT32_C(0x5) << 5)
83953 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K  (UINT32_C(0x6) << 5)
83955 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K  (UINT32_C(0x7) << 5)
83957 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M	(UINT32_C(0x8) << 5)
83959 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M	(UINT32_C(0x9) << 5)
83961 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M	(UINT32_C(0xa) << 5)
83963 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M	(UINT32_C(0xb) << 5)
83965 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M   (UINT32_C(0xc) << 5)
83967 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M   (UINT32_C(0xd) << 5)
83969 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M   (UINT32_C(0xe) << 5)
83971 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M  (UINT32_C(0xf) << 5)
83973 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M  (UINT32_C(0x10) << 5)
83975 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M  (UINT32_C(0x11) << 5)
83977 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G	(UINT32_C(0x12) << 5)
83979 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G	(UINT32_C(0x13) << 5)
83981 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G	(UINT32_C(0x14) << 5)
83983 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G	(UINT32_C(0x15) << 5)
83985 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G   (UINT32_C(0x16) << 5)
83987 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G   (UINT32_C(0x17) << 5)
83989 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G   (UINT32_C(0x18) << 5)
83991 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G  (UINT32_C(0x19) << 5)
83993 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G  (UINT32_C(0x1a) << 5)
83995 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G  (UINT32_C(0x1b) << 5)
83997 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T	(UINT32_C(0x1c) << 5)
83999 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T	(UINT32_C(0x1d) << 5)
84001 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T	(UINT32_C(0x1e) << 5)
84003 		#define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T	(UINT32_C(0x1f) << 5)
84006 	#define SQ_FR_PMR_HDR_V3_NUMLEVELS_MASK		UINT32_C(0xc00)
84012 		#define SQ_FR_PMR_HDR_V3_NUMLEVELS_PHYSICAL	(UINT32_C(0x0) << 10)
84019 		#define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER1		(UINT32_C(0x1) << 10)
84027 		#define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2		(UINT32_C(0x2) << 10)
84053 	#define SQ_BIND_V3_WQE_TYPE_BIND_V3 UINT32_C(0x1c)
84058 	 * 0, and the SQ is configured to support Unsignaled
84063 	#define SQ_BIND_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
84068 	#define SQ_BIND_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
84073 	#define SQ_BIND_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
84075 	 * This flag is not applicable and should be 0 for a local memory
84078 	#define SQ_BIND_V3_FLAGS_SE			UINT32_C(0x8)
84080 	 * This flag is not applicable and should be 0 for a local memory
84083 	#define SQ_BIND_V3_FLAGS_INLINE		UINT32_C(0x10)
84085 	 * This flag is not applicable and should be 0 for a local memory
84088 	#define SQ_BIND_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
84093 	#define SQ_BIND_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
84100 	#define SQ_BIND_V3_WQE_SIZE_MASK  UINT32_C(0x3f)
84101 	#define SQ_BIND_V3_WQE_SIZE_SFT   0
84107 	#define SQ_BIND_V3_ZERO_BASED	UINT32_C(0x40)
84127 	#define SQ_BIND_V3_MW_TYPE	UINT32_C(0x80)
84129 		#define SQ_BIND_V3__TYPE1	(UINT32_C(0x0) << 7)
84131 		#define SQ_BIND_V3__TYPE2	(UINT32_C(0x1) << 7)
84135 	 * the operation is allowed. '0' means operation is
84146 	#define SQ_BIND_V3_ACCESS_CNTL_LOCAL_WRITE	UINT32_C(0x1)
84148 	#define SQ_BIND_V3_ACCESS_CNTL_REMOTE_READ	UINT32_C(0x2)
84156 	#define SQ_BIND_V3_ACCESS_CNTL_REMOTE_WRITE	UINT32_C(0x4)
84164 	#define SQ_BIND_V3_ACCESS_CNTL_REMOTE_ATOMIC	UINT32_C(0x8)
84172 	#define SQ_BIND_V3_ACCESS_CNTL_WINDOW_BIND	UINT32_C(0x10)
84214 	#define SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3 UINT32_C(0x1c)
84219 	 * 0, and the SQ is configured to support Unsignaled
84224 	#define SQ_BIND_HDR_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
84229 	#define SQ_BIND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
84234 	#define SQ_BIND_HDR_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
84236 	 * This flag is not applicable and should be 0 for a local memory
84239 	#define SQ_BIND_HDR_V3_FLAGS_SE			UINT32_C(0x8)
84241 	 * This flag is not applicable and should be 0 for a local memory
84244 	#define SQ_BIND_HDR_V3_FLAGS_INLINE		UINT32_C(0x10)
84246 	 * This flag is not applicable and should be 0 for a local memory
84249 	#define SQ_BIND_HDR_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
84254 	#define SQ_BIND_HDR_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
84261 	#define SQ_BIND_HDR_V3_WQE_SIZE_MASK  UINT32_C(0x3f)
84262 	#define SQ_BIND_HDR_V3_WQE_SIZE_SFT   0
84268 	#define SQ_BIND_HDR_V3_ZERO_BASED	UINT32_C(0x40)
84288 	#define SQ_BIND_HDR_V3_MW_TYPE	UINT32_C(0x80)
84290 		#define SQ_BIND_HDR_V3__TYPE1	(UINT32_C(0x0) << 7)
84292 		#define SQ_BIND_HDR_V3__TYPE2	(UINT32_C(0x1) << 7)
84296 	 * the operation is allowed. '0' means operation is
84307 	#define SQ_BIND_HDR_V3_ACCESS_CNTL_LOCAL_WRITE	UINT32_C(0x1)
84309 	#define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_READ	UINT32_C(0x2)
84317 	#define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_WRITE	UINT32_C(0x4)
84325 	#define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC	UINT32_C(0x8)
84333 	#define SQ_BIND_HDR_V3_ACCESS_CNTL_WINDOW_BIND	UINT32_C(0x10)
84373 	#define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e)
84378 	 * 0, and the SQ is configured to support Unsignaled
84383 	#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
84388 	#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
84396 	#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
84398 	 * This flag is not applicable and should be 0 for a local memory
84401 	#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SE			UINT32_C(0x8)
84403 	 * This flag is not applicable and should be 0 for a local memory
84406 	#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_INLINE		UINT32_C(0x10)
84408 	 * This flag is not applicable and should be 0 for a local memory
84411 	#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
84416 	#define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
84424 	#define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_MASK UINT32_C(0x3f)
84425 	#define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_SFT 0
84445 	#define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e)
84450 	 * 0, and the SQ is configured to support Unsignaled
84455 	#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SIGNAL_COMP		UINT32_C(0x1)
84460 	#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE	UINT32_C(0x2)
84468 	#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_UC_FENCE		UINT32_C(0x4)
84470 	 * This flag is not applicable and should be 0 for a local memory
84473 	#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SE			UINT32_C(0x8)
84475 	 * This flag is not applicable and should be 0 for a local memory
84478 	#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_INLINE		UINT32_C(0x10)
84480 	 * This flag is not applicable and should be 0 for a local memory
84483 	#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_WQE_TS_EN		UINT32_C(0x20)
84488 	#define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_DEBUG_TRACE		UINT32_C(0x40)
84496 	#define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
84497 	#define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_SFT 0
84520 	#define RQ_WQE_WQE_TYPE_RCV UINT32_C(0x80)
84541 	#define RQ_WQE_WR_ID_MASK UINT32_C(0xfffff)
84542 	#define RQ_WQE_WR_ID_SFT 0
84561 	#define RQ_WQE_HDR_WQE_TYPE_RCV UINT32_C(0x80)
84582 	#define RQ_WQE_HDR_WR_ID_MASK UINT32_C(0xfffff)
84583 	#define RQ_WQE_HDR_WR_ID_SFT 0
84597 	#define RQ_WQE_V3_WQE_TYPE_RCV_V3 UINT32_C(0x90)
84629 	#define RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3 UINT32_C(0x90)
84658 	#define CQ_BASE_TOGGLE			UINT32_C(0x1)
84660 	#define CQ_BASE_CQE_TYPE_MASK		UINT32_C(0x1e)
84666 		#define CQ_BASE_CQE_TYPE_REQ		(UINT32_C(0x0) << 1)
84671 		#define CQ_BASE_CQE_TYPE_RES_RC		(UINT32_C(0x1) << 1)
84676 		#define CQ_BASE_CQE_TYPE_RES_UD		(UINT32_C(0x2) << 1)
84681 		#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1	(UINT32_C(0x3) << 1)
84687 		#define CQ_BASE_CQE_TYPE_RES_UD_CFA	(UINT32_C(0x4) << 1)
84692 		#define CQ_BASE_CQE_TYPE_REQ_V3		(UINT32_C(0x8) << 1)
84697 		#define CQ_BASE_CQE_TYPE_RES_RC_V3	(UINT32_C(0x9) << 1)
84703 		#define CQ_BASE_CQE_TYPE_RES_UD_V3	(UINT32_C(0xa) << 1)
84709 		#define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3  (UINT32_C(0xb) << 1)
84716 		#define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3	(UINT32_C(0xc) << 1)
84721 		#define CQ_BASE_CQE_TYPE_NO_OP		(UINT32_C(0xd) << 1)
84726 		#define CQ_BASE_CQE_TYPE_TERMINAL	(UINT32_C(0xe) << 1)
84732 		#define CQ_BASE_CQE_TYPE_CUT_OFF		(UINT32_C(0xf) << 1)
84737 	#define CQ_BASE_STATUS_OK			UINT32_C(0x0)
84744 	#define CQ_BASE_STATUS_BAD_RESPONSE_ERR	UINT32_C(0x1)
84758 	#define CQ_BASE_STATUS_LOCAL_LENGTH_ERR	UINT32_C(0x2)
84765 	#define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR	UINT32_C(0x3)
84775 	#define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR	UINT32_C(0x4)
84785 	#define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x5)
84794 	#define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR	UINT32_C(0x6)
84801 	#define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR   UINT32_C(0x7)
84812 	#define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8)
84822 	#define CQ_BASE_STATUS_REMOTE_ACCESS_ERR	UINT32_C(0x9)
84832 	#define CQ_BASE_STATUS_REMOTE_OPERATION_ERR	UINT32_C(0xa)
84839 	#define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR	UINT32_C(0xb)
84846 	#define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR	UINT32_C(0xc)
84851 	#define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR   UINT32_C(0xd)
84857 	#define CQ_BASE_STATUS_HW_FLUSH_ERR		UINT32_C(0xe)
84863 	#define CQ_BASE_STATUS_OVERFLOW_ERR		UINT32_C(0xf)
84885 	 * QPC.sq_size (i.e. the valid range of the SQ Consumer Index is 0
84898 	#define CQ_REQ_TOGGLE	UINT32_C(0x1)
84900 	#define CQ_REQ_CQE_TYPE_MASK UINT32_C(0x1e)
84906 		#define CQ_REQ_CQE_TYPE_REQ   (UINT32_C(0x0) << 1)
84911 	 * the driver. When this bit is '0', it indicates that the packet
84918 	#define CQ_REQ_PUSH	UINT32_C(0x20)
84921 	/* OK is 0 */
84922 	#define CQ_REQ_STATUS_OK			UINT32_C(0x0)
84924 	#define CQ_REQ_STATUS_BAD_RESPONSE_ERR	UINT32_C(0x1)
84926 	#define CQ_REQ_STATUS_LOCAL_LENGTH_ERR	UINT32_C(0x2)
84928 	#define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR	UINT32_C(0x3)
84930 	#define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x4)
84932 	#define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR   UINT32_C(0x5)
84934 	#define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6)
84936 	#define CQ_REQ_STATUS_REMOTE_ACCESS_ERR	UINT32_C(0x7)
84938 	#define CQ_REQ_STATUS_REMOTE_OPERATION_ERR	UINT32_C(0x8)
84940 	#define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR	UINT32_C(0x9)
84942 	#define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR	UINT32_C(0xa)
84944 	#define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR   UINT32_C(0xb)
84983 	#define CQ_RES_RC_TOGGLE	UINT32_C(0x1)
84985 	#define CQ_RES_RC_CQE_TYPE_MASK  UINT32_C(0x1e)
84991 		#define CQ_RES_RC_CQE_TYPE_RES_RC  (UINT32_C(0x1) << 1)
84995 	/* OK is 0 */
84996 	#define CQ_RES_RC_STATUS_OK			UINT32_C(0x0)
84998 	#define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR	UINT32_C(0x1)
85000 	#define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR	UINT32_C(0x2)
85002 	#define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x3)
85004 	#define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR	UINT32_C(0x4)
85006 	#define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR   UINT32_C(0x5)
85008 	#define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6)
85010 	#define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR   UINT32_C(0x7)
85012 	#define CQ_RES_RC_STATUS_HW_FLUSH_ERR		UINT32_C(0x8)
85019 	#define CQ_RES_RC_FLAGS_SRQ		UINT32_C(0x1)
85021 		#define CQ_RES_RC_FLAGS_SRQ_RQ	UINT32_C(0x0)
85023 		#define CQ_RES_RC_FLAGS_SRQ_SRQ	UINT32_C(0x1)
85026 	#define CQ_RES_RC_FLAGS_IMM		UINT32_C(0x2)
85028 	#define CQ_RES_RC_FLAGS_INV		UINT32_C(0x4)
85029 	#define CQ_RES_RC_FLAGS_RDMA	UINT32_C(0x8)
85031 		#define CQ_RES_RC_FLAGS_RDMA_SEND	(UINT32_C(0x0) << 3)
85033 		#define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE  (UINT32_C(0x1) << 3)
85041 	#define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
85042 	#define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0
85054 	#define CQ_RES_UD_LENGTH_MASK UINT32_C(0x3fff)
85055 	#define CQ_RES_UD_LENGTH_SFT 0
85062 	#define CQ_RES_UD_CFA_METADATA_VID_MASK UINT32_C(0xfff)
85063 	#define CQ_RES_UD_CFA_METADATA_VID_SFT 0
85065 	#define CQ_RES_UD_CFA_METADATA_DE	UINT32_C(0x1000)
85067 	#define CQ_RES_UD_CFA_METADATA_PRI_MASK UINT32_C(0xe000)
85089 	#define CQ_RES_UD_TOGGLE	UINT32_C(0x1)
85091 	#define CQ_RES_UD_CQE_TYPE_MASK  UINT32_C(0x1e)
85097 		#define CQ_RES_UD_CQE_TYPE_RES_UD  (UINT32_C(0x2) << 1)
85105 	#define CQ_RES_UD_STATUS_OK			UINT32_C(0x0)
85113 	#define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR	UINT32_C(0x1)
85120 	#define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR	UINT32_C(0x2)
85122 	#define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x3)
85124 	#define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR   UINT32_C(0x4)
85126 	#define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
85128 	#define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
85130 	#define CQ_RES_UD_STATUS_HW_FLUSH_ERR		UINT32_C(0x8)
85137 	#define CQ_RES_UD_FLAGS_SRQ		UINT32_C(0x1)
85139 		#define CQ_RES_UD_FLAGS_SRQ_RQ		UINT32_C(0x0)
85141 		#define CQ_RES_UD_FLAGS_SRQ_SRQ		UINT32_C(0x1)
85144 	#define CQ_RES_UD_FLAGS_IMM		UINT32_C(0x2)
85145 	#define CQ_RES_UD_FLAGS_UNUSED_MASK	UINT32_C(0xc)
85147 	#define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK	UINT32_C(0x30)
85150 		#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1	(UINT32_C(0x0) << 4)
85152 		#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4	(UINT32_C(0x2) << 4)
85154 		#define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6	(UINT32_C(0x3) << 4)
85160 	#define CQ_RES_UD_FLAGS_META_FORMAT_MASK	UINT32_C(0x3c0)
85163 		#define CQ_RES_UD_FLAGS_META_FORMAT_NONE	(UINT32_C(0x0) << 6)
85166 	 * - metadata[11:0] contains the vlan VID value.
85170 		#define CQ_RES_UD_FLAGS_META_FORMAT_VLAN	(UINT32_C(0x1) << 6)
85175 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
85176 	 * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier.
85177 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
85178 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
85179 	 * - IPV4 = 0 (not populated)
85180 	 * - IPV6 = Flow Label[19:0]
85181 	 * - PPPoE = sessionID[15:0]
85182 	 * - MPLs = Outer label[19:0]
85183 	 * - UPAR = Selected[31:0] with bit mask
85185 		#define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID   (UINT32_C(0x2) << 6)
85190 		#define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA   (UINT32_C(0x3) << 6)
85194 	 * - metadata[8:0] contains the outer_l3_offset.
85195 	 * - metadata[15:9] contains the inner_l2_offset[6:0]
85197 		#define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET  (UINT32_C(0x4) << 6)
85203 	#define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK  UINT32_C(0xc00)
85211 	#define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
85212 	#define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0
85214 	#define CQ_RES_UD_SRC_QP_HIGH_MASK	UINT32_C(0xff000000)
85227 	#define CQ_RES_UD_V2_LENGTH_MASK UINT32_C(0x3fff)
85228 	#define CQ_RES_UD_V2_LENGTH_SFT 0
85232 	#define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
85233 	#define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0
85235 	#define CQ_RES_UD_V2_CFA_METADATA0_DE	UINT32_C(0x1000)
85237 	#define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
85259 	#define CQ_RES_UD_V2_TOGGLE	UINT32_C(0x1)
85261 	#define CQ_RES_UD_V2_CQE_TYPE_MASK  UINT32_C(0x1e)
85267 		#define CQ_RES_UD_V2_CQE_TYPE_RES_UD  (UINT32_C(0x2) << 1)
85275 	#define CQ_RES_UD_V2_STATUS_OK			UINT32_C(0x0)
85283 	#define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR	UINT32_C(0x1)
85290 	#define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR	UINT32_C(0x2)
85292 	#define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x3)
85294 	#define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR   UINT32_C(0x4)
85296 	#define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
85298 	#define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
85300 	#define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR		UINT32_C(0x8)
85307 	#define CQ_RES_UD_V2_FLAGS_SRQ			UINT32_C(0x1)
85309 		#define CQ_RES_UD_V2_FLAGS_SRQ_RQ		UINT32_C(0x0)
85311 		#define CQ_RES_UD_V2_FLAGS_SRQ_SRQ		UINT32_C(0x1)
85314 	#define CQ_RES_UD_V2_FLAGS_IMM			UINT32_C(0x2)
85315 	#define CQ_RES_UD_V2_FLAGS_UNUSED_MASK		UINT32_C(0xc)
85317 	#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK	UINT32_C(0x30)
85320 		#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1	(UINT32_C(0x0) << 4)
85322 		#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4	(UINT32_C(0x2) << 4)
85324 		#define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6	(UINT32_C(0x3) << 4)
85327 	#define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK	UINT32_C(0x3c0)
85330 		#define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE	(UINT32_C(0x0) << 6)
85333 	 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
85334 	 * de, vid[11:0]} The metadata2 field contains the table scope
85335 	 * and action record pointer. - metadata2[25:0] contains the
85339 		#define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR  (UINT32_C(0x1) << 6)
85343 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
85346 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
85347 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
85348 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
85349 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
85350 	 * - IPv4 = 0 (not populated)
85351 	 * - IPv6 = Flow Label[19:0]
85352 	 * - PPPoE = sessionID[15:0]
85353 	 * - MPLs = Outer label[19:0]
85354 	 * - UPAR = Selected[31:0] with bit mask
85356 		#define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 6)
85360 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
85364 		#define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 6)
85368 	 * - metadata[8:0] contains the outer_l3_offset.
85369 	 * - metadata[15:9] contains the inner_l2_offset[6:0]
85371 		#define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET   (UINT32_C(0x4) << 6)
85379 	#define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK	UINT32_C(0xfffff)
85380 	#define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT		0
85381 	#define CQ_RES_UD_V2_CFA_METADATA1_MASK		UINT32_C(0xf00000)
85383 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
85384 	#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK	UINT32_C(0x700000)
85386 	/* 0x88a8 */
85387 		#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8   (UINT32_C(0x0) << 20)
85388 	/* 0x8100 */
85389 		#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100   (UINT32_C(0x1) << 20)
85390 	/* 0x9100 */
85391 		#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100   (UINT32_C(0x2) << 20)
85392 	/* 0x9200 */
85393 		#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200   (UINT32_C(0x3) << 20)
85394 	/* 0x9300 */
85395 		#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300   (UINT32_C(0x4) << 20)
85397 		#define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG	(UINT32_C(0x5) << 20)
85399 	/* When meta_format != 0, this value is the VLAN valid. */
85400 	#define CQ_RES_UD_V2_CFA_METADATA1_VALID		UINT32_C(0x800000)
85402 	#define CQ_RES_UD_V2_SRC_QP_HIGH_MASK		UINT32_C(0xff000000)
85415 	#define CQ_RES_UD_CFA_LENGTH_MASK UINT32_C(0x3fff)
85416 	#define CQ_RES_UD_CFA_LENGTH_SFT 0
85430 	#define CQ_RES_UD_CFA_QID_MASK UINT32_C(0xfffff)
85431 	#define CQ_RES_UD_CFA_QID_SFT 0
85438 	#define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK UINT32_C(0xfff)
85439 	#define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT  0
85441 	#define CQ_RES_UD_CFA_CFA_METADATA_DE	UINT32_C(0x1000)
85443 	#define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK UINT32_C(0xe000)
85446 	#define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK UINT32_C(0xffff0000)
85461 	#define CQ_RES_UD_CFA_TOGGLE		UINT32_C(0x1)
85463 	#define CQ_RES_UD_CFA_CQE_TYPE_MASK	UINT32_C(0x1e)
85471 		#define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA  (UINT32_C(0x4) << 1)
85479 	#define CQ_RES_UD_CFA_STATUS_OK			UINT32_C(0x0)
85487 	#define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR	UINT32_C(0x1)
85494 	#define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR	UINT32_C(0x2)
85496 	#define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x3)
85498 	#define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR   UINT32_C(0x4)
85500 	#define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
85502 	#define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
85504 	#define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR		UINT32_C(0x8)
85511 	#define CQ_RES_UD_CFA_FLAGS_SRQ		UINT32_C(0x1)
85513 		#define CQ_RES_UD_CFA_FLAGS_SRQ_RQ		UINT32_C(0x0)
85515 		#define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ		UINT32_C(0x1)
85518 	#define CQ_RES_UD_CFA_FLAGS_IMM		UINT32_C(0x2)
85519 	#define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK	UINT32_C(0xc)
85521 	#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK	UINT32_C(0x30)
85524 		#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1	(UINT32_C(0x0) << 4)
85526 		#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4	(UINT32_C(0x2) << 4)
85528 		#define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6	(UINT32_C(0x3) << 4)
85534 	#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK	UINT32_C(0x3c0)
85537 	 * If ext_meta_format is equal to 0, there is no metadata
85540 		#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE	(UINT32_C(0x0) << 6)
85542 	 * If ext_meta_format is equal to 0, the metadata field contains
85544 	 * - metadata[11:0] contains the vlan VID value.
85549 		#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN	(UINT32_C(0x1) << 6)
85553 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
85554 	 * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier
85555 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
85556 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
85557 	 * - IPV4 = 0 (not populated)
85558 	 * - IPV6 = Flow Label[19:0]
85559 	 * - PPPoE = sessionID[15:0]
85560 	 * - MPLs = Outer label[19:0]
85561 	 * - UPAR = Selected[31:0] with bit mask
85563 		#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID   (UINT32_C(0x2) << 6)
85568 		#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA   (UINT32_C(0x3) << 6)
85573 	 * - metadata[8:0] contains the outer_l3_offset.
85578 		#define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET  (UINT32_C(0x4) << 6)
85584 	#define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK  UINT32_C(0xc00)
85592 	#define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
85593 	#define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0
85595 	#define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK	UINT32_C(0xff000000)
85608 	#define CQ_RES_UD_CFA_V2_LENGTH_MASK UINT32_C(0x3fff)
85609 	#define CQ_RES_UD_CFA_V2_LENGTH_SFT 0
85613 	#define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
85614 	#define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0
85616 	#define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE	UINT32_C(0x1000)
85618 	#define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
85628 	#define CQ_RES_UD_CFA_V2_QID_MASK UINT32_C(0xfffff)
85629 	#define CQ_RES_UD_CFA_V2_QID_SFT 0
85633 	 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
85634 	 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
85635 	 *   act_rec_ptr[25:0]}
85636 	 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
85637 	 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
85638 	 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
85656 	#define CQ_RES_UD_CFA_V2_TOGGLE		UINT32_C(0x1)
85658 	#define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK	UINT32_C(0x1e)
85666 		#define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA  (UINT32_C(0x4) << 1)
85674 	#define CQ_RES_UD_CFA_V2_STATUS_OK			UINT32_C(0x0)
85682 	#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR	UINT32_C(0x1)
85689 	#define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR	UINT32_C(0x2)
85691 	#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x3)
85693 	#define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR   UINT32_C(0x4)
85695 	#define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
85697 	#define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
85699 	#define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR		UINT32_C(0x8)
85706 	#define CQ_RES_UD_CFA_V2_FLAGS_SRQ			UINT32_C(0x1)
85708 		#define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ		UINT32_C(0x0)
85710 		#define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ		UINT32_C(0x1)
85713 	#define CQ_RES_UD_CFA_V2_FLAGS_IMM			UINT32_C(0x2)
85714 	#define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK		UINT32_C(0xc)
85716 	#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK	UINT32_C(0x30)
85719 		#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1	(UINT32_C(0x0) << 4)
85721 		#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4	(UINT32_C(0x2) << 4)
85723 		#define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6	(UINT32_C(0x3) << 4)
85726 	#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK	UINT32_C(0x3c0)
85729 		#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE	(UINT32_C(0x0) << 6)
85732 	 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
85733 	 * de, vid[11:0]} The metadata2 field contains the table scope
85734 	 * and action record pointer. - metadata2[25:0] contains the
85738 		#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR  (UINT32_C(0x1) << 6)
85742 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
85745 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
85746 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
85747 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
85748 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
85749 	 * - IPv4 = 0 (not populated)
85750 	 * - IPv6 = Flow Label[19:0]
85751 	 * - PPPoE = sessionID[15:0]
85752 	 * - MPLs = Outer label[19:0]
85753 	 * - UPAR = Selected[31:0] with bit mask
85755 		#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 6)
85759 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
85763 		#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 6)
85767 	 * - metadata[8:0] contains the outer_l3_offset.
85768 	 * - metadata[15:9] contains the inner_l2_offset[6:0]
85770 		#define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET   (UINT32_C(0x4) << 6)
85778 	#define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK	UINT32_C(0xfffff)
85779 	#define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT		0
85780 	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK		UINT32_C(0xf00000)
85782 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
85783 	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK	UINT32_C(0x700000)
85785 	/* 0x88a8 */
85786 		#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8   (UINT32_C(0x0) << 20)
85787 	/* 0x8100 */
85788 		#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100   (UINT32_C(0x1) << 20)
85789 	/* 0x9100 */
85790 		#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100   (UINT32_C(0x2) << 20)
85791 	/* 0x9200 */
85792 		#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200   (UINT32_C(0x3) << 20)
85793 	/* 0x9300 */
85794 		#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300   (UINT32_C(0x4) << 20)
85796 		#define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG	(UINT32_C(0x5) << 20)
85798 	/* When meta_format != 0, this value is the VLAN valid. */
85799 	#define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID		UINT32_C(0x800000)
85801 	#define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK		UINT32_C(0xff000000)
85814 	#define CQ_RES_RAWETH_QP1_LENGTH_MASK UINT32_C(0x3fff)
85815 	#define CQ_RES_RAWETH_QP1_LENGTH_SFT 0
85817 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK		UINT32_C(0x3ff)
85818 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT		0
85824 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR		UINT32_C(0x1)
85829 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK		UINT32_C(0x3c0)
85835 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN	(UINT32_C(0x0) << 6)
85841 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP		(UINT32_C(0x1) << 6)
85848 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP		(UINT32_C(0x2) << 6)
85855 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP		(UINT32_C(0x3) << 6)
85862 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE		(UINT32_C(0x4) << 6)
85869 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE		(UINT32_C(0x5) << 6)
85876 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP		(UINT32_C(0x7) << 6)
85882 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP   (UINT32_C(0x8) << 6)
85888 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP	(UINT32_C(0x9) << 6)
85895 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR			UINT32_C(0x10)
85900 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR			UINT32_C(0x20)
85905 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR			UINT32_C(0x40)
85910 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR			UINT32_C(0x80)
85915 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR			UINT32_C(0x100)
85921 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK		UINT32_C(0xe00)
85927 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 9)
85933 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	(UINT32_C(0x1) << 9)
85939 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	(UINT32_C(0x2) << 9)
85945 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR	(UINT32_C(0x3) << 9)
85951 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	(UINT32_C(0x4) << 9)
85957 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	(UINT32_C(0x5) << 9)
85960 	 * have failed (e.g. TTL = 0) in the tunnel header. Valid
85963 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL		(UINT32_C(0x6) << 9)
85970 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK			UINT32_C(0xf000)
85976 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 12)
85983 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION		(UINT32_C(0x1) << 12)
85988 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN		(UINT32_C(0x2) << 12)
85991 	 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
85993 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL		(UINT32_C(0x3) << 12)
85999 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR		(UINT32_C(0x4) << 12)
86005 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR	(UINT32_C(0x5) << 12)
86010 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN		(UINT32_C(0x6) << 12)
86012 …#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL  (UINT32_C(0x7) << …
86018 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN		(UINT32_C(0x8) << 12)
86036 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC		UINT32_C(0x1)
86042 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC		UINT32_C(0x2)
86048 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC		UINT32_C(0x4)
86054 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC		UINT32_C(0x8)
86059 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK	UINT32_C(0xf0)
86062 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE		(UINT32_C(0x0) << 4)
86066 	 * - raweth_qp1_metadata[11:0] contains the vlan VID value.
86071 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN		(UINT32_C(0x1) << 4)
86076 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
86077 	 * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier.
86078 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
86079 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
86080 	 * - IPV4 = 0 (not populated)
86081 	 * - IPV6 = Flow Label[19:0]
86082 	 * - PPPoE = sessionID[15:0]
86083 	 * - MPLs = Outer label[19:0]
86084 	 * - UPAR = Selected[31:0] with bit mask
86086 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 4)
86091 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 4)
86095 	 * - metadata[8:0] contains the outer_l3_offset.
86096 	 * - metadata[15:9] contains the inner_l2_offset[6:0]
86098 		#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET	(UINT32_C(0x4) << 4)
86102 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
86106 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE			UINT32_C(0x100)
86111 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC	UINT32_C(0x200)
86116 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK	UINT32_C(0xc00)
86124 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK	UINT32_C(0xffff0000)
86131 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK	UINT32_C(0xffff)
86132 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT	0
86134 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK	UINT32_C(0xfff)
86135 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT		0
86137 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE		UINT32_C(0x1000)
86139 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK	UINT32_C(0xe000)
86142 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK	UINT32_C(0xffff0000)
86150 	#define CQ_RES_RAWETH_QP1_TOGGLE		UINT32_C(0x1)
86152 	#define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK	UINT32_C(0x1e)
86158 		#define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1  (UINT32_C(0x3) << 1)
86166 	#define CQ_RES_RAWETH_QP1_STATUS_OK			UINT32_C(0x0)
86174 	#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR	UINT32_C(0x1)
86181 	#define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR	UINT32_C(0x2)
86183 	#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x3)
86185 	#define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR   UINT32_C(0x4)
86187 	#define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
86189 	#define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
86191 	#define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR		UINT32_C(0x8)
86198 	#define CQ_RES_RAWETH_QP1_FLAGS_SRQ	UINT32_C(0x1)
86200 		#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ	UINT32_C(0x0)
86202 		#define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ   UINT32_C(0x1)
86210 	#define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK	UINT32_C(0xfffff)
86211 	#define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT	0
86218 	#define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000)
86231 	#define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK UINT32_C(0x3fff)
86232 	#define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0
86234 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK		UINT32_C(0x3ff)
86235 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT		0
86241 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR		UINT32_C(0x1)
86246 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK		UINT32_C(0x3c0)
86252 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN	(UINT32_C(0x0) << 6)
86258 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP		(UINT32_C(0x1) << 6)
86265 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP		(UINT32_C(0x2) << 6)
86272 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP		(UINT32_C(0x3) << 6)
86279 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE		(UINT32_C(0x4) << 6)
86286 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE		(UINT32_C(0x5) << 6)
86293 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP		(UINT32_C(0x7) << 6)
86299 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP   (UINT32_C(0x8) << 6)
86305 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP	(UINT32_C(0x9) << 6)
86312 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR			UINT32_C(0x10)
86317 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR			UINT32_C(0x20)
86322 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR			UINT32_C(0x40)
86327 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR			UINT32_C(0x80)
86332 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR			UINT32_C(0x100)
86338 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK		UINT32_C(0xe00)
86344 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 9)
86350 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	(UINT32_C(0x1) << 9)
86356 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	(UINT32_C(0x2) << 9)
86362 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR	(UINT32_C(0x3) << 9)
86368 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	(UINT32_C(0x4) << 9)
86374 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	(UINT32_C(0x5) << 9)
86377 	 * have failed (e.g. TTL = 0) in the tunnel header. Valid
86380 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL		(UINT32_C(0x6) << 9)
86387 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK			UINT32_C(0xf000)
86393 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 12)
86400 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION		(UINT32_C(0x1) << 12)
86405 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN		(UINT32_C(0x2) << 12)
86408 	 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
86410 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL		(UINT32_C(0x3) << 12)
86416 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR		(UINT32_C(0x4) << 12)
86422 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR	(UINT32_C(0x5) << 12)
86427 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN		(UINT32_C(0x6) << 12)
86429 …#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL  (UINT32_C(0x7) …
86435 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN		(UINT32_C(0x8) << 12)
86440 	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
86441 	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0
86443 	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE	UINT32_C(0x1000)
86445 	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
86454 	 * When this bit is '0', the cs_ok field has the following
86455 	 * definition:- ip_cs_ok[2:0] = The number of header groups with a
86462 	 * field has the following definition: - hdr_cnt[2:0] = The number of
86469 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE		UINT32_C(0x8)
86471 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK	UINT32_C(0xf0)
86474 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE		(UINT32_C(0x0) << 4)
86477 	 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
86478 	 * de, vid[11:0]} The metadata2 field contains the table scope
86479 	 * and action record pointer. - metadata2[25:0] contains the
86483 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR	(UINT32_C(0x1) << 4)
86487 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
86490 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
86491 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
86492 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
86493 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
86494 	 * - IPv4 = 0 (not populated)
86495 	 * - IPv6 = Flow Label[19:0]
86496 	 * - PPPoE = sessionID[15:0]
86497 	 * - MPLs = Outer label[19:0]
86498 	 * - UPAR = Selected[31:0] with bit mask
86500 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 4)
86504 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
86508 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 4)
86512 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
86515 	 * - metadata2[8:0] contains the outer_l3_offset.
86520 		#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET	(UINT32_C(0x4) << 4)
86524 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
86528 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE			UINT32_C(0x100)
86533 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC	UINT32_C(0x200)
86539 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK		UINT32_C(0xfc00)
86547 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK	UINT32_C(0xffff0000)
86552 	 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
86553 	 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
86554 	 *   act_rec_ptr[25:0]}
86555 	 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
86556 	 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
86557 	 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
86568 	#define CQ_RES_RAWETH_QP1_V2_TOGGLE		UINT32_C(0x1)
86570 	#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK	UINT32_C(0x1e)
86576 		#define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1  (UINT32_C(0x3) << 1)
86584 	#define CQ_RES_RAWETH_QP1_V2_STATUS_OK			UINT32_C(0x0)
86592 	#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR	UINT32_C(0x1)
86599 	#define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR	UINT32_C(0x2)
86601 	#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x3)
86603 	#define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR   UINT32_C(0x4)
86605 	#define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
86607 	#define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
86609 	#define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR		UINT32_C(0x8)
86616 	#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ	UINT32_C(0x1)
86618 		#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ	UINT32_C(0x0)
86620 		#define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ   UINT32_C(0x1)
86628 	#define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK	UINT32_C(0xfffff)
86629 	#define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT		0
86630 	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK		UINT32_C(0xf00000)
86632 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
86633 	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK	UINT32_C(0x700000)
86635 	/* 0x88a8 */
86636 		#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8   (UINT32_C(0x0) << 20)
86637 	/* 0x8100 */
86638 		#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100   (UINT32_C(0x1) << 20)
86639 	/* 0x9100 */
86640 		#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100   (UINT32_C(0x2) << 20)
86641 	/* 0x9200 */
86642 		#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200   (UINT32_C(0x3) << 20)
86643 	/* 0x9300 */
86644 		#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300   (UINT32_C(0x4) << 20)
86646 		#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG	(UINT32_C(0x5) << 20)
86648 	/* When meta_format != 0, this value is the VLAN valid. */
86649 	#define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID		UINT32_C(0x800000)
86657 	#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000)
86691 	#define CQ_TERMINAL_TOGGLE	UINT32_C(0x1)
86693 	#define CQ_TERMINAL_CQE_TYPE_MASK	UINT32_C(0x1e)
86699 		#define CQ_TERMINAL_CQE_TYPE_TERMINAL  (UINT32_C(0xe) << 1)
86704 	#define CQ_TERMINAL_STATUS_OK UINT32_C(0x0)
86723 	#define CQ_CUTOFF_TOGGLE		UINT32_C(0x1)
86725 	#define CQ_CUTOFF_CQE_TYPE_MASK	UINT32_C(0x1e)
86728 		#define CQ_CUTOFF_CQE_TYPE_CUT_OFF	(UINT32_C(0xf) << 1)
86744 	#define CQ_CUTOFF_RESIZE_TOGGLE_MASK UINT32_C(0x60)
86749 	#define CQ_CUTOFF_STATUS_OK UINT32_C(0x0)
86768 	#define CQ_NO_OP_TOGGLE	UINT32_C(0x1)
86770 	#define CQ_NO_OP_CQE_TYPE_MASK UINT32_C(0x1e)
86776 		#define CQ_NO_OP_CQE_TYPE_NO_OP  (UINT32_C(0xd) << 1)
86781 	#define CQ_NO_OP_STATUS_OK UINT32_C(0x0)
86805 	 * (i.e. the valid range of the SQ Consumer Index is 0 to
86824 	#define CQ_REQ_V3_TOGGLE	UINT32_C(0x1)
86826 	#define CQ_REQ_V3_CQE_TYPE_MASK  UINT32_C(0x1e)
86832 		#define CQ_REQ_V3_CQE_TYPE_REQ_V3  (UINT32_C(0x8) << 1)
86837 	 * the driver. When this bit is '0', it indicates that the packet
86845 	#define CQ_REQ_V3_PUSH	UINT32_C(0x20)
86849 	#define CQ_REQ_V3_STATUS_OK			UINT32_C(0x0)
86856 	#define CQ_REQ_V3_STATUS_BAD_RESPONSE_ERR	UINT32_C(0x1)
86870 	#define CQ_REQ_V3_STATUS_LOCAL_LENGTH_ERR	UINT32_C(0x2)
86880 	#define CQ_REQ_V3_STATUS_LOCAL_QP_OPERATION_ERR	UINT32_C(0x4)
86890 	#define CQ_REQ_V3_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x5)
86897 	#define CQ_REQ_V3_STATUS_MEMORY_MGT_OPERATION_ERR   UINT32_C(0x7)
86908 	#define CQ_REQ_V3_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8)
86918 	#define CQ_REQ_V3_STATUS_REMOTE_ACCESS_ERR	UINT32_C(0x9)
86928 	#define CQ_REQ_V3_STATUS_REMOTE_OPERATION_ERR	UINT32_C(0xa)
86935 	#define CQ_REQ_V3_STATUS_RNR_NAK_RETRY_CNT_ERR	UINT32_C(0xb)
86942 	#define CQ_REQ_V3_STATUS_TRANSPORT_RETRY_CNT_ERR	UINT32_C(0xc)
86947 	#define CQ_REQ_V3_STATUS_WORK_REQUEST_FLUSHED_ERR   UINT32_C(0xd)
86953 	#define CQ_REQ_V3_STATUS_OVERFLOW_ERR		UINT32_C(0xf)
86968  * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The
87009 	#define CQ_RES_RC_V3_TOGGLE		UINT32_C(0x1)
87011 	#define CQ_RES_RC_V3_CQE_TYPE_MASK	UINT32_C(0x1e)
87017 		#define CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3  (UINT32_C(0x9) << 1)
87022 	#define CQ_RES_RC_V3_STATUS_OK			UINT32_C(0x0)
87036 	#define CQ_RES_RC_V3_STATUS_LOCAL_LENGTH_ERR	UINT32_C(0x2)
87046 	#define CQ_RES_RC_V3_STATUS_LOCAL_QP_OPERATION_ERR	UINT32_C(0x4)
87056 	#define CQ_RES_RC_V3_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x5)
87065 	#define CQ_RES_RC_V3_STATUS_LOCAL_ACCESS_ERROR	UINT32_C(0x6)
87076 	#define CQ_RES_RC_V3_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8)
87081 	#define CQ_RES_RC_V3_STATUS_WORK_REQUEST_FLUSHED_ERR   UINT32_C(0xd)
87087 	#define CQ_RES_RC_V3_STATUS_HW_FLUSH_ERR		UINT32_C(0xe)
87093 	#define CQ_RES_RC_V3_STATUS_OVERFLOW_ERR		UINT32_C(0xf)
87100 	#define CQ_RES_RC_V3_FLAGS_SRQ		UINT32_C(0x1)
87102 		#define CQ_RES_RC_V3_FLAGS_SRQ_RQ	UINT32_C(0x0)
87104 		#define CQ_RES_RC_V3_FLAGS_SRQ_SRQ	UINT32_C(0x1)
87107 	#define CQ_RES_RC_V3_FLAGS_IMM		UINT32_C(0x2)
87109 	#define CQ_RES_RC_V3_FLAGS_INV		UINT32_C(0x4)
87110 	#define CQ_RES_RC_V3_FLAGS_RDMA	UINT32_C(0x8)
87112 		#define CQ_RES_RC_V3_FLAGS_RDMA_SEND	(UINT32_C(0x0) << 3)
87114 		#define CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE  (UINT32_C(0x1) << 3)
87128  * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The
87145 	#define CQ_RES_UD_V3_LENGTH_MASK UINT32_C(0x3fff)
87146 	#define CQ_RES_UD_V3_LENGTH_SFT 0
87170 	#define CQ_RES_UD_V3_TOGGLE		UINT32_C(0x1)
87172 	#define CQ_RES_UD_V3_CQE_TYPE_MASK	UINT32_C(0x1e)
87179 		#define CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3  (UINT32_C(0xa) << 1)
87184 	#define CQ_RES_UD_V3_STATUS_OK			UINT32_C(0x0)
87191 	#define CQ_RES_UD_V3_STATUS_HW_LOCAL_LENGTH_ERR	UINT32_C(0x3)
87201 	#define CQ_RES_UD_V3_STATUS_LOCAL_QP_OPERATION_ERR   UINT32_C(0x4)
87211 	#define CQ_RES_UD_V3_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x5)
87216 	#define CQ_RES_UD_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
87222 	#define CQ_RES_UD_V3_STATUS_HW_FLUSH_ERR		UINT32_C(0xe)
87228 	#define CQ_RES_UD_V3_STATUS_OVERFLOW_ERR		UINT32_C(0xf)
87235 	#define CQ_RES_UD_V3_FLAGS_SRQ		UINT32_C(0x1)
87237 		#define CQ_RES_UD_V3_FLAGS_SRQ_RQ		UINT32_C(0x0)
87239 		#define CQ_RES_UD_V3_FLAGS_SRQ_SRQ		UINT32_C(0x1)
87242 	#define CQ_RES_UD_V3_FLAGS_IMM		UINT32_C(0x2)
87243 	#define CQ_RES_UD_V3_FLAGS_UNUSED_MASK	UINT32_C(0xc)
87245 	#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_MASK  UINT32_C(0x30)
87248 		#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V1	(UINT32_C(0x0) << 4)
87250 		#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV4  (UINT32_C(0x2) << 4)
87252 		#define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6  (UINT32_C(0x3) << 4)
87266  * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The
87283 	#define CQ_RES_RAWETH_QP1_V3_LENGTH_MASK UINT32_C(0x3fff)
87284 	#define CQ_RES_RAWETH_QP1_V3_LENGTH_SFT 0
87291 	#define CQ_RES_RAWETH_QP1_V3_ERROR			UINT32_C(0x1)
87296 	#define CQ_RES_RAWETH_QP1_V3_ITYPE_MASK		UINT32_C(0x3c0)
87302 		#define CQ_RES_RAWETH_QP1_V3_ITYPE_NOT_KNOWN		(UINT32_C(0x0) << 6)
87308 		#define CQ_RES_RAWETH_QP1_V3_ITYPE_IP			(UINT32_C(0x1) << 6)
87315 		#define CQ_RES_RAWETH_QP1_V3_ITYPE_TCP			(UINT32_C(0x2) << 6)
87322 		#define CQ_RES_RAWETH_QP1_V3_ITYPE_UDP			(UINT32_C(0x3) << 6)
87329 		#define CQ_RES_RAWETH_QP1_V3_ITYPE_FCOE		(UINT32_C(0x4) << 6)
87336 		#define CQ_RES_RAWETH_QP1_V3_ITYPE_ROCE		(UINT32_C(0x5) << 6)
87343 		#define CQ_RES_RAWETH_QP1_V3_ITYPE_ICMP		(UINT32_C(0x7) << 6)
87349 		#define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_WO_TIMESTAMP	(UINT32_C(0x8) << 6)
87355 		#define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP	(UINT32_C(0x9) << 6)
87357 	#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_MASK	UINT32_C(0xf000)
87359 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
87360 	#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
87362 	/* When meta_format != 0, this value is the VLAN valid. */
87363 	#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_VALID	UINT32_C(0x8000)
87369 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_IP_CS_ERROR			UINT32_C(0x10)
87374 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_L4_CS_ERROR			UINT32_C(0x20)
87379 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_IP_CS_ERROR			UINT32_C(0x40)
87384 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_L4_CS_ERROR			UINT32_C(0x80)
87389 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_CRC_ERROR			UINT32_C(0x100)
87395 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK		UINT32_C(0xe00)
87401 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 9)
87407 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	(UINT32_C(0x1) << 9)
87413 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	(UINT32_C(0x2) << 9)
87419 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	(UINT32_C(0x3) << 9)
87425 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	(UINT32_C(0x4) << 9)
87428 	 * have failed (e.g. TTL = 0) in the tunnel header. Valid
87431 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL		(UINT32_C(0x5) << 9)
87437 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR	(UINT32_C(0x6) << 9)
87444 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_MASK			UINT32_C(0xf000)
87450 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR		(UINT32_C(0x0) << 12)
87457 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION		(UINT32_C(0x1) << 12)
87462 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN		(UINT32_C(0x2) << 12)
87465 	 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
87467 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL		(UINT32_C(0x3) << 12)
87473 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR		(UINT32_C(0x4) << 12)
87479 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR	(UINT32_C(0x5) << 12)
87484 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN		(UINT32_C(0x6) << 12)
87486 …#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL  (UINT32_C(0x7) …
87492 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN		(UINT32_C(0x8) << 12)
87497 	#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
87498 	#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_SFT 0
87500 	#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_DE	UINT32_C(0x1000)
87502 	#define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
87515 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_CS_CALC		UINT32_C(0x1)
87521 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_L4_CS_CALC		UINT32_C(0x2)
87527 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_CS_CALC		UINT32_C(0x4)
87533 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_L4_CS_CALC		UINT32_C(0x8)
87535 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_MASK	UINT32_C(0xf0)
87538 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_NONE		(UINT32_C(0x0) << 4)
87543 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
87548 	 * - metadata2[25:0] contains the action record pointer.
87551 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR	(UINT32_C(0x1) << 4)
87556 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
87561 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
87562 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
87563 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
87564 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
87565 	 * - IPv4 = 0 (not populated)
87566 	 * - IPv6 = Flow Label[19:0]
87567 	 * - PPPoE = sessionID[15:0]
87568 	 * - MPLs = Outer label[19:0]
87569 	 * - UPAR = Selected[31:0] with bit mask
87571 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 4)
87576 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
87581 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 4)
87586 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
87591 	 * - metadata2[8:0] contains the outer_l3_offset.
87596 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET	(UINT32_C(0x4) << 4)
87600 	 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
87604 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_TYPE			UINT32_C(0x100)
87609 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC	UINT32_C(0x200)
87610 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE		UINT32_C(0x400)
87612 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV4		(UINT32_C(0x0) << 10)
87614 		#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6		(UINT32_C(0x1) << 10)
87622 	#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK	UINT32_C(0xffff0000)
87628 	 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
87629 	 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
87630 	 *   act_rec_ptr[25:0]}
87631 	 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
87632 	 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
87633 	 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
87642 	#define CQ_RES_RAWETH_QP1_V3_TOGGLE			UINT32_C(0x1)
87644 	#define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_MASK		UINT32_C(0x1e)
87651 		#define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3  (UINT32_C(0xb) << 1)
87656 	#define CQ_RES_RAWETH_QP1_V3_STATUS_OK			UINT32_C(0x0)
87663 	#define CQ_RES_RAWETH_QP1_V3_STATUS_HW_LOCAL_LENGTH_ERR	UINT32_C(0x3)
87673 	#define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_QP_OPERATION_ERR   UINT32_C(0x4)
87683 	#define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x5)
87688 	#define CQ_RES_RAWETH_QP1_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
87694 	#define CQ_RES_RAWETH_QP1_V3_STATUS_HW_FLUSH_ERR		UINT32_C(0xe)
87700 	#define CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR		UINT32_C(0xf)
87707 	#define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ	UINT32_C(0x1)
87709 		#define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_RQ	UINT32_C(0x0)
87711 		#define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ   UINT32_C(0x1)
87736  * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The
87753 	#define CQ_RES_UD_CFA_V3_LENGTH_MASK UINT32_C(0x3fff)
87754 	#define CQ_RES_UD_CFA_V3_LENGTH_SFT 0
87758 	#define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
87759 	#define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_SFT 0
87761 	#define CQ_RES_UD_CFA_V3_CFA_METADATA0_DE	UINT32_C(0x1000)
87763 	#define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
87774 	#define CQ_RES_UD_CFA_V3_QID_MASK		UINT32_C(0x7ff)
87775 	#define CQ_RES_UD_CFA_V3_QID_SFT			0
87776 	#define CQ_RES_UD_CFA_V3_UNUSED_MASK		UINT32_C(0xff800)
87778 	#define CQ_RES_UD_CFA_V3_CFA_METADATA1_MASK	UINT32_C(0xf00000)
87780 	/* When meta_format != 0, this value is the VLAN TPID_SEL. */
87781 	#define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000)
87783 	/* When meta_format != 0, this value is the VLAN valid. */
87784 	#define CQ_RES_UD_CFA_V3_CFA_METADATA1_VALID	UINT32_C(0x800000)
87786 	#define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_MASK	UINT32_C(0xff000000)
87792 	 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
87793 	 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
87794 	 *   act_rec_ptr[25:0]}
87795 	 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
87796 	 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
87797 	 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
87813 	#define CQ_RES_UD_CFA_V3_TOGGLE		UINT32_C(0x1)
87815 	#define CQ_RES_UD_CFA_V3_CQE_TYPE_MASK	UINT32_C(0x1e)
87823 		#define CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3  (UINT32_C(0xc) << 1)
87828 	#define CQ_RES_UD_CFA_V3_STATUS_OK			UINT32_C(0x0)
87835 	#define CQ_RES_UD_CFA_V3_STATUS_HW_LOCAL_LENGTH_ERR	UINT32_C(0x3)
87845 	#define CQ_RES_UD_CFA_V3_STATUS_LOCAL_QP_OPERATION_ERR   UINT32_C(0x4)
87855 	#define CQ_RES_UD_CFA_V3_STATUS_LOCAL_PROTECTION_ERR	UINT32_C(0x5)
87860 	#define CQ_RES_UD_CFA_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
87866 	#define CQ_RES_UD_CFA_V3_STATUS_HW_FLUSH_ERR		UINT32_C(0xe)
87872 	#define CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR		UINT32_C(0xf)
87879 	#define CQ_RES_UD_CFA_V3_FLAGS_SRQ			UINT32_C(0x1)
87881 		#define CQ_RES_UD_CFA_V3_FLAGS_SRQ_RQ		UINT32_C(0x0)
87883 		#define CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ		UINT32_C(0x1)
87886 	#define CQ_RES_UD_CFA_V3_FLAGS_IMM			UINT32_C(0x2)
87887 	#define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_MASK		UINT32_C(0xc)
87889 	#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_MASK	UINT32_C(0x30)
87892 		#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V1	(UINT32_C(0x0) << 4)
87894 		#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV4	(UINT32_C(0x2) << 4)
87896 		#define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6	(UINT32_C(0x3) << 4)
87899 	#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_MASK	UINT32_C(0x3c0)
87902 		#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_NONE	(UINT32_C(0x0) << 6)
87907 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
87912 	 * - metadata2[25:0] contains the action record pointer.
87915 		#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_ACT_REC_PTR  (UINT32_C(0x1) << 6)
87920 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
87925 	 * - VXLAN = VNI[23:0] -> VXLAN Network ID
87926 	 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
87927 	 * - NVGRE = TNI[23:0] -> Tenant Network ID
87928 	 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
87929 	 * - IPv4 = 0 (not populated)
87930 	 * - IPv6 = Flow Label[19:0]
87931 	 * - PPPoE = sessionID[15:0]
87932 	 * - MPLs = Outer label[19:0]
87933 	 * - UPAR = Selected[31:0] with bit mask
87935 		#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_TUNNEL_ID	(UINT32_C(0x2) << 6)
87940 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
87945 		#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_CHDR_DATA	(UINT32_C(0x3) << 6)
87950 	 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
87955 	 * - metadata2[8:0] contains the outer_l3_offset.
87960 		#define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_HDR_OFFSET   (UINT32_C(0x4) << 6)
87980 	#define NQ_BASE_TYPE_MASK	UINT32_C(0x3f)
87981 	#define NQ_BASE_TYPE_SFT		0
87983 		#define NQ_BASE_TYPE_CQ_NOTIFICATION  UINT32_C(0x30)
87985 		#define NQ_BASE_TYPE_SRQ_EVENT	UINT32_C(0x32)
87987 		#define NQ_BASE_TYPE_DBQ_EVENT	UINT32_C(0x34)
87989 		#define NQ_BASE_TYPE_QP_EVENT	UINT32_C(0x38)
87991 		#define NQ_BASE_TYPE_FUNC_EVENT	UINT32_C(0x3a)
87993 		#define NQ_BASE_TYPE_NQ_REASSIGN	UINT32_C(0x3c)
87996 	#define NQ_BASE_INFO10_MASK	UINT32_C(0xffc0)
88007 	 * will write 1. The odd passes will write 0.
88009 	#define NQ_BASE_V	UINT32_C(0x1)
88011 	#define NQ_BASE_INFO63_MASK UINT32_C(0xfffffffe)
88027 	#define NQ_CN_TYPE_MASK	UINT32_C(0x3f)
88028 	#define NQ_CN_TYPE_SFT		0
88030 		#define NQ_CN_TYPE_CQ_NOTIFICATION  UINT32_C(0x30)
88043 	#define NQ_CN_TOGGLE_MASK	UINT32_C(0xc0)
88055 	 * will write 1. The odd passes will write 0.
88057 	#define NQ_CN_V	UINT32_C(0x1)
88076 	#define NQ_SRQ_EVENT_TYPE_MASK	UINT32_C(0x3f)
88077 	#define NQ_SRQ_EVENT_TYPE_SFT	0
88079 		#define NQ_SRQ_EVENT_TYPE_SRQ_EVENT  UINT32_C(0x32)
88086 	#define NQ_SRQ_EVENT_TOGGLE_MASK   UINT32_C(0xc0)
88094 	#define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT UINT32_C(0x1)
88107 	 * will write 1. The odd passes will write 0.
88109 	#define NQ_SRQ_EVENT_V	UINT32_C(0x1)
88130 	#define NQ_DBQ_EVENT_TYPE_MASK	UINT32_C(0x3f)
88131 	#define NQ_DBQ_EVENT_TYPE_SFT	0
88133 		#define NQ_DBQ_EVENT_TYPE_DBQ_EVENT  UINT32_C(0x34)
88142 	#define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT UINT32_C(0x1)
88149 	#define NQ_DBQ_EVENT_DB_PFID_MASK UINT32_C(0xf)
88150 	#define NQ_DBQ_EVENT_DB_PFID_SFT 0
88156 	#define NQ_DBQ_EVENT_DB_DPI_MASK UINT32_C(0xfffff)
88157 	#define NQ_DBQ_EVENT_DB_DPI_SFT 0
88162 	 * will write 1. The odd passes will write 0.
88164 	#define NQ_DBQ_EVENT_V	UINT32_C(0x1)
88171 	#define NQ_DBQ_EVENT_DB_XID_MASK UINT32_C(0xfffff)
88172 	#define NQ_DBQ_EVENT_DB_XID_SFT  0
88177 	#define NQ_DBQ_EVENT_DB_TYPE_MASK UINT32_C(0xf0000000)
88196 	#define NQ_REASSIGN_TYPE_MASK	UINT32_C(0x3f)
88197 	#define NQ_REASSIGN_TYPE_SFT	0
88199 		#define NQ_REASSIGN_TYPE_NQ_REASSIGN  UINT32_C(0x3c)
88211 	 * will write 1. The odd passes will write 0.
88213 	#define NQ_REASSIGN_V	UINT32_C(0x1)
88227 	#define XRRQ_IRRQ_TYPE	UINT32_C(0x1)
88229 		#define XRRQ_IRRQ_TYPE_READ_REQ	UINT32_C(0x0)
88231 		#define XRRQ_IRRQ_TYPE_ATOMIC_REQ  UINT32_C(0x1)
88238 	#define XRRQ_IRRQ_CREDITS_MASK   UINT32_C(0xf800)
88244 	#define XRRQ_IRRQ_PSN_MASK UINT32_C(0xffffff)
88245 	#define XRRQ_IRRQ_PSN_SFT 0
88253 	#define XRRQ_IRRQ_MSN_MASK UINT32_C(0xffffff)
88254 	#define XRRQ_IRRQ_MSN_SFT 0
88280 	#define XRRQ_ORRQ_TYPE	UINT32_C(0x1)
88282 		#define XRRQ_ORRQ_TYPE_READ_REQ	UINT32_C(0x0)
88284 		#define XRRQ_ORRQ_TYPE_ATOMIC_REQ  UINT32_C(0x1)
88307 	#define XRRQ_ORRQ_NUM_SGES_MASK  UINT32_C(0xf800)
88317 	#define XRRQ_ORRQ_PSN_MASK UINT32_C(0xffffff)
88318 	#define XRRQ_ORRQ_PSN_SFT 0
88326 	#define XRRQ_ORRQ_END_PSN_MASK UINT32_C(0xffffff)
88327 	#define XRRQ_ORRQ_END_PSN_SFT 0
88334 	 * aligned 0b0000 lsb added to get 64 bit address.
88349 	 * This field indicates if the PTE is valid. A value of '0'
88354 	#define PTU_PTE_VALID		UINT32_C(0x1)
88363 	#define PTU_PTE_LAST		UINT32_C(0x2)
88370 	#define PTU_PTE_NEXT_TO_LAST	UINT32_C(0x4)
88372 	#define PTU_PTE_UNUSED_MASK	UINT32_C(0xff8)
88379 	#define PTU_PTE_PAGE_MASK	UINT32_C(0xfffffffffffff000)L
88389 	 * This field indicates if the PTE is valid. A value of '0'
88394 	#define PTU_PDE_VALID	UINT32_C(0x1)
88396 	#define PTU_PDE_UNUSED_MASK UINT32_C(0xffe)
88403 	#define PTU_PDE_PAGE_MASK  UINT32_C(0xfffffffffffff000)L
88409  * format directly to byte offset 0 of the appropriate doorbell page.
88434 	#define DBC_DBC_INDEX_MASK UINT32_C(0xffffff)
88435 	#define DBC_DBC_INDEX_SFT  0
88444 	#define DBC_DBC_EPOCH	UINT32_C(0x1000000)
88455 	#define DBC_DBC_TOGGLE_MASK UINT32_C(0x6000000)
88467 	#define DBC_DBC_XID_MASK	UINT32_C(0xfffff)
88468 	#define DBC_DBC_XID_SFT	0
88473 	#define DBC_DBC_PATH_MASK	UINT32_C(0x3000000)
88476 		#define DBC_DBC_PATH_ROCE	(UINT32_C(0x0) << 24)
88478 		#define DBC_DBC_PATH_L2		(UINT32_C(0x1) << 24)
88480 		#define DBC_DBC_PATH_ENGINE	(UINT32_C(0x2) << 24)
88489 	#define DBC_DBC_VALID		UINT32_C(0x4000000)
88495 	#define DBC_DBC_DEBUG_TRACE	UINT32_C(0x8000000)
88497 	#define DBC_DBC_TYPE_MASK	UINT32_C(0xf0000000)
88505 		#define DBC_DBC_TYPE_SQ		(UINT32_C(0x0) << 28)
88511 		#define DBC_DBC_TYPE_RQ		(UINT32_C(0x1) << 28)
88517 		#define DBC_DBC_TYPE_SRQ		(UINT32_C(0x2) << 28)
88525 		#define DBC_DBC_TYPE_SRQ_ARM	(UINT32_C(0x3) << 28)
88531 		#define DBC_DBC_TYPE_CQ		(UINT32_C(0x4) << 28)
88536 		#define DBC_DBC_TYPE_CQ_ARMSE	(UINT32_C(0x5) << 28)
88542 		#define DBC_DBC_TYPE_CQ_ARMALL	(UINT32_C(0x6) << 28)
88551 		#define DBC_DBC_TYPE_CQ_ARMENA	(UINT32_C(0x7) << 28)
88562 		#define DBC_DBC_TYPE_SRQ_ARMENA	(UINT32_C(0x8) << 28)
88570 		#define DBC_DBC_TYPE_CQ_CUTOFF_ACK  (UINT32_C(0x9) << 28)
88576 		#define DBC_DBC_TYPE_NQ		(UINT32_C(0xa) << 28)
88581 		#define DBC_DBC_TYPE_NQ_ARM	(UINT32_C(0xb) << 28)
88587 		#define DBC_DBC_TYPE_NQ_MASK	(UINT32_C(0xe) << 28)
88598 		#define DBC_DBC_TYPE_NULL	(UINT32_C(0xf) << 28)
88630 	#define DBC_DBC64_INDEX_MASK	UINT32_C(0xffffff)
88631 	#define DBC_DBC64_INDEX_SFT	0
88640 	#define DBC_DBC64_EPOCH		UINT32_C(0x1000000)
88651 	#define DBC_DBC64_TOGGLE_MASK	UINT32_C(0x6000000)
88662 	#define DBC_DBC64_XID_MASK	UINT32_C(0xfffff00000000)L
88668 	#define DBC_DBC64_PATH_MASK	UINT32_C(0x300000000000000)L
88671 		#define DBC_DBC64_PATH_ROCE	(UINT32_C(0x0)L << 56)
88673 		#define DBC_DBC64_PATH_L2		(UINT32_C(0x1)L << 56)
88675 		#define DBC_DBC64_PATH_ENGINE	(UINT32_C(0x2)L << 56)
88684 	#define DBC_DBC64_VALID		UINT32_C(0x400000000000000)L
88690 	#define DBC_DBC64_DEBUG_TRACE	UINT32_C(0x800000000000000)L
88692 	#define DBC_DBC64_TYPE_MASK	UINT32_C(0xf000000000000000)L
88700 		#define DBC_DBC64_TYPE_SQ		(UINT32_C(0x0)L << 60)
88706 		#define DBC_DBC64_TYPE_RQ		(UINT32_C(0x1)L << 60)
88712 		#define DBC_DBC64_TYPE_SRQ		(UINT32_C(0x2)L << 60)
88720 		#define DBC_DBC64_TYPE_SRQ_ARM	(UINT32_C(0x3)L << 60)
88726 		#define DBC_DBC64_TYPE_CQ		(UINT32_C(0x4)L << 60)
88731 		#define DBC_DBC64_TYPE_CQ_ARMSE	(UINT32_C(0x5)L << 60)
88737 		#define DBC_DBC64_TYPE_CQ_ARMALL	(UINT32_C(0x6)L << 60)
88746 		#define DBC_DBC64_TYPE_CQ_ARMENA	(UINT32_C(0x7)L << 60)
88757 		#define DBC_DBC64_TYPE_SRQ_ARMENA	(UINT32_C(0x8)L << 60)
88765 		#define DBC_DBC64_TYPE_CQ_CUTOFF_ACK  (UINT32_C(0x9)L << 60)
88771 		#define DBC_DBC64_TYPE_NQ		(UINT32_C(0xa)L << 60)
88776 		#define DBC_DBC64_TYPE_NQ_ARM	(UINT32_C(0xb)L << 60)
88782 		#define DBC_DBC64_TYPE_NQ_MASK	(UINT32_C(0xe)L << 60)
88793 		#define DBC_DBC64_TYPE_NULL	(UINT32_C(0xf)L << 60)
88814 	#define DBC_DBC32_XID_MASK UINT32_C(0xfffff)
88815 	#define DBC_DBC32_XID_SFT  0
88820 	#define DBC_DBC32_PATH_MASK UINT32_C(0xc00000)
88823 		#define DBC_DBC32_PATH_ROCE  (UINT32_C(0x0) << 22)
88825 		#define DBC_DBC32_PATH_L2	(UINT32_C(0x1) << 22)
88828 	 * When abs=0, this value is the value to add to the appropriate
88836 	#define DBC_DBC32_INCR_MASK UINT32_C(0xf000000)
88839 	#define DBC_DBC32_ABS	UINT32_C(0x10000000)
88841 	#define DBC_DBC32_TYPE_MASK UINT32_C(0xe0000000)
88848 		#define DBC_DBC32_TYPE_SQ	(UINT32_C(0x0) << 29)
88855  * combine buffer) within doorbell page. WCB#0 = offset 16, WCB#1 =
88886 	#define DB_PUSH_START_DB_INDEX_MASK	UINT32_C(0xffffff)
88887 	#define DB_PUSH_START_DB_INDEX_SFT	0
88893 	#define DB_PUSH_START_DB_PI_LO_MASK	UINT32_C(0xff000000)
88901 	#define DB_PUSH_START_DB_XID_MASK	UINT32_C(0xfffff00000000)L
88908 	#define DB_PUSH_START_DB_PI_HI_MASK	UINT32_C(0xf0000000000000)L
88911 	#define DB_PUSH_START_DB_TYPE_MASK	UINT32_C(0xf000000000000000)L
88918 		#define DB_PUSH_START_DB_TYPE_PUSH_START  (UINT32_C(0xc)L << 60)
88924 		#define DB_PUSH_START_DB_TYPE_PUSH_END	(UINT32_C(0xd)L << 60)
88931  * buffer) within doorbell page. WCB#0 = offset 16, WCB#1 = offset 24,
88965 	#define DB_PUSH_END_DB_INDEX_MASK	UINT32_C(0xffffff)
88966 	#define DB_PUSH_END_DB_INDEX_SFT	0
88972 	#define DB_PUSH_END_DB_PI_LO_MASK	UINT32_C(0xff000000)
88980 	#define DB_PUSH_END_DB_XID_MASK	UINT32_C(0xfffff00000000)L
88987 	#define DB_PUSH_END_DB_PI_HI_MASK	UINT32_C(0xf0000000000000)L
88993 	#define DB_PUSH_END_DB_PATH_MASK	UINT32_C(0x300000000000000)L
88996 		#define DB_PUSH_END_DB_PATH_ROCE	(UINT32_C(0x0)L << 56)
88998 		#define DB_PUSH_END_DB_PATH_L2	(UINT32_C(0x1)L << 56)
89000 		#define DB_PUSH_END_DB_PATH_ENGINE	(UINT32_C(0x2)L << 56)
89007 	#define DB_PUSH_END_DB_DEBUG_TRACE	UINT32_C(0x800000000000000)L
89009 	#define DB_PUSH_END_DB_TYPE_MASK	UINT32_C(0xf000000000000000)L
89016 		#define DB_PUSH_END_DB_TYPE_PUSH_START   (UINT32_C(0xc)L << 60)
89022 		#define DB_PUSH_END_DB_TYPE_PUSH_END	(UINT32_C(0xd)L << 60)
89038 	 * push_index should be written to 0. The push_index should point
89047 	#define DB_PUSH_INFO_PUSH_INDEX_MASK UINT32_C(0xffffff)
89048 	#define DB_PUSH_INFO_PUSH_INDEX_SFT 0
89051 	 * 0 means 256B size of push. The push write is done in 8B units
89057 	#define DB_PUSH_INFO_PUSH_SIZE_MASK UINT32_C(0x1f000000)
89064  * message format directly to byte offset 0xC of the appropriate
89108 	#define DBC_ABSOLUTE_DB_32_INDEX_MASK	UINT32_C(0xffff)
89109 	#define DBC_ABSOLUTE_DB_32_INDEX_SFT	0
89118 	#define DBC_ABSOLUTE_DB_32_EPOCH	UINT32_C(0x10000)
89129 	#define DBC_ABSOLUTE_DB_32_TOGGLE_MASK	UINT32_C(0x60000)
89139 	#define DBC_ABSOLUTE_DB_32_MXID_MASK	UINT32_C(0x1f80000)
89145 	#define DBC_ABSOLUTE_DB_32_PATH_MASK	UINT32_C(0x6000000)
89148 		#define DBC_ABSOLUTE_DB_32_PATH_ROCE	(UINT32_C(0x0) << 25)
89150 		#define DBC_ABSOLUTE_DB_32_PATH_L2	(UINT32_C(0x1) << 25)
89159 	#define DBC_ABSOLUTE_DB_32_VALID	UINT32_C(0x8000000)
89161 	#define DBC_ABSOLUTE_DB_32_TYPE_MASK	UINT32_C(0xf0000000)
89169 		#define DBC_ABSOLUTE_DB_32_TYPE_SQ	(UINT32_C(0x0) << 28)
89175 		#define DBC_ABSOLUTE_DB_32_TYPE_RQ	(UINT32_C(0x1) << 28)
89181 		#define DBC_ABSOLUTE_DB_32_TYPE_SRQ	(UINT32_C(0x2) << 28)
89189 		#define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARM	(UINT32_C(0x3) << 28)
89195 		#define DBC_ABSOLUTE_DB_32_TYPE_CQ	(UINT32_C(0x4) << 28)
89200 		#define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMSE	(UINT32_C(0x5) << 28)
89206 		#define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMALL   (UINT32_C(0x6) << 28)
89216 		#define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMENA   (UINT32_C(0x7) << 28)
89227 		#define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARMENA  (UINT32_C(0x8) << 28)
89233 		#define DBC_ABSOLUTE_DB_32_TYPE_NQ	(UINT32_C(0xa) << 28)
89238 		#define DBC_ABSOLUTE_DB_32_TYPE_NQ_ARM	(UINT32_C(0xb) << 28)
89244 		#define DBC_ABSOLUTE_DB_32_TYPE_NQ_MASK	(UINT32_C(0xe) << 28)
89255 		#define DBC_ABSOLUTE_DB_32_TYPE_NULL	(UINT32_C(0xf) << 28)
89279 	#define DBC_RELATIVE_DB_32_XID_MASK	UINT32_C(0xfffff)
89280 	#define DBC_RELATIVE_DB_32_XID_SFT	0
89285 	#define DBC_RELATIVE_DB_32_PATH_MASK	UINT32_C(0xc00000)
89288 		#define DBC_RELATIVE_DB_32_PATH_ROCE	(UINT32_C(0x0) << 22)
89290 		#define DBC_RELATIVE_DB_32_PATH_L2	(UINT32_C(0x1) << 22)
89299 	#define DBC_RELATIVE_DB_32_INCR_MASK	UINT32_C(0x1f000000)
89302 	#define DBC_RELATIVE_DB_32_TYPE_MASK	UINT32_C(0xe0000000)
89310 		#define DBC_RELATIVE_DB_32_TYPE_SQ	(UINT32_C(0x0) << 29)
89316 		#define DBC_RELATIVE_DB_32_TYPE_SRQ	(UINT32_C(0x1) << 29)
89322 		#define DBC_RELATIVE_DB_32_TYPE_CQ	(UINT32_C(0x2) << 29)
89328 		#define DBC_RELATIVE_DB_32_TYPE_CQ_ARMALL  (UINT32_C(0x3) << 29)
89334 		#define DBC_RELATIVE_DB_32_TYPE_NQ	(UINT32_C(0x4) << 29)
89339 		#define DBC_RELATIVE_DB_32_TYPE_NQ_ARM	(UINT32_C(0x5) << 29)
89345 		#define DBC_RELATIVE_DB_32_TYPE_NQ_MASK	(UINT32_C(0x6) << 29)
89364 	#define DBC_DRK_VALID	UINT32_C(0x1)
89366 	#define DBC_DRK_LAST	UINT32_C(0x2)
89368 	#define DBC_DRK_LINKED	UINT32_C(0x4)
89373 	#define DBC_DRK_DB_FORMAT	UINT32_C(0x8)
89375 		#define DBC_DRK_DB_FORMAT_B64   (UINT32_C(0x0) << 3)
89381 		#define DBC_DRK_DB_FORMAT_B32A  (UINT32_C(0x1) << 3)
89388 	#define DBC_DRK_STRIDE_MASK   UINT32_C(0x300)
89395 		#define DBC_DRK_STRIDE_OFF	(UINT32_C(0x0) << 8)
89402 		#define DBC_DRK_STRIDE_SZ64	(UINT32_C(0x1) << 8)
89409 		#define DBC_DRK_STRIDE_SZ128	(UINT32_C(0x2) << 8)
89415 	#define DBC_DRK_SIZE_MASK	UINT32_C(0xc00)
89418 		#define DBC_DRK_SIZE_FOUR	(UINT32_C(0x0) << 10)
89420 		#define DBC_DRK_SIZE_ONE	(UINT32_C(0x1) << 10)
89422 		#define DBC_DRK_SIZE_TWO	(UINT32_C(0x2) << 10)
89424 		#define DBC_DRK_SIZE_THREE	(UINT32_C(0x3) << 10)
89436 	#define DBC_DRK_PI_MASK UINT32_C(0xffff)
89437 	#define DBC_DRK_PI_SFT 0
89439 	 * It is the application memory page(4KB) pointer when linked = 0.
89463 	#define DBC_DRK64_VALID	UINT32_C(0x1)
89465 	#define DBC_DRK64_LAST	UINT32_C(0x2)
89467 	#define DBC_DRK64_LINKED	UINT32_C(0x4)
89472 	#define DBC_DRK64_DB_FORMAT	UINT32_C(0x8)
89474 		#define DBC_DRK64_DB_FORMAT_B64   (UINT32_C(0x0) << 3)
89480 		#define DBC_DRK64_DB_FORMAT_B32A  (UINT32_C(0x1) << 3)
89487 	#define DBC_DRK64_STRIDE_MASK   UINT32_C(0x300)
89494 		#define DBC_DRK64_STRIDE_OFF	(UINT32_C(0x0) << 8)
89501 		#define DBC_DRK64_STRIDE_SZ64	(UINT32_C(0x1) << 8)
89508 		#define DBC_DRK64_STRIDE_SZ128	(UINT32_C(0x2) << 8)
89514 	#define DBC_DRK64_SIZE_MASK	UINT32_C(0xc00)
89517 		#define DBC_DRK64_SIZE_FOUR	(UINT32_C(0x0) << 10)
89519 		#define DBC_DRK64_SIZE_ONE	(UINT32_C(0x1) << 10)
89521 		#define DBC_DRK64_SIZE_TWO	(UINT32_C(0x2) << 10)
89523 		#define DBC_DRK64_SIZE_THREE	(UINT32_C(0x3) << 10)
89534 	#define DBC_DRK64_PI_MASK	UINT32_C(0xffff00000000)L
89537 	 * It is the application memory page(4KB) pointer when linked = 0.
89548  * format directly to byte offset 0 of the appropriate doorbell page.
89579 	#define DBC_DBC_V3_INDEX_MASK UINT32_C(0xffffff)
89580 	#define DBC_DBC_V3_INDEX_SFT  0
89589 	#define DBC_DBC_V3_EPOCH	UINT32_C(0x1000000)
89600 	#define DBC_DBC_V3_TOGGLE_MASK UINT32_C(0x6000000)
89613 	#define DBC_DBC_V3_XID_MASK	UINT32_C(0xfff)
89614 	#define DBC_DBC_V3_XID_SFT	0
89619 	#define DBC_DBC_V3_PATH_MASK	UINT32_C(0x3000000)
89622 		#define DBC_DBC_V3_PATH_ROCE	(UINT32_C(0x0) << 24)
89624 		#define DBC_DBC_V3_PATH_L2		(UINT32_C(0x1) << 24)
89633 	#define DBC_DBC_V3_VALID		UINT32_C(0x4000000)
89639 	#define DBC_DBC_V3_DEBUG_TRACE	UINT32_C(0x8000000)
89641 	#define DBC_DBC_V3_TYPE_MASK	UINT32_C(0xf0000000)
89648 		#define DBC_DBC_V3_TYPE_SQ		(UINT32_C(0x0) << 28)
89654 		#define DBC_DBC_V3_TYPE_RQ		(UINT32_C(0x1) << 28)
89660 		#define DBC_DBC_V3_TYPE_SRQ		(UINT32_C(0x2) << 28)
89669 		#define DBC_DBC_V3_TYPE_SRQ_ARM	(UINT32_C(0x3) << 28)
89680 		#define DBC_DBC_V3_TYPE_CQ		(UINT32_C(0x4) << 28)
89691 		#define DBC_DBC_V3_TYPE_CQ_ARMSE	(UINT32_C(0x5) << 28)
89702 		#define DBC_DBC_V3_TYPE_CQ_ARMALL	(UINT32_C(0x6) << 28)
89713 		#define DBC_DBC_V3_TYPE_CQ_ARMENA	(UINT32_C(0x7) << 28)
89724 		#define DBC_DBC_V3_TYPE_SRQ_ARMENA	(UINT32_C(0x8) << 28)
89735 		#define DBC_DBC_V3_TYPE_CQ_CUTOFF_ACK  (UINT32_C(0x9) << 28)
89754 		#define DBC_DBC_V3_TYPE_NQ		(UINT32_C(0xa) << 28)
89761 		#define DBC_DBC_V3_TYPE_NQ_ARM	(UINT32_C(0xb) << 28)
89780 		#define DBC_DBC_V3_TYPE_CQ_REASSIGN	(UINT32_C(0xc) << 28)
89787 		#define DBC_DBC_V3_TYPE_NQ_MASK	(UINT32_C(0xe) << 28)
89795 		#define DBC_DBC_V3_TYPE_NULL	(UINT32_C(0xf) << 28)
89801  * message format directly to offset 0x40 of the appropriate doorbell
89824 	#define DBC_XP_XID_MASK	UINT32_C(0xfff)
89825 	#define DBC_XP_XID_SFT	0
89831 	#define DBC_XP_DEBUG_TRACE	UINT32_C(0x1000000)
89833 	#define DBC_XP_TYPE_MASK	UINT32_C(0xf0000000)
89841 		#define DBC_XP_TYPE_SQ	(UINT32_C(0x0) << 28)
89847 		#define DBC_XP_TYPE_RQ	(UINT32_C(0x1) << 28)
89853 		#define DBC_XP_TYPE_SRQ	(UINT32_C(0x2) << 28)
89876 	 * A value below 0x8000 is an indication that the firmware is still
89880 	 * >	0x0000 to 0x00FF : SBL state information
89881 	 * >	0x0200 to 0x02FF : SBI state information
89882 	 * >	0x0400 to 0x04FF : SRT state information
89883 	 * >	0x0600 to 0x06FF : CRT/CHIMP state information
89884 	 * >	0x0800 to 0x08FF : External Firmware state information
89885 	 * >	0x0A00 to 0x0FFF : Reserved for future fw functionality
89887 	 * A value of 0x8000 indicates firmware is ready and healthy. The
89890 	 * A value over 0x8000 is an indication that the firmware has
89896 	 * >	0x81XX - 0xBFXX  : 63 ASIC blocks
89897 	 * >	0xC0XX to 0xFDXX : 62 Firmware modules
89898 	 * >	0xFE00 to 0xFEFF : External firmware module
89899 	 * >	0xFFXX	: Reserved for future
89901 	#define FW_STATUS_REG_CODE_MASK		UINT32_C(0xffff)
89902 	#define FW_STATUS_REG_CODE_SFT		0
89904 		#define FW_STATUS_REG_CODE_READY		UINT32_C(0x8000)
89915 	#define FW_STATUS_REG_IMAGE_DEGRADED	UINT32_C(0x10000)
89924 	 * is greater than 0x8000 (32768 decimal).
89926 	#define FW_STATUS_REG_RECOVERABLE		UINT32_C(0x20000)
89935 	 * greater than 0x8000 (32768 decimal).
89937 	#define FW_STATUS_REG_CRASHDUMP_ONGOING	UINT32_C(0x40000)
89944 	 * code field is greater than 0x8000 (32768 decimal).
89946 	#define FW_STATUS_REG_CRASHDUMP_COMPLETE	UINT32_C(0x80000)
89955 	 * 0x8000 (32768 decimal).
89957 	#define FW_STATUS_REG_SHUTDOWN		UINT32_C(0x100000)
89964 	 * than 0x8000 (32768 decimal).
89966 	#define FW_STATUS_REG_CRASHED_NO_MASTER	UINT32_C(0x200000)
89971 	 * This bit is valid only when the code field is greater than 0x8000
89974 	#define FW_STATUS_REG_RECOVERING		UINT32_C(0x400000)
89979 	#define FW_STATUS_REG_MANU_DEBUG_STATUS	UINT32_C(0x800000)
89984  * offset: 0x31001F0). Host software is expected to read from this
89997 	#define HCOMM_STATUS_VER_MASK	UINT32_C(0xff)
89998 	#define HCOMM_STATUS_VER_SFT	0
89999 		#define HCOMM_STATUS_VER_LATEST	UINT32_C(0x1)
90005 	#define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
90007 		#define HCOMM_STATUS_SIGNATURE_VAL   (UINT32_C(0x484353) << 8)
90010 	#define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK	UINT32_C(0x3)
90011 	#define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT	0
90013 		#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG  UINT32_C(0x0)
90015 		#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC	UINT32_C(0x1)
90017 		#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0	UINT32_C(0x2)
90019 		#define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1	UINT32_C(0x3)
90025 	#define HCOMM_STATUS_TRUE_OFFSET_MASK	UINT32_C(0xfffffffc)
90030 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
90055 	 * * 0x0-0xFFF8 - The function ID
90056 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90057 	 * * 0xFFFD - Reserved for user-space HWRM interface
90058 	 * * 0xFFFF - HWRM
90089 	#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_NVM_TEST		UINT32_C(0x1)
90091 	#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_LINK_TEST		UINT32_C(0x2)
90093 	#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_REGISTER_TEST		UINT32_C(0x4)
90095 	#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_MEMORY_TEST		UINT32_C(0x8)
90097 	#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PCIE_SERDES_TEST	UINT32_C(0x10)
90099 	#define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_ETHERNET_SERDES_TEST	UINT32_C(0x20)
90102 	#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_NVM_TEST		UINT32_C(0x1)
90104 	#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_LINK_TEST		UINT32_C(0x2)
90106 	#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_REGISTER_TEST		UINT32_C(0x4)
90108 	#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_MEMORY_TEST		UINT32_C(0x8)
90110 	#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_PCIE_SERDES_TEST	UINT32_C(0x10)
90112 	#define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_ETHERNET_SERDES_TEST	UINT32_C(0x20)
90132 	#define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED  UINT32_C(0x0)
90134 	#define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED  UINT32_C(0x1)
90136 	#define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED UINT32_C(0x2)
90138 	#define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED UINT32_C(0x3)
90140 	#define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED UINT32_C(0x4)
90176 	 * * 0x0-0xFFF8 - The function ID
90177 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90178 	 * * 0xFFFD - Reserved for user-space HWRM interface
90179 	 * * 0xFFFF - HWRM
90192 	#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_NVM_TEST		UINT32_C(0x1)
90194 	#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_LINK_TEST		UINT32_C(0x2)
90196 	#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_REGISTER_TEST		UINT32_C(0x4)
90198 	#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_MEMORY_TEST		UINT32_C(0x8)
90200 	#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_PCIE_SERDES_TEST	UINT32_C(0x10)
90202 	#define HWRM_SELFTEST_EXEC_INPUT_FLAGS_ETHERNET_SERDES_TEST	UINT32_C(0x20)
90220 	#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_NVM_TEST		UINT32_C(0x1)
90222 	#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_LINK_TEST		UINT32_C(0x2)
90224 	#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_REGISTER_TEST		UINT32_C(0x4)
90226 	#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_MEMORY_TEST		UINT32_C(0x8)
90228 	#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PCIE_SERDES_TEST	UINT32_C(0x10)
90230 	#define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_ETHERNET_SERDES_TEST	UINT32_C(0x20)
90234 	 * failed(0).
90241 	#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_NVM_TEST		UINT32_C(0x1)
90246 	#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_LINK_TEST		UINT32_C(0x2)
90251 	#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_REGISTER_TEST		UINT32_C(0x4)
90256 	#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_MEMORY_TEST		UINT32_C(0x8)
90261 	#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PCIE_SERDES_TEST	UINT32_C(0x10)
90266 	#define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_ETHERNET_SERDES_TEST	UINT32_C(0x20)
90301 	 * * 0x0-0xFFF8 - The function ID
90302 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90303 	 * * 0xFFFD - Reserved for user-space HWRM interface
90304 	 * * 0xFFFF - HWRM
90361 	 * * 0x0-0xFFF8 - The function ID
90362 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90363 	 * * 0xFFFD - Reserved for user-space HWRM interface
90364 	 * * 0xFFFF - HWRM
90378 	 * copying the data to the host from. This should be set to 0 on the
90394 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_MASK	UINT32_C(0x7)
90395 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_SFT	0
90397 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_EYE_PROJECTION	UINT32_C(0x8)
90399 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_PCIE_SERDES_TEST	UINT32_C(0x10)
90401 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_ETHERNET_SERDES_TEST	UINT32_C(0x20)
90407 	 * Valid values from 0 to 16.
90409 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PCIE_LANE_NO_MASK	UINT32_C(0xf)
90410 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PCIE_LANE_NO_SFT	0
90412 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION		UINT32_C(0x10)
90413 	/* Value 0 indicates Horizontal plot request. */
90414 		#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_HORIZONTAL	(UINT32_C(0x0) << 4)
90416 		#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_VERTICAL	(UINT32_C(0x1) << 4)
90419 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE		UINT32_C(0x20)
90421 	 * Value 0 indicates left/top projection in horizontal/vertical
90424 		#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_LEFT_TOP	(UINT32_C(0x0) << 5)
90430 …#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM  (UINT32_C(0x1) <<…
90433 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_RSVD_MASK		UINT32_C(0xc0)
90441 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E8  UINT32_C(0x0)
90443 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E9  UINT32_C(0x1)
90445 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E10 UINT32_C(0x2)
90447 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E11 UINT32_C(0x3)
90449 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E12 UINT32_C(0x4)
90457 	 * Value 0 indicates that collection of the eyescope should be
90461 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_SYNCHRONOUS UINT32_C(0x0)
90466 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_START	UINT32_C(0x1)
90471 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_PROGRESS	UINT32_C(0x2)
90477 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_STOP	UINT32_C(0x3)
90505 	 * current eyescope operation in tenths of a percentage. 0 (0.0) to
90516 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE		UINT32_C(0x1)
90518 	 * Value 0 indicates that bit_count value is a raw total
90521 …efine HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_TOTAL  UINT32_C(0x0)
90527 …efine HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_POW2   UINT32_C(0x1)
90530 	#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_RSVD_MASK			UINT32_C(0xfe)
90573 	 * * 0x0-0xFFF8 - The function ID
90574 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90575 	 * * 0xFFFD - Reserved for user-space HWRM interface
90576 	 * * 0xFFFF - HWRM
90587 	 * This field indicates the lock/unlock operation. 0 means Unlock and
90639 	 * * 0x0-0xFFF8 - The function ID
90640 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90641 	 * * 0xFFFD - Reserved for user-space HWRM interface
90642 	 * * 0xFFFF - HWRM
90668 	 * The value can wrap around. On error, a value of 0 on all ticks
90674 	 * The value can wrap around. On error, a value of 0 on all ticks
90680 	 * The value can wrap around. On error, a value of 0 on all ticks
90718 	 * * 0x0-0xFFF8 - The function ID
90719 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90720 	 * * 0xFFFD - Reserved for user-space HWRM interface
90721 	 * * 0xFFFF - HWRM
90736 	#define HWRM_MFG_OTP_CFG_INPUT_ENABLES_CRID		UINT32_C(0x1)
90741 	#define HWRM_MFG_OTP_CFG_INPUT_ENABLES_SRT_REV_ID	UINT32_C(0x2)
90746 	#define HWRM_MFG_OTP_CFG_INPUT_ENABLES_CRT_REV_ID	UINT32_C(0x4)
90751 	#define HWRM_MFG_OTP_CFG_INPUT_ENABLES_SBI_REV_ID	UINT32_C(0x8)
90756 	#define HWRM_MFG_OTP_CFG_INPUT_ENABLES_MAX_SPEED_SELECT	UINT32_C(0x10)
90768 	#define HWRM_MFG_OTP_CFG_INPUT_MAX_SPEED_CFG_VALUE_NOT_CONFIGURED UINT32_C(0x0)
90770 	#define HWRM_MFG_OTP_CFG_INPUT_MAX_SPEED_CFG_VALUE_50G		UINT32_C(0x1)
90772 	#define HWRM_MFG_OTP_CFG_INPUT_MAX_SPEED_CFG_VALUE_100G	UINT32_C(0x2)
90774 	#define HWRM_MFG_OTP_CFG_INPUT_MAX_SPEED_CFG_VALUE_200G	UINT32_C(0x3)
90824 	 * * 0x0-0xFFF8 - The function ID
90825 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90826 	 * * 0xFFFD - Reserved for user-space HWRM interface
90827 	 * * 0xFFFF - HWRM
90842 	#define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_CRID		UINT32_C(0x1)
90847 	#define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_SRT_REV_ID	UINT32_C(0x2)
90852 	#define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_CRT_REV_ID	UINT32_C(0x4)
90857 	#define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_SBI_REV_ID	UINT32_C(0x8)
90862 	#define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_MAX_SPEED_SELECT	UINT32_C(0x10)
90893 	#define HWRM_MFG_OTP_QCFG_OUTPUT_MAX_SPEED_NOT_CONFIGURED UINT32_C(0x0)
90895 	#define HWRM_MFG_OTP_QCFG_OUTPUT_MAX_SPEED_50G		UINT32_C(0x1)
90897 	#define HWRM_MFG_OTP_QCFG_OUTPUT_MAX_SPEED_100G	UINT32_C(0x2)
90899 	#define HWRM_MFG_OTP_QCFG_OUTPUT_MAX_SPEED_200G	UINT32_C(0x3)
90904 	#define HWRM_MFG_OTP_QCFG_OUTPUT_ENABLES_BITMAP_MAX_SPEED	UINT32_C(0x10)
90906 	#define HWRM_MFG_OTP_QCFG_OUTPUT_ENABLES_BITMAP_ENABLES_VALID	UINT32_C(0x8000)
90941 	 * * 0x0-0xFFF8 - The function ID
90942 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90943 	 * * 0xFFFD - Reserved for user-space HWRM interface
90944 	 * * 0xFFFF - HWRM
90970 	#define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_INCREMENTAL UINT32_C(0x1)
90972 	#define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_FIXED	UINT32_C(0x2)
90974 	#define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_RANDOM	UINT32_C(0x3)
91025 	 * * 0x0-0xFFF8 - The function ID
91026 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91027 	 * * 0xFFFD - Reserved for user-space HWRM interface
91028 	 * * 0xFFFF - HWRM
91044 	/* i2c slave address. If set to 0xffff, fw will decide what to use. */
91101 	 * * 0x0-0xFFF8 - The function ID
91102 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91103 	 * * 0xFFFD - Reserved for user-space HWRM interface
91104 	 * * 0xFFFF - HWRM
91120 	/* i2c slave address. If set to 0xffff, fw will decide what to use. */
91181 	 * * 0x0-0xFFF8 - The function ID
91182 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91183 	 * * 0xFFFD - Reserved for user-space HWRM interface
91184 	 * * 0xFFFF - HWRM
91233 	 * field is optional. When set to 0, the SoC will determine the
91242 	#define HWRM_MFG_SOC_IMAGE_INPUT_FLAGS_START	UINT32_C(0x1)
91247 	#define HWRM_MFG_SOC_IMAGE_INPUT_FLAGS_END	UINT32_C(0x2)
91253 	 * shall increment this number by 1. The value 0 is used when
91307 	 * * 0x0-0xFFF8 - The function ID
91308 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91309 	 * * 0xFFFD - Reserved for user-space HWRM interface
91310 	 * * 0xFFFF - HWRM
91403 	 * * 0x0-0xFFF8 - The function ID
91404 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91405 	 * * 0xFFFD - Reserved for user-space HWRM interface
91406 	 * * 0xFFFF - HWRM
91421 	#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_INPUT_FLAGS_FORCE	UINT32_C(0x1)
91441 	#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_ALREADY_LOCKED	UINT32_C(0x1)
91443 	#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_NOT_EMPTY		UINT32_C(0x2)
91445 	#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_MISSING_FACT_CFG	UINT32_C(0x4)
91447 	#define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_MISSING_VPD	UINT32_C(0x8)
91482 	 * * 0x0-0xFFF8 - The function ID
91483 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91484 	 * * 0xFFFD - Reserved for user-space HWRM interface
91485 	 * * 0xFFFF - HWRM
91559 	 * * 0x0-0xFFF8 - The function ID
91560 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91561 	 * * 0xFFFD - Reserved for user-space HWRM interface
91562 	 * * 0xFFFF - HWRM
91588 	#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_IS_EMPTY	UINT32_C(0x1)
91590 	#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_CHECKSUM_FAIL	UINT32_C(0x2)
91592 	#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_MALFORMED_DATA	UINT32_C(0x4)
91594 	#define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_NOT_LOCKED	UINT32_C(0x8)
91630 	 * * 0x0-0xFFF8 - The function ID
91631 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91632 	 * * 0xFFFD - Reserved for user-space HWRM interface
91633 	 * * 0xFFFF - HWRM
91648 	/* Provisioning slot number. 0-indexed. */
91660 	#define HWRM_MFG_PRVSN_EXPORT_CSR_INPUT_FLAGS_SECURE_SOC_SUPPORT	UINT32_C(0x1)
91675 	/* Provisioning slot number. 0-indexed. */
91701 	#define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_UNKNOWN	UINT32_C(0x0)
91703 	#define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_SLOT_INVALID  UINT32_C(0x1)
91705 	#define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_BUFFER_LENGTH UINT32_C(0x2)
91733 	 * * 0x0-0xFFF8 - The function ID
91734 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91735 	 * * 0xFFFD - Reserved for user-space HWRM interface
91736 	 * * 0xFFFF - HWRM
91751 	/* Provisioning slot number. 0-indexed. */
91763 	#define HWRM_MFG_PRVSN_IMPORT_CERT_INPUT_FLAGS_SECURE_SOC_SUPPORT	UINT32_C(0x1)
91778 	/* Provisioning slot number. 0-indexed. */
91783 	#define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_NOT_PROVISIONED UINT32_C(0x0)
91785 	#define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_PROVISIONED	UINT32_C(0x1)
91808 	#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_UNKNOWN		UINT32_C(0x0)
91810 	#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_SLOT_INVALID	UINT32_C(0x1)
91812 	#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_SLOT_LOCKED	UINT32_C(0x2)
91814 	#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_STORAGE		UINT32_C(0x3)
91816 	#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_CERT_VERIFY_FAIL	UINT32_C(0x4)
91818 	#define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_SIGNED_DEVICE_CERT UINT32_C(0x5)
91846 	 * * 0x0-0xFFF8 - The function ID
91847 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91848 	 * * 0xFFFD - Reserved for user-space HWRM interface
91849 	 * * 0xFFFF - HWRM
91880 	#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_INVALID  UINT32_C(0x0)
91882 	#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_SPDM	UINT32_C(0x1)
91884 	#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_CERBERUS UINT32_C(0x2)
91886 	#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_NONE	UINT32_C(0xff)
91892 	 * The slot_status field is undetermined if get_state_valid = 0.
91896 	#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_MASK	UINT32_C(0xff)
91897 	#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_SFT		0
91899 		#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_NOT_PROVISIONED  UINT32_C(0x0)
91904 		#define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_PROVISIONED	UINT32_C(0x1)
91941 	 * * 0x0-0xFFF8 - The function ID
91942 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91943 	 * * 0xFFFD - Reserved for user-space HWRM interface
91944 	 * * 0xFFFF - HWRM
91959 	/* Provisioning slot number. 0-indexed. */
91971 	#define HWRM_MFG_PRVSN_EXPORT_CERT_INPUT_FLAGS_SECURE_SOC_SUPPORT	UINT32_C(0x1)
91986 	/* Provisioning slot number. 0-indexed. */
91992 	 * return a successful response with cert_len equal to 0.
92016 	#define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_UNKNOWN	UINT32_C(0x0)
92018 	#define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_SLOT_INVALID  UINT32_C(0x1)
92023 	#define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_CERT_INVALID  UINT32_C(0x2)
92025 	#define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_BUFFER_LENGTH UINT32_C(0x3)
92053 	 * * 0x0-0xFFF8 - The function ID
92054 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92055 	 * * 0xFFFD - Reserved for user-space HWRM interface
92056 	 * * 0xFFFF - HWRM
92086 	#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_INVALID UINT32_C(0x0)
92088 	#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_VALID   UINT32_C(0x1)
92096 	#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_BOOTUP UINT32_C(0x0)
92098 	#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_LIVE   UINT32_C(0x1)
92103 	#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_TYPE_SHA256 UINT32_C(0x0)
92105 	#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_TYPE_SHA384 UINT32_C(0x1)
92107 	#define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_TYPE_SHA512 UINT32_C(0x2)
92147 	 * * 0x0-0xFFF8 - The function ID
92148 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92149 	 * * 0xFFFD - Reserved for user-space HWRM interface
92150 	 * * 0xFFFF - HWRM
92177 	/* PBL version info. Start at 0, roll if change in structure */
92238 	 * * 0x0-0xFFF8 - The function ID
92239 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92240 	 * * 0xFFFD - Reserved for user-space HWRM interface
92241 	 * * 0xFFFF - HWRM
92275 	#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PERIPHERAL_TEST	UINT32_C(0x1)
92287 	#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_CO_CPU_MEMORY	UINT32_C(0x1)
92289 	#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_DPLL_EEPROM	UINT32_C(0x2)
92291 	#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_DPLL_MMCX	UINT32_C(0x4)
92293 	#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_GNSS		UINT32_C(0x8)
92295 	#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_CO_CPU_PCIE	UINT32_C(0x10)
92297 	#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_INTERNAL_FABRIC	UINT32_C(0x20)
92299 	#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_OCXO		UINT32_C(0x40)
92301 	#define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_TELECOM_PLL	UINT32_C(0x80)
92336 	 * * 0x0-0xFFF8 - The function ID
92337 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92338 	 * * 0xFFFD - Reserved for user-space HWRM interface
92339 	 * * 0xFFFF - HWRM
92355 	#define HWRM_MFG_SELFTEST_EXEC_INPUT_FLAGS_PERIPHERAL_TEST	UINT32_C(0x1)
92363 	#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_CO_CPU_MEMORY	UINT32_C(0x1)
92365 	#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_DPLL_EEPROM	UINT32_C(0x2)
92367 	#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_DPLL_MMCX	UINT32_C(0x4)
92369 	#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_GNSS		UINT32_C(0x8)
92371 	#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_CO_CPU_PCIE	UINT32_C(0x10)
92373 	#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_INTERNAL_FABRIC	UINT32_C(0x20)
92375 	#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_OCXO		UINT32_C(0x40)
92377 	#define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_TELECOM_PLL	UINT32_C(0x80)
92394 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PERIPHERAL_TEST	UINT32_C(0x1)
92398 	 * failed(0).
92405 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PERIPHERAL_TEST	UINT32_C(0x1)
92414 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_CO_CPU_MEMORY	UINT32_C(0x1)
92416 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_DPLL_EEPROM	UINT32_C(0x2)
92418 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_DPLL_MMCX	UINT32_C(0x4)
92420 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_GNSS		UINT32_C(0x8)
92422 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_CO_CPU_PCIE	UINT32_C(0x10)
92424 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_INTERNAL_FABRIC	UINT32_C(0x20)
92426 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_OCXO		UINT32_C(0x40)
92428 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_TELECOM_PLL	UINT32_C(0x80)
92436 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_CO_CPU_MEMORY	UINT32_C(0x1)
92438 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_DPLL_EEPROM	UINT32_C(0x2)
92440 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_DPLL_MMCX	UINT32_C(0x4)
92442 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_GNSS		UINT32_C(0x8)
92444 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_CO_CPU_PCIE	UINT32_C(0x10)
92446 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_INTERNAL_FABRIC	UINT32_C(0x20)
92451 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_OCXO		UINT32_C(0x40)
92453 	#define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_TELECOM_PLL	UINT32_C(0x80)
92488 	 * * 0x0-0xFFF8 - The function ID
92489 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92490 	 * * 0xFFFD - Reserved for user-space HWRM interface
92491 	 * * 0xFFFF - HWRM
92503 	 * to 0x14e4 when used for Broadcom internal use when
92510 	#define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_INVALID UINT32_C(0x0)
92512 	#define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG UINT32_C(0x1)
92517 	#define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_INVALID UINT32_C(0x0)
92519 	#define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW UINT32_C(0x1)
92521 	#define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_ROCE	UINT32_C(0x2)
92582 	 * * 0x0-0xFFF8 - The function ID
92583 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92584 	 * * 0xFFFD - Reserved for user-space HWRM interface
92585 	 * * 0xFFFF - HWRM
92635 	 * * 0x0-0xFFF8 - The function ID
92636 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92637 	 * * 0xFFFD - Reserved for user-space HWRM interface
92638 	 * * 0xFFFF - HWRM
92677 	#define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_DESTINATION UINT32_C(0x0)
92679 	#define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_QP	UINT32_C(0x1)
92729 	 * * 0x0-0xFFF8 - The function ID
92730 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92731 	 * * 0xFFFD - Reserved for user-space HWRM interface
92732 	 * * 0xFFFF - HWRM
92747 	#define HWRM_UDCC_CFG_INPUT_ENABLES_UDCC_MODE	UINT32_C(0x1)
92751 	#define HWRM_UDCC_CFG_INPUT_UDCC_MODE_DISABLED UINT32_C(0x0)
92753 	#define HWRM_UDCC_CFG_INPUT_UDCC_MODE_ENABLED  UINT32_C(0x1)
92803 	 * * 0x0-0xFFF8 - The function ID
92804 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92805 	 * * 0xFFFD - Reserved for user-space HWRM interface
92806 	 * * 0xFFFF - HWRM
92865 	 * * 0x0-0xFFF8 - The function ID
92866 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92867 	 * * 0xFFFD - Reserved for user-space HWRM interface
92868 	 * * 0xFFFF - HWRM
92880 	#define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_SESSION_STATE	UINT32_C(0x1)
92882 	#define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_DEST_MAC		UINT32_C(0x2)
92884 	#define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_SRC_MAC		UINT32_C(0x4)
92886 	#define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_TX_STATS_RECORD	UINT32_C(0x8)
92888 	#define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_RX_STATS_RECORD	UINT32_C(0x10)
92896 	#define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_ENABLED		UINT32_C(0x1)
92898 	#define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_FLOW_NOT_CREATED	UINT32_C(0x2)
92900 	#define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_FLOW_HAS_BEEN_DELETED	UINT32_C(0x4)
92967 	 * * 0x0-0xFFF8 - The function ID
92968 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
92969 	 * * 0xFFFD - Reserved for user-space HWRM interface
92970 	 * * 0xFFFF - HWRM
93003 	#define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_ENABLED		UINT32_C(0x1)
93005 	#define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_FLOW_NOT_CREATED	UINT32_C(0x2)
93007 	#define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_FLOW_HAS_BEEN_DELETED	UINT32_C(0x4)
93068 	 * * 0x0-0xFFF8 - The function ID
93069 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
93070 	 * * 0xFFFD - Reserved for user-space HWRM interface
93071 	 * * 0xFFFF - HWRM
93178 	 * * 0x0-0xFFF8 - The function ID
93179 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
93180 	 * * 0xFFFD - Reserved for user-space HWRM interface
93181 	 * * 0xFFFF - HWRM
93265 	 * * 0x0-0xFFF8 - The function ID
93266 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
93267 	 * * 0xFFFD - Reserved for user-space HWRM interface
93268 	 * * 0xFFFF - HWRM
93358 	 * * 0x0-0xFFF8 - The function ID
93359 	 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
93360 	 * * 0xFFFD - Reserved for user-space HWRM interface
93361 	 * * 0xFFFF - HWRM