Lines Matching +full:0 +full:x422
71 * * 0x0-0xFFF8 - The function ID
72 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
73 * * 0xFFFD - Reserved for user-space HWRM interface
74 * * 0xFFFF - HWRM
104 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
109 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
111 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
113 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
115 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
117 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
119 #define TLV_TYPE_QUERY_ROCE_CC_GEN2 UINT32_C(0x6)
121 #define TLV_TYPE_MODIFY_ROCE_CC_GEN2 UINT32_C(0x7)
123 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY UINT32_C(0x8001)
125 #define TLV_TYPE_ENGINE_CKV_IV UINT32_C(0x8003)
127 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG UINT32_C(0x8004)
129 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT UINT32_C(0x8005)
131 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS UINT32_C(0x8006)
133 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY UINT32_C(0x8007)
135 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE UINT32_C(0x8008)
137 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY UINT32_C(0x8009)
139 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS UINT32_C(0x800a)
151 * For TLV encapsulated messages this field must be 0x8000.
160 #define TLV_FLAGS_MORE UINT32_C(0x1)
162 #define TLV_FLAGS_MORE_LAST UINT32_C(0x0)
164 #define TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
171 #define TLV_FLAGS_REQUIRED UINT32_C(0x2)
173 #define TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
175 #define TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
186 * Global TLV range: `0 - (63k-1)`
220 * 0x0 - 0xFFF8 - Used for function ids
221 * 0xFFF8 - 0xFFFE - Reserved for internal processors
222 * 0xFFFF - HWRM
270 * 17185 (0x4321).
274 #define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
278 /* Default target_id (0x0) to maintain compatibility with old driver */
279 #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
281 #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
293 (((x) < 0x80) ? \
294 ((x) == 0x0 ? "HWRM_VER_GET": \
295 ((x) == 0xb ? "HWRM_FUNC_ECHO_RESPONSE": \
296 ((x) == 0xc ? "HWRM_ERROR_RECOVERY_QCFG": \
297 ((x) == 0xd ? "HWRM_FUNC_DRV_IF_CHANGE": \
298 ((x) == 0xe ? "HWRM_FUNC_BUF_UNRGTR": \
299 ((x) == 0xf ? "HWRM_FUNC_VF_CFG": \
300 ((x) == 0x10 ? "HWRM_RESERVED1": \
301 ((x) == 0x11 ? "HWRM_FUNC_RESET": \
302 ((x) == 0x12 ? "HWRM_FUNC_GETFID": \
303 ((x) == 0x13 ? "HWRM_FUNC_VF_ALLOC": \
304 ((x) == 0x14 ? "HWRM_FUNC_VF_FREE": \
305 ((x) == 0x15 ? "HWRM_FUNC_QCAPS": \
306 ((x) == 0x16 ? "HWRM_FUNC_QCFG": \
307 ((x) == 0x17 ? "HWRM_FUNC_CFG": \
308 ((x) == 0x18 ? "HWRM_FUNC_QSTATS": \
309 ((x) == 0x19 ? "HWRM_FUNC_CLR_STATS": \
310 ((x) == 0x1a ? "HWRM_FUNC_DRV_UNRGTR": \
311 ((x) == 0x1b ? "HWRM_FUNC_VF_RESC_FREE": \
312 ((x) == 0x1c ? "HWRM_FUNC_VF_VNIC_IDS_QUERY": \
313 ((x) == 0x1d ? "HWRM_FUNC_DRV_RGTR": \
314 ((x) == 0x1e ? "HWRM_FUNC_DRV_QVER": \
315 ((x) == 0x1f ? "HWRM_FUNC_BUF_RGTR": \
316 ((x) == 0x20 ? "HWRM_PORT_PHY_CFG": \
317 ((x) == 0x21 ? "HWRM_PORT_MAC_CFG": \
318 ((x) == 0x22 ? "HWRM_PORT_TS_QUERY": \
319 ((x) == 0x23 ? "HWRM_PORT_QSTATS": \
320 ((x) == 0x24 ? "HWRM_PORT_LPBK_QSTATS": \
321 ((x) == 0x25 ? "HWRM_PORT_CLR_STATS": \
322 ((x) == 0x26 ? "HWRM_PORT_LPBK_CLR_STATS": \
323 ((x) == 0x27 ? "HWRM_PORT_PHY_QCFG": \
324 ((x) == 0x28 ? "HWRM_PORT_MAC_QCFG": \
325 ((x) == 0x29 ? "HWRM_PORT_MAC_PTP_QCFG": \
326 ((x) == 0x2a ? "HWRM_PORT_PHY_QCAPS": \
327 ((x) == 0x2b ? "HWRM_PORT_PHY_I2C_WRITE": \
328 ((x) == 0x2c ? "HWRM_PORT_PHY_I2C_READ": \
329 ((x) == 0x2d ? "HWRM_PORT_LED_CFG": \
330 ((x) == 0x2e ? "HWRM_PORT_LED_QCFG": \
331 ((x) == 0x2f ? "HWRM_PORT_LED_QCAPS": \
332 ((x) == 0x30 ? "HWRM_QUEUE_QPORTCFG": \
333 ((x) == 0x31 ? "HWRM_QUEUE_QCFG": \
334 ((x) == 0x32 ? "HWRM_QUEUE_CFG": \
335 ((x) == 0x33 ? "HWRM_FUNC_VLAN_CFG": \
336 ((x) == 0x34 ? "HWRM_FUNC_VLAN_QCFG": \
337 ((x) == 0x35 ? "HWRM_QUEUE_PFCENABLE_QCFG": \
338 ((x) == 0x36 ? "HWRM_QUEUE_PFCENABLE_CFG": \
339 ((x) == 0x37 ? "HWRM_QUEUE_PRI2COS_QCFG": \
340 ((x) == 0x38 ? "HWRM_QUEUE_PRI2COS_CFG": \
341 ((x) == 0x39 ? "HWRM_QUEUE_COS2BW_QCFG": \
342 ((x) == 0x3a ? "HWRM_QUEUE_COS2BW_CFG": \
343 ((x) == 0x3b ? "HWRM_QUEUE_DSCP_QCAPS": \
344 ((x) == 0x3c ? "HWRM_QUEUE_DSCP2PRI_QCFG": \
345 ((x) == 0x3d ? "HWRM_QUEUE_DSCP2PRI_CFG": \
346 ((x) == 0x40 ? "HWRM_VNIC_ALLOC": \
347 ((x) == 0x41 ? "HWRM_VNIC_FREE": \
348 ((x) == 0x42 ? "HWRM_VNIC_CFG": \
349 ((x) == 0x43 ? "HWRM_VNIC_QCFG": \
350 ((x) == 0x44 ? "HWRM_VNIC_TPA_CFG": \
351 ((x) == 0x45 ? "HWRM_VNIC_TPA_QCFG": \
352 ((x) == 0x46 ? "HWRM_VNIC_RSS_CFG": \
353 ((x) == 0x47 ? "HWRM_VNIC_RSS_QCFG": \
354 ((x) == 0x48 ? "HWRM_VNIC_PLCMODES_CFG": \
355 ((x) == 0x49 ? "HWRM_VNIC_PLCMODES_QCFG": \
356 ((x) == 0x4a ? "HWRM_VNIC_QCAPS": \
357 ((x) == 0x4b ? "HWRM_VNIC_UPDATE": \
358 ((x) == 0x50 ? "HWRM_RING_ALLOC": \
359 ((x) == 0x51 ? "HWRM_RING_FREE": \
360 ((x) == 0x52 ? "HWRM_RING_CMPL_RING_QAGGINT_PARAMS": \
361 ((x) == 0x53 ? "HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS": \
362 ((x) == 0x54 ? "HWRM_RING_AGGINT_QCAPS": \
363 ((x) == 0x55 ? "HWRM_RING_SCHQ_ALLOC": \
364 ((x) == 0x56 ? "HWRM_RING_SCHQ_CFG": \
365 ((x) == 0x57 ? "HWRM_RING_SCHQ_FREE": \
366 ((x) == 0x5e ? "HWRM_RING_RESET": \
367 ((x) == 0x60 ? "HWRM_RING_GRP_ALLOC": \
368 ((x) == 0x61 ? "HWRM_RING_GRP_FREE": \
369 ((x) == 0x62 ? "HWRM_RING_CFG": \
370 ((x) == 0x63 ? "HWRM_RING_QCFG": \
371 ((x) == 0x64 ? "HWRM_RESERVED5": \
372 ((x) == 0x65 ? "HWRM_RESERVED6": \
373 ((x) == 0x70 ? "HWRM_VNIC_RSS_COS_LB_CTX_ALLOC": \
374 ((x) == 0x71 ? "HWRM_VNIC_RSS_COS_LB_CTX_FREE": \
376 (((x) < 0x100) ? \
377 ((x) == 0x80 ? "HWRM_QUEUE_MPLS_QCAPS": \
378 ((x) == 0x81 ? "HWRM_QUEUE_MPLSTC2PRI_QCFG": \
379 ((x) == 0x82 ? "HWRM_QUEUE_MPLSTC2PRI_CFG": \
380 ((x) == 0x83 ? "HWRM_QUEUE_VLANPRI_QCAPS": \
381 ((x) == 0x84 ? "HWRM_QUEUE_VLANPRI2PRI_QCFG": \
382 ((x) == 0x85 ? "HWRM_QUEUE_VLANPRI2PRI_CFG": \
383 ((x) == 0x86 ? "HWRM_QUEUE_GLOBAL_CFG": \
384 ((x) == 0x87 ? "HWRM_QUEUE_GLOBAL_QCFG": \
385 ((x) == 0x88 ? "HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG": \
386 ((x) == 0x89 ? "HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG": \
387 ((x) == 0x8a ? "HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG": \
388 ((x) == 0x8b ? "HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG": \
389 ((x) == 0x8c ? "HWRM_QUEUE_QCAPS": \
390 ((x) == 0x8d ? "HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG": \
391 ((x) == 0x8e ? "HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG": \
392 ((x) == 0x8f ? "HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG": \
393 ((x) == 0x90 ? "HWRM_CFA_L2_FILTER_ALLOC": \
394 ((x) == 0x91 ? "HWRM_CFA_L2_FILTER_FREE": \
395 ((x) == 0x92 ? "HWRM_CFA_L2_FILTER_CFG": \
396 ((x) == 0x93 ? "HWRM_CFA_L2_SET_RX_MASK": \
397 ((x) == 0x94 ? "HWRM_CFA_VLAN_ANTISPOOF_CFG": \
398 ((x) == 0x95 ? "HWRM_CFA_TUNNEL_FILTER_ALLOC": \
399 ((x) == 0x96 ? "HWRM_CFA_TUNNEL_FILTER_FREE": \
400 ((x) == 0x97 ? "HWRM_CFA_ENCAP_RECORD_ALLOC": \
401 ((x) == 0x98 ? "HWRM_CFA_ENCAP_RECORD_FREE": \
402 ((x) == 0x99 ? "HWRM_CFA_NTUPLE_FILTER_ALLOC": \
403 ((x) == 0x9a ? "HWRM_CFA_NTUPLE_FILTER_FREE": \
404 ((x) == 0x9b ? "HWRM_CFA_NTUPLE_FILTER_CFG": \
405 ((x) == 0x9c ? "HWRM_CFA_EM_FLOW_ALLOC": \
406 ((x) == 0x9d ? "HWRM_CFA_EM_FLOW_FREE": \
407 ((x) == 0x9e ? "HWRM_CFA_EM_FLOW_CFG": \
408 ((x) == 0xa0 ? "HWRM_TUNNEL_DST_PORT_QUERY": \
409 ((x) == 0xa1 ? "HWRM_TUNNEL_DST_PORT_ALLOC": \
410 ((x) == 0xa2 ? "HWRM_TUNNEL_DST_PORT_FREE": \
411 ((x) == 0xa3 ? "HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG": \
412 ((x) == 0xaf ? "HWRM_STAT_CTX_ENG_QUERY": \
413 ((x) == 0xb0 ? "HWRM_STAT_CTX_ALLOC": \
414 ((x) == 0xb1 ? "HWRM_STAT_CTX_FREE": \
415 ((x) == 0xb2 ? "HWRM_STAT_CTX_QUERY": \
416 ((x) == 0xb3 ? "HWRM_STAT_CTX_CLR_STATS": \
417 ((x) == 0xb4 ? "HWRM_PORT_QSTATS_EXT": \
418 ((x) == 0xb5 ? "HWRM_PORT_PHY_MDIO_WRITE": \
419 ((x) == 0xb6 ? "HWRM_PORT_PHY_MDIO_READ": \
420 ((x) == 0xb7 ? "HWRM_PORT_PHY_MDIO_BUS_ACQUIRE": \
421 ((x) == 0xb8 ? "HWRM_PORT_PHY_MDIO_BUS_RELEASE": \
422 ((x) == 0xb9 ? "HWRM_PORT_QSTATS_EXT_PFC_WD": \
423 ((x) == 0xba ? "HWRM_RESERVED7": \
424 ((x) == 0xbb ? "HWRM_PORT_TX_FIR_CFG": \
425 ((x) == 0xbc ? "HWRM_PORT_TX_FIR_QCFG": \
426 ((x) == 0xbd ? "HWRM_PORT_ECN_QSTATS": \
427 ((x) == 0xbe ? "HWRM_FW_LIVEPATCH_QUERY": \
428 ((x) == 0xbf ? "HWRM_FW_LIVEPATCH": \
429 ((x) == 0xc0 ? "HWRM_FW_RESET": \
430 ((x) == 0xc1 ? "HWRM_FW_QSTATUS": \
431 ((x) == 0xc2 ? "HWRM_FW_HEALTH_CHECK": \
432 ((x) == 0xc3 ? "HWRM_FW_SYNC": \
433 ((x) == 0xc4 ? "HWRM_FW_STATE_QCAPS": \
434 ((x) == 0xc5 ? "HWRM_FW_STATE_QUIESCE": \
435 ((x) == 0xc6 ? "HWRM_FW_STATE_BACKUP": \
436 ((x) == 0xc7 ? "HWRM_FW_STATE_RESTORE": \
437 ((x) == 0xc8 ? "HWRM_FW_SET_TIME": \
438 ((x) == 0xc9 ? "HWRM_FW_GET_TIME": \
439 ((x) == 0xca ? "HWRM_FW_SET_STRUCTURED_DATA": \
440 ((x) == 0xcb ? "HWRM_FW_GET_STRUCTURED_DATA": \
441 ((x) == 0xcc ? "HWRM_FW_IPC_MAILBOX": \
442 ((x) == 0xcd ? "HWRM_FW_ECN_CFG": \
443 ((x) == 0xce ? "HWRM_FW_ECN_QCFG": \
444 ((x) == 0xcf ? "HWRM_FW_SECURE_CFG": \
445 ((x) == 0xd0 ? "HWRM_EXEC_FWD_RESP": \
446 ((x) == 0xd1 ? "HWRM_REJECT_FWD_RESP": \
447 ((x) == 0xd2 ? "HWRM_FWD_RESP": \
448 ((x) == 0xd3 ? "HWRM_FWD_ASYNC_EVENT_CMPL": \
449 ((x) == 0xd4 ? "HWRM_OEM_CMD": \
450 ((x) == 0xd5 ? "HWRM_PORT_PRBS_TEST": \
451 ((x) == 0xd6 ? "HWRM_PORT_SFP_SIDEBAND_CFG": \
452 ((x) == 0xd7 ? "HWRM_PORT_SFP_SIDEBAND_QCFG": \
453 ((x) == 0xd8 ? "HWRM_FW_STATE_UNQUIESCE": \
454 ((x) == 0xd9 ? "HWRM_PORT_DSC_DUMP": \
455 ((x) == 0xda ? "HWRM_PORT_EP_TX_QCFG": \
456 ((x) == 0xdb ? "HWRM_PORT_EP_TX_CFG": \
457 ((x) == 0xdc ? "HWRM_PORT_CFG": \
458 ((x) == 0xdd ? "HWRM_PORT_QCFG": \
459 ((x) == 0xdf ? "HWRM_PORT_MAC_QCAPS": \
460 ((x) == 0xe0 ? "HWRM_TEMP_MONITOR_QUERY": \
461 ((x) == 0xe1 ? "HWRM_REG_POWER_QUERY": \
462 ((x) == 0xe2 ? "HWRM_CORE_FREQUENCY_QUERY": \
463 ((x) == 0xe3 ? "HWRM_REG_POWER_HISTOGRAM": \
464 ((x) == 0xf0 ? "HWRM_WOL_FILTER_ALLOC": \
465 ((x) == 0xf1 ? "HWRM_WOL_FILTER_FREE": \
466 ((x) == 0xf2 ? "HWRM_WOL_FILTER_QCFG": \
467 ((x) == 0xf3 ? "HWRM_WOL_REASON_QCFG": \
468 ((x) == 0xf4 ? "HWRM_CFA_METER_QCAPS": \
469 ((x) == 0xf5 ? "HWRM_CFA_METER_PROFILE_ALLOC": \
470 ((x) == 0xf6 ? "HWRM_CFA_METER_PROFILE_FREE": \
471 ((x) == 0xf7 ? "HWRM_CFA_METER_PROFILE_CFG": \
472 ((x) == 0xf8 ? "HWRM_CFA_METER_INSTANCE_ALLOC": \
473 ((x) == 0xf9 ? "HWRM_CFA_METER_INSTANCE_FREE": \
474 ((x) == 0xfa ? "HWRM_CFA_METER_INSTANCE_CFG": \
475 ((x) == 0xfd ? "HWRM_CFA_VFR_ALLOC": \
476 ((x) == 0xfe ? "HWRM_CFA_VFR_FREE": \
478 (((x) < 0x180) ? \
479 ((x) == 0x100 ? "HWRM_CFA_VF_PAIR_ALLOC": \
480 ((x) == 0x101 ? "HWRM_CFA_VF_PAIR_FREE": \
481 ((x) == 0x102 ? "HWRM_CFA_VF_PAIR_INFO": \
482 ((x) == 0x103 ? "HWRM_CFA_FLOW_ALLOC": \
483 ((x) == 0x104 ? "HWRM_CFA_FLOW_FREE": \
484 ((x) == 0x105 ? "HWRM_CFA_FLOW_FLUSH": \
485 ((x) == 0x106 ? "HWRM_CFA_FLOW_STATS": \
486 ((x) == 0x107 ? "HWRM_CFA_FLOW_INFO": \
487 ((x) == 0x108 ? "HWRM_CFA_DECAP_FILTER_ALLOC": \
488 ((x) == 0x109 ? "HWRM_CFA_DECAP_FILTER_FREE": \
489 ((x) == 0x10a ? "HWRM_CFA_VLAN_ANTISPOOF_QCFG": \
490 ((x) == 0x10b ? "HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC": \
491 ((x) == 0x10c ? "HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE": \
492 ((x) == 0x10d ? "HWRM_CFA_PAIR_ALLOC": \
493 ((x) == 0x10e ? "HWRM_CFA_PAIR_FREE": \
494 ((x) == 0x10f ? "HWRM_CFA_PAIR_INFO": \
495 ((x) == 0x110 ? "HWRM_FW_IPC_MSG": \
496 ((x) == 0x111 ? "HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO": \
497 ((x) == 0x112 ? "HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE": \
498 ((x) == 0x113 ? "HWRM_CFA_FLOW_AGING_TIMER_RESET": \
499 ((x) == 0x114 ? "HWRM_CFA_FLOW_AGING_CFG": \
500 ((x) == 0x115 ? "HWRM_CFA_FLOW_AGING_QCFG": \
501 ((x) == 0x116 ? "HWRM_CFA_FLOW_AGING_QCAPS": \
502 ((x) == 0x117 ? "HWRM_CFA_CTX_MEM_RGTR": \
503 ((x) == 0x118 ? "HWRM_CFA_CTX_MEM_UNRGTR": \
504 ((x) == 0x119 ? "HWRM_CFA_CTX_MEM_QCTX": \
505 ((x) == 0x11a ? "HWRM_CFA_CTX_MEM_QCAPS": \
506 ((x) == 0x11b ? "HWRM_CFA_COUNTER_QCAPS": \
507 ((x) == 0x11c ? "HWRM_CFA_COUNTER_CFG": \
508 ((x) == 0x11d ? "HWRM_CFA_COUNTER_QCFG": \
509 ((x) == 0x11e ? "HWRM_CFA_COUNTER_QSTATS": \
510 ((x) == 0x11f ? "HWRM_CFA_TCP_FLAG_PROCESS_QCFG": \
511 ((x) == 0x120 ? "HWRM_CFA_EEM_QCAPS": \
512 ((x) == 0x121 ? "HWRM_CFA_EEM_CFG": \
513 ((x) == 0x122 ? "HWRM_CFA_EEM_QCFG": \
514 ((x) == 0x123 ? "HWRM_CFA_EEM_OP": \
515 ((x) == 0x124 ? "HWRM_CFA_ADV_FLOW_MGNT_QCAPS": \
516 ((x) == 0x125 ? "HWRM_CFA_TFLIB": \
517 ((x) == 0x126 ? "HWRM_CFA_LAG_GROUP_MEMBER_RGTR": \
518 ((x) == 0x127 ? "HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR": \
519 ((x) == 0x128 ? "HWRM_CFA_TLS_FILTER_ALLOC": \
520 ((x) == 0x129 ? "HWRM_CFA_TLS_FILTER_FREE": \
521 ((x) == 0x12a ? "HWRM_CFA_RELEASE_AFM_FUNC": \
522 ((x) == 0x12e ? "HWRM_ENGINE_CKV_STATUS": \
523 ((x) == 0x12f ? "HWRM_ENGINE_CKV_CKEK_ADD": \
524 ((x) == 0x130 ? "HWRM_ENGINE_CKV_CKEK_DELETE": \
525 ((x) == 0x131 ? "HWRM_ENGINE_CKV_KEY_ADD": \
526 ((x) == 0x132 ? "HWRM_ENGINE_CKV_KEY_DELETE": \
527 ((x) == 0x133 ? "HWRM_ENGINE_CKV_FLUSH": \
528 ((x) == 0x134 ? "HWRM_ENGINE_CKV_RNG_GET": \
529 ((x) == 0x135 ? "HWRM_ENGINE_CKV_KEY_GEN": \
530 ((x) == 0x136 ? "HWRM_ENGINE_CKV_KEY_LABEL_CFG": \
531 ((x) == 0x137 ? "HWRM_ENGINE_CKV_KEY_LABEL_QCFG": \
532 ((x) == 0x13c ? "HWRM_ENGINE_QG_CONFIG_QUERY": \
533 ((x) == 0x13d ? "HWRM_ENGINE_QG_QUERY": \
534 ((x) == 0x13e ? "HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY": \
535 ((x) == 0x13f ? "HWRM_ENGINE_QG_METER_PROFILE_QUERY": \
536 ((x) == 0x140 ? "HWRM_ENGINE_QG_METER_PROFILE_ALLOC": \
537 ((x) == 0x141 ? "HWRM_ENGINE_QG_METER_PROFILE_FREE": \
538 ((x) == 0x142 ? "HWRM_ENGINE_QG_METER_QUERY": \
539 ((x) == 0x143 ? "HWRM_ENGINE_QG_METER_BIND": \
540 ((x) == 0x144 ? "HWRM_ENGINE_QG_METER_UNBIND": \
541 ((x) == 0x145 ? "HWRM_ENGINE_QG_FUNC_BIND": \
542 ((x) == 0x146 ? "HWRM_ENGINE_SG_CONFIG_QUERY": \
543 ((x) == 0x147 ? "HWRM_ENGINE_SG_QUERY": \
544 ((x) == 0x148 ? "HWRM_ENGINE_SG_METER_QUERY": \
545 ((x) == 0x149 ? "HWRM_ENGINE_SG_METER_CONFIG": \
546 ((x) == 0x14a ? "HWRM_ENGINE_SG_QG_BIND": \
547 ((x) == 0x14b ? "HWRM_ENGINE_QG_SG_UNBIND": \
548 ((x) == 0x154 ? "HWRM_ENGINE_CONFIG_QUERY": \
549 ((x) == 0x155 ? "HWRM_ENGINE_STATS_CONFIG": \
550 ((x) == 0x156 ? "HWRM_ENGINE_STATS_CLEAR": \
551 ((x) == 0x157 ? "HWRM_ENGINE_STATS_QUERY": \
552 ((x) == 0x158 ? "HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR": \
553 ((x) == 0x15e ? "HWRM_ENGINE_RQ_ALLOC": \
554 ((x) == 0x15f ? "HWRM_ENGINE_RQ_FREE": \
555 ((x) == 0x160 ? "HWRM_ENGINE_CQ_ALLOC": \
556 ((x) == 0x161 ? "HWRM_ENGINE_CQ_FREE": \
557 ((x) == 0x162 ? "HWRM_ENGINE_NQ_ALLOC": \
558 ((x) == 0x163 ? "HWRM_ENGINE_NQ_FREE": \
559 ((x) == 0x164 ? "HWRM_ENGINE_ON_DIE_RQE_CREDITS": \
560 ((x) == 0x165 ? "HWRM_ENGINE_FUNC_QCFG": \
562 (((x) < 0x200) ? \
563 ((x) == 0x190 ? "HWRM_FUNC_RESOURCE_QCAPS": \
564 ((x) == 0x191 ? "HWRM_FUNC_VF_RESOURCE_CFG": \
565 ((x) == 0x192 ? "HWRM_FUNC_BACKING_STORE_QCAPS": \
566 ((x) == 0x193 ? "HWRM_FUNC_BACKING_STORE_CFG": \
567 ((x) == 0x194 ? "HWRM_FUNC_BACKING_STORE_QCFG": \
568 ((x) == 0x195 ? "HWRM_FUNC_VF_BW_CFG": \
569 ((x) == 0x196 ? "HWRM_FUNC_VF_BW_QCFG": \
570 ((x) == 0x197 ? "HWRM_FUNC_HOST_PF_IDS_QUERY": \
571 ((x) == 0x198 ? "HWRM_FUNC_QSTATS_EXT": \
572 ((x) == 0x199 ? "HWRM_STAT_EXT_CTX_QUERY": \
573 ((x) == 0x19a ? "HWRM_FUNC_SPD_CFG": \
574 ((x) == 0x19b ? "HWRM_FUNC_SPD_QCFG": \
575 ((x) == 0x19c ? "HWRM_FUNC_PTP_PIN_QCFG": \
576 ((x) == 0x19d ? "HWRM_FUNC_PTP_PIN_CFG": \
577 ((x) == 0x19e ? "HWRM_FUNC_PTP_CFG": \
578 ((x) == 0x19f ? "HWRM_FUNC_PTP_TS_QUERY": \
579 ((x) == 0x1a0 ? "HWRM_FUNC_PTP_EXT_CFG": \
580 ((x) == 0x1a1 ? "HWRM_FUNC_PTP_EXT_QCFG": \
581 ((x) == 0x1a2 ? "HWRM_FUNC_KEY_CTX_ALLOC": \
582 ((x) == 0x1a3 ? "HWRM_FUNC_BACKING_STORE_CFG_V2": \
583 ((x) == 0x1a4 ? "HWRM_FUNC_BACKING_STORE_QCFG_V2": \
584 ((x) == 0x1a5 ? "HWRM_FUNC_DBR_PACING_CFG": \
585 ((x) == 0x1a6 ? "HWRM_FUNC_DBR_PACING_QCFG": \
586 ((x) == 0x1a7 ? "HWRM_FUNC_DBR_PACING_BROADCAST_EVENT": \
587 ((x) == 0x1a8 ? "HWRM_FUNC_BACKING_STORE_QCAPS_V2": \
588 ((x) == 0x1a9 ? "HWRM_FUNC_DBR_PACING_NQLIST_QUERY": \
589 ((x) == 0x1aa ? "HWRM_FUNC_DBR_RECOVERY_COMPLETED": \
590 ((x) == 0x1ab ? "HWRM_FUNC_SYNCE_CFG": \
591 ((x) == 0x1ac ? "HWRM_FUNC_SYNCE_QCFG": \
592 ((x) == 0x1ad ? "HWRM_FUNC_KEY_CTX_FREE": \
593 ((x) == 0x1ae ? "HWRM_FUNC_LAG_MODE_CFG": \
594 ((x) == 0x1af ? "HWRM_FUNC_LAG_MODE_QCFG": \
595 ((x) == 0x1b0 ? "HWRM_FUNC_LAG_CREATE": \
596 ((x) == 0x1b1 ? "HWRM_FUNC_LAG_UPDATE": \
597 ((x) == 0x1b2 ? "HWRM_FUNC_LAG_FREE": \
598 ((x) == 0x1b3 ? "HWRM_FUNC_LAG_QCFG": \
600 (((x) < 0x280) ? \
601 ((x) == 0x200 ? "HWRM_SELFTEST_QLIST": \
602 ((x) == 0x201 ? "HWRM_SELFTEST_EXEC": \
603 ((x) == 0x202 ? "HWRM_SELFTEST_IRQ": \
604 ((x) == 0x203 ? "HWRM_SELFTEST_RETRIEVE_SERDES_DATA": \
605 ((x) == 0x204 ? "HWRM_PCIE_QSTATS": \
606 ((x) == 0x205 ? "HWRM_MFG_FRU_WRITE_CONTROL": \
607 ((x) == 0x206 ? "HWRM_MFG_TIMERS_QUERY": \
608 ((x) == 0x207 ? "HWRM_MFG_OTP_CFG": \
609 ((x) == 0x208 ? "HWRM_MFG_OTP_QCFG": \
610 ((x) == 0x209 ? "HWRM_MFG_HDMA_TEST": \
611 ((x) == 0x20a ? "HWRM_MFG_FRU_EEPROM_WRITE": \
612 ((x) == 0x20b ? "HWRM_MFG_FRU_EEPROM_READ": \
613 ((x) == 0x20c ? "HWRM_MFG_SOC_IMAGE": \
614 ((x) == 0x20d ? "HWRM_MFG_SOC_QSTATUS": \
615 ((x) == 0x20e ? "HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE": \
616 ((x) == 0x20f ? "HWRM_MFG_PARAM_CRITICAL_DATA_READ": \
617 ((x) == 0x210 ? "HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH": \
618 ((x) == 0x211 ? "HWRM_MFG_PRVSN_EXPORT_CSR": \
619 ((x) == 0x212 ? "HWRM_MFG_PRVSN_IMPORT_CERT": \
620 ((x) == 0x213 ? "HWRM_MFG_PRVSN_GET_STATE": \
621 ((x) == 0x214 ? "HWRM_MFG_GET_NVM_MEASUREMENT": \
622 ((x) == 0x215 ? "HWRM_MFG_PSOC_QSTATUS": \
623 ((x) == 0x216 ? "HWRM_MFG_SELFTEST_QLIST": \
624 ((x) == 0x217 ? "HWRM_MFG_SELFTEST_EXEC": \
625 ((x) == 0x218 ? "HWRM_STAT_GENERIC_QSTATS": \
626 ((x) == 0x219 ? "HWRM_MFG_PRVSN_EXPORT_CERT": \
627 ((x) == 0x21a ? "HWRM_STAT_DB_ERROR_QSTATS": \
628 ((x) == 0x258 ? "HWRM_UDCC_QCAPS": \
629 ((x) == 0x259 ? "HWRM_UDCC_CFG": \
630 ((x) == 0x25a ? "HWRM_UDCC_QCFG": \
631 ((x) == 0x25b ? "HWRM_UDCC_SESSION_CFG": \
632 ((x) == 0x25c ? "HWRM_UDCC_SESSION_QCFG": \
633 ((x) == 0x25d ? "HWRM_UDCC_SESSION_QUERY": \
634 ((x) == 0x25e ? "HWRM_UDCC_COMP_CFG": \
635 ((x) == 0x25f ? "HWRM_UDCC_COMP_QCFG": \
636 ((x) == 0x260 ? "HWRM_UDCC_COMP_QUERY": \
638 (((x) < 0x300) ? \
639 ((x) == 0x2bc ? "HWRM_TF": \
640 ((x) == 0x2bd ? "HWRM_TF_VERSION_GET": \
641 ((x) == 0x2c6 ? "HWRM_TF_SESSION_OPEN": \
642 ((x) == 0x2c8 ? "HWRM_TF_SESSION_REGISTER": \
643 ((x) == 0x2c9 ? "HWRM_TF_SESSION_UNREGISTER": \
644 ((x) == 0x2ca ? "HWRM_TF_SESSION_CLOSE": \
645 ((x) == 0x2cb ? "HWRM_TF_SESSION_QCFG": \
646 ((x) == 0x2cc ? "HWRM_TF_SESSION_RESC_QCAPS": \
647 ((x) == 0x2cd ? "HWRM_TF_SESSION_RESC_ALLOC": \
648 ((x) == 0x2ce ? "HWRM_TF_SESSION_RESC_FREE": \
649 ((x) == 0x2cf ? "HWRM_TF_SESSION_RESC_FLUSH": \
650 ((x) == 0x2d0 ? "HWRM_TF_SESSION_RESC_INFO": \
651 ((x) == 0x2d1 ? "HWRM_TF_SESSION_HOTUP_STATE_SET": \
652 ((x) == 0x2d2 ? "HWRM_TF_SESSION_HOTUP_STATE_GET": \
653 ((x) == 0x2da ? "HWRM_TF_TBL_TYPE_GET": \
654 ((x) == 0x2db ? "HWRM_TF_TBL_TYPE_SET": \
655 ((x) == 0x2dc ? "HWRM_TF_TBL_TYPE_BULK_GET": \
656 ((x) == 0x2ea ? "HWRM_TF_EM_INSERT": \
657 ((x) == 0x2eb ? "HWRM_TF_EM_DELETE": \
658 ((x) == 0x2ec ? "HWRM_TF_EM_HASH_INSERT": \
659 ((x) == 0x2ed ? "HWRM_TF_EM_MOVE": \
660 ((x) == 0x2f8 ? "HWRM_TF_TCAM_SET": \
661 ((x) == 0x2f9 ? "HWRM_TF_TCAM_GET": \
662 ((x) == 0x2fa ? "HWRM_TF_TCAM_MOVE": \
663 ((x) == 0x2fb ? "HWRM_TF_TCAM_FREE": \
664 ((x) == 0x2fc ? "HWRM_TF_GLOBAL_CFG_SET": \
665 ((x) == 0x2fd ? "HWRM_TF_GLOBAL_CFG_GET": \
666 ((x) == 0x2fe ? "HWRM_TF_IF_TBL_SET": \
667 ((x) == 0x2ff ? "HWRM_TF_IF_TBL_GET": \
669 (((x) < 0x380) ? \
670 ((x) == 0x300 ? "HWRM_TF_RESC_USAGE_SET": \
671 ((x) == 0x301 ? "HWRM_TF_RESC_USAGE_QUERY": \
672 ((x) == 0x302 ? "HWRM_TF_TBL_TYPE_ALLOC": \
673 ((x) == 0x303 ? "HWRM_TF_TBL_TYPE_FREE": \
675 (((x) < 0x400) ? \
676 ((x) == 0x380 ? "HWRM_TFC_TBL_SCOPE_QCAPS": \
677 ((x) == 0x381 ? "HWRM_TFC_TBL_SCOPE_ID_ALLOC": \
678 ((x) == 0x382 ? "HWRM_TFC_TBL_SCOPE_CONFIG": \
679 ((x) == 0x383 ? "HWRM_TFC_TBL_SCOPE_DECONFIG": \
680 ((x) == 0x384 ? "HWRM_TFC_TBL_SCOPE_FID_ADD": \
681 ((x) == 0x385 ? "HWRM_TFC_TBL_SCOPE_FID_REM": \
682 ((x) == 0x386 ? "HWRM_TFC_TBL_SCOPE_POOL_ALLOC": \
683 ((x) == 0x387 ? "HWRM_TFC_TBL_SCOPE_POOL_FREE": \
684 ((x) == 0x388 ? "HWRM_TFC_SESSION_ID_ALLOC": \
685 ((x) == 0x389 ? "HWRM_TFC_SESSION_FID_ADD": \
686 ((x) == 0x38a ? "HWRM_TFC_SESSION_FID_REM": \
687 ((x) == 0x38b ? "HWRM_TFC_IDENT_ALLOC": \
688 ((x) == 0x38c ? "HWRM_TFC_IDENT_FREE": \
689 ((x) == 0x38d ? "HWRM_TFC_IDX_TBL_ALLOC": \
690 ((x) == 0x38e ? "HWRM_TFC_IDX_TBL_ALLOC_SET": \
691 ((x) == 0x38f ? "HWRM_TFC_IDX_TBL_SET": \
692 ((x) == 0x390 ? "HWRM_TFC_IDX_TBL_GET": \
693 ((x) == 0x391 ? "HWRM_TFC_IDX_TBL_FREE": \
694 ((x) == 0x392 ? "HWRM_TFC_GLOBAL_ID_ALLOC": \
695 ((x) == 0x393 ? "HWRM_TFC_TCAM_SET": \
696 ((x) == 0x394 ? "HWRM_TFC_TCAM_GET": \
697 ((x) == 0x395 ? "HWRM_TFC_TCAM_ALLOC": \
698 ((x) == 0x396 ? "HWRM_TFC_TCAM_ALLOC_SET": \
699 ((x) == 0x397 ? "HWRM_TFC_TCAM_FREE": \
700 ((x) == 0x398 ? "HWRM_TFC_IF_TBL_SET": \
701 ((x) == 0x399 ? "HWRM_TFC_IF_TBL_GET": \
702 ((x) == 0x39a ? "HWRM_TFC_TBL_SCOPE_CONFIG_GET": \
703 ((x) == 0x39b ? "HWRM_TFC_RESC_USAGE_QUERY": \
704 ((x) == 0x39c ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS": \
705 ((x) == 0x39d ? "HWRM_QUEUE_PFCWD_TIMEOUT_CFG": \
706 ((x) == 0x39e ? "HWRM_QUEUE_PFCWD_TIMEOUT_QCFG": \
708 (((x) < 0x480) ? \
709 ((x) == 0x400 ? "HWRM_SV": \
711 (((x) < 0xff80) ? \
712 ((x) == 0xff0f ? "HWRM_DBG_LOG_BUFFER_FLUSH": \
713 ((x) == 0xff10 ? "HWRM_DBG_READ_DIRECT": \
714 ((x) == 0xff11 ? "HWRM_DBG_READ_INDIRECT": \
715 ((x) == 0xff12 ? "HWRM_DBG_WRITE_DIRECT": \
716 ((x) == 0xff13 ? "HWRM_DBG_WRITE_INDIRECT": \
717 ((x) == 0xff14 ? "HWRM_DBG_DUMP": \
718 ((x) == 0xff15 ? "HWRM_DBG_ERASE_NVM": \
719 ((x) == 0xff16 ? "HWRM_DBG_CFG": \
720 ((x) == 0xff17 ? "HWRM_DBG_COREDUMP_LIST": \
721 ((x) == 0xff18 ? "HWRM_DBG_COREDUMP_INITIATE": \
722 ((x) == 0xff19 ? "HWRM_DBG_COREDUMP_RETRIEVE": \
723 ((x) == 0xff1a ? "HWRM_DBG_FW_CLI": \
724 ((x) == 0xff1b ? "HWRM_DBG_I2C_CMD": \
725 ((x) == 0xff1c ? "HWRM_DBG_RING_INFO_GET": \
726 ((x) == 0xff1d ? "HWRM_DBG_CRASHDUMP_HEADER": \
727 ((x) == 0xff1e ? "HWRM_DBG_CRASHDUMP_ERASE": \
728 ((x) == 0xff1f ? "HWRM_DBG_DRV_TRACE": \
729 ((x) == 0xff20 ? "HWRM_DBG_QCAPS": \
730 ((x) == 0xff21 ? "HWRM_DBG_QCFG": \
731 ((x) == 0xff22 ? "HWRM_DBG_CRASHDUMP_MEDIUM_CFG": \
732 ((x) == 0xff23 ? "HWRM_DBG_USEQ_ALLOC": \
733 ((x) == 0xff24 ? "HWRM_DBG_USEQ_FREE": \
734 ((x) == 0xff25 ? "HWRM_DBG_USEQ_FLUSH": \
735 ((x) == 0xff26 ? "HWRM_DBG_USEQ_QCAPS": \
736 ((x) == 0xff27 ? "HWRM_DBG_USEQ_CW_CFG": \
737 ((x) == 0xff28 ? "HWRM_DBG_USEQ_SCHED_CFG": \
738 ((x) == 0xff29 ? "HWRM_DBG_USEQ_RUN": \
739 ((x) == 0xff2a ? "HWRM_DBG_USEQ_DELIVERY_REQ": \
740 ((x) == 0xff2b ? "HWRM_DBG_USEQ_RESP_HDR": \
742 (((x) <= 0xffff) ? \
743 ((x) == 0xffea ? "HWRM_NVM_GET_VPD_FIELD_INFO": \
744 ((x) == 0xffeb ? "HWRM_NVM_SET_VPD_FIELD_INFO": \
745 ((x) == 0xffec ? "HWRM_NVM_DEFRAG": \
746 ((x) == 0xffed ? "HWRM_NVM_REQ_ARBITRATION": \
747 ((x) == 0xffee ? "HWRM_NVM_FACTORY_DEFAULTS": \
748 ((x) == 0xffef ? "HWRM_NVM_VALIDATE_OPTION": \
749 ((x) == 0xfff0 ? "HWRM_NVM_FLUSH": \
750 ((x) == 0xfff1 ? "HWRM_NVM_GET_VARIABLE": \
751 ((x) == 0xfff2 ? "HWRM_NVM_SET_VARIABLE": \
752 ((x) == 0xfff3 ? "HWRM_NVM_INSTALL_UPDATE": \
753 ((x) == 0xfff4 ? "HWRM_NVM_MODIFY": \
754 ((x) == 0xfff5 ? "HWRM_NVM_VERIFY_UPDATE": \
755 ((x) == 0xfff6 ? "HWRM_NVM_GET_DEV_INFO": \
756 ((x) == 0xfff7 ? "HWRM_NVM_ERASE_DIR_ENTRY": \
757 ((x) == 0xfff8 ? "HWRM_NVM_MOD_DIR_ENTRY": \
758 ((x) == 0xfff9 ? "HWRM_NVM_FIND_DIR_ENTRY": \
759 ((x) == 0xfffa ? "HWRM_NVM_GET_DIR_ENTRIES": \
760 ((x) == 0xfffb ? "HWRM_NVM_GET_DIR_INFO": \
761 ((x) == 0xfffc ? "HWRM_NVM_RAW_DUMP": \
762 ((x) == 0xfffd ? "HWRM_NVM_READ": \
763 ((x) == 0xfffe ? "HWRM_NVM_WRITE": \
764 ((x) == 0xffff ? "HWRM_NVM_RAW_WRITE_BLK": \
797 #define HWRM_VER_GET UINT32_C(0x0)
798 #define HWRM_FUNC_ECHO_RESPONSE UINT32_C(0xb)
799 #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
800 #define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
801 #define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
802 #define HWRM_FUNC_VF_CFG UINT32_C(0xf)
804 #define HWRM_RESERVED1 UINT32_C(0x10)
805 #define HWRM_FUNC_RESET UINT32_C(0x11)
806 #define HWRM_FUNC_GETFID UINT32_C(0x12)
807 #define HWRM_FUNC_VF_ALLOC UINT32_C(0x13)
808 #define HWRM_FUNC_VF_FREE UINT32_C(0x14)
809 #define HWRM_FUNC_QCAPS UINT32_C(0x15)
810 #define HWRM_FUNC_QCFG UINT32_C(0x16)
811 #define HWRM_FUNC_CFG UINT32_C(0x17)
812 #define HWRM_FUNC_QSTATS UINT32_C(0x18)
813 #define HWRM_FUNC_CLR_STATS UINT32_C(0x19)
814 #define HWRM_FUNC_DRV_UNRGTR UINT32_C(0x1a)
815 #define HWRM_FUNC_VF_RESC_FREE UINT32_C(0x1b)
816 #define HWRM_FUNC_VF_VNIC_IDS_QUERY UINT32_C(0x1c)
817 #define HWRM_FUNC_DRV_RGTR UINT32_C(0x1d)
818 #define HWRM_FUNC_DRV_QVER UINT32_C(0x1e)
819 #define HWRM_FUNC_BUF_RGTR UINT32_C(0x1f)
820 #define HWRM_PORT_PHY_CFG UINT32_C(0x20)
821 #define HWRM_PORT_MAC_CFG UINT32_C(0x21)
823 #define HWRM_PORT_TS_QUERY UINT32_C(0x22)
824 #define HWRM_PORT_QSTATS UINT32_C(0x23)
825 #define HWRM_PORT_LPBK_QSTATS UINT32_C(0x24)
827 #define HWRM_PORT_CLR_STATS UINT32_C(0x25)
829 #define HWRM_PORT_LPBK_CLR_STATS UINT32_C(0x26)
830 #define HWRM_PORT_PHY_QCFG UINT32_C(0x27)
831 #define HWRM_PORT_MAC_QCFG UINT32_C(0x28)
833 #define HWRM_PORT_MAC_PTP_QCFG UINT32_C(0x29)
834 #define HWRM_PORT_PHY_QCAPS UINT32_C(0x2a)
835 #define HWRM_PORT_PHY_I2C_WRITE UINT32_C(0x2b)
836 #define HWRM_PORT_PHY_I2C_READ UINT32_C(0x2c)
837 #define HWRM_PORT_LED_CFG UINT32_C(0x2d)
838 #define HWRM_PORT_LED_QCFG UINT32_C(0x2e)
839 #define HWRM_PORT_LED_QCAPS UINT32_C(0x2f)
840 #define HWRM_QUEUE_QPORTCFG UINT32_C(0x30)
841 #define HWRM_QUEUE_QCFG UINT32_C(0x31)
842 #define HWRM_QUEUE_CFG UINT32_C(0x32)
843 #define HWRM_FUNC_VLAN_CFG UINT32_C(0x33)
844 #define HWRM_FUNC_VLAN_QCFG UINT32_C(0x34)
845 #define HWRM_QUEUE_PFCENABLE_QCFG UINT32_C(0x35)
846 #define HWRM_QUEUE_PFCENABLE_CFG UINT32_C(0x36)
847 #define HWRM_QUEUE_PRI2COS_QCFG UINT32_C(0x37)
848 #define HWRM_QUEUE_PRI2COS_CFG UINT32_C(0x38)
849 #define HWRM_QUEUE_COS2BW_QCFG UINT32_C(0x39)
850 #define HWRM_QUEUE_COS2BW_CFG UINT32_C(0x3a)
851 #define HWRM_QUEUE_DSCP_QCAPS UINT32_C(0x3b)
852 #define HWRM_QUEUE_DSCP2PRI_QCFG UINT32_C(0x3c)
853 #define HWRM_QUEUE_DSCP2PRI_CFG UINT32_C(0x3d)
854 #define HWRM_VNIC_ALLOC UINT32_C(0x40)
855 #define HWRM_VNIC_FREE UINT32_C(0x41)
856 #define HWRM_VNIC_CFG UINT32_C(0x42)
857 #define HWRM_VNIC_QCFG UINT32_C(0x43)
858 #define HWRM_VNIC_TPA_CFG UINT32_C(0x44)
860 #define HWRM_VNIC_TPA_QCFG UINT32_C(0x45)
861 #define HWRM_VNIC_RSS_CFG UINT32_C(0x46)
862 #define HWRM_VNIC_RSS_QCFG UINT32_C(0x47)
863 #define HWRM_VNIC_PLCMODES_CFG UINT32_C(0x48)
864 #define HWRM_VNIC_PLCMODES_QCFG UINT32_C(0x49)
865 #define HWRM_VNIC_QCAPS UINT32_C(0x4a)
867 #define HWRM_VNIC_UPDATE UINT32_C(0x4b)
868 #define HWRM_RING_ALLOC UINT32_C(0x50)
869 #define HWRM_RING_FREE UINT32_C(0x51)
870 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)
871 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)
872 #define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)
873 #define HWRM_RING_SCHQ_ALLOC UINT32_C(0x55)
874 #define HWRM_RING_SCHQ_CFG UINT32_C(0x56)
875 #define HWRM_RING_SCHQ_FREE UINT32_C(0x57)
876 #define HWRM_RING_RESET UINT32_C(0x5e)
877 #define HWRM_RING_GRP_ALLOC UINT32_C(0x60)
878 #define HWRM_RING_GRP_FREE UINT32_C(0x61)
879 #define HWRM_RING_CFG UINT32_C(0x62)
880 #define HWRM_RING_QCFG UINT32_C(0x63)
882 #define HWRM_RESERVED5 UINT32_C(0x64)
884 #define HWRM_RESERVED6 UINT32_C(0x65)
885 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC UINT32_C(0x70)
886 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE UINT32_C(0x71)
887 #define HWRM_QUEUE_MPLS_QCAPS UINT32_C(0x80)
888 #define HWRM_QUEUE_MPLSTC2PRI_QCFG UINT32_C(0x81)
889 #define HWRM_QUEUE_MPLSTC2PRI_CFG UINT32_C(0x82)
890 #define HWRM_QUEUE_VLANPRI_QCAPS UINT32_C(0x83)
891 #define HWRM_QUEUE_VLANPRI2PRI_QCFG UINT32_C(0x84)
892 #define HWRM_QUEUE_VLANPRI2PRI_CFG UINT32_C(0x85)
893 #define HWRM_QUEUE_GLOBAL_CFG UINT32_C(0x86)
894 #define HWRM_QUEUE_GLOBAL_QCFG UINT32_C(0x87)
895 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG UINT32_C(0x88)
896 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG UINT32_C(0x89)
897 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG UINT32_C(0x8a)
898 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG UINT32_C(0x8b)
899 #define HWRM_QUEUE_QCAPS UINT32_C(0x8c)
900 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG UINT32_C(0x8d)
901 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG UINT32_C(0x8e)
902 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG UINT32_C(0x8f)
903 #define HWRM_CFA_L2_FILTER_ALLOC UINT32_C(0x90)
904 #define HWRM_CFA_L2_FILTER_FREE UINT32_C(0x91)
905 #define HWRM_CFA_L2_FILTER_CFG UINT32_C(0x92)
906 #define HWRM_CFA_L2_SET_RX_MASK UINT32_C(0x93)
907 #define HWRM_CFA_VLAN_ANTISPOOF_CFG UINT32_C(0x94)
908 #define HWRM_CFA_TUNNEL_FILTER_ALLOC UINT32_C(0x95)
909 #define HWRM_CFA_TUNNEL_FILTER_FREE UINT32_C(0x96)
911 #define HWRM_CFA_ENCAP_RECORD_ALLOC UINT32_C(0x97)
913 #define HWRM_CFA_ENCAP_RECORD_FREE UINT32_C(0x98)
914 #define HWRM_CFA_NTUPLE_FILTER_ALLOC UINT32_C(0x99)
915 #define HWRM_CFA_NTUPLE_FILTER_FREE UINT32_C(0x9a)
916 #define HWRM_CFA_NTUPLE_FILTER_CFG UINT32_C(0x9b)
918 #define HWRM_CFA_EM_FLOW_ALLOC UINT32_C(0x9c)
920 #define HWRM_CFA_EM_FLOW_FREE UINT32_C(0x9d)
922 #define HWRM_CFA_EM_FLOW_CFG UINT32_C(0x9e)
923 #define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
924 #define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
925 #define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
926 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG UINT32_C(0xa3)
927 #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
928 #define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
929 #define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
930 #define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
931 #define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
932 #define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
933 #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
934 #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
935 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE UINT32_C(0xb7)
936 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE UINT32_C(0xb8)
937 #define HWRM_PORT_QSTATS_EXT_PFC_WD UINT32_C(0xb9)
939 #define HWRM_RESERVED7 UINT32_C(0xba)
940 #define HWRM_PORT_TX_FIR_CFG UINT32_C(0xbb)
941 #define HWRM_PORT_TX_FIR_QCFG UINT32_C(0xbc)
942 #define HWRM_PORT_ECN_QSTATS UINT32_C(0xbd)
943 #define HWRM_FW_LIVEPATCH_QUERY UINT32_C(0xbe)
944 #define HWRM_FW_LIVEPATCH UINT32_C(0xbf)
945 #define HWRM_FW_RESET UINT32_C(0xc0)
946 #define HWRM_FW_QSTATUS UINT32_C(0xc1)
947 #define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
948 #define HWRM_FW_SYNC UINT32_C(0xc3)
949 #define HWRM_FW_STATE_QCAPS UINT32_C(0xc4)
950 #define HWRM_FW_STATE_QUIESCE UINT32_C(0xc5)
951 #define HWRM_FW_STATE_BACKUP UINT32_C(0xc6)
952 #define HWRM_FW_STATE_RESTORE UINT32_C(0xc7)
954 #define HWRM_FW_SET_TIME UINT32_C(0xc8)
956 #define HWRM_FW_GET_TIME UINT32_C(0xc9)
958 #define HWRM_FW_SET_STRUCTURED_DATA UINT32_C(0xca)
960 #define HWRM_FW_GET_STRUCTURED_DATA UINT32_C(0xcb)
962 #define HWRM_FW_IPC_MAILBOX UINT32_C(0xcc)
963 #define HWRM_FW_ECN_CFG UINT32_C(0xcd)
964 #define HWRM_FW_ECN_QCFG UINT32_C(0xce)
965 #define HWRM_FW_SECURE_CFG UINT32_C(0xcf)
966 #define HWRM_EXEC_FWD_RESP UINT32_C(0xd0)
967 #define HWRM_REJECT_FWD_RESP UINT32_C(0xd1)
968 #define HWRM_FWD_RESP UINT32_C(0xd2)
969 #define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
970 #define HWRM_OEM_CMD UINT32_C(0xd4)
972 #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
973 #define HWRM_PORT_SFP_SIDEBAND_CFG UINT32_C(0xd6)
974 #define HWRM_PORT_SFP_SIDEBAND_QCFG UINT32_C(0xd7)
975 #define HWRM_FW_STATE_UNQUIESCE UINT32_C(0xd8)
977 #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9)
978 #define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda)
979 #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb)
980 #define HWRM_PORT_CFG UINT32_C(0xdc)
981 #define HWRM_PORT_QCFG UINT32_C(0xdd)
983 #define HWRM_PORT_MAC_QCAPS UINT32_C(0xdf)
984 #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
985 #define HWRM_REG_POWER_QUERY UINT32_C(0xe1)
986 #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2)
987 #define HWRM_REG_POWER_HISTOGRAM UINT32_C(0xe3)
988 #define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
989 #define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
990 #define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
991 #define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
993 #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
995 #define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
997 #define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
999 #define HWRM_CFA_METER_PROFILE_CFG UINT32_C(0xf7)
1001 #define HWRM_CFA_METER_INSTANCE_ALLOC UINT32_C(0xf8)
1003 #define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
1005 #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
1007 #define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
1009 #define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
1011 #define HWRM_CFA_VF_PAIR_ALLOC UINT32_C(0x100)
1013 #define HWRM_CFA_VF_PAIR_FREE UINT32_C(0x101)
1015 #define HWRM_CFA_VF_PAIR_INFO UINT32_C(0x102)
1017 #define HWRM_CFA_FLOW_ALLOC UINT32_C(0x103)
1019 #define HWRM_CFA_FLOW_FREE UINT32_C(0x104)
1021 #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105)
1022 #define HWRM_CFA_FLOW_STATS UINT32_C(0x106)
1023 #define HWRM_CFA_FLOW_INFO UINT32_C(0x107)
1025 #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108)
1027 #define HWRM_CFA_DECAP_FILTER_FREE UINT32_C(0x109)
1028 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG UINT32_C(0x10a)
1029 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC UINT32_C(0x10b)
1030 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE UINT32_C(0x10c)
1032 #define HWRM_CFA_PAIR_ALLOC UINT32_C(0x10d)
1034 #define HWRM_CFA_PAIR_FREE UINT32_C(0x10e)
1036 #define HWRM_CFA_PAIR_INFO UINT32_C(0x10f)
1038 #define HWRM_FW_IPC_MSG UINT32_C(0x110)
1039 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
1040 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
1042 #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
1044 #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
1046 #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
1048 #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
1050 #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
1052 #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
1054 #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
1056 #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
1058 #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
1060 #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
1062 #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
1064 #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
1066 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
1068 #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
1070 #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
1072 #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
1074 #define HWRM_CFA_EEM_OP UINT32_C(0x123)
1076 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
1078 #define HWRM_CFA_TFLIB UINT32_C(0x125)
1080 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR UINT32_C(0x126)
1082 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR UINT32_C(0x127)
1084 #define HWRM_CFA_TLS_FILTER_ALLOC UINT32_C(0x128)
1086 #define HWRM_CFA_TLS_FILTER_FREE UINT32_C(0x129)
1088 #define HWRM_CFA_RELEASE_AFM_FUNC UINT32_C(0x12a)
1093 #define HWRM_ENGINE_CKV_STATUS UINT32_C(0x12e)
1095 #define HWRM_ENGINE_CKV_CKEK_ADD UINT32_C(0x12f)
1097 #define HWRM_ENGINE_CKV_CKEK_DELETE UINT32_C(0x130)
1099 #define HWRM_ENGINE_CKV_KEY_ADD UINT32_C(0x131)
1101 #define HWRM_ENGINE_CKV_KEY_DELETE UINT32_C(0x132)
1103 #define HWRM_ENGINE_CKV_FLUSH UINT32_C(0x133)
1105 #define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
1107 #define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
1109 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
1111 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
1113 #define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
1115 #define HWRM_ENGINE_QG_QUERY UINT32_C(0x13d)
1117 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY UINT32_C(0x13e)
1119 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY UINT32_C(0x13f)
1121 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC UINT32_C(0x140)
1123 #define HWRM_ENGINE_QG_METER_PROFILE_FREE UINT32_C(0x141)
1125 #define HWRM_ENGINE_QG_METER_QUERY UINT32_C(0x142)
1127 #define HWRM_ENGINE_QG_METER_BIND UINT32_C(0x143)
1129 #define HWRM_ENGINE_QG_METER_UNBIND UINT32_C(0x144)
1131 #define HWRM_ENGINE_QG_FUNC_BIND UINT32_C(0x145)
1133 #define HWRM_ENGINE_SG_CONFIG_QUERY UINT32_C(0x146)
1135 #define HWRM_ENGINE_SG_QUERY UINT32_C(0x147)
1137 #define HWRM_ENGINE_SG_METER_QUERY UINT32_C(0x148)
1139 #define HWRM_ENGINE_SG_METER_CONFIG UINT32_C(0x149)
1141 #define HWRM_ENGINE_SG_QG_BIND UINT32_C(0x14a)
1143 #define HWRM_ENGINE_QG_SG_UNBIND UINT32_C(0x14b)
1145 #define HWRM_ENGINE_CONFIG_QUERY UINT32_C(0x154)
1147 #define HWRM_ENGINE_STATS_CONFIG UINT32_C(0x155)
1149 #define HWRM_ENGINE_STATS_CLEAR UINT32_C(0x156)
1151 #define HWRM_ENGINE_STATS_QUERY UINT32_C(0x157)
1156 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR UINT32_C(0x158)
1158 #define HWRM_ENGINE_RQ_ALLOC UINT32_C(0x15e)
1160 #define HWRM_ENGINE_RQ_FREE UINT32_C(0x15f)
1162 #define HWRM_ENGINE_CQ_ALLOC UINT32_C(0x160)
1164 #define HWRM_ENGINE_CQ_FREE UINT32_C(0x161)
1166 #define HWRM_ENGINE_NQ_ALLOC UINT32_C(0x162)
1168 #define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
1170 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
1172 #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
1174 #define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
1176 #define HWRM_FUNC_VF_RESOURCE_CFG UINT32_C(0x191)
1178 #define HWRM_FUNC_BACKING_STORE_QCAPS UINT32_C(0x192)
1180 #define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)
1182 #define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)
1184 #define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)
1186 #define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)
1188 #define HWRM_FUNC_HOST_PF_IDS_QUERY UINT32_C(0x197)
1190 #define HWRM_FUNC_QSTATS_EXT UINT32_C(0x198)
1192 #define HWRM_STAT_EXT_CTX_QUERY UINT32_C(0x199)
1194 #define HWRM_FUNC_SPD_CFG UINT32_C(0x19a)
1196 #define HWRM_FUNC_SPD_QCFG UINT32_C(0x19b)
1198 #define HWRM_FUNC_PTP_PIN_QCFG UINT32_C(0x19c)
1200 #define HWRM_FUNC_PTP_PIN_CFG UINT32_C(0x19d)
1202 #define HWRM_FUNC_PTP_CFG UINT32_C(0x19e)
1204 #define HWRM_FUNC_PTP_TS_QUERY UINT32_C(0x19f)
1206 #define HWRM_FUNC_PTP_EXT_CFG UINT32_C(0x1a0)
1208 #define HWRM_FUNC_PTP_EXT_QCFG UINT32_C(0x1a1)
1210 #define HWRM_FUNC_KEY_CTX_ALLOC UINT32_C(0x1a2)
1212 #define HWRM_FUNC_BACKING_STORE_CFG_V2 UINT32_C(0x1a3)
1214 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 UINT32_C(0x1a4)
1216 #define HWRM_FUNC_DBR_PACING_CFG UINT32_C(0x1a5)
1218 #define HWRM_FUNC_DBR_PACING_QCFG UINT32_C(0x1a6)
1223 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7)
1225 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8)
1227 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY UINT32_C(0x1a9)
1232 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED UINT32_C(0x1aa)
1234 #define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab)
1236 #define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac)
1238 #define HWRM_FUNC_KEY_CTX_FREE UINT32_C(0x1ad)
1240 #define HWRM_FUNC_LAG_MODE_CFG UINT32_C(0x1ae)
1242 #define HWRM_FUNC_LAG_MODE_QCFG UINT32_C(0x1af)
1244 #define HWRM_FUNC_LAG_CREATE UINT32_C(0x1b0)
1246 #define HWRM_FUNC_LAG_UPDATE UINT32_C(0x1b1)
1248 #define HWRM_FUNC_LAG_FREE UINT32_C(0x1b2)
1250 #define HWRM_FUNC_LAG_QCFG UINT32_C(0x1b3)
1252 #define HWRM_SELFTEST_QLIST UINT32_C(0x200)
1254 #define HWRM_SELFTEST_EXEC UINT32_C(0x201)
1256 #define HWRM_SELFTEST_IRQ UINT32_C(0x202)
1258 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA UINT32_C(0x203)
1260 #define HWRM_PCIE_QSTATS UINT32_C(0x204)
1262 #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
1264 #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
1266 #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
1268 #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
1273 #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
1275 #define HWRM_MFG_FRU_EEPROM_WRITE UINT32_C(0x20a)
1277 #define HWRM_MFG_FRU_EEPROM_READ UINT32_C(0x20b)
1279 #define HWRM_MFG_SOC_IMAGE UINT32_C(0x20c)
1281 #define HWRM_MFG_SOC_QSTATUS UINT32_C(0x20d)
1283 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE UINT32_C(0x20e)
1285 #define HWRM_MFG_PARAM_CRITICAL_DATA_READ UINT32_C(0x20f)
1287 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH UINT32_C(0x210)
1292 #define HWRM_MFG_PRVSN_EXPORT_CSR UINT32_C(0x211)
1297 #define HWRM_MFG_PRVSN_IMPORT_CERT UINT32_C(0x212)
1302 #define HWRM_MFG_PRVSN_GET_STATE UINT32_C(0x213)
1307 #define HWRM_MFG_GET_NVM_MEASUREMENT UINT32_C(0x214)
1309 #define HWRM_MFG_PSOC_QSTATUS UINT32_C(0x215)
1314 #define HWRM_MFG_SELFTEST_QLIST UINT32_C(0x216)
1319 #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217)
1321 #define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218)
1326 #define HWRM_MFG_PRVSN_EXPORT_CERT UINT32_C(0x219)
1328 #define HWRM_STAT_DB_ERROR_QSTATS UINT32_C(0x21a)
1333 #define HWRM_UDCC_QCAPS UINT32_C(0x258)
1335 #define HWRM_UDCC_CFG UINT32_C(0x259)
1340 #define HWRM_UDCC_QCFG UINT32_C(0x25a)
1342 #define HWRM_UDCC_SESSION_CFG UINT32_C(0x25b)
1344 #define HWRM_UDCC_SESSION_QCFG UINT32_C(0x25c)
1346 #define HWRM_UDCC_SESSION_QUERY UINT32_C(0x25d)
1348 #define HWRM_UDCC_COMP_CFG UINT32_C(0x25e)
1350 #define HWRM_UDCC_COMP_QCFG UINT32_C(0x25f)
1352 #define HWRM_UDCC_COMP_QUERY UINT32_C(0x260)
1354 #define HWRM_TF UINT32_C(0x2bc)
1356 #define HWRM_TF_VERSION_GET UINT32_C(0x2bd)
1358 #define HWRM_TF_SESSION_OPEN UINT32_C(0x2c6)
1360 #define HWRM_TF_SESSION_REGISTER UINT32_C(0x2c8)
1362 #define HWRM_TF_SESSION_UNREGISTER UINT32_C(0x2c9)
1364 #define HWRM_TF_SESSION_CLOSE UINT32_C(0x2ca)
1366 #define HWRM_TF_SESSION_QCFG UINT32_C(0x2cb)
1368 #define HWRM_TF_SESSION_RESC_QCAPS UINT32_C(0x2cc)
1370 #define HWRM_TF_SESSION_RESC_ALLOC UINT32_C(0x2cd)
1372 #define HWRM_TF_SESSION_RESC_FREE UINT32_C(0x2ce)
1374 #define HWRM_TF_SESSION_RESC_FLUSH UINT32_C(0x2cf)
1376 #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0)
1378 #define HWRM_TF_SESSION_HOTUP_STATE_SET UINT32_C(0x2d1)
1380 #define HWRM_TF_SESSION_HOTUP_STATE_GET UINT32_C(0x2d2)
1382 #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da)
1384 #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db)
1386 #define HWRM_TF_TBL_TYPE_BULK_GET UINT32_C(0x2dc)
1388 #define HWRM_TF_EM_INSERT UINT32_C(0x2ea)
1390 #define HWRM_TF_EM_DELETE UINT32_C(0x2eb)
1392 #define HWRM_TF_EM_HASH_INSERT UINT32_C(0x2ec)
1394 #define HWRM_TF_EM_MOVE UINT32_C(0x2ed)
1396 #define HWRM_TF_TCAM_SET UINT32_C(0x2f8)
1398 #define HWRM_TF_TCAM_GET UINT32_C(0x2f9)
1400 #define HWRM_TF_TCAM_MOVE UINT32_C(0x2fa)
1402 #define HWRM_TF_TCAM_FREE UINT32_C(0x2fb)
1404 #define HWRM_TF_GLOBAL_CFG_SET UINT32_C(0x2fc)
1406 #define HWRM_TF_GLOBAL_CFG_GET UINT32_C(0x2fd)
1408 #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe)
1410 #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff)
1412 #define HWRM_TF_RESC_USAGE_SET UINT32_C(0x300)
1414 #define HWRM_TF_RESC_USAGE_QUERY UINT32_C(0x301)
1416 #define HWRM_TF_TBL_TYPE_ALLOC UINT32_C(0x302)
1418 #define HWRM_TF_TBL_TYPE_FREE UINT32_C(0x303)
1420 #define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380)
1422 #define HWRM_TFC_TBL_SCOPE_ID_ALLOC UINT32_C(0x381)
1424 #define HWRM_TFC_TBL_SCOPE_CONFIG UINT32_C(0x382)
1426 #define HWRM_TFC_TBL_SCOPE_DECONFIG UINT32_C(0x383)
1428 #define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384)
1430 #define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385)
1432 #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386)
1434 #define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387)
1436 #define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388)
1438 #define HWRM_TFC_SESSION_FID_ADD UINT32_C(0x389)
1440 #define HWRM_TFC_SESSION_FID_REM UINT32_C(0x38a)
1442 #define HWRM_TFC_IDENT_ALLOC UINT32_C(0x38b)
1444 #define HWRM_TFC_IDENT_FREE UINT32_C(0x38c)
1446 #define HWRM_TFC_IDX_TBL_ALLOC UINT32_C(0x38d)
1448 #define HWRM_TFC_IDX_TBL_ALLOC_SET UINT32_C(0x38e)
1450 #define HWRM_TFC_IDX_TBL_SET UINT32_C(0x38f)
1452 #define HWRM_TFC_IDX_TBL_GET UINT32_C(0x390)
1454 #define HWRM_TFC_IDX_TBL_FREE UINT32_C(0x391)
1456 #define HWRM_TFC_GLOBAL_ID_ALLOC UINT32_C(0x392)
1458 #define HWRM_TFC_TCAM_SET UINT32_C(0x393)
1460 #define HWRM_TFC_TCAM_GET UINT32_C(0x394)
1462 #define HWRM_TFC_TCAM_ALLOC UINT32_C(0x395)
1464 #define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396)
1466 #define HWRM_TFC_TCAM_FREE UINT32_C(0x397)
1468 #define HWRM_TFC_IF_TBL_SET UINT32_C(0x398)
1470 #define HWRM_TFC_IF_TBL_GET UINT32_C(0x399)
1472 #define HWRM_TFC_TBL_SCOPE_CONFIG_GET UINT32_C(0x39a)
1474 #define HWRM_TFC_RESC_USAGE_QUERY UINT32_C(0x39b)
1479 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS UINT32_C(0x39c)
1481 #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG UINT32_C(0x39d)
1486 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG UINT32_C(0x39e)
1488 #define HWRM_SV UINT32_C(0x400)
1490 #define HWRM_DBG_LOG_BUFFER_FLUSH UINT32_C(0xff0f)
1492 #define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
1494 #define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
1496 #define HWRM_DBG_WRITE_DIRECT UINT32_C(0xff12)
1498 #define HWRM_DBG_WRITE_INDIRECT UINT32_C(0xff13)
1499 #define HWRM_DBG_DUMP UINT32_C(0xff14)
1501 #define HWRM_DBG_ERASE_NVM UINT32_C(0xff15)
1503 #define HWRM_DBG_CFG UINT32_C(0xff16)
1505 #define HWRM_DBG_COREDUMP_LIST UINT32_C(0xff17)
1507 #define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)
1509 #define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)
1511 #define HWRM_DBG_FW_CLI UINT32_C(0xff1a)
1513 #define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)
1515 #define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
1517 #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
1519 #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
1521 #define HWRM_DBG_DRV_TRACE UINT32_C(0xff1f)
1523 #define HWRM_DBG_QCAPS UINT32_C(0xff20)
1525 #define HWRM_DBG_QCFG UINT32_C(0xff21)
1527 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG UINT32_C(0xff22)
1529 #define HWRM_DBG_USEQ_ALLOC UINT32_C(0xff23)
1531 #define HWRM_DBG_USEQ_FREE UINT32_C(0xff24)
1533 #define HWRM_DBG_USEQ_FLUSH UINT32_C(0xff25)
1535 #define HWRM_DBG_USEQ_QCAPS UINT32_C(0xff26)
1537 #define HWRM_DBG_USEQ_CW_CFG UINT32_C(0xff27)
1539 #define HWRM_DBG_USEQ_SCHED_CFG UINT32_C(0xff28)
1541 #define HWRM_DBG_USEQ_RUN UINT32_C(0xff29)
1543 #define HWRM_DBG_USEQ_DELIVERY_REQ UINT32_C(0xff2a)
1545 #define HWRM_DBG_USEQ_RESP_HDR UINT32_C(0xff2b)
1546 #define HWRM_NVM_GET_VPD_FIELD_INFO UINT32_C(0xffea)
1547 #define HWRM_NVM_SET_VPD_FIELD_INFO UINT32_C(0xffeb)
1548 #define HWRM_NVM_DEFRAG UINT32_C(0xffec)
1549 #define HWRM_NVM_REQ_ARBITRATION UINT32_C(0xffed)
1551 #define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
1552 #define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
1553 #define HWRM_NVM_FLUSH UINT32_C(0xfff0)
1554 #define HWRM_NVM_GET_VARIABLE UINT32_C(0xfff1)
1555 #define HWRM_NVM_SET_VARIABLE UINT32_C(0xfff2)
1556 #define HWRM_NVM_INSTALL_UPDATE UINT32_C(0xfff3)
1557 #define HWRM_NVM_MODIFY UINT32_C(0xfff4)
1558 #define HWRM_NVM_VERIFY_UPDATE UINT32_C(0xfff5)
1559 #define HWRM_NVM_GET_DEV_INFO UINT32_C(0xfff6)
1560 #define HWRM_NVM_ERASE_DIR_ENTRY UINT32_C(0xfff7)
1561 #define HWRM_NVM_MOD_DIR_ENTRY UINT32_C(0xfff8)
1562 #define HWRM_NVM_FIND_DIR_ENTRY UINT32_C(0xfff9)
1563 #define HWRM_NVM_GET_DIR_ENTRIES UINT32_C(0xfffa)
1564 #define HWRM_NVM_GET_DIR_INFO UINT32_C(0xfffb)
1565 #define HWRM_NVM_RAW_DUMP UINT32_C(0xfffc)
1566 #define HWRM_NVM_READ UINT32_C(0xfffd)
1567 #define HWRM_NVM_WRITE UINT32_C(0xfffe)
1568 #define HWRM_NVM_RAW_WRITE_BLK UINT32_C(0xffff)
1579 #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
1581 #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
1586 #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
1593 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
1599 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
1604 #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
1609 #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
1614 #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
1619 #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
1624 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
1629 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
1634 #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
1640 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
1646 #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
1652 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
1657 #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
1662 #define HWRM_ERR_CODE_BUSY UINT32_C(0x10)
1667 #define HWRM_ERR_CODE_RESOURCE_LOCKED UINT32_C(0x11)
1674 #define HWRM_ERR_CODE_PF_UNAVAILABLE UINT32_C(0x12)
1679 #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT UINT32_C(0x13)
1687 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
1689 #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
1691 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
1697 (((x) < 0x80) ? \
1698 ((x) == 0x0 ? "SUCCESS": \
1699 ((x) == 0x1 ? "FAIL": \
1700 ((x) == 0x2 ? "INVALID_PARAMS": \
1701 ((x) == 0x3 ? "RESOURCE_ACCESS_DENIED": \
1702 ((x) == 0x4 ? "RESOURCE_ALLOC_ERROR": \
1703 ((x) == 0x5 ? "INVALID_FLAGS": \
1704 ((x) == 0x6 ? "INVALID_ENABLES": \
1705 ((x) == 0x7 ? "UNSUPPORTED_TLV": \
1706 ((x) == 0x8 ? "NO_BUFFER": \
1707 ((x) == 0x9 ? "UNSUPPORTED_OPTION_ERR": \
1708 ((x) == 0xa ? "HOT_RESET_PROGRESS": \
1709 ((x) == 0xb ? "HOT_RESET_FAIL": \
1710 ((x) == 0xc ? "NO_FLOW_COUNTER_DURING_ALLOC": \
1711 ((x) == 0xd ? "KEY_HASH_COLLISION": \
1712 ((x) == 0xe ? "KEY_ALREADY_EXISTS": \
1713 ((x) == 0xf ? "HWRM_ERROR": \
1714 ((x) == 0x10 ? "BUSY": \
1715 ((x) == 0x11 ? "RESOURCE_LOCKED": \
1716 ((x) == 0x12 ? "PF_UNAVAILABLE": \
1717 ((x) == 0x13 ? "ENTITY_NOT_PRESENT": \
1719 (((x) < 0x8080) ? \
1720 ((x) == 0x8000 ? "TLV_ENCAPSULATED_RESPONSE": \
1722 (((x) <= 0xffff) ? \
1723 ((x) == 0xfffe ? "UNKNOWN_ERR": \
1724 ((x) == 0xffff ? "CMD_NOT_SUPPORTED": \
1785 #define HW_HASH_INDEX_SIZE 0x80
1790 #define HWRM_TARGET_ID_BONO 0xFFF8
1792 #define HWRM_TARGET_ID_KONG 0xFFF9
1794 #define HWRM_TARGET_ID_APE 0xFFFA
1801 #define HWRM_TARGET_ID_TOOLS 0xFFFD
1832 * * 0x0-0xFFF8 - The function ID
1833 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
1834 * * 0xFFFD - Reserved for user-space HWRM interface
1835 * * 0xFFFF - HWRM
2000 * If set to 0, then secure firmware update behavior is
2003 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED UINT32_C(0x1)
2006 * If set to 0, then firmware based DCBX agent capability
2009 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED UINT32_C(0x2)
2012 * If set to 0, then HWRM short command format is not supported.
2014 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED UINT32_C(0x4)
2017 * If set to 0, then HWRM short command format is not required.
2019 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED UINT32_C(0x8)
2022 * If set to 0, then the KONG host mailbox channel is not supported.
2023 * By default, this flag should be 0 for older version of core
2026 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED UINT32_C(0x10)
2029 * to the legacy 16bit flow handle. If set to 0, then the 64bit flow
2030 * handle is not supported. By default, this flag should be 0 for
2033 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED UINT32_C(0x20)
2037 * l2 traffic. If set to 0, then filter types not supported. By
2038 * default, this flag should be 0 for older version of core firmware.
2040 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED UINT32_C(0x40)
2043 * model. If set to 0, firmware can't supported virtio vSwitch
2045 * By default, this flag should be 0 for older version of core
2048 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED UINT32_C(0x80)
2051 * If set to 0, firmware is not capable to support trusted VF.
2052 * By default, this flag should be 0 for older version of core
2055 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED UINT32_C(0x100)
2058 * If set to 0, firmware is not capable to support flow aging.
2059 * By default, this flag should be 0 for older version of core
2062 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED UINT32_C(0x200)
2066 * If set to 0, firmware is not capable to support advanced flow
2067 * counters. By default, this flag should be 0 for older version of
2070 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED UINT32_C(0x400)
2074 * If set to 0, firmware is not capable to support the use of the
2076 * By default, this flag should be 0 for older version of core
2079 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED UINT32_C(0x800)
2083 * If set to 0, then the firmware doesn't support the advance CFA
2085 * By default, this flag should be 0 for older version of core
2088 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED UINT32_C(0x1000)
2092 * If set to 0, then the firmware doesn't support TFLIB features.
2093 * By default, this flag should be 0 for older version of core
2096 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED UINT32_C(0x2000)
2099 * If set to 0, then the firmware doesn't support TruFlow features.
2100 * By default, this flag should be 0 for older version of
2103 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED UINT32_C(0x4000)
2106 * If set to 0, then firmware doesn't support secure boot.
2108 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE UINT32_C(0x8000)
2112 * If set to 0, then firmware does not support the secure solution
2115 #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SECURE_SOC_CAPABLE UINT32_C(0x10000)
2174 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_ASIC UINT32_C(0x0)
2176 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_FPGA UINT32_C(0x1)
2178 #define HWRM_VER_GET_OUTPUT_CHIP_PLATFORM_TYPE_PALLADIUM UINT32_C(0x2)
2211 * If set to 0, device is ready to accept all HWRM commands.
2213 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY UINT32_C(0x1)
2216 * If set to 0, external version not present.
2218 #define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL UINT32_C(0x2)
2226 * If this flag and dev_not_rdy flag are set to 0, device is ready
2229 #define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE UINT32_C(0x4)
2402 #define CFA_BDS_READ_CMD_DATA_MSG_OPCODE_READ UINT32_C(0x0)
2407 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
2408 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_SFT 0
2410 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
2412 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
2416 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2417 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2423 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2424 #define CFA_BDS_READ_CMD_DATA_MSG_DATA_SIZE_SFT 0
2427 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
2428 #define CFA_BDS_READ_CMD_DATA_MSG_TABLE_INDEX_SFT 0
2447 #define CFA_BDS_WRITE_CMD_DATA_MSG_OPCODE_WRITE UINT32_C(0x1)
2452 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
2453 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
2455 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
2457 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
2463 #define CFA_BDS_WRITE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
2466 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2467 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2473 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2474 #define CFA_BDS_WRITE_CMD_DATA_MSG_DATA_SIZE_SFT 0
2477 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
2478 #define CFA_BDS_WRITE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
2500 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_OPCODE_READ_CLR UINT32_C(0x2)
2505 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
2506 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_SFT 0
2508 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
2510 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
2514 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2515 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2521 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2522 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0
2525 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
2526 #define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_SFT 0
2536 * can read. Bit 0 of the field will clear bits 15:0 of the first word
2554 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_OPCODE_EM_INSERT UINT32_C(0x3)
2561 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
2562 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_UNUSED_SFT 0
2567 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
2570 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2571 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2577 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2578 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_DATA_SIZE_SFT 0
2581 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
2582 #define CFA_BDS_EM_INSERT_CMD_DATA_MSG_TABLE_INDEX_SFT 0
2601 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_OPCODE_EM_DELETE UINT32_C(0x4)
2608 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_MASK UINT32_C(0xf)
2609 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_UNUSED_SFT 0
2614 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_WRITE_THRU UINT32_C(0x10)
2617 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2618 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2624 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2625 #define CFA_BDS_EM_DELETE_CMD_DATA_MSG_DATA_SIZE_SFT 0
2649 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_OPCODE_INVALIDATE UINT32_C(0x5)
2654 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf)
2655 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_SFT 0
2657 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_ACTION UINT32_C(0x0)
2659 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_TYPE_EM UINT32_C(0x1)
2663 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2664 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2667 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2668 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0
2671 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
2672 #define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0
2682 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_OPCODE_EVENT_COLLECT UINT32_C(0x6)
2687 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
2688 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_TABLE_SCOPE_SFT 0
2694 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)
2695 #define CFA_BDS_EVENT_COLLECT_CMD_DATA_MSG_DATA_SIZE_SFT 0
2712 #define CE_BDS_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
2713 #define CE_BDS_ADD_DATA_MSG_OPCODE_SFT 0
2719 #define CE_BDS_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
2725 #define CE_BDS_ADD_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
2731 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_MASK UINT32_C(0xf000000)
2734 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 UINT32_C(0x1000000)
2736 #define CE_BDS_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 UINT32_C(0x2000000)
2743 #define CE_BDS_ADD_DATA_MSG_VERSION_MASK UINT32_C(0xf0000000)
2746 #define CE_BDS_ADD_DATA_MSG__TLS1_2 (UINT32_C(0x0) << 28)
2748 #define CE_BDS_ADD_DATA_MSG__TLS1_3 (UINT32_C(0x1) << 28)
2752 #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f)
2753 #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 0
2755 #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX UINT32_C(0x11)
2757 #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX UINT32_C(0x12)
2820 #define CE_BDS_DELETE_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
2821 #define CE_BDS_DELETE_DATA_MSG_OPCODE_SFT 0
2831 #define CE_BDS_DELETE_DATA_MSG_OPCODE_DELETE UINT32_C(0x2)
2837 #define CE_BDS_DELETE_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
2840 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f000000)
2843 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 24)
2845 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 24)
2847 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_TX (UINT32_C(0x14) << 24)
2849 #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24)
2861 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_MASK UINT32_C(0xf)
2862 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_SFT 0
2867 #define CE_BDS_RESYNC_RESP_ACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2873 #define CE_BDS_RESYNC_RESP_ACK_MSG_KID_MASK UINT32_C(0xfffff0)
2879 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS UINT32_C(0x1000000)
2884 #define CE_BDS_RESYNC_RESP_ACK_MSG_RESYNC_STATUS_ACK (UINT32_C(0x0) << 24)
2911 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_MASK UINT32_C(0xf)
2912 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_SFT 0
2917 #define CE_BDS_RESYNC_RESP_NACK_MSG_OPCODE_RESYNC UINT32_C(0x3)
2923 #define CE_BDS_RESYNC_RESP_NACK_MSG_KID_MASK UINT32_C(0xfffff0)
2929 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS UINT32_C(0x1000000)
2934 #define CE_BDS_RESYNC_RESP_NACK_MSG_RESYNC_STATUS_NACK (UINT32_C(0x1) << 24)
2970 #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR UINT32_C(0x1)
2982 #define CRYPTO_PRESYNC_BD_CMD_FLAGS_FULL_REPLAY_RETRAN UINT32_C(0x2)
2987 * Header of the active TLS record. This field is set to 0 during
2998 * be re-transmitted. This field is initialized to 0 during Mid-path BD
3009 * that need to be re-transmitted. This field is initialized to 0 during
3022 * initialized to 0 when presync BD is detected by taking the value from
3031 * Initial Vector (IV). The field is initialized to 0 during Mid-path BD
3049 #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf)
3050 #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_SFT 0
3056 #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1)
3062 #define CE_BDS_QUIC_ADD_DATA_MSG_KID_MASK UINT32_C(0xfffff0)
3065 #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_MASK UINT32_C(0xf000000)
3068 #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 (UINT32_C(0x1) << 24)
3070 #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 (UINT32_C(0x2) << 24)
3072 #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20 (UINT32_C(0x3) << 24)
3075 #define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_MASK UINT32_C(0xf0000000)
3078 #define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_2 (UINT32_C(0x0) << 28)
3080 #define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_3 (UINT32_C(0x1) << 28)
3082 #define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2 (UINT32_C(0x2) << 28)
3084 #define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2_ROCE (UINT32_C(0x3) << 28)
3086 #define CE_BDS_QUIC_ADD_DATA_MSG__QUIC (UINT32_C(0x4) << 28)
3090 #define CE_BDS_QUIC_ADD_DATA_MSG_KEY_PHASE UINT32_C(0x1)
3092 #define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_MASK UINT32_C(0x3e)
3095 #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x7c0)
3098 #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_TX (UINT32_C(0x14) << 6)
3100 #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 6)
3133 #define BD_BASE_TYPE_MASK UINT32_C(0x3f)
3134 #define BD_BASE_TYPE_SFT 0
3139 #define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)
3144 #define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)
3149 #define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)
3154 #define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)
3159 #define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)
3164 #define BD_BASE_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
3169 #define BD_BASE_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
3175 #define BD_BASE_TYPE_TX_BD_TIMEDTX UINT32_C(0xa)
3180 #define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)
3186 #define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
3201 #define TX_BD_SHORT_TYPE_MASK UINT32_C(0x3f)
3202 #define TX_BD_SHORT_TYPE_SFT 0
3207 #define TX_BD_SHORT_TYPE_TX_BD_SHORT UINT32_C(0x0)
3214 #define TX_BD_SHORT_FLAGS_MASK UINT32_C(0xffc0)
3221 #define TX_BD_SHORT_FLAGS_PACKET_END UINT32_C(0x40)
3227 * is set to 0, then the packet will be completed normally.
3231 #define TX_BD_SHORT_FLAGS_NO_CMPL UINT32_C(0x80)
3238 * BD in the packet. A value of 0 indicates
3243 #define TX_BD_SHORT_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3253 #define TX_BD_SHORT_FLAGS_LHINT_MASK UINT32_C(0x6000)
3256 #define TX_BD_SHORT_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
3258 #define TX_BD_SHORT_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
3260 #define TX_BD_SHORT_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
3262 #define TX_BD_SHORT_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
3270 * is set to 0, then the Consumer Index is only updated as soon
3275 #define TX_BD_SHORT_FLAGS_COAL_NOW UINT32_C(0x8000)
3315 #define TX_BD_LONG_TYPE_MASK UINT32_C(0x3f)
3316 #define TX_BD_LONG_TYPE_SFT 0
3321 #define TX_BD_LONG_TYPE_TX_BD_LONG UINT32_C(0x10)
3328 #define TX_BD_LONG_FLAGS_MASK UINT32_C(0xffc0)
3335 #define TX_BD_LONG_FLAGS_PACKET_END UINT32_C(0x40)
3341 * is set to 0, then the packet will be completed normally.
3345 #define TX_BD_LONG_FLAGS_NO_CMPL UINT32_C(0x80)
3352 * BD in the packet. A value of 0 indicates
3357 #define TX_BD_LONG_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3367 #define TX_BD_LONG_FLAGS_LHINT_MASK UINT32_C(0x6000)
3370 #define TX_BD_LONG_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
3372 #define TX_BD_LONG_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
3374 #define TX_BD_LONG_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
3376 #define TX_BD_LONG_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
3384 * is set to 0, then the Consumer Index is only updated as soon
3389 #define TX_BD_LONG_FLAGS_COAL_NOW UINT32_C(0x8000)
3437 #define TX_BD_LONG_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
3446 #define TX_BD_LONG_LFLAGS_IP_CHKSUM UINT32_C(0x2)
3458 #define TX_BD_LONG_LFLAGS_NOCRC UINT32_C(0x4)
3477 #define TX_BD_LONG_LFLAGS_STAMP UINT32_C(0x8)
3494 #define TX_BD_LONG_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
3506 #define TX_BD_LONG_LFLAGS_LSO UINT32_C(0x20)
3510 * 0xffff.
3514 * 0x7fff.
3516 #define TX_BD_LONG_LFLAGS_IPID_FMT UINT32_C(0x40)
3528 #define TX_BD_LONG_LFLAGS_T_IPID UINT32_C(0x80)
3533 #define TX_BD_LONG_LFLAGS_ROCE_CRC UINT32_C(0x100)
3538 #define TX_BD_LONG_LFLAGS_FCOE_CRC UINT32_C(0x200)
3541 * to 0, then TWE provides the timestamp.
3548 #define TX_BD_LONG_LFLAGS_BD_TS_EN UINT32_C(0x400)
3553 #define TX_BD_LONG_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
3564 #define TX_BD_LONG_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
3571 * If outer UDP checksum is 0, then do not update it.
3575 #define TX_BD_LONG_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
3584 #define TX_BD_LONG_LFLAGS_OT_IPID UINT32_C(0x4000)
3594 #define TX_BD_LONG_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
3605 #define TX_BD_LONG_HDR_SIZE_MASK UINT32_C(0x1ff)
3606 #define TX_BD_LONG_HDR_SIZE_SFT 0
3617 #define TX_BD_LONG_KID_OR_TS_LOW_MASK UINT32_C(0xfe00)
3627 #define TX_BD_LONG_MSS_MASK UINT32_C(0x7fff)
3628 #define TX_BD_LONG_MSS_SFT 0
3639 #define TX_BD_LONG_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
3646 #define TX_BD_LONG_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
3647 #define TX_BD_LONG_CFA_ACTION_HIGH_SFT 0
3661 #define TX_BD_LONG_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
3662 #define TX_BD_LONG_CFA_META_VLAN_VID_SFT 0
3664 #define TX_BD_LONG_CFA_META_VLAN_DE UINT32_C(0x1000)
3666 #define TX_BD_LONG_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
3669 #define TX_BD_LONG_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
3671 /* 0x88a8 */
3672 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
3673 /* 0x8100 */
3674 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
3675 /* 0x9100 */
3676 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
3677 /* 0x9200 */
3678 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
3679 /* 0x9300 */
3680 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
3682 #define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
3685 #define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
3693 #define TX_BD_LONG_CFA_META_KEY_MASK UINT32_C(0xf0000000)
3696 #define TX_BD_LONG_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
3698 * - meta[17:16] - TPID select value (0 = 0x8100).
3700 * - meta[11:0] - VID value.
3702 #define TX_BD_LONG_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
3706 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
3708 * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if
3711 #define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER (UINT32_C(0x2) << 28)
3727 #define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)
3728 #define TX_BD_LONG_INLINE_TYPE_SFT 0
3733 #define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)
3739 #define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)
3746 #define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)
3750 * If this bit is set to 0, then the packet will be completed
3755 #define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)
3761 #define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
3764 #define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)
3772 * is set to 0, then the Consumer Index is only updated as soon
3777 #define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)
3818 #define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
3825 #define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)
3835 #define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)
3841 #define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)
3848 #define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
3850 * This bit must be 0 for BDs of this type. LSO is not supported with
3853 #define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)
3855 #define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)
3857 #define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)
3862 #define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)
3867 #define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)
3870 * to 0, then TWE provides the timestamp.
3877 #define TX_BD_LONG_INLINE_LFLAGS_BD_TS_EN UINT32_C(0x400)
3882 #define TX_BD_LONG_INLINE_LFLAGS_DEBUG_TRACE UINT32_C(0x800)
3888 #define TX_BD_LONG_INLINE_LFLAGS_STAMP_1STEP UINT32_C(0x1000)
3895 * is 0, then do not update it. If outer UDP checksum is non zero, then
3898 #define TX_BD_LONG_INLINE_LFLAGS_OT_IP_CHKSUM UINT32_C(0x2000)
3907 #define TX_BD_LONG_INLINE_LFLAGS_OT_IPID UINT32_C(0x4000)
3917 #define TX_BD_LONG_INLINE_LFLAGS_CRYPTO_EN UINT32_C(0x8000)
3920 #define TX_BD_LONG_INLINE_UNUSED UINT32_C(0x1)
3931 #define TX_BD_LONG_INLINE_KID_OR_TS_LOW_MASK UINT32_C(0xfe)
3934 #define TX_BD_LONG_INLINE_UNUSED_MASK UINT32_C(0x7fff)
3935 #define TX_BD_LONG_INLINE_UNUSED_SFT 0
3946 #define TX_BD_LONG_INLINE_KID_OR_TS_HIGH_MASK UINT32_C(0xffff8000)
3953 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
3954 #define TX_BD_LONG_INLINE_CFA_ACTION_HIGH_SFT 0
3968 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
3969 #define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0
3971 #define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)
3973 #define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
3976 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
3978 /* 0x88a8 */
3979 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
3980 /* 0x8100 */
3981 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
3982 /* 0x9100 */
3983 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
3984 /* 0x9200 */
3985 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
3986 /* 0x9300 */
3987 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
3989 #define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
3991 #define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
3999 #define TX_BD_LONG_INLINE_CFA_META_KEY_MASK UINT32_C(0xf0000000)
4002 #define TX_BD_LONG_INLINE_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
4004 * - meta[17:16] - TPID select value (0 = 0x8100).
4006 * - meta[11:0] - VID value.
4008 #define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
4012 * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta
4014 * - SR2 - {4'd0, cfa_meta[27:0]} is used for metadata output if
4017 #define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER (UINT32_C(0x2) << 28)
4026 #define TX_BD_EMPTY_TYPE_MASK UINT32_C(0x3f)
4027 #define TX_BD_EMPTY_TYPE_SFT 0
4032 #define TX_BD_EMPTY_TYPE_TX_BD_EMPTY UINT32_C(0x1)
4046 #define TX_BD_MP_CMD_TYPE_MASK UINT32_C(0x3f)
4047 #define TX_BD_MP_CMD_TYPE_SFT 0
4052 #define TX_BD_MP_CMD_TYPE_TX_BD_MP_CMD UINT32_C(0x8)
4054 #define TX_BD_MP_CMD_FLAGS_MASK UINT32_C(0xffc0)
4057 #define TX_BD_MP_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
4064 #define TX_BD_MP_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
4092 #define TX_BD_PRESYNC_CMD_TYPE_MASK UINT32_C(0x3f)
4093 #define TX_BD_PRESYNC_CMD_TYPE_SFT 0
4098 #define TX_BD_PRESYNC_CMD_TYPE_TX_BD_PRESYNC_CMD UINT32_C(0x9)
4100 #define TX_BD_PRESYNC_CMD_FLAGS_MASK UINT32_C(0xffc0)
4103 #define TX_BD_PRESYNC_CMD_FLAGS_UNUSED_MASK UINT32_C(0xc0)
4110 #define TX_BD_PRESYNC_CMD_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
4138 #define TX_BD_PRESYNC_CMD_KID_VAL_MASK UINT32_C(0xfffff)
4139 #define TX_BD_PRESYNC_CMD_KID_VAL_SFT 0
4154 #define TX_BD_TIMEDTX_TYPE_MASK UINT32_C(0x3f)
4155 #define TX_BD_TIMEDTX_TYPE_SFT 0
4161 #define TX_BD_TIMEDTX_TYPE_TX_BD_TIMEDTX UINT32_C(0xa)
4164 #define TX_BD_TIMEDTX_FLAGS_MASK UINT32_C(0xffc0)
4170 #define TX_BD_TIMEDTX_FLAGS_KIND_MASK UINT32_C(0x1c0)
4180 #define TX_BD_TIMEDTX_FLAGS_KIND_ASAP (UINT32_C(0x0) << 6)
4189 #define TX_BD_TIMEDTX_FLAGS_KIND_SO_TXTIME (UINT32_C(0x1) << 6)
4197 #define TX_BD_TIMEDTX_FLAGS_KIND_PACE (UINT32_C(0x2) << 6)
4222 #define TX_BD_TIMEDTX_RATE_VAL_MASK UINT32_C(0x1ffffff)
4223 #define TX_BD_TIMEDTX_RATE_VAL_SFT 0
4239 #define RX_PROD_PKT_BD_TYPE_MASK UINT32_C(0x3f)
4240 #define RX_PROD_PKT_BD_TYPE_SFT 0
4245 #define RX_PROD_PKT_BD_TYPE_RX_PROD_PKT UINT32_C(0x4)
4247 #define RX_PROD_PKT_BD_FLAGS_MASK UINT32_C(0xffc0)
4259 #define RX_PROD_PKT_BD_FLAGS_SOP_PAD UINT32_C(0x40)
4269 #define RX_PROD_PKT_BD_FLAGS_EOP_PAD UINT32_C(0x80)
4284 #define RX_PROD_PKT_BD_FLAGS_BUFFERS_MASK UINT32_C(0x300)
4318 #define RX_PROD_BFR_BD_TYPE_MASK UINT32_C(0x3f)
4319 #define RX_PROD_BFR_BD_TYPE_SFT 0
4324 #define RX_PROD_BFR_BD_TYPE_RX_PROD_BFR UINT32_C(0x5)
4326 #define RX_PROD_BFR_BD_FLAGS_MASK UINT32_C(0xffc0)
4357 #define RX_PROD_AGG_BD_TYPE_MASK UINT32_C(0x3f)
4358 #define RX_PROD_AGG_BD_TYPE_SFT 0
4363 #define RX_PROD_AGG_BD_TYPE_RX_PROD_AGG UINT32_C(0x6)
4365 #define RX_PROD_AGG_BD_FLAGS_MASK UINT32_C(0xffc0)
4376 #define RX_PROD_AGG_BD_FLAGS_EOP_PAD UINT32_C(0x40)
4418 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
4419 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
4421 #define CFA_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
4424 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c0)
4427 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_OK (UINT32_C(0x0) << 6)
4429 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_UNSPRT_ERR (UINT32_C(0x1) << 6)
4434 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_FMT_ERR (UINT32_C(0x2) << 6)
4439 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_SCOPE_ERR (UINT32_C(0x3) << 6)
4447 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_ADDR_ERR (UINT32_C(0x4) << 6)
4452 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_CACHE_ERR (UINT32_C(0x5) << 6)
4459 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EM_FAIL (UINT32_C(0x6) << 6)
4464 #define CFA_CMPLS_CMP_DATA_MSG_STATUS_EVENT_COLLECT_FAIL (UINT32_C(0x7) << 6)
4466 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc00)
4469 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_MASK UINT32_C(0xff000)
4475 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ (UINT32_C(0x0) << 12)
4480 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_WRITE (UINT32_C(0x1) << 12)
4486 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_READ_CLR (UINT32_C(0x2) << 12)
4492 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_INSERT (UINT32_C(0x3) << 12)
4494 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EM_DELETE (UINT32_C(0x4) << 12)
4499 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_INVALIDATE (UINT32_C(0x5) << 12)
4501 #define CFA_CMPLS_CMP_DATA_MSG_OPCODE_EVENT_COLLECT (UINT32_C(0x6) << 12)
4506 * between 0 and 128. A value of zero indicates that there is no DMA
4509 #define CFA_CMPLS_CMP_DATA_MSG_DMA_LENGTH_MASK UINT32_C(0xff00000)
4515 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf0000000)
4518 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_TE_CFA (UINT32_C(0x2) << 28)
4520 #define CFA_CMPLS_CMP_DATA_MSG_MP_CLIENT_RE_CFA (UINT32_C(0x3) << 28)
4531 * write 1. The odd passes will write 0.
4533 #define CFA_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
4534 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xe)
4540 #define CFA_CMPLS_CMP_DATA_MSG_HASH_MSB_MASK UINT32_C(0xfff0)
4544 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xf)
4545 #define CFA_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 0
4546 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_MASK UINT32_C(0xf0)
4549 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_ACTION (UINT32_C(0x0) << 4)
4551 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_TYPE_EM (UINT32_C(0x1) << 4)
4555 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)
4556 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_SCOPE_SFT 0
4563 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_MASK UINT32_C(0x3ffffff)
4564 #define CFA_CMPLS_CMP_DATA_MSG_TABLE_INDEX_SFT 0
4609 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MASK UINT32_C(0x3f)
4610 #define CE_CMPLS_CMP_DATA_MSG_TYPE_SFT 0
4612 #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
4614 #define CE_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc0)
4620 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0xf00)
4623 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 8)
4625 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 8)
4627 #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 8)
4633 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf000)
4636 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_TCE (UINT32_C(0x0) << 12)
4638 #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE (UINT32_C(0x1) << 12)
4642 #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0xf)
4643 #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 0
4645 #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK UINT32_C(0x0)
4647 #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR UINT32_C(0x1)
4649 #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR UINT32_C(0x2)
4651 #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR UINT32_C(0x3)
4653 #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR UINT32_C(0x4)
4658 #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR UINT32_C(0x5)
4660 #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xfff0)
4671 * write 1. The odd passes will write 0.
4673 #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1)
4674 #define CE_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xfffffffe)
4681 #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0xfffff)
4682 #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 0
4683 #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_MASK UINT32_C(0xfff00000)
4698 #define CMPL_BASE_TYPE_MASK UINT32_C(0x3f)
4699 #define CMPL_BASE_TYPE_SFT 0
4704 #define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
4709 #define CMPL_BASE_TYPE_NO_OP UINT32_C(0x1)
4714 #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2)
4719 #define CMPL_BASE_TYPE_TX_L2_PKT_TS UINT32_C(0x4)
4726 #define CMPL_BASE_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
4733 #define CMPL_BASE_TYPE_RX_L2_V2 UINT32_C(0xf)
4739 #define CMPL_BASE_TYPE_RX_L2_COMPRESS UINT32_C(0x10)
4744 #define CMPL_BASE_TYPE_RX_L2 UINT32_C(0x11)
4750 #define CMPL_BASE_TYPE_RX_AGG UINT32_C(0x12)
4756 #define CMPL_BASE_TYPE_RX_TPA_START UINT32_C(0x13)
4762 #define CMPL_BASE_TYPE_RX_TPA_END UINT32_C(0x15)
4769 #define CMPL_BASE_TYPE_RX_TPA_AGG UINT32_C(0x16)
4774 #define CMPL_BASE_TYPE_RX_L2_V3 UINT32_C(0x17)
4780 #define CMPL_BASE_TYPE_RX_TPA_START_V3 UINT32_C(0x19)
4786 #define CMPL_BASE_TYPE_STAT_EJECT UINT32_C(0x1a)
4794 #define CMPL_BASE_TYPE_VEE_FLUSH UINT32_C(0x1c)
4799 #define CMPL_BASE_TYPE_MID_PATH_SHORT UINT32_C(0x1e)
4804 #define CMPL_BASE_TYPE_MID_PATH_LONG UINT32_C(0x1f)
4809 #define CMPL_BASE_TYPE_HWRM_DONE UINT32_C(0x20)
4811 #define CMPL_BASE_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
4813 #define CMPL_BASE_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
4815 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
4817 #define CMPL_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
4819 #define CMPL_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
4821 #define CMPL_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
4823 #define CMPL_BASE_TYPE_QP_EVENT UINT32_C(0x38)
4825 #define CMPL_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
4834 * will write 1. The odd passes will write 0.
4837 #define CMPL_BASE_V UINT32_C(0x1)
4838 #define CMPL_BASE_INFO3_MASK UINT32_C(0xfffffffe)
4855 #define TX_CMPL_TYPE_MASK UINT32_C(0x3f)
4856 #define TX_CMPL_TYPE_SFT 0
4861 #define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
4863 #define TX_CMPL_FLAGS_MASK UINT32_C(0xffc0)
4870 #define TX_CMPL_FLAGS_ERROR UINT32_C(0x40)
4874 * by the driver. When this bit is '0', it indicates that the
4878 #define TX_CMPL_FLAGS_PUSH UINT32_C(0x80)
4892 * will write 1. The odd passes will write 0.
4894 #define TX_CMPL_V UINT32_C(0x1)
4895 #define TX_CMPL_ERRORS_MASK UINT32_C(0xfffe)
4901 #define TX_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
4904 #define TX_CMPL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
4909 #define TX_CMPL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
4915 #define TX_CMPL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
4921 #define TX_CMPL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
4927 #define TX_CMPL_ERRORS_DMA_ERROR UINT32_C(0x40)
4932 #define TX_CMPL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
4938 #define TX_CMPL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
4944 #define TX_CMPL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
4948 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
4954 #define TX_CMPL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
4972 #define TX_CMPL_COAL_TYPE_MASK UINT32_C(0x3f)
4973 #define TX_CMPL_COAL_TYPE_SFT 0
4978 #define TX_CMPL_COAL_TYPE_TX_L2_COAL UINT32_C(0x2)
4980 #define TX_CMPL_COAL_FLAGS_MASK UINT32_C(0xffc0)
4987 #define TX_CMPL_COAL_FLAGS_ERROR UINT32_C(0x40)
4991 * by the driver. When this bit is '0', it indicates that the
4995 #define TX_CMPL_COAL_FLAGS_PUSH UINT32_C(0x80)
5018 * will write 1. The odd passes will write 0.
5020 #define TX_CMPL_COAL_V UINT32_C(0x1)
5021 #define TX_CMPL_COAL_ERRORS_MASK UINT32_C(0xfffe)
5027 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
5030 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
5035 #define TX_CMPL_COAL_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
5041 #define TX_CMPL_COAL_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
5047 #define TX_CMPL_COAL_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
5053 #define TX_CMPL_COAL_ERRORS_DMA_ERROR UINT32_C(0x40)
5058 #define TX_CMPL_COAL_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
5064 #define TX_CMPL_COAL_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
5070 #define TX_CMPL_COAL_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
5074 * timestamp_lo fields are invalid. When this bit is '0' for a PTP
5080 #define TX_CMPL_COAL_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
5088 #define TX_CMPL_COAL_SQ_CONS_IDX_MASK UINT32_C(0xffffff)
5089 #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0
5102 #define TX_CMPL_PACKET_TIMESTAMP_TYPE_MASK UINT32_C(0x3f)
5103 #define TX_CMPL_PACKET_TIMESTAMP_TYPE_SFT 0
5108 #define TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS UINT32_C(0x4)
5110 #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_MASK UINT32_C(0xfc0)
5116 #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_ERROR UINT32_C(0x40)
5123 #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE UINT32_C(0x80)
5125 #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PM (UINT32_C(0x0) << 7)
5127 #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA (UINT32_C(0x1) << 7)
5138 #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_FALLBACK UINT32_C(0x100)
5140 * For 2-step PTP timestamps, bits[3:0] of this field represent the
5148 #define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_MASK UINT32_C(0xf000)
5168 * will write 1. The odd passes will write 0.
5170 #define TX_CMPL_PACKET_TIMESTAMP_V UINT32_C(0x1)
5171 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_MASK UINT32_C(0xfffe)
5178 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
5181 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_NO_ERROR (UINT32_C(0x0) << 1)
5183 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT (UINT32_C(0x2) << 1)
5189 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10)
5194 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20)
5200 * for the timestamp completion and will always be '0'.
5202 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_DMA_ERROR UINT32_C(0x40)
5207 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80)
5213 * timestamp completion, and will always be '0'.
5215 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100)
5221 * and will always be '0'.
5223 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_INTERNAL_ERROR UINT32_C(0x200)
5227 * fields are invalid. When this bit is '0' in a timestamp
5231 * bit will always be '0'.
5233 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400)
5242 * and will always be '0'.
5244 #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TTX_OVERTIME_ERROR UINT32_C(0x800)
5248 * This is bits [31:0] of the nanoseconds portion of the packet
5266 #define RX_PKT_CMPL_TYPE_MASK UINT32_C(0x3f)
5267 #define RX_PKT_CMPL_TYPE_SFT 0
5272 #define RX_PKT_CMPL_TYPE_RX_L2 UINT32_C(0x11)
5274 #define RX_PKT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5281 #define RX_PKT_CMPL_FLAGS_ERROR UINT32_C(0x40)
5283 #define RX_PKT_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5289 #define RX_PKT_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
5294 #define RX_PKT_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
5300 #define RX_PKT_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
5303 #define RX_PKT_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
5308 #define RX_PKT_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
5313 #define RX_PKT_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5319 #define RX_PKT_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
5325 #define RX_PKT_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
5331 #define RX_PKT_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
5337 #define RX_PKT_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
5343 #define RX_PKT_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
5349 #define RX_PKT_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
5355 #define RX_PKT_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
5361 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12)
5367 #define RX_PKT_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
5385 * will write 1. The odd passes will write 0.
5387 #define RX_PKT_CMPL_V1 UINT32_C(0x1)
5394 #define RX_PKT_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
5397 #define RX_PKT_CMPL_UNUSED1_MASK UINT32_C(0xc0)
5401 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5418 #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0)
5425 #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1)
5432 #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2)
5438 #define RX_PKT_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3)
5467 #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
5473 #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
5479 #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
5485 #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
5487 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
5490 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
5493 * - metadata[11:0] contains the vlan VID value.
5498 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
5503 * - VXLAN = VNI[23:0] -> VXLAN Network ID
5504 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
5505 * - NVGRE = TNI[23:0] -> Tenant Network ID
5506 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
5507 * - IPV4 = 0 (not populated)
5508 * - IPV6 = Flow Label[19:0]
5509 * - PPPoE = sessionID[15:0]
5510 * - MPLs = Outer label[19:0]
5511 * - UPAR = Selected[31:0] with bit mask
5513 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
5518 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
5523 * - metadata[8:0] contains the outer_l3_offset.
5528 #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
5532 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
5536 #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
5541 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
5546 #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
5554 #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
5562 #define RX_PKT_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
5563 #define RX_PKT_CMPL_METADATA_VID_SFT 0
5565 #define RX_PKT_CMPL_METADATA_DE UINT32_C(0x1000)
5567 #define RX_PKT_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
5570 #define RX_PKT_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
5576 * will write 1. The odd passes will write 0.
5578 #define RX_PKT_CMPL_V2 UINT32_C(0x1)
5579 #define RX_PKT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
5587 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
5590 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
5599 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
5605 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
5610 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
5615 #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
5621 #define RX_PKT_CMPL_ERRORS_IP_CS_ERROR UINT32_C(0x10)
5626 #define RX_PKT_CMPL_ERRORS_L4_CS_ERROR UINT32_C(0x20)
5631 #define RX_PKT_CMPL_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
5636 #define RX_PKT_CMPL_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
5641 #define RX_PKT_CMPL_ERRORS_CRC_ERROR UINT32_C(0x100)
5647 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
5653 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
5659 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
5665 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
5671 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9)
5677 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9)
5683 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9)
5686 * have failed (e.g. TTL = 0) in the tunnel header. Valid
5689 #define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9)
5696 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
5702 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
5709 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
5714 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
5717 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
5719 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
5725 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
5731 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
5736 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
5738 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
5744 #define RX_PKT_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
5759 #define RX_PKT_CMPL_REORDER_MASK UINT32_C(0xffffff)
5760 #define RX_PKT_CMPL_REORDER_SFT 0
5774 #define RX_PKT_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
5775 #define RX_PKT_V2_CMPL_TYPE_SFT 0
5782 #define RX_PKT_V2_CMPL_TYPE_RX_L2_V2 UINT32_C(0xf)
5784 #define RX_PKT_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
5791 #define RX_PKT_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
5793 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
5799 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
5804 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
5810 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
5817 #define RX_PKT_V2_CMPL_FLAGS_PLACEMENT_TRUNCATION (UINT32_C(0x3) << 7)
5820 #define RX_PKT_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
5829 #define RX_PKT_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
5834 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
5840 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
5846 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
5852 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
5858 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
5864 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
5870 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
5876 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
5882 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12)
5888 #define RX_PKT_V2_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
5906 * will write 1. The odd passes will write 0.
5908 #define RX_PKT_V2_CMPL_V1 UINT32_C(0x1)
5915 #define RX_PKT_V2_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
5918 #define RX_PKT_V2_CMPL_UNUSED1_MASK UINT32_C(0xc0)
5922 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
5939 #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_0 UINT32_C(0x0)
5946 #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_1 UINT32_C(0x1)
5953 #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_2 UINT32_C(0x2)
5959 #define RX_PKT_V2_CMPL_RSS_HASH_TYPE_ENUM_3 UINT32_C(0x3)
5970 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
5971 #define RX_PKT_V2_CMPL_PAYLOAD_OFFSET_SFT 0
5973 #define RX_PKT_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
5975 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
5976 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
5978 /* 0x88a8 */
5979 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 12)
5980 /* 0x8100 */
5981 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 12)
5982 /* 0x9100 */
5983 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 12)
5984 /* 0x9200 */
5985 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 12)
5986 /* 0x9300 */
5987 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 12)
5989 #define RX_PKT_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 12)
5991 /* When meta_format != 0, this value is the VLAN valid. */
5992 #define RX_PKT_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
6008 * When this bit is '0', the cs_ok field has the following definition:-
6009 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
6016 * hdr_cnt[2:0] = The number of header groups that were parsed by the
6022 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_ALL_OK_MODE UINT32_C(0x8)
6024 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
6027 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
6030 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
6031 * de, vid[11:0]} The metadata2 field contains the table scope
6032 * and action record pointer. - metadata2[25:0] contains the
6036 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
6040 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
6043 * - VXLAN = VNI[23:0] -> VXLAN Network ID
6044 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
6045 * - NVGRE = TNI[23:0] -> Tenant Network ID
6046 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
6047 * - IPv4 = 0 (not populated)
6048 * - IPv6 = Flow Label[19:0]
6049 * - PPPoE = sessionID[15:0]
6050 * - MPLs = Outer label[19:0]
6051 * - UPAR = Selected[31:0] with bit mask
6053 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
6057 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
6061 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
6065 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
6068 * - metadata2[8:0] contains the outer_l3_offset.
6073 #define RX_PKT_V2_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
6077 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6081 #define RX_PKT_V2_CMPL_HI_FLAGS2_IP_TYPE UINT32_C(0x100)
6086 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
6092 #define RX_PKT_V2_CMPL_HI_FLAGS2_CS_OK_MASK UINT32_C(0xfc00)
6100 #define RX_PKT_V2_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
6105 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
6106 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
6107 * act_rec_ptr[25:0]}
6108 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
6109 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
6110 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
6119 * will write 1. The odd passes will write 0.
6121 #define RX_PKT_V2_CMPL_HI_V2 UINT32_C(0x1)
6122 #define RX_PKT_V2_CMPL_HI_ERRORS_MASK UINT32_C(0xfffe)
6130 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
6133 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
6143 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
6150 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
6155 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
6160 #define RX_PKT_V2_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
6166 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_MASK UINT32_C(0x70)
6172 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 4)
6177 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_VERSION (UINT32_C(0x1) << 4)
6182 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_HDR_LEN (UINT32_C(0x2) << 4)
6188 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_TOTAL_ERROR (UINT32_C(0x3) << 4)
6194 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_UDP_TOTAL_ERROR (UINT32_C(0x4) << 4)
6197 * failed (e.g. TTL = 0) in the outer tunnel header. Valid for
6200 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L3_BAD_TTL (UINT32_C(0x5) << 4)
6205 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_IP_CS_ERROR (UINT32_C(0x6) << 4)
6210 #define RX_PKT_V2_CMPL_HI_ERRORS_OT_PKT_ERROR_OT_L4_CS_ERROR (UINT32_C(0x7) << 4)
6216 #define RX_PKT_V2_CMPL_HI_ERRORS_CRC_ERROR UINT32_C(0x100)
6221 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
6227 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
6232 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
6237 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
6243 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x3) << 9)
6249 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x4) << 9)
6252 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
6254 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 9)
6259 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR (UINT32_C(0x6) << 9)
6264 #define RX_PKT_V2_CMPL_HI_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR (UINT32_C(0x7) << 9)
6271 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
6277 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
6284 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
6289 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
6292 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
6294 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
6300 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
6306 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
6311 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
6313 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
6319 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
6324 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_IP_CS_ERROR (UINT32_C(0x9) << 12)
6329 #define RX_PKT_V2_CMPL_HI_ERRORS_PKT_ERROR_L4_CS_ERROR (UINT32_C(0xa) << 12)
6337 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
6338 #define RX_PKT_V2_CMPL_HI_METADATA0_VID_SFT 0
6340 #define RX_PKT_V2_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
6342 #define RX_PKT_V2_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
6362 #define RX_PKT_V3_CMPL_TYPE_MASK UINT32_C(0x3f)
6363 #define RX_PKT_V3_CMPL_TYPE_SFT 0
6370 #define RX_PKT_V3_CMPL_TYPE_RX_L2_V3 UINT32_C(0x17)
6372 #define RX_PKT_V3_CMPL_FLAGS_MASK UINT32_C(0xffc0)
6379 #define RX_PKT_V3_CMPL_FLAGS_ERROR UINT32_C(0x40)
6381 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
6387 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_NORMAL (UINT32_C(0x0) << 7)
6392 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
6398 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
6405 #define RX_PKT_V3_CMPL_FLAGS_PLACEMENT_TRUNCATION (UINT32_C(0x3) << 7)
6408 #define RX_PKT_V3_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
6417 #define RX_PKT_V3_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
6422 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
6428 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
6434 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
6440 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
6446 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
6452 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
6458 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
6464 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
6470 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12)
6478 #define RX_PKT_V3_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
6496 * will write 1. The odd passes will write 0.
6498 #define RX_PKT_V3_CMPL_V1 UINT32_C(0x1)
6505 #define RX_PKT_V3_CMPL_AGG_BUFS_MASK UINT32_C(0x3e)
6508 #define RX_PKT_V3_CMPL_UNUSED1 UINT32_C(0x40)
6511 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
6521 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80)
6528 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_0 (UINT32_C(0x0) << 7)
6533 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_1 (UINT32_C(0x1) << 7)
6540 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_2 (UINT32_C(0x2) << 7)
6546 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_3 (UINT32_C(0x3) << 7)
6551 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_4 (UINT32_C(0x4) << 7)
6556 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_5 (UINT32_C(0x5) << 7)
6562 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_6 (UINT32_C(0x6) << 7)
6568 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_7 (UINT32_C(0x7) << 7)
6575 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_8 (UINT32_C(0x8) << 7)
6582 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_9 (UINT32_C(0x9) << 7)
6589 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_10 (UINT32_C(0xa) << 7)
6596 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_11 (UINT32_C(0xb) << 7)
6598 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_12 (UINT32_C(0xc) << 7)
6603 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_13 (UINT32_C(0xd) << 7)
6608 #define RX_PKT_V3_CMPL_RSS_HASH_TYPE_ENUM_14 (UINT32_C(0xe) << 7)
6622 #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_MASK UINT32_C(0x1ff)
6623 #define RX_PKT_V3_CMPL_PAYLOAD_OFFSET_SFT 0
6625 #define RX_PKT_V3_CMPL_METADATA1_MASK UINT32_C(0xf000)
6627 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
6628 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
6630 /* 0x88a8 */
6631 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 12)
6632 /* 0x8100 */
6633 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 12)
6634 /* 0x9100 */
6635 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 12)
6636 /* 0x9200 */
6637 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 12)
6638 /* 0x9300 */
6639 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 12)
6641 #define RX_PKT_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 12)
6643 /* When meta_format != 0, this value is the VLAN valid. */
6644 #define RX_PKT_V3_CMPL_METADATA1_VALID UINT32_C(0x8000)
6664 #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_CS_CALC UINT32_C(0x1)
6670 #define RX_PKT_V3_CMPL_HI_FLAGS2_L4_CS_CALC UINT32_C(0x2)
6676 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
6682 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
6684 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
6687 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
6690 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
6691 * de, vid[11:0]} The metadata2 field contains the table scope
6692 * and action record pointer. - metadata2[25:0] contains the
6696 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
6700 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
6703 * - VXLAN = VNI[23:0] -> VXLAN Network ID
6704 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
6705 * - NVGRE = TNI[23:0] -> Tenant Network ID
6706 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
6707 * - IPv4 = 0 (not populated)
6708 * - IPv6 = Flow Label[19:0]
6709 * - PPPoE = sessionID[15:0]
6710 * - MPLs = Outer label[19:0]
6711 * - UPAR = Selected[31:0] with bit mask
6713 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
6717 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
6721 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
6725 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
6728 * - metadata2[8:0] contains the outer_l3_offset.
6733 #define RX_PKT_V3_CMPL_HI_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
6737 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
6741 #define RX_PKT_V3_CMPL_HI_FLAGS2_IP_TYPE UINT32_C(0x100)
6746 #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
6752 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE UINT32_C(0x400)
6754 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV4 (UINT32_C(0x0) << 10)
6756 #define RX_PKT_V3_CMPL_HI_FLAGS2_T_IP_TYPE_IPV6 (UINT32_C(0x1) << 10)
6764 #define RX_PKT_V3_CMPL_HI_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
6769 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
6770 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
6771 * act_rec_ptr[25:0]}
6772 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
6773 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
6774 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
6781 * will write 1. The odd passes will write 0.
6783 #define RX_PKT_V3_CMPL_HI_V2 UINT32_C(0x1)
6784 #define RX_PKT_V3_CMPL_HI_ERRORS_MASK UINT32_C(0xfffe)
6792 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
6795 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
6802 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
6809 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
6814 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
6819 #define RX_PKT_V3_CMPL_HI_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
6822 #define RX_PKT_V3_CMPL_HI_ERRORS_IP_CS_ERROR UINT32_C(0x10)
6827 #define RX_PKT_V3_CMPL_HI_ERRORS_L4_CS_ERROR UINT32_C(0x20)
6832 #define RX_PKT_V3_CMPL_HI_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
6834 #define RX_PKT_V3_CMPL_HI_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
6839 #define RX_PKT_V3_CMPL_HI_ERRORS_CRC_ERROR UINT32_C(0x100)
6844 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
6850 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
6855 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
6860 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
6866 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x3) << 9)
6872 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x4) << 9)
6875 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
6877 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 9)
6883 #define RX_PKT_V3_CMPL_HI_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (UINT32_C(0x6) << 9)
6890 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
6896 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
6903 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
6908 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
6911 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
6913 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
6919 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
6925 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
6930 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
6932 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 12)
6938 #define RX_PKT_V3_CMPL_HI_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
6946 #define RX_PKT_V3_CMPL_HI_METADATA0_VID_MASK UINT32_C(0xfff)
6947 #define RX_PKT_V3_CMPL_HI_METADATA0_VID_SFT 0
6949 #define RX_PKT_V3_CMPL_HI_METADATA0_DE UINT32_C(0x1000)
6951 #define RX_PKT_V3_CMPL_HI_METADATA0_PRI_MASK UINT32_C(0xe000)
6974 #define RX_PKT_COMPRESS_CMPL_TYPE_MASK UINT32_C(0x3f)
6975 #define RX_PKT_COMPRESS_CMPL_TYPE_SFT 0
6983 #define RX_PKT_COMPRESS_CMPL_TYPE_RX_L2_COMPRESS UINT32_C(0x10)
6985 #define RX_PKT_COMPRESS_CMPL_FLAGS_MASK UINT32_C(0xffc0)
6992 #define RX_PKT_COMPRESS_CMPL_FLAGS_ERROR UINT32_C(0x40)
6998 #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE UINT32_C(0x100)
7000 #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV4 (UINT32_C(0x0) << 8)
7002 #define RX_PKT_COMPRESS_CMPL_FLAGS_T_IP_TYPE_IPV6 (UINT32_C(0x1) << 8)
7006 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
7010 #define RX_PKT_COMPRESS_CMPL_FLAGS_IP_TYPE UINT32_C(0x200)
7012 #define RX_PKT_COMPRESS_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
7017 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
7023 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 12)
7029 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_IP (UINT32_C(0x1) << 12)
7035 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
7041 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 12)
7047 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 12)
7053 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 12)
7059 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 12)
7065 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 12)
7073 #define RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 12)
7093 * will write 1. The odd passes will write 0.
7095 #define RX_PKT_COMPRESS_CMPL_V1 UINT32_C(0x1)
7097 #define RX_PKT_COMPRESS_CMPL_UNUSED_MASK UINT32_C(0xe)
7099 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_MASK UINT32_C(0xff0)
7102 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_ERROR UINT32_C(0x10)
7107 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_ERROR UINT32_C(0x20)
7112 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_ERROR UINT32_C(0x40)
7114 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_ERROR UINT32_C(0x80)
7120 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_IP_CS_CALC UINT32_C(0x100)
7126 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_L4_CS_CALC UINT32_C(0x200)
7132 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_IP_CS_CALC UINT32_C(0x400)
7138 #define RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_T_L4_CS_CALC UINT32_C(0x800)
7140 #define RX_PKT_COMPRESS_CMPL_METADATA1_MASK UINT32_C(0xf000)
7142 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
7143 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
7145 /* 0x88a8 */
7146 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 12)
7147 /* 0x8100 */
7148 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 12)
7149 /* 0x9100 */
7150 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 12)
7151 /* 0x9200 */
7152 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 12)
7153 /* 0x9300 */
7154 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 12)
7156 #define RX_PKT_COMPRESS_CMPL_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 12)
7158 /* When meta_format != 0, this value is the VLAN valid. */
7159 #define RX_PKT_COMPRESS_CMPL_METADATA1_VALID UINT32_C(0x8000)
7162 /* When meta_format!=0, this value is the VLAN VID. */
7163 #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_MASK UINT32_C(0xfff)
7164 #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_VID_SFT 0
7165 /* When meta_format!=0, this value is the VLAN DE. */
7166 #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_DE UINT32_C(0x1000)
7167 /* When meta_format!=0, this value is the VLAN PRI. */
7168 #define RX_PKT_COMPRESS_CMPL_VLANC_TCID_PRI_MASK UINT32_C(0xe000)
7172 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_MASK UINT32_C(0xffff)
7173 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_OPAQUE_SFT 0
7180 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_AGG_BUFS_MASK UINT32_C(0x1f0000)
7182 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_MASK UINT32_C(0x1fe00000)
7189 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_MASK UINT32_C(0x1e00000)
7195 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 2…
7202 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1…
7207 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2…
7210 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
7212 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) <<…
7218 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4…
7224 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x…
7229 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6…
7231 …PRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << 21)
7237 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8…
7243 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe000000)
7249 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) <<…
7254 …_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 25)
7259 …_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 25)
7265 …_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x3) << 25)
7271 …PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x4) << 25)
7274 * (e.g. TTL = 0) in the tunnel header. Valid for IPv4, and IPv6.
7276 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5…
7281 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_IP_CS_ERROR (UINT32_C(0x…
7286 …#define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_T_PKT_ERROR_T_L4_CS_ERROR (UINT32_C(0x…
7292 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_ERRORS_CRC_ERROR UINT32_C(0x10000000)
7294 #define RX_PKT_COMPRESS_CMPL_ERRORS_AGG_BUFS_OPAQUE_UNUSED1_MASK UINT32_C(0xe0000000)
7300 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7313 #define RX_TPA_START_CMPL_TYPE_MASK UINT32_C(0x3f)
7314 #define RX_TPA_START_CMPL_TYPE_SFT 0
7320 #define RX_TPA_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
7322 #define RX_TPA_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
7324 /* This bit will always be '0' for TPA start completions. */
7325 #define RX_TPA_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
7327 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
7337 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
7343 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
7352 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
7362 #define RX_TPA_START_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
7365 #define RX_TPA_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
7367 #define RX_TPA_START_CMPL_FLAGS_UNUSED UINT32_C(0x800)
7372 #define RX_TPA_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
7378 #define RX_TPA_START_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
7393 * will write 1. The odd passes will write 0.
7399 * will write 1. The odd passes will write 0.
7401 #define RX_TPA_START_CMPL_V1 UINT32_C(0x1)
7405 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
7409 * * 0: The RSS hash was computed over source IP address,
7440 #define RX_TPA_START_CMPL_UNUSED2_MASK UINT32_C(0x1ff)
7441 #define RX_TPA_START_CMPL_UNUSED2_SFT 0
7447 #define RX_TPA_START_CMPL_AGG_ID_MASK UINT32_C(0xfe00)
7460 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7471 #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
7477 #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
7483 #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
7489 #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
7491 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
7494 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
7497 * - metadata[11:0] contains the vlan VID value.
7502 #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
7506 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
7508 #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
7515 #define RX_TPA_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
7516 #define RX_TPA_START_CMPL_METADATA_VID_SFT 0
7518 #define RX_TPA_START_CMPL_METADATA_DE UINT32_C(0x1000)
7520 #define RX_TPA_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
7523 #define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
7529 * will write 1. The odd passes will write 0.
7531 #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
7548 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
7549 #define RX_TPA_START_CMPL_OUTER_L3_OFFSET_SFT 0
7554 #define RX_TPA_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
7560 #define RX_TPA_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
7567 #define RX_TPA_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
7573 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7588 #define RX_TPA_START_V2_CMPL_TYPE_MASK UINT32_C(0x3f)
7589 #define RX_TPA_START_V2_CMPL_TYPE_SFT 0
7597 #define RX_TPA_START_V2_CMPL_TYPE_RX_TPA_START_V2 UINT32_C(0xd)
7599 #define RX_TPA_START_V2_CMPL_FLAGS_MASK UINT32_C(0xffc0)
7605 #define RX_TPA_START_V2_CMPL_FLAGS_ERROR UINT32_C(0x40)
7607 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
7617 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
7623 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
7631 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_JUMBO (UINT32_C(0x4) << 7)
7640 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
7650 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
7658 #define RX_TPA_START_V2_CMPL_FLAGS_PLACEMENT_IOC_HDS (UINT32_C(0x7) << 7)
7661 #define RX_TPA_START_V2_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
7670 #define RX_TPA_START_V2_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
7675 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
7681 #define RX_TPA_START_V2_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
7698 * will write 1. The odd passes will write 0.
7704 * will write 1. The odd passes will write 0.
7706 #define RX_TPA_START_V2_CMPL_V1 UINT32_C(0x1)
7710 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
7714 * * 0: The RSS hash was computed over source IP address,
7749 #define RX_TPA_START_V2_CMPL_AGG_ID_MASK UINT32_C(0xfff)
7750 #define RX_TPA_START_V2_CMPL_AGG_ID_SFT 0
7751 #define RX_TPA_START_V2_CMPL_METADATA1_MASK UINT32_C(0xf000)
7753 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
7754 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
7756 /* 0x88a8 */
7757 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 12)
7758 /* 0x8100 */
7759 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 12)
7760 /* 0x9100 */
7761 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 12)
7762 /* 0x9200 */
7763 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 12)
7764 /* 0x9300 */
7765 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 12)
7767 #define RX_TPA_START_V2_CMPL_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 12)
7769 /* When meta_format != 0, this value is the VLAN valid. */
7770 #define RX_TPA_START_V2_CMPL_METADATA1_VALID UINT32_C(0x8000)
7784 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7791 #define RX_TPA_START_V2_CMPL_FLAGS2_AGG_GRO UINT32_C(0x4)
7793 * When this bit is '0', the cs_ok field has the following definition:-
7794 * ip_cs_ok[2:0] = The number of header groups with a valid IP checksum
7801 * hdr_cnt[2:0] = The number of header groups that were parsed by the
7807 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_ALL_OK_MODE UINT32_C(0x8)
7809 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
7812 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
7815 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
7816 * de, vid[11:0]} The metadata2 field contains the table scope
7817 * and action record pointer. - metadata2[25:0] contains the
7821 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
7825 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
7828 * - VXLAN = VNI[23:0] -> VXLAN Network ID
7829 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
7830 * - NVGRE = TNI[23:0] -> Tenant Network ID
7831 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
7832 * - IPv4 = 0 (not populated)
7833 * - IPv6 = Flow Label[19:0]
7834 * - PPPoE = sessionID[15:0]
7835 * - MPLs = Outer label[19:0]
7836 * - UPAR = Selected[31:0] with bit mask
7838 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
7842 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
7846 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
7850 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
7853 * - metadata2[8:0] contains the outer_l3_offset.
7858 #define RX_TPA_START_V2_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
7862 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
7866 #define RX_TPA_START_V2_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
7871 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
7881 #define RX_TPA_START_V2_CMPL_FLAGS2_CS_OK_MASK UINT32_C(0xfc00)
7891 #define RX_TPA_START_V2_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
7896 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
7897 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
7898 * act_rec_ptr[25:0]}
7899 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
7900 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
7901 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
7910 * will write 1. The odd passes will write 0.
7912 #define RX_TPA_START_V2_CMPL_V2 UINT32_C(0x1)
7913 #define RX_TPA_START_V2_CMPL_ERRORS_MASK UINT32_C(0xfffe)
7920 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
7923 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
7934 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
7939 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
7944 #define RX_TPA_START_V2_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
7951 /* When meta_format != 0, this value is the VLAN VID. */
7952 #define RX_TPA_START_V2_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
7953 #define RX_TPA_START_V2_CMPL_METADATA0_VID_SFT 0
7954 /* When meta_format != 0, this value is the VLAN DE. */
7955 #define RX_TPA_START_V2_CMPL_METADATA0_DE UINT32_C(0x1000)
7956 /* When meta_format != 0, this value is the VLAN PRI. */
7957 #define RX_TPA_START_V2_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
7963 * hdr_offsets[8:0] contains the outer_l3_offset.
7973 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
7988 #define RX_TPA_START_V3_CMPL_TYPE_MASK UINT32_C(0x3f)
7989 #define RX_TPA_START_V3_CMPL_TYPE_SFT 0
7997 #define RX_TPA_START_V3_CMPL_TYPE_RX_TPA_START_V3 UINT32_C(0x19)
7999 #define RX_TPA_START_V3_CMPL_FLAGS_MASK UINT32_C(0xffc0)
8005 #define RX_TPA_START_V3_CMPL_FLAGS_ERROR UINT32_C(0x40)
8007 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
8017 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
8023 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
8031 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_JUMBO (UINT32_C(0x4) << 7)
8040 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
8050 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
8058 #define RX_TPA_START_V3_CMPL_FLAGS_PLACEMENT_IOC_HDS (UINT32_C(0x7) << 7)
8061 #define RX_TPA_START_V3_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
8070 #define RX_TPA_START_V3_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
8075 #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
8081 #define RX_TPA_START_V3_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
8099 * will write 1. The odd passes will write 0.
8101 #define RX_TPA_START_V3_CMPL_V1 UINT32_C(0x1)
8103 #define RX_TPA_START_V3_CMPL_UNUSED1_MASK UINT32_C(0x7e)
8107 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
8111 * * 0: The RSS hash was computed over source IP address,
8156 #define RX_TPA_START_V3_CMPL_RSS_HASH_TYPE_MASK UINT32_C(0xff80)
8169 #define RX_TPA_START_V3_CMPL_AGG_ID_MASK UINT32_C(0xfff)
8170 #define RX_TPA_START_V3_CMPL_AGG_ID_SFT 0
8171 #define RX_TPA_START_V3_CMPL_METADATA1_MASK UINT32_C(0xf000)
8173 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
8174 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
8176 /* 0x88a8 */
8177 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 12)
8178 /* 0x8100 */
8179 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 12)
8180 /* 0x9100 */
8181 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 12)
8182 /* 0x9200 */
8183 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 12)
8184 /* 0x9300 */
8185 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 12)
8187 #define RX_TPA_START_V3_CMPL_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 12)
8189 /* When meta_format != 0, this value is the VLAN valid. */
8190 #define RX_TPA_START_V3_CMPL_METADATA1_VALID UINT32_C(0x8000)
8204 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
8215 #define RX_TPA_START_V3_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
8221 #define RX_TPA_START_V3_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
8227 #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
8233 #define RX_TPA_START_V3_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
8235 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
8238 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
8241 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
8242 * de, vid[11:0]} The metadata2 field contains the table scope
8243 * and action record pointer. - metadata2[25:0] contains the
8247 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
8251 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
8254 * - VXLAN = VNI[23:0] -> VXLAN Network ID
8255 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
8256 * - NVGRE = TNI[23:0] -> Tenant Network ID
8257 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
8258 * - IPv4 = 0 (not populated)
8259 * - IPv6 = Flow Label[19:0]
8260 * - PPPoE = sessionID[15:0]
8261 * - MPLs = Outer label[19:0]
8262 * - UPAR = Selected[31:0] with bit mask
8264 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
8268 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
8272 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
8276 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
8279 * - metadata2[8:0] contains the outer_l3_offset.
8284 #define RX_TPA_START_V3_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
8288 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
8292 #define RX_TPA_START_V3_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
8297 #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
8303 #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE UINT32_C(0x400)
8305 #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV4 (UINT32_C(0x0) << 10)
8307 #define RX_TPA_START_V3_CMPL_FLAGS2_T_IP_TYPE_IPV6 (UINT32_C(0x1) << 10)
8310 #define RX_TPA_START_V3_CMPL_FLAGS2_AGG_GRO UINT32_C(0x800)
8319 #define RX_TPA_START_V3_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
8324 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
8325 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
8326 * act_rec_ptr[25:0]}
8327 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
8328 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
8329 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
8338 * will write 1. The odd passes will write 0.
8340 #define RX_TPA_START_V3_CMPL_V2 UINT32_C(0x1)
8341 #define RX_TPA_START_V3_CMPL_ERRORS_MASK UINT32_C(0xfffe)
8348 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
8351 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
8362 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
8367 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
8372 #define RX_TPA_START_V3_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
8379 /* When meta_format != 0, this value is the VLAN VID. */
8380 #define RX_TPA_START_V3_CMPL_METADATA0_VID_MASK UINT32_C(0xfff)
8381 #define RX_TPA_START_V3_CMPL_METADATA0_VID_SFT 0
8382 /* When meta_format != 0, this value is the VLAN DE. */
8383 #define RX_TPA_START_V3_CMPL_METADATA0_DE UINT32_C(0x1000)
8384 /* When meta_format != 0, this value is the VLAN PRI. */
8385 #define RX_TPA_START_V3_CMPL_METADATA0_PRI_MASK UINT32_C(0xe000)
8391 * hdr_offsets[8:0] contains the outer_l3_offset.
8401 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
8414 #define RX_TPA_END_CMPL_TYPE_MASK UINT32_C(0x3f)
8415 #define RX_TPA_END_CMPL_TYPE_SFT 0
8421 #define RX_TPA_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
8423 #define RX_TPA_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
8430 #define RX_TPA_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
8432 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
8442 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
8448 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
8456 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_JUMBO (UINT32_C(0x4) << 7)
8465 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
8475 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
8483 #define RX_TPA_END_CMPL_FLAGS_PLACEMENT_IOC_HDS (UINT32_C(0x7) << 7)
8486 #define RX_TPA_END_CMPL_FLAGS_TIMESTAMP_VALID UINT32_C(0x400)
8495 #define RX_TPA_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
8505 #define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
8521 * will write 1. The odd passes will write 0.
8527 * will write 1. The odd passes will write 0.
8529 #define RX_TPA_END_CMPL_V1 UINT32_C(0x1)
8537 #define RX_TPA_END_CMPL_AGG_BUFS_MASK UINT32_C(0x7e)
8551 #define RX_TPA_END_CMPL_UNUSED2 UINT32_C(0x1)
8557 #define RX_TPA_END_CMPL_AGG_ID_MASK UINT32_C(0xfe)
8568 * Timestamp present indication. When '0', no Timestamp
8579 * `hwrm_vnic_qcaps.max_aggs_supported` value is 0.
8589 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
8590 #define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
8611 * will write 1. The odd passes will write 0.
8613 #define RX_TPA_END_CMPL_V2 UINT32_C(0x1)
8614 #define RX_TPA_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
8622 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
8630 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
8641 #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR (UINT32_C(0x4) << 1)
8657 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
8670 #define RX_TPA_V2_START_CMPL_TYPE_MASK UINT32_C(0x3f)
8671 #define RX_TPA_V2_START_CMPL_TYPE_SFT 0
8677 #define RX_TPA_V2_START_CMPL_TYPE_RX_TPA_START UINT32_C(0x13)
8679 #define RX_TPA_V2_START_CMPL_FLAGS_MASK UINT32_C(0xffc0)
8681 /* This bit will always be '0' for TPA start completions. */
8682 #define RX_TPA_V2_START_CMPL_FLAGS_ERROR UINT32_C(0x40)
8684 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
8694 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
8700 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
8709 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
8719 #define RX_TPA_V2_START_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
8722 #define RX_TPA_V2_START_CMPL_FLAGS_RSS_VALID UINT32_C(0x400)
8732 #define RX_TPA_V2_START_CMPL_FLAGS_TIMESTAMP_FLD_FORMAT UINT32_C(0x800)
8737 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
8743 #define RX_TPA_V2_START_CMPL_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 12)
8758 * will write 1. The odd passes will write 0.
8764 * will write 1. The odd passes will write 0.
8766 #define RX_TPA_V2_START_CMPL_V1 UINT32_C(0x1)
8770 * {tuple_extrac_op[1:0],rss_profile_id[4:0],tuple_extrac_op[2]}.
8774 * * 0: The RSS hash was computed over source IP address,
8815 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
8826 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
8832 #define RX_TPA_V2_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
8838 #define RX_TPA_V2_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
8844 #define RX_TPA_V2_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
8846 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
8849 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
8852 * - metadata[11:0] contains the vlan VID value.
8857 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
8862 * - VXLAN = VNI[23:0] -> VXLAN Network ID
8863 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
8864 * - NVGRE = TNI[23:0] -> Tenant Network ID
8865 * - GRE = KEY[31:0] -> key field with bit mask. Zero if K = 0
8866 * - IPV4 = 0 (not populated)
8867 * - IPV6 = Flow Label[19:0]
8868 * - PPPoE = sessionID[15:0]
8869 * - MPLs = Outer label[19:0]
8870 * - UPAR = Selected[31:0] with bit mask
8872 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
8877 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
8882 * - metadata[8:0] contains the outer_l3_offset.
8887 #define RX_TPA_V2_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
8891 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
8893 #define RX_TPA_V2_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
8898 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
8903 #define RX_TPA_V2_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
8913 #define RX_TPA_V2_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
8921 #define RX_TPA_V2_START_CMPL_METADATA_VID_MASK UINT32_C(0xfff)
8922 #define RX_TPA_V2_START_CMPL_METADATA_VID_SFT 0
8924 #define RX_TPA_V2_START_CMPL_METADATA_DE UINT32_C(0x1000)
8926 #define RX_TPA_V2_START_CMPL_METADATA_PRI_MASK UINT32_C(0xe000)
8929 #define RX_TPA_V2_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
8935 * will write 1. The odd passes will write 0.
8937 #define RX_TPA_V2_START_CMPL_V2 UINT32_C(0x1)
8938 #define RX_TPA_V2_START_CMPL_ERRORS_MASK UINT32_C(0xfffe)
8946 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
8949 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
8954 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
8959 #define RX_TPA_V2_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
8982 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_MASK UINT32_C(0x1ff)
8983 #define RX_TPA_V2_START_CMPL_OUTER_L3_OFFSET_SFT 0
8988 #define RX_TPA_V2_START_CMPL_INNER_L2_OFFSET_MASK UINT32_C(0x3fe00)
8994 #define RX_TPA_V2_START_CMPL_INNER_L3_OFFSET_MASK UINT32_C(0x7fc0000)
9001 #define RX_TPA_V2_START_CMPL_INNER_L4_SIZE_MASK UINT32_C(0xf8000000)
9007 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
9020 #define RX_TPA_V2_END_CMPL_TYPE_MASK UINT32_C(0x3f)
9021 #define RX_TPA_V2_END_CMPL_TYPE_SFT 0
9027 #define RX_TPA_V2_END_CMPL_TYPE_RX_TPA_END UINT32_C(0x15)
9029 #define RX_TPA_V2_END_CMPL_FLAGS_MASK UINT32_C(0xffc0)
9036 #define RX_TPA_V2_END_CMPL_FLAGS_ERROR UINT32_C(0x40)
9038 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_MASK UINT32_C(0x380)
9048 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_JUMBO (UINT32_C(0x1) << 7)
9054 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_HDS (UINT32_C(0x2) << 7)
9063 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_JUMBO (UINT32_C(0x5) << 7)
9073 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_GRO_HDS (UINT32_C(0x6) << 7)
9081 #define RX_TPA_V2_END_CMPL_FLAGS_PLACEMENT_IOC_HDS (UINT32_C(0x7) << 7)
9084 #define RX_TPA_V2_END_CMPL_FLAGS_UNUSED UINT32_C(0x400)
9093 #define RX_TPA_V2_END_CMPL_FLAGS_PKT_METADATA_PRESENT UINT32_C(0x800)
9103 #define RX_TPA_V2_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
9120 * will write 1. The odd passes will write 0.
9122 #define RX_TPA_V2_END_CMPL_V1 UINT32_C(0x1)
9140 * Timestamp present indication. When '0', no Timestamp
9151 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
9165 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
9166 #define RX_TPA_V2_END_CMPL_TPA_DUP_ACKS_SFT 0
9198 * will write 1. The odd passes will write 0.
9200 #define RX_TPA_V2_END_CMPL_V2 UINT32_C(0x1)
9201 #define RX_TPA_V2_END_CMPL_ERRORS_MASK UINT32_C(0xfffe)
9209 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
9212 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
9219 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (UINT32_C(0x2) << 1)
9224 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
9235 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR (UINT32_C(0x4) << 1)
9240 #define RX_TPA_V2_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
9252 * `hwrm_vnic_qcaps.max_aggs_supported` value is greater than 0.
9265 #define RX_TPA_V2_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
9266 #define RX_TPA_V2_ABUF_CMPL_TYPE_SFT 0
9272 #define RX_TPA_V2_ABUF_CMPL_TYPE_RX_TPA_AGG UINT32_C(0x16)
9292 * will write 1. The odd passes will write 0.
9294 #define RX_TPA_V2_ABUF_CMPL_V UINT32_C(0x1)
9315 #define RX_ABUF_CMPL_TYPE_MASK UINT32_C(0x3f)
9316 #define RX_ABUF_CMPL_TYPE_SFT 0
9322 #define RX_ABUF_CMPL_TYPE_RX_AGG UINT32_C(0x12)
9342 * will write 1. The odd passes will write 0.
9344 #define RX_ABUF_CMPL_V UINT32_C(0x1)
9361 #define VEE_FLUSH_TYPE_MASK UINT32_C(0x3f)
9362 #define VEE_FLUSH_TYPE_SFT 0
9370 #define VEE_FLUSH_TYPE_VEE_FLUSH UINT32_C(0x1c)
9373 #define VEE_FLUSH_DOWNSTREAM_PATH UINT32_C(0x40)
9375 #define VEE_FLUSH_DOWNSTREAM_PATH_TX (UINT32_C(0x0) << 6)
9377 #define VEE_FLUSH_DOWNSTREAM_PATH_RX (UINT32_C(0x1) << 6)
9389 * write 1. The odd passes will write 0.
9391 #define VEE_FLUSH_V UINT32_C(0x1)
9407 #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
9408 #define EJECT_CMPL_TYPE_SFT 0
9414 #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
9416 #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
9423 #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
9438 * will write 1. The odd passes will write 0.
9440 #define EJECT_CMPL_V UINT32_C(0x1)
9441 #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
9448 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
9451 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (UINT32_C(0x0) << 1)
9456 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (UINT32_C(0x1) << 1)
9461 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (UINT32_C(0x3) << 1)
9466 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (UINT32_C(0x5) << 1)
9485 #define HWRM_CMPL_TYPE_MASK UINT32_C(0x3f)
9486 #define HWRM_CMPL_TYPE_SFT 0
9491 #define HWRM_CMPL_TYPE_HWRM_DONE UINT32_C(0x20)
9501 * will write 1. The odd passes will write 0.
9503 #define HWRM_CMPL_V UINT32_C(0x1)
9526 #define HWRM_FWD_REQ_CMPL_TYPE_MASK UINT32_C(0x3f)
9527 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
9529 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ UINT32_C(0x22)
9532 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK UINT32_C(0xffc0)
9537 * 0x0 - 0xFFF8 - Used for function ids
9538 * 0xFFF8 - 0xFFFE - Reserved for internal processors
9539 * 0xFFFF - HWRM
9549 * will write 1. The odd passes will write 0.
9551 #define HWRM_FWD_REQ_CMPL_V UINT32_C(0x1)
9553 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK UINT32_C(0xfffffffe)
9568 #define HWRM_FWD_RESP_CMPL_TYPE_MASK UINT32_C(0x3f)
9569 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
9571 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP UINT32_C(0x24)
9576 * 0x0 - 0xFFF8 - Used for function ids
9577 * 0xFFF8 - 0xFFFE - Reserved for internal processors
9578 * 0xFFFF - HWRM
9590 * will write 1. The odd passes will write 0.
9592 #define HWRM_FWD_RESP_CMPL_V UINT32_C(0x1)
9594 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK UINT32_C(0xfffffffe)
9609 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK UINT32_C(0x3f)
9610 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
9612 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
9617 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE UINT32_C(0x0)
9619 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE UINT32_C(0x1)
9621 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE UINT32_C(0x2)
9623 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)
9625 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED UINT32_C(0x4)
9627 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED UINT32_C(0x5)
9629 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE UINT32_C(0x6)
9631 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE UINT32_C(0x7)
9633 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY UINT32_C(0x8)
9635 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY UINT32_C(0x9)
9640 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG UINT32_C(0xa)
9642 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD UINT32_C(0x10)
9644 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD UINT32_C(0x11)
9646 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT UINT32_C(0x12)
9648 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD UINT32_C(0x20)
9650 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD UINT32_C(0x21)
9652 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR UINT32_C(0x30)
9654 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE UINT32_C(0x31)
9656 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32)
9658 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33)
9660 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE UINT32_C(0x34)
9662 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE UINT32_C(0x35)
9664 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED UINT32_C(0x36)
9671 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION UINT32_C(0x37)
9676 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ UINT32_C(0x38)
9682 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE UINT32_C(0x39)
9689 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE UINT32_C(0x3a)
9695 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE UINT32_C(0x3b)
9700 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE UINT32_C(0x3c)
9705 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE UINT32_C(0x3d)
9710 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE UINT32_C(0x3e)
9715 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE UINT32_C(0x3f)
9721 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE UINT32_C(0x40)
9726 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE UINT32_C(0x41)
9731 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST UINT32_C(0x42)
9737 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE UINT32_C(0x43)
9742 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP UINT32_C(0x44)
9748 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
9755 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD UINT32_C(0x46)
9760 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE UINT32_C(0x47)
9767 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE UINT32_C(0x48)
9774 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR UINT32_C(0x49)
9780 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR UINT32_C(0x4a)
9786 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE UINT32_C(0x4b)
9793 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER UINT32_C(0x4c)
9795 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID UINT32_C(0x4d)
9801 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG UINT32_C(0xfe)
9803 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR UINT32_C(0xff)
9811 * will write 1. The odd passes will write 0.
9813 #define HWRM_ASYNC_EVENT_CMPL_V UINT32_C(0x1)
9815 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK UINT32_C(0xfe)
9826 (((x) < 0x80) ? \
9827 ((x) == 0x0 ? "LINK_STATUS_CHANGE": \
9828 ((x) == 0x1 ? "LINK_MTU_CHANGE": \
9829 ((x) == 0x2 ? "LINK_SPEED_CHANGE": \
9830 ((x) == 0x3 ? "DCB_CONFIG_CHANGE": \
9831 ((x) == 0x4 ? "PORT_CONN_NOT_ALLOWED": \
9832 ((x) == 0x5 ? "LINK_SPEED_CFG_NOT_ALLOWED": \
9833 ((x) == 0x6 ? "LINK_SPEED_CFG_CHANGE": \
9834 ((x) == 0x7 ? "PORT_PHY_CFG_CHANGE": \
9835 ((x) == 0x8 ? "RESET_NOTIFY": \
9836 ((x) == 0x9 ? "ERROR_RECOVERY": \
9837 ((x) == 0xa ? "RING_MONITOR_MSG": \
9838 ((x) == 0x10 ? "FUNC_DRVR_UNLOAD": \
9839 ((x) == 0x11 ? "FUNC_DRVR_LOAD": \
9840 ((x) == 0x12 ? "FUNC_FLR_PROC_CMPLT": \
9841 ((x) == 0x20 ? "PF_DRVR_UNLOAD": \
9842 ((x) == 0x21 ? "PF_DRVR_LOAD": \
9843 ((x) == 0x30 ? "VF_FLR": \
9844 ((x) == 0x31 ? "VF_MAC_ADDR_CHANGE": \
9845 ((x) == 0x32 ? "PF_VF_COMM_STATUS_CHANGE": \
9846 ((x) == 0x33 ? "VF_CFG_CHANGE": \
9847 ((x) == 0x34 ? "LLFC_PFC_CHANGE": \
9848 ((x) == 0x35 ? "DEFAULT_VNIC_CHANGE": \
9849 ((x) == 0x36 ? "HW_FLOW_AGED": \
9850 ((x) == 0x37 ? "DEBUG_NOTIFICATION": \
9851 ((x) == 0x38 ? "EEM_CACHE_FLUSH_REQ": \
9852 ((x) == 0x39 ? "EEM_CACHE_FLUSH_DONE": \
9853 ((x) == 0x3a ? "TCP_FLAG_ACTION_CHANGE": \
9854 ((x) == 0x3b ? "EEM_FLOW_ACTIVE": \
9855 ((x) == 0x3c ? "EEM_CFG_CHANGE": \
9856 ((x) == 0x3d ? "TFLIB_DEFAULT_VNIC_CHANGE": \
9857 ((x) == 0x3e ? "TFLIB_LINK_STATUS_CHANGE": \
9858 ((x) == 0x3f ? "QUIESCE_DONE": \
9859 ((x) == 0x40 ? "DEFERRED_RESPONSE": \
9860 ((x) == 0x41 ? "PFC_WATCHDOG_CFG_CHANGE": \
9861 ((x) == 0x42 ? "ECHO_REQUEST": \
9862 ((x) == 0x43 ? "PHC_UPDATE": \
9863 ((x) == 0x44 ? "PPS_TIMESTAMP": \
9864 ((x) == 0x45 ? "ERROR_REPORT": \
9865 ((x) == 0x46 ? "DOORBELL_PACING_THRESHOLD": \
9866 ((x) == 0x47 ? "RSS_CHANGE": \
9867 ((x) == 0x48 ? "DOORBELL_PACING_NQ_UPDATE": \
9868 ((x) == 0x49 ? "HW_DOORBELL_RECOVERY_READ_ERROR": \
9869 ((x) == 0x4a ? "CTX_ERROR": \
9870 ((x) == 0x4b ? "UDCC_SESSION_CHANGE": \
9871 ((x) == 0x4c ? "DBG_BUF_PRODUCER": \
9872 ((x) == 0x4d ? "MAX_RGTR_EVENT_ID": \
9874 (((x) < 0x100) ? \
9875 ((x) == 0xfe ? "FW_TRACE_MSG": \
9876 ((x) == 0xff ? "HWRM_ERROR": \
9892 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK UINT32_C(0x3f)
9893 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
9895 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
9900 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE UINT32_C(0x0)
9908 * will write 1. The odd passes will write 0.
9910 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V UINT32_C(0x1)
9912 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
9921 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE UINT32_C(0x1)
9923 * If this bit set to 0, then it indicates that the link
9926 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN UINT32_C(0x0)
9931 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP UINT32_C(0x1)
9934 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK UINT32_C(0xe)
9937 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff0)
9940 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK UINT32_C(0xff00000)
9955 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK UINT32_C(0x3f)
9956 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
9958 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
9963 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE UINT32_C(0x1)
9971 * will write 1. The odd passes will write 0.
9973 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V UINT32_C(0x1)
9975 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
9984 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK UINT32_C(0xffff)
9985 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
9999 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK UINT32_C(0x3f)
10000 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
10002 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10007 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE UINT32_C(0x2)
10015 * will write 1. The odd passes will write 0.
10017 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V UINT32_C(0x1)
10019 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10031 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE UINT32_C(0x1)
10033 …#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK UINT32_C(0…
10036 …M_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (UINT32_C(0x1) << 1)
10038 …HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (UINT32_C(0xa) << 1)
10040 …WRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (UINT32_C(0x14) << 1)
10042 …_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (UINT32_C(0x19) << 1)
10044 …_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (UINT32_C(0x64) << 1)
10046 …_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (UINT32_C(0xc8) << 1)
10048 …_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (UINT32_C(0xfa) << 1)
10050 …ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (UINT32_C(0x190) << 1)
10052 …ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (UINT32_C(0x1f4) << 1)
10054 …ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (UINT32_C(0x3e8) << 1)
10057 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff0000)
10072 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK UINT32_C(0x3f)
10073 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
10075 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10080 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE UINT32_C(0x3)
10085 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS UINT32_C(0x1)
10087 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC UINT32_C(0x2)
10089 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP UINT32_C(0x4)
10091 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_DSCP UINT32_C(0x8)
10096 * will write 1. The odd passes will write 0.
10098 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V UINT32_C(0x1)
10100 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10109 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
10110 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
10112 …HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK UINT32_C(0xff0000)
10115 …ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (UINT32_C(0xff) << 16)
10118 …#define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK UINT32_C(0…
10121 …RM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (UINT32_C(0xff) << 24)
10136 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK UINT32_C(0x3f)
10137 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
10139 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10144 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED UINT32_C(0x4)
10152 * will write 1. The odd passes will write 0.
10154 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V UINT32_C(0x1)
10156 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK UINT32_C(0xfe)
10165 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
10166 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
10172 …#define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK UINT32_C(0…
10175 …RM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (UINT32_C(0x0) << 16)
10177 …C_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (UINT32_C(0x1) << 16)
10179 …C_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (UINT32_C(0x2) << 16)
10181 …ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (UINT32_C(0x3) << 16)
10196 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK UINT32_C(0x3f)
10197 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0
10199 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10204 … HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED UINT32_C(0x5)
10212 * will write 1. The odd passes will write 0.
10214 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V UINT32_C(0x1)
10216 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK UINT32_C(0xfe)
10225 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
10226 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
10240 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
10241 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0
10243 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10248 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE UINT32_C(0x6)
10256 * will write 1. The odd passes will write 0.
10258 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V UINT32_C(0x1)
10260 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10269 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
10270 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
10274 * If set to 0, then there is no change in supported link speeds
10277 …M_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE UINT32_C(0x10000)
10281 * If set to 0, then the link speed configuration on the port is
10284 …#define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG UINT32_C(0x…
10298 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
10299 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_SFT 0
10301 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10306 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_ID_PORT_PHY_CFG_CHANGE UINT32_C(0x7)
10314 * will write 1. The odd passes will write 0.
10316 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_V UINT32_C(0x1)
10318 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10327 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff)
10328 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
10332 * If set to 0, then there is no change in FEC configuration.
10334 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_FEC_CFG_CHANGE UINT32_C(0x10000)
10338 * If set to 0, then there is no change in EEE configuration
10341 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_EEE_CFG_CHANGE UINT32_C(0x20000)
10345 * If set to 0, then there is no change in the pause
10348 #define HWRM_ASYNC_EVENT_CMPL_PORT_PHY_CFG_CHANGE_EVENT_DATA1_PAUSE_CFG_CHANGE UINT32_C(0x40000)
10362 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK UINT32_C(0x3f)
10363 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0
10365 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10370 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY UINT32_C(0x8)
10377 * If the status code is equal to 0x8000, then the reset is initiated
10379 * state. If the status code is not equal to 0x8000, then the reset is
10382 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK UINT32_C(0xffff)
10383 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0
10388 * will write 1. The odd passes will write 0.
10390 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)
10392 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
10411 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK UINT32_C(0xff)
10412 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0
10416 * if set to 0, there is no change in L2 client behavior.
10418 …ine HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE UINT32_C(0x1)
10422 * If set to 0, then there is no change in L2 client behavior.
10424 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN UINT32_C(0x2)
10427 #define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK UINT32_C(0xff00)
10430 …SYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (UINT32_C(0x1) << 8)
10432 …#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (UINT32_C(0x…
10434 …M_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (UINT32_C(0x3) << 8)
10436 …#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (UINT32_C(0x4) << 8)
10441 …#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (UINT32_C(0x5) <…
10446 * Range 0-65535
10448 …#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK UINT32_C(0xffff00…
10463 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK UINT32_C(0x3f)
10464 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
10466 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10476 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY UINT32_C(0x9)
10484 * will write 1. The odd passes will write 0.
10486 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
10488 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
10497 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK UINT32_C(0xff)
10498 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0
10502 * detects a fatal error. If set to 0, master function functionality
10505 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC UINT32_C(0x1)
10508 * If set to 0, error recovery is disabled.
10510 #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED UINT32_C(0x2)
10524 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK UINT32_C(0x3f)
10525 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0
10527 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10532 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG UINT32_C(0xa)
10537 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK UINT32_C(0xff)
10538 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0
10540 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX UINT32_C(0x0)
10542 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX UINT32_C(0x1)
10544 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL UINT32_C(0x2)
10550 * will write 1. The odd passes will write 0.
10552 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V UINT32_C(0x1)
10554 #define HWRM_ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK UINT32_C(0xfe)
10578 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK UINT32_C(0x3f)
10579 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
10581 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10586 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD UINT32_C(0x10)
10594 * will write 1. The odd passes will write 0.
10596 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V UINT32_C(0x1)
10598 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
10607 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
10608 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
10622 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK UINT32_C(0x3f)
10623 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
10625 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10630 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD UINT32_C(0x11)
10638 * will write 1. The odd passes will write 0.
10640 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V UINT32_C(0x1)
10642 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
10651 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
10652 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
10666 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK UINT32_C(0x3f)
10667 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0
10669 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10674 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT UINT32_C(0x12)
10682 * will write 1. The odd passes will write 0.
10684 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V UINT32_C(0x1)
10686 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK UINT32_C(0xfe)
10695 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
10696 #define HWRM_ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0
10710 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK UINT32_C(0x3f)
10711 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
10713 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10718 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD UINT32_C(0x20)
10726 * will write 1. The odd passes will write 0.
10728 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V UINT32_C(0x1)
10730 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK UINT32_C(0xfe)
10739 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
10740 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
10742 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK UINT32_C(0x70000)
10757 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK UINT32_C(0x3f)
10758 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
10760 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10765 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD UINT32_C(0x21)
10773 * will write 1. The odd passes will write 0.
10775 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V UINT32_C(0x1)
10777 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK UINT32_C(0xfe)
10786 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK UINT32_C(0xffff)
10787 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
10789 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK UINT32_C(0x70000)
10804 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK UINT32_C(0x3f)
10805 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
10807 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10812 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR UINT32_C(0x30)
10820 * will write 1. The odd passes will write 0.
10822 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V UINT32_C(0x1)
10824 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK UINT32_C(0xfe)
10833 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK UINT32_C(0xffff)
10834 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
10836 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_PF_ID_MASK UINT32_C(0xff0000)
10851 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK UINT32_C(0x3f)
10852 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
10854 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10859 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE UINT32_C(0x31)
10867 * will write 1. The odd passes will write 0.
10869 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V UINT32_C(0x1)
10871 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10880 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK UINT32_C(0xffff)
10881 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
10895 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK UINT32_C(0x3f)
10896 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0
10898 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10903 …ine HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE UINT32_C(0x32)
10911 * will write 1. The odd passes will write 0.
10913 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V UINT32_C(0x1)
10915 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10926 * If this bit set to 0, then it indicates that the PF-VF
10929 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED UINT32_C(0x1)
10943 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
10944 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0
10946 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
10951 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE UINT32_C(0x33)
10963 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK UINT32_C(0xffff)
10964 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
10969 * will write 1. The odd passes will write 0.
10971 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V UINT32_C(0x1)
10973 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
10989 * If set to 0, then this bit should be ignored.
10991 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE UINT32_C(0x1)
10995 * If set to 0, then this bit should be ignored.
10997 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE UINT32_C(0x2)
11001 * If set to 0, then this bit should be ignored.
11003 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE UINT32_C(0x4)
11007 * If set to 0, then this bit should be ignored.
11009 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE UINT32_C(0x8)
11013 * If set to 0, then this bit should be ignored.
11015 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE UINT32_C(0x10)
11020 * If set to 0, then this bit should be ignored.
11022 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE UINT32_C(0x20)
11036 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_MASK UINT32_C(0x3f)
11037 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_SFT 0
11039 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11042 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_UNUSED1_MASK UINT32_C(0xffc0)
11047 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_ID_LLFC_PFC_CHANGE UINT32_C(0x34)
11055 * will write 1. The odd passes will write 0.
11057 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_V UINT32_C(0x1)
11059 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11068 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_MASK UINT32_C(0x3)
11069 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_SFT 0
11074 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_LLFC UINT32_C(0x1)
11079 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_LLFC_PFC_PFC UINT32_C(0x2)
11082 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_MASK UINT32_C(0x1c)
11085 #define HWRM_ASYNC_EVENT_CMPL_LLFC_PFC_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0x1fffe0)
11100 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK UINT32_C(0x3f)
11101 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0
11103 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11106 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK UINT32_C(0xffc0)
11111 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION UINT32_C(0x35)
11119 * will write 1. The odd passes will write 0.
11121 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V UINT32_C(0x1)
11123 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11132 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK UINT32_C(0x3)
11133 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0
11138 … HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC UINT32_C(0x1)
11143 … HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE UINT32_C(0x2)
11146 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK UINT32_C(0x3fc)
11149 #define HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK UINT32_C(0x3fffc00)
11164 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK UINT32_C(0x3f)
11165 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
11167 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11172 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED UINT32_C(0x36)
11180 * will write 1. The odd passes will write 0.
11182 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
11184 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
11193 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK UINT32_C(0x7fffffff)
11194 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0
11196 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION UINT32_C(0x80000000)
11198 * If this bit set to 0, then it indicates that the aged
11201 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (UINT32_C(0x0) << 31)
11206 #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (UINT32_C(0x1) << 31)
11221 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK UINT32_C(0x3f)
11222 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0
11224 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11229 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ UINT32_C(0x38)
11237 * will write 1. The odd passes will write 0.
11239 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V UINT32_C(0x1)
11241 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK UINT32_C(0xfe)
11262 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK UINT32_C(0x3f)
11263 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0
11265 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11273 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE UINT32_C(0x39)
11281 * will write 1. The odd passes will write 0.
11283 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V UINT32_C(0x1)
11285 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK UINT32_C(0xfe)
11294 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK UINT32_C(0xffff)
11295 #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
11309 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK UINT32_C(0x3f)
11310 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT 0
11312 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11317 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE UINT32_C(0x3a)
11325 * will write 1. The odd passes will write 0.
11327 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V UINT32_C(0x1)
11329 #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11350 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK UINT32_C(0x3f)
11351 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
11353 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11358 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE UINT32_C(0x3b)
11363 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK UINT32_C(0x3fffffff)
11364 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT 0
11369 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION UINT32_C(0x40000000)
11370 /* If this bit is set to 0, then it indicates that this rx flow. */
11371 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX (UINT32_C(0x0) << 30)
11373 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX (UINT32_C(0x1) << 30)
11379 * will write 1. The odd passes will write 0.
11381 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
11383 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK UINT32_C(0xfe)
11392 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK UINT32_C(0x3fffffff)
11393 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT 0
11398 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION UINT32_C(0x40000000)
11399 /* If this bit is set to 0, then it indicates that this is rx flow. */
11400 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX (UINT32_C(0x0) << 30)
11402 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX (UINT32_C(0x1) << 30)
11406 * this bit is set to 0, the event_data1 is the EEM global
11410 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE UINT32_C(0x80000000)
11411 /* EEM flow aging mode 0. */
11412 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 (UINT32_C(0x0) << 31)
11414 #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 (UINT32_C(0x1) << 31)
11429 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
11430 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
11432 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11437 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE UINT32_C(0x3c)
11445 * will write 1. The odd passes will write 0.
11447 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
11449 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11459 * 0 to indicate the EEM TX configuration is disabled.
11461 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE UINT32_C(0x1)
11463 * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
11466 #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE UINT32_C(0x2)
11480 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_MASK UINT32_C(0x3f)
11481 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_SFT 0
11483 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11488 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_ID_QUIESCE_DONE UINT32_C(0x3f)
11493 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_MASK UINT32_C(0xff)
11494 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SFT 0
11499 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_SUCCESS UINT32_C(0x0)
11504 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_TIMEOUT UINT32_C(0x1)
11509 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_QUIESCE_STATUS_ERROR UINT32_C(0x2)
11512 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_OPAQUE_MASK UINT32_C(0xff00)
11520 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_MASK UINT32_C(0xff0000)
11526 …#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_INCOMPLETE_NQ UINT32_C(0x1…
11528 …#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_1 UINT32_C(0x2…
11530 …#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_2 UINT32_C(0x4…
11532 …#define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA2_IDLE_STATE_FLAGS_IDLE_STATUS_3 UINT32_C(0x8…
11537 * will write 1. The odd passes will write 0.
11539 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_V UINT32_C(0x1)
11541 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_OPAQUE_MASK UINT32_C(0xfe)
11550 #define HWRM_ASYNC_EVENT_CMPL_QUIESCE_DONE_EVENT_DATA1_TIMESTAMP UINT32_C(0x1)
11564 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK UINT32_C(0x3f)
11565 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0
11567 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11575 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE UINT32_C(0x40)
11586 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK UINT32_C(0xffff)
11587 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0
11592 * will write 1. The odd passes will write 0.
11594 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V UINT32_C(0x1)
11596 #define HWRM_ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK UINT32_C(0xfe)
11617 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_MASK UINT32_C(0x3f)
11618 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_SFT 0
11620 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11625 …#define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE UINT32_C(0x…
11633 * will write 1. The odd passes will write 0.
11635 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_V UINT32_C(0x1)
11637 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
11649 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_MASK UINT32_C(0xff)
11650 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_SFT 0
11651 /* 1 means PFC WD for COS0 is on, 0 - off. */
11652 …fine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS0 UINT32_C(0x1)
11653 /* 1 means PFC WD for COS1 is on, 0 - off. */
11654 …fine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS1 UINT32_C(0x2)
11655 /* 1 means PFC WD for COS2 is on, 0 - off. */
11656 …fine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS2 UINT32_C(0x4)
11657 /* 1 means PFC WD for COS3 is on, 0 - off. */
11658 …fine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS3 UINT32_C(0x8)
11659 /* 1 means PFC WD for COS4 is on, 0 - off. */
11660 …ine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS4 UINT32_C(0x10)
11661 /* 1 means PFC WD for COS5 is on, 0 - off. */
11662 …ine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS5 UINT32_C(0x20)
11663 /* 1 means PFC WD for COS6 is on, 0 - off. */
11664 …ine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS6 UINT32_C(0x40)
11665 /* 1 means PFC WD for COS7 is on, 0 - off. */
11666 …ine HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PFC_WD_COS_PFC_WD_COS7 UINT32_C(0x80)
11668 #define HWRM_ASYNC_EVENT_CMPL_PFC_WATCHDOG_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK UINT32_C(0xffff00)
11683 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK UINT32_C(0x3f)
11684 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0
11686 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11694 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST UINT32_C(0x42)
11702 * will write 1. The odd passes will write 0.
11704 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V UINT32_C(0x1)
11706 #define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe)
11727 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK UINT32_C(0x3f)
11728 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0
11730 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11739 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE UINT32_C(0x43)
11744 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK UINT32_C(0xffff)
11745 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0
11747 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK UINT32_C(0xffff0000)
11753 * will write 1. The odd passes will write 0.
11755 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_V UINT32_C(0x1)
11757 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK UINT32_C(0xfe)
11766 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK UINT32_C(0xf)
11767 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0
11772 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER UINT32_C(0x1)
11777 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY UINT32_C(0x2)
11782 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER UINT32_C(0x3)
11788 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE UINT32_C(0x4)
11794 #define HWRM_ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK UINT32_C(0xffff0)
11809 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK UINT32_C(0x3f)
11810 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0
11812 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11823 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP UINT32_C(0x44)
11828 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE UINT32_C(0x1)
11830 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL UINT32_C(0x0)
11832 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL UINT32_C(0x1)
11838 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK UINT32_C(0xe)
11845 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK UINT32_C(0xffff0)
11851 * will write 1. The odd passes will write 0.
11853 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V UINT32_C(0x1)
11855 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK UINT32_C(0xfe)
11864 …#define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK UINT32_C(0xffffff…
11865 #define HWRM_ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0
11879 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK UINT32_C(0x3f)
11880 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0
11882 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11891 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
11899 * will write 1. The odd passes will write 0.
11901 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_V UINT32_C(0x1)
11903 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK UINT32_C(0xfe)
11915 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
11916 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
11930 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_MASK UINT32_C(0x3f)
11931 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_SFT 0
11933 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11943 …e HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_EVENT_ID_DOORBELL_PACING_THRESHOLD UINT32_C(0x46)
11951 * will write 1. The odd passes will write 0.
11953 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_V UINT32_C(0x1)
11955 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_THRESHOLD_OPAQUE_MASK UINT32_C(0xfe)
11976 #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_MASK UINT32_C(0x3f)
11977 #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_SFT 0
11979 #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
11988 #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE UINT32_C(0x47)
11996 * will write 1. The odd passes will write 0.
11998 #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_V UINT32_C(0x1)
12000 #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
12021 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_MASK UINT32_C(0x3f)
12022 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_SFT 0
12024 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12034 …e HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE UINT32_C(0x48)
12042 * will write 1. The odd passes will write 0.
12044 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_V UINT32_C(0x1)
12046 #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_MASK UINT32_C(0xfe)
12067 #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_MASK UINT32_C(0x3f)
12068 #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_SFT 0
12070 …#define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12081 …_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR UINT32_C(0x49)
12089 * will write 1. The odd passes will write 0.
12091 #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_V UINT32_C(0x1)
12093 #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_MASK UINT32_C(0xfe)
12105 …RM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_MASK UINT32_C(0xf)
12106 #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SFT 0
12111 …_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SQ_ERR UINT32_C(0x1)
12116 …_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_RQ_ERR UINT32_C(0x2)
12121 …ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SRQ_ERR UINT32_C(0x4)
12126 …_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR UINT32_C(0x8)
12140 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_MASK UINT32_C(0x3f)
12141 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_SFT 0
12143 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12154 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_ID_CTX_ERROR UINT32_C(0x4a)
12159 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE UINT32_C(0x1)
12161 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_ALLOC UINT32_C(0x0)
12163 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_CTX_OP_CODE_FREE UINT32_C(0x1)
12166 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_NUM_CTXS_MASK UINT32_C(0xfffe)
12169 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA2_FID_MASK UINT32_C(0xffff0000)
12175 * will write 1. The odd passes will write 0.
12177 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_V UINT32_C(0x1)
12179 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_OPAQUE_MASK UINT32_C(0xfe)
12188 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_MASK UINT32_C(0xffffffff)
12189 #define HWRM_ASYNC_EVENT_CMPL_CTX_ERROR_EVENT_DATA1_START_XID_SFT 0
12203 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_MASK UINT32_C(0x3f)
12204 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_SFT 0
12206 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12214 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_ID_UDCC_SESSION_CHANGE UINT32_C(0x4b)
12219 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_MASK UINT32_C(0xff)
12220 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_SFT 0
12222 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_CREATED UINT32_C(0x0)
12224 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA2_SESSION_ID_OP_CODE_FREED UINT32_C(0x1)
12230 * will write 1. The odd passes will write 0.
12232 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_V UINT32_C(0x1)
12234 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
12243 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_MASK UINT32_C(0xffff)
12244 #define HWRM_ASYNC_EVENT_UDCC_SESSION_CHANGE_EVENT_DATA1_UDCC_SESSION_ID_SFT 0
12258 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK UINT32_C(0x3f)
12259 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT 0
12261 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12271 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER UINT32_C(0x4c)
12282 …#define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_MASK UINT32_C(0xf…
12283 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURRENT_BUFFER_OFFSET_SFT 0
12288 * will write 1. The odd passes will write 0.
12290 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V UINT32_C(0x1)
12292 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK UINT32_C(0xfe)
12301 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK UINT32_C(0xffff)
12302 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT 0
12304 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE UINT32_C(0x0)
12306 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE UINT32_C(0x1)
12308 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE UINT32_C(0x2)
12310 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE UINT32_C(0x3)
12312 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE UINT32_C(0x4)
12314 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE UINT32_C(0x5)
12316 #define HWRM_ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6)
12331 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK UINT32_C(0x3f)
12332 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
12334 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12339 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG UINT32_C(0xfe)
12341 /* Trace byte 0 to 3 */
12344 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK UINT32_C(0xff)
12345 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
12347 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK UINT32_C(0xff00)
12350 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK UINT32_C(0xff0000)
12353 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK UINT32_C(0xff000000)
12359 * will write 1. The odd passes will write 0.
12361 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
12363 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
12368 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING UINT32_C(0x1)
12370 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE UINT32_C(0x0)
12372 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL UINT32_C(0x1)
12375 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE UINT32_C(0x2)
12377 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY (UINT32_C(0x0) << 1)
12379 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY (UINT32_C(0x1) << 1)
12384 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK UINT32_C(0xff)
12385 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
12387 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK UINT32_C(0xff00)
12392 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK UINT32_C(0xff)
12393 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
12395 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK UINT32_C(0xff00)
12398 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK UINT32_C(0xff0000)
12401 #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK UINT32_C(0xff000000)
12416 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK UINT32_C(0x3f)
12417 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
12419 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12424 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR UINT32_C(0xff)
12429 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK UINT32_C(0xff)
12430 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
12432 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING UINT32_C(0x0)
12434 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL UINT32_C(0x1)
12436 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL UINT32_C(0x2)
12442 * will write 1. The odd passes will write 0.
12444 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
12446 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
12455 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP UINT32_C(0x1)
12469 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK UINT32_C(0x3f)
12470 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0
12472 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12481 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12489 * will write 1. The odd passes will write 0.
12491 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V UINT32_C(0x1)
12493 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK UINT32_C(0xfe)
12502 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
12503 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0
12505 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED UINT32_C(0x0)
12510 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM UINT32_C(0x1)
12518 …#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL UINT32_C(0x…
12523 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM UINT32_C(0x3)
12529 …WRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD UINT32_C(0x4)
12534 …ine HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD UINT32_C(0x5)
12539 …YNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED UINT32_C(0x6)
12544 (((x) < 0x80) ? \
12545 ((x) == 0x0 ? "RESERVED": \
12546 ((x) == 0x1 ? "PAUSE_STORM": \
12547 ((x) == 0x2 ? "INVALID_SIGNAL": \
12548 ((x) == 0x3 ? "NVM": \
12549 ((x) == 0x4 ? "DOORBELL_DROP_THRESHOLD": \
12550 ((x) == 0x5 ? "THERMAL_THRESHOLD": \
12551 ((x) == 0x6 ? "DUAL_DATA_RATE_NOT_SUPPORTED": \
12567 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK UINT32_C(0x3f)
12568 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0
12570 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12579 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12587 * will write 1. The odd passes will write 0.
12589 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V UINT32_C(0x1)
12591 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK UINT32_C(0xfe)
12600 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
12601 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0
12606 …ne HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM UINT32_C(0x1)
12621 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK UINT32_C(0x3f)
12622 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0
12624 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12633 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12638 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK UINT32_C(0xff)
12639 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0
12644 * will write 1. The odd passes will write 0.
12646 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V UINT32_C(0x1)
12648 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK UINT32_C(0xfe)
12657 …#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xf…
12658 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0
12666 …M_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL UINT32_C(0x2)
12681 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK UINT32_C(0x3f)
12682 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0
12684 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12693 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12698 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK UINT32_C(0xffffffff)
12699 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0
12704 * will write 1. The odd passes will write 0.
12706 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V UINT32_C(0x1)
12708 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK UINT32_C(0xfe)
12717 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
12718 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0
12723 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR UINT32_C(0x3)
12726 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK UINT32_C(0xff00)
12733 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (UINT32_C(0x1) << 8)
12739 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (UINT32_C(0x2) << 8)
12754 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK UINT32_C(0x3f)
12755 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0
12757 …ne HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12766 …ine HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12774 * will write 1. The odd passes will write 0.
12776 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V UINT32_C(0x1)
12778 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK UINT32_C(0xfe)
12787 …M_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
12788 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0
12794 …_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD UINT32_C(0x4)
12800 …ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK UINT32_C(0xffffff00)
12815 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK UINT32_C(0x3f)
12816 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT 0
12818 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12827 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12832 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK UINT32_C(0xff)
12833 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0
12838 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK UINT32_C(0xff00)
12844 * will write 1. The odd passes will write 0.
12846 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V UINT32_C(0x1)
12848 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK UINT32_C(0xfe)
12857 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
12858 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT 0
12867 …ine HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT UINT32_C(0x5)
12870 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK UINT32_C(0x700)
12873 …#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN (UINT32_C(0x0) …
12875 …HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL (UINT32_C(0x1) << 8)
12877 …#define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL (UINT32_C(0x2)…
12883 …HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN (UINT32_C(0x3) << 8)
12889 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR UINT32_C(0x800)
12891 …_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (UINT32_C(0x0) << 11)
12893 …_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (UINT32_C(0x1) << 11)
12908 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK UINT32_C(0x3f)
12909 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT 0
12911 …RM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT UINT32_C(0x2e)
12920 …WRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT UINT32_C(0x45)
12928 * will write 1. The odd passes will write 0.
12930 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V UINT32_C(0x1)
12932 #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK UINT32_C(0xfe)
12941 …C_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK UINT32_C(0xff)
12942 …fine HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT 0
12947 …ORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED UINT32_C(0x6)
12956 #define METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
12957 #define METADATA_BASE_MSG_MD_TYPE_SFT 0
12959 #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0)
12965 #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
12970 #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
12972 #define METADATA_BASE_MSG_MD_TYPE_QUIC UINT32_C(0x3)
12977 #define METADATA_BASE_MSG_MD_TYPE_ILLEGAL UINT32_C(0x1f)
12986 #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
12997 #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK UINT32_C(0x1f)
12998 #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0
13004 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
13009 #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
13016 #define TLS_METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0)
13019 #define TLS_METADATA_BASE_MSG_FLAGS_MASK UINT32_C(0x1fffe00)
13025 #define TLS_METADATA_BASE_MSG_FLAGS_DECRYPTED UINT32_C(0x200)
13030 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK UINT32_C(0xc00)
13036 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_NOT_VALID (UINT32_C(0x0) << 10)
13042 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_CUR_REC (UINT32_C(0x1) << 10)
13048 #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_PRIOR_REC (UINT32_C(0x2) << 10)
13051 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK UINT32_C(0x3000)
13057 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED (UINT32_C(0x0) << 12)
13062 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS (UINT32_C(0x1) << 12)
13068 #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE (UINT32_C(0x2) << 12)
13074 #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID UINT32_C(0x4000)
13080 #define TLS_METADATA_BASE_MSG_FLAGS_CTX_LOAD_ERR UINT32_C(0x8000)
13082 #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_MASK UINT32_C(0x70000)
13085 #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER (UINT32_C(0x0) << 16)
13087 #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER (UINT32_C(0x1) << 16)
13089 #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH (UINT32_C(0x2) << 16)
13091 #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC (UINT32_C(0x3) << 16)
13096 #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT (UINT32_C(0x4) << 16)
13101 …#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL (UINT32_C(0x5) << 16)
13103 #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS (UINT32_C(0x6) << 16)
13108 …#define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT (UINT32_C(0x7) << 16)
13114 #define TLS_METADATA_BASE_MSG_KID_LO_MASK UINT32_C(0xfe000000)
13121 #define TLS_METADATA_BASE_MSG_KID_HI_MASK UINT32_C(0x1fff)
13122 #define TLS_METADATA_BASE_MSG_KID_HI_SFT 0
13131 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK UINT32_C(0x1f)
13132 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0
13138 #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1)
13145 #define TLS_METADATA_INSYNC_MSG_LINK_MASK UINT32_C(0x1e0)
13148 #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK UINT32_C(0x1fffe00)
13154 #define TLS_METADATA_INSYNC_MSG_FLAGS_DECRYPTED UINT32_C(0x200)
13159 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK UINT32_C(0xc00)
13165 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_NOT_VALID (UINT32_C(0x0) << 10)
13171 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_CUR_REC (UINT32_C(0x1) << 10)
13177 #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_PRIOR_REC (UINT32_C(0x2) << 10)
13180 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK UINT32_C(0x3000)
13186 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED (UINT32_C(0x0) << 12)
13191 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SUCCESS (UINT32_C(0x1) << 12)
13197 #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_FAILURE (UINT32_C(0x2) << 12)
13203 #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID UINT32_C(0x4000)
13209 #define TLS_METADATA_INSYNC_MSG_FLAGS_CTX_LOAD_ERR UINT32_C(0x8000)
13211 #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK UINT32_C(0x70000)
13214 #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER (UINT32_C(0x0) << 16)
13216 #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER (UINT32_C(0x1) << 16)
13218 #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH (UINT32_C(0x2) << 16)
13220 #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC (UINT32_C(0x3) << 16)
13225 #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT (UINT32_C(0x4) << 16)
13230 …#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL (UINT32_C(0x5) << …
13232 #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS (UINT32_C(0x6) << 16)
13237 …#define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT (UINT32_C(0x7) << …
13243 #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK UINT32_C(0xfe000000)
13250 #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
13251 #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0
13284 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK UINT32_C(0x1f)
13285 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0
13290 #define TLS_METADATA_RESYNC_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2)
13297 #define TLS_METADATA_RESYNC_MSG_LINK_MASK UINT32_C(0x1e0)
13300 #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK UINT32_C(0x1fffe00)
13306 #define TLS_METADATA_RESYNC_MSG_FLAGS_DECRYPTED UINT32_C(0x200)
13311 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK UINT32_C(0xc00)
13317 #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_NOT_VALID (UINT32_C(0x0) << 10)
13320 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK UINT32_C(0x3000)
13326 #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED (UINT32_C(0x0) << 12)
13332 #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID UINT32_C(0x4000)
13338 #define TLS_METADATA_RESYNC_MSG_FLAGS_CTX_LOAD_ERR UINT32_C(0x8000)
13340 #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK UINT32_C(0x70000)
13343 #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER (UINT32_C(0x0) << 16)
13345 #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER (UINT32_C(0x1) << 16)
13347 #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH (UINT32_C(0x2) << 16)
13349 #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC (UINT32_C(0x3) << 16)
13354 #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT (UINT32_C(0x4) << 16)
13359 …#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL (UINT32_C(0x5) << …
13361 #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS (UINT32_C(0x6) << 16)
13366 …#define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT (UINT32_C(0x7) << …
13372 #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK UINT32_C(0xfe000000)
13379 #define TLS_METADATA_RESYNC_MSG_KID_HI_MASK UINT32_C(0x1fff)
13380 #define TLS_METADATA_RESYNC_MSG_KID_HI_SFT 0
13409 #define TX_DOORBELL_IDX_MASK UINT32_C(0xffffff)
13410 #define TX_DOORBELL_IDX_SFT 0
13413 * that is begin requested. This value is '0' for TX
13416 #define TX_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
13419 #define TX_DOORBELL_KEY_TX (UINT32_C(0x0) << 28)
13433 #define RX_DOORBELL_IDX_MASK UINT32_C(0xffffff)
13434 #define RX_DOORBELL_IDX_SFT 0
13440 #define RX_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
13443 #define RX_DOORBELL_KEY_RX (UINT32_C(0x1) << 28)
13457 #define CMPL_DOORBELL_IDX_MASK UINT32_C(0xffffff)
13458 #define CMPL_DOORBELL_IDX_SFT 0
13461 * update when it is '1'. When it is '0', the BDIDX
13464 #define CMPL_DOORBELL_IDX_VALID UINT32_C(0x4000000)
13468 * interrupt is to be masked. A '0' indicates the interrupt
13471 #define CMPL_DOORBELL_MASK UINT32_C(0x8000000)
13477 #define CMPL_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
13480 #define CMPL_DOORBELL_KEY_CMPL (UINT32_C(0x2) << 28)
13497 #define STATUS_DOORBELL_IDX_MASK UINT32_C(0xffffff)
13498 #define STATUS_DOORBELL_IDX_SFT 0
13504 #define STATUS_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
13507 #define STATUS_DOORBELL_KEY_STAT (UINT32_C(0x3) << 28)
13520 #define PUSH32_DOORBELL_IDX_MASK UINT32_C(0xffffff)
13521 #define PUSH32_DOORBELL_IDX_SFT 0
13529 * A value of 0 indicates 16x16B BD spaces are consumed.
13531 #define PUSH32_DOORBELL_SZ_MASK UINT32_C(0xf000000)
13538 #define PUSH32_DOORBELL_KEY_MASK UINT32_C(0xf0000000)
13541 #define PUSH32_DOORBELL_KEY_PUSH (UINT32_C(0x4) << 28)
13545 #define PUSH32_DOORBELL_TYPE_MASK UINT32_C(0x3f)
13546 #define PUSH32_DOORBELL_TYPE_SFT 0
13551 #define PUSH32_DOORBELL_TYPE_TX_BD_LONG UINT32_C(0x10)
13558 #define PUSH32_DOORBELL_FLAGS_MASK UINT32_C(0xffc0)
13567 #define PUSH32_DOORBELL_FLAGS_PACKET_END UINT32_C(0x40)
13573 * is set to 0, then the packet will be completed normally.
13577 #define PUSH32_DOORBELL_FLAGS_NO_CMPL UINT32_C(0x80)
13585 #define PUSH32_DOORBELL_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)
13595 #define PUSH32_DOORBELL_FLAGS_LHINT_MASK UINT32_C(0x6000)
13598 #define PUSH32_DOORBELL_FLAGS_LHINT_LT512 (UINT32_C(0x0) << 13)
13600 #define PUSH32_DOORBELL_FLAGS_LHINT_LT1K (UINT32_C(0x1) << 13)
13602 #define PUSH32_DOORBELL_FLAGS_LHINT_LT2K (UINT32_C(0x2) << 13)
13604 #define PUSH32_DOORBELL_FLAGS_LHINT_GTE2K (UINT32_C(0x3) << 13)
13612 * is set to 0, then the Consumer Index is only updated as soon
13617 #define PUSH32_DOORBELL_FLAGS_COAL_NOW UINT32_C(0x8000)
13647 #define PUSH32_DOORBELL_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
13656 #define PUSH32_DOORBELL_LFLAGS_IP_CHKSUM UINT32_C(0x2)
13668 #define PUSH32_DOORBELL_LFLAGS_NOCRC UINT32_C(0x4)
13675 #define PUSH32_DOORBELL_LFLAGS_STAMP UINT32_C(0x8)
13692 #define PUSH32_DOORBELL_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
13704 #define PUSH32_DOORBELL_LFLAGS_LSO UINT32_C(0x20)
13708 * 0xffff.
13712 * 0x7fff.
13714 #define PUSH32_DOORBELL_LFLAGS_IPID_FMT UINT32_C(0x40)
13726 #define PUSH32_DOORBELL_LFLAGS_T_IPID UINT32_C(0x80)
13731 #define PUSH32_DOORBELL_LFLAGS_ROCE_CRC UINT32_C(0x100)
13736 #define PUSH32_DOORBELL_LFLAGS_FCOE_CRC UINT32_C(0x200)
13747 #define PUSH32_DOORBELL_HDR_SIZE_MASK UINT32_C(0x1ff)
13748 #define PUSH32_DOORBELL_HDR_SIZE_SFT 0
13757 #define PUSH32_DOORBELL_MSS_MASK UINT32_C(0x7fff)
13758 #define PUSH32_DOORBELL_MSS_SFT 0
13773 #define PUSH32_DOORBELL_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
13774 #define PUSH32_DOORBELL_CFA_META_VLAN_VID_SFT 0
13776 #define PUSH32_DOORBELL_CFA_META_VLAN_DE UINT32_C(0x1000)
13778 #define PUSH32_DOORBELL_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
13781 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
13783 /* 0x88a8 */
13784 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
13785 /* 0x8100 */
13786 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
13787 /* 0x9100 */
13788 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
13789 /* 0x9200 */
13790 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
13791 /* 0x9300 */
13792 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
13794 #define PUSH32_DOORBELL_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
13797 #define PUSH32_DOORBELL_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
13805 #define PUSH32_DOORBELL_CFA_META_KEY_MASK UINT32_C(0xf0000000)
13808 #define PUSH32_DOORBELL_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
13810 * - meta[17:16] - TPID select value (0 = 0x8100).
13812 * - meta[11:0] - VID value.
13814 #define PUSH32_DOORBELL_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
13848 * * 0x0-0xFFF8 - The function ID
13849 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13850 * * 0xFFFD - Reserved for user-space HWRM interface
13851 * * 0xFFFF - HWRM
13866 #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
13881 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL UINT32_C(0x0)
13883 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME UINT32_C(0x1)
13891 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN UINT32_C(0x2)
13899 #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF UINT32_C(0x3)
13949 * * 0x0-0xFFF8 - The function ID
13950 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
13951 * * 0xFFFD - Reserved for user-space HWRM interface
13952 * * 0xFFFF - HWRM
13967 #define HWRM_FUNC_GETFID_INPUT_ENABLES_PCI_ID UINT32_C(0x1)
14028 * * 0x0-0xFFF8 - The function ID
14029 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14030 * * 0xFFFD - Reserved for user-space HWRM interface
14031 * * 0xFFFF - HWRM
14046 #define HWRM_FUNC_VF_ALLOC_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
14103 * * 0x0-0xFFF8 - The function ID
14104 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14105 * * 0xFFFD - Reserved for user-space HWRM interface
14106 * * 0xFFFF - HWRM
14121 #define HWRM_FUNC_VF_FREE_INPUT_ENABLES_FIRST_VF_ID UINT32_C(0x1)
14129 * 0xFFFF - Cleanup all children of this PF.
14179 * * 0x0-0xFFF8 - The function ID
14180 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14181 * * 0xFFFD - Reserved for user-space HWRM interface
14182 * * 0xFFFF - HWRM
14197 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_MTU UINT32_C(0x1)
14202 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_GUEST_VLAN UINT32_C(0x2)
14207 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR UINT32_C(0x4)
14212 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x8)
14217 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS UINT32_C(0x10)
14222 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS UINT32_C(0x20)
14227 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS UINT32_C(0x40)
14232 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS UINT32_C(0x80)
14237 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS UINT32_C(0x100)
14242 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS UINT32_C(0x200)
14247 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS UINT32_C(0x400)
14252 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS UINT32_C(0x800)
14257 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_TX_KEY_CTXS UINT32_C(0x1000)
14262 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_KTLS_RX_KEY_CTXS UINT32_C(0x2000)
14267 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_TX_KEY_CTXS UINT32_C(0x4000)
14272 #define HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_QUIC_RX_KEY_CTXS UINT32_C(0x8000)
14324 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST UINT32_C(0x1)
14332 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST UINT32_C(0x2)
14340 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST UINT32_C(0x4)
14348 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST UINT32_C(0x8)
14356 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST UINT32_C(0x10)
14364 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST UINT32_C(0x20)
14372 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST UINT32_C(0x40)
14380 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST UINT32_C(0x80)
14389 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE UINT32_C(0x100)
14395 #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE UINT32_C(0x200)
14470 * * 0x0-0xFFF8 - The function ID
14471 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
14472 * * 0xFFFD - Reserved for user-space HWRM interface
14473 * * 0xFFFF - HWRM
14485 * 0xFF... (All Fs) if the query is for the requesting
14487 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
14513 * 0xFF... (All Fs) if this function is not associated with
14515 * 0xFF... (All Fs) if this function is called from a VF.
14520 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PUSH_MODE_SUPPORTED UINT32_C(0x1)
14525 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GLOBAL_MSIX_AUTOMASKING UINT32_C(0x2)
14532 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED UINT32_C(0x4)
14537 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V1_SUPPORTED UINT32_C(0x8)
14542 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ROCE_V2_SUPPORTED UINT32_C(0x10)
14547 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_MAGICPKT_SUPPORTED UINT32_C(0x20)
14552 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WOL_BMP_SUPPORTED UINT32_C(0x40)
14557 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_RING_RL_SUPPORTED UINT32_C(0x80)
14562 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_TX_BW_CFG_SUPPORTED UINT32_C(0x100)
14568 * If this query is for a PF and this flag is set to 0, then
14572 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_TX_RING_RL_SUPPORTED UINT32_C(0x200)
14578 * If this query is for a PF and this flag is set to 0, then
14582 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VF_BW_CFG_SUPPORTED UINT32_C(0x400)
14589 * If set to 0, then standard TX ring mode is not available
14592 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_STD_TX_RING_MODE_SUPPORTED UINT32_C(0x800)
14599 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED UINT32_C(0x1000)
14606 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED UINT32_C(0x2000)
14613 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_GRE_TUN_FLAGS_SUPPORTED UINT32_C(0x4000)
14620 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_MPLS_TUN_FLAGS_SUPPORTED UINT32_C(0x8000)
14626 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PCIE_STATS_SUPPORTED UINT32_C(0x10000)
14633 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADOPTED_PF_SUPPORTED UINT32_C(0x20000)
14640 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED UINT32_C(0x40000)
14647 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED UINT32_C(0x80000)
14652 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE UINT32_C(0x100000)
14658 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC UINT32_C(0x200000)
14663 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE UINT32_C(0x400000)
14668 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE UINT32_C(0x800000)
14674 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED UINT32_C(0x1000000)
14681 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD UINT32_C(0x2000000)
14683 * If the query is for a VF, then this flag (always set to 0) shall
14689 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED UINT32_C(0x4000000)
14691 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED UINT32_C(0x8000000)
14696 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_COREDUMP_CMD_SUPPORTED UINT32_C(0x10000000)
14701 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_CRASHDUMP_CMD_SUPPORTED UINT32_C(0x20000000)
14712 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PFC_WD_STATS_SUPPORTED UINT32_C(0x40000000)
14717 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DBG_QCAPS_CMD_SUPPORTED UINT32_C(0x80000000)
14757 * 0xFF... (All Fs) if this command is called on a PF with
14764 * PF with SR-IOV enabled. 0xFF... (All Fs) if this
14841 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_MARK_SUPPORTED UINT32_C(0x1)
14846 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECN_STATS_SUPPORTED UINT32_C(0x2)
14851 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EXT_HW_STATS_SUPPORTED UINT32_C(0x4)
14857 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HOT_RESET_IF_SUPPORT UINT32_C(0x8)
14859 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PROXY_MODE_SUPPORT UINT32_C(0x10)
14864 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT UINT32_C(0x20)
14869 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SCHQ_SUPPORTED UINT32_C(0x40)
14874 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED UINT32_C(0x80)
14879 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED UINT32_C(0x100)
14887 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED UINT32_C(0x200)
14892 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED UINT32_C(0x400)
14897 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE UINT32_C(0x800)
14902 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE UINT32_C(0x1000)
14907 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED UINT32_C(0x2000)
14912 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED UINT32_C(0x4000)
14920 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED UINT32_C(0x8000)
14925 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NPAR_1_2_SUPPORTED UINT32_C(0x10000)
14927 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PTM_SUPPORTED UINT32_C(0x20000)
14929 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_PPS_SUPPORTED UINT32_C(0x40000)
14935 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED UINT32_C(0x80000)
14942 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PARTITION_BW_SUPPORTED UINT32_C(0x100000)
14947 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED UINT32_C(0x200000)
14949 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_KTLS_SUPPORTED UINT32_C(0x400000)
14957 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EP_RATE_CONTROL UINT32_C(0x800000)
14965 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_MIN_BW_SUPPORTED UINT32_C(0x1000000)
14970 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_COAL_CMPL_CAP UINT32_C(0x2000000)
14976 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_SUPPORTED UINT32_C(0x4000000)
14981 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BS_V2_REQUIRED UINT32_C(0x8000000)
14986 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED UINT32_C(0x10000000)
14991 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DBR_PACING_SUPPORTED UINT32_C(0x20000000)
14996 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED UINT32_C(0x40000000)
15001 …#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED UINT32_C(0x800000…
15010 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TCE UINT32_C(0x1)
15016 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RCE UINT32_C(0x2)
15022 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_TE_CFA UINT32_C(0x4)
15028 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_RE_CFA UINT32_C(0x8)
15034 #define HWRM_FUNC_QCAPS_OUTPUT_MPC_CHNLS_CAP_PRIMATE UINT32_C(0x10)
15045 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED UINT32_C(0x1)
15047 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED UINT32_C(0x2)
15053 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED UINT32_C(0x4)
15058 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED UINT32_C(0x8)
15063 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED UINT32_C(0x10)
15068 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_GENERIC_STATS_SUPPORTED UINT32_C(0x20)
15073 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDP_GSO_SUPPORTED UINT32_C(0x40)
15078 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SYNCE_SUPPORTED UINT32_C(0x80)
15081 * supporting doorbell pacing version 0. As doorbell pacing
15091 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED UINT32_C(0x100)
15101 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED UINT32_C(0x200)
15108 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED UINT32_C(0x400)
15113 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED UINT32_C(0x800)
15120 * support steering to multiple address domains, a value of 0 in
15121 * bit 0 of the steering tag specifies the address is associated
15125 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_STEERING_TAG_SUPPORTED UINT32_C(0x1000)
15130 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED UINT32_C(0x2000)
15136 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED UINT32_C(0x4000)
15143 * 2. If it is cleared to '0', it indicates that the driver has to
15147 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED UINT32_C(0x8000)
15152 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED UINT32_C(0x10000)
15157 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED UINT32_C(0x20000)
15162 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED UINT32_C(0x40000)
15167 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED UINT32_C(0x80000)
15172 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED UINT32_C(0x100000)
15177 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDCC_SUPPORTED UINT32_C(0x200000)
15185 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED UINT32_C(0x400000)
15196 * If this bit is '0', the FW will use to legacy behavior.
15202 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED UINT32_C(0x800000)
15207 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED UINT32_C(0x1000000)
15212 #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_LPBK_STATS_SUPPORTED UINT32_C(0x2000000)
15218 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN UINT32_C(0x1)
15223 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NGE UINT32_C(0x2)
15228 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE UINT32_C(0x4)
15233 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE UINT32_C(0x8)
15238 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_GRE UINT32_C(0x10)
15243 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP UINT32_C(0x20)
15248 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_MPLS UINT32_C(0x40)
15253 #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE UINT32_C(0x80)
15260 #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_TX_CK UINT32_C(0x1)
15266 #define HWRM_FUNC_QCAPS_OUTPUT_XID_PARTITION_CAP_RX_CK UINT32_C(0x2)
15358 * * 0x0-0xFFF8 - The function ID
15359 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
15360 * * 0xFFFD - Reserved for user-space HWRM interface
15361 * * 0xFFFF - HWRM
15373 * 0xFF... (All Fs) if the query is for the requesting
15375 * 0xFFFE (REQUESTING_PARENT_FID) This is a special FID
15400 * 0xFF... (All Fs) if this function is not associated with
15406 * function. The value of 0 for this field indicates
15418 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_MAGICPKT_ENABLED UINT32_C(0x1)
15423 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_OOB_WOL_BMP_ENABLED UINT32_C(0x2)
15427 * If set to 0, then DCBX agent is not running in the firmware.
15429 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_DCBX_AGENT_ENABLED UINT32_C(0x4)
15436 * If set to 0, then the standard TX ring mode is disabled
15442 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_STD_TX_RING_MODE_ENABLED UINT32_C(0x8)
15446 * If set to 0 then the LLDP agent is not running in the firmware.
15448 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FW_LLDP_AGENT_ENABLED UINT32_C(0x10)
15453 * If set to 0, then multi-host mode is inactive for this function
15456 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST UINT32_C(0x20)
15459 * set this field to 0 and the HWRM client shall ignore this field.
15462 * HWRM shall set this field to 0.
15464 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF UINT32_C(0x40)
15467 * device. If set to 0, then secure mode is disabled (or normal mode)
15470 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED UINT32_C(0x80)
15474 * doorbells. If set to 0, then this PF is not allowed to use
15479 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS UINT32_C(0x100)
15484 * If set to 0, then the adapter is not currently able to initiate
15487 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_HOT_RESET_ALLOWED UINT32_C(0x200)
15490 * reserved TX rings of this function. If set to 0, then PPP tx push
15493 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_PPP_PUSH_MODE_ENABLED UINT32_C(0x400)
15498 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED UINT32_C(0x800)
15503 * If set to 0, then the adapter is not currently able to initiate
15506 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED UINT32_C(0x1000)
15511 * If set to 0, then multi-root mode is inactive for this function
15514 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT UINT32_C(0x2000)
15519 * If set to 0, RoCE is disabled on all child VFs.
15521 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ENABLE_RDMA_SRIOV UINT32_C(0x4000)
15524 * is valid. If this bit is 0, the driver should not use the
15527 #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_ROCE_VNIC_ID_VALID UINT32_C(0x8000)
15594 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_SPF UINT32_C(0x0)
15596 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_MPFS UINT32_C(0x1)
15598 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0 UINT32_C(0x2)
15600 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5 UINT32_C(0x3)
15602 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0 UINT32_C(0x4)
15604 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_2 UINT32_C(0x5)
15606 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_UNKNOWN UINT32_C(0xff)
15610 * port_partition. HWRM shall return unavail (i.e. value of 0) for this
15616 #define HWRM_FUNC_QCFG_OUTPUT_PORT_PF_CNT_UNAVAIL UINT32_C(0x0)
15627 * A value of 0 indicates the minimum bandwidth is not configured.
15631 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
15632 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_SFT 0
15634 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE UINT32_C(0x10000000)
15636 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
15638 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
15641 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
15644 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
15646 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
15648 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
15650 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
15652 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
15654 #define HWRM_FUNC_QCFG_OUTPUT_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
15659 * A value of 0 indicates that the maximum bandwidth is not configured.
15663 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
15664 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_SFT 0
15666 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE UINT32_C(0x10000000)
15668 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
15670 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
15673 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
15676 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
15678 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
15680 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
15682 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
15684 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
15686 #define HWRM_FUNC_QCFG_OUTPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
15694 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
15696 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEB UINT32_C(0x1)
15698 #define HWRM_FUNC_QCFG_OUTPUT_EVB_MODE_VEPA UINT32_C(0x2)
15706 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK UINT32_C(0x3)
15707 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0
15709 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 UINT32_C(0x0)
15711 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 UINT32_C(0x1)
15714 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK UINT32_C(0xc)
15717 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (UINT32_C(0x0) << 2)
15719 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (UINT32_C(0x1) << 2)
15724 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO (UINT32_C(0x2) << 2)
15727 #define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK UINT32_C(0xf0)
15732 * 0xFF... (All Fs) if this command is called on a PF with
15782 * specific endpoint, with bit 0 indicating EP 0 and bit 3 indicating
15784 * - a single root system would return 0x1
15785 * - a 2x8 system (where EPs 0 and 2 are active) would return 0x5
15786 * - a 4x4 system (where EPs 0-3 are active) would return 0xF
15813 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK UINT32_C(0x7fff)
15814 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_SFT 0
15816 #define HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID UINT32_C(0x8000)
15822 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TCE_ENABLED UINT32_C(0x1)
15827 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RCE_ENABLED UINT32_C(0x2)
15833 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_TE_CFA_ENABLED UINT32_C(0x4)
15839 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_RE_CFA_ENABLED UINT32_C(0x8)
15844 #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED UINT32_C(0x10)
15851 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0)
15853 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1)
15855 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2)
15857 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3)
15859 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4)
15861 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)
15863 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)
15865 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)
15867 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8)
15869 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9)
15871 #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa)
15875 * RoCE vnic id, then the roce_vnic_id_valid bit in flags is set to 0.
15882 * of the link the partition is associated with. A value of 0
15889 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
15890 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_SFT 0
15895 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE UINT32_C(0x10000000)
15897 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
15899 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
15902 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
15905 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
15911 * of the link the partition is associated with. A value of 0
15918 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
15919 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_SFT 0
15924 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE UINT32_C(0x10000000)
15926 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
15928 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
15931 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
15934 #define HWRM_FUNC_QCFG_OUTPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
15952 #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)
15954 #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1)
15964 * feature, 0xffff will be returned.
15974 * valid lag_id is from 0 to 7, if there is no valid lag_id,
15975 * 0xff will be returned.
15985 * function is not a member of any LAG, the fw_lag_id will be 0xff.
16036 #define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_TX_CK UINT32_C(0x1)
16041 #define HWRM_FUNC_QCFG_OUTPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2)
16076 * * 0x0-0xFFF8 - The function ID
16077 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
16078 * * 0xFFFD - Reserved for user-space HWRM interface
16079 * * 0xFFFF - HWRM
16092 * If set to 0xFF... (All Fs), then the configuration is
16112 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE UINT32_C(0x1)
16121 #define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE UINT32_C(0x2)
16123 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSVD_MASK UINT32_C(0x1fc)
16132 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE UINT32_C(0x200)
16143 #define HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE UINT32_C(0x400)
16148 #define HWRM_FUNC_CFG_INPUT_FLAGS_VIRT_MAC_PERSIST UINT32_C(0x800)
16156 #define HWRM_FUNC_CFG_INPUT_FLAGS_NO_AUTOCLEAR_STATISTIC UINT32_C(0x1000)
16164 #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST UINT32_C(0x2000)
16172 #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST UINT32_C(0x4000)
16180 #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST UINT32_C(0x8000)
16188 #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST UINT32_C(0x10000)
16196 #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST UINT32_C(0x20000)
16204 #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST UINT32_C(0x40000)
16212 #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST UINT32_C(0x80000)
16220 #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST UINT32_C(0x100000)
16229 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE UINT32_C(0x200000)
16235 #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC UINT32_C(0x400000)
16243 #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST UINT32_C(0x800000)
16252 #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE UINT32_C(0x1000000)
16259 #define HWRM_FUNC_CFG_INPUT_FLAGS_PREBOOT_LEGACY_L2_RINGS UINT32_C(0x2000000)
16261 * If this bit is set to 0, then the interface does not support hot
16264 * flag to 0, adapter cannot do the hot reset. In this state, if the
16269 #define HWRM_FUNC_CFG_INPUT_FLAGS_HOT_RESET_IF_EN_DIS UINT32_C(0x4000000)
16278 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_ENABLE UINT32_C(0x8000000)
16286 #define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE UINT32_C(0x10000000)
16292 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE UINT32_C(0x20000000)
16298 #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE UINT32_C(0x40000000)
16304 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_MTU UINT32_C(0x1)
16309 #define HWRM_FUNC_CFG_INPUT_ENABLES_MRU UINT32_C(0x2)
16314 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS UINT32_C(0x4)
16319 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS UINT32_C(0x8)
16324 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS UINT32_C(0x10)
16329 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS UINT32_C(0x20)
16334 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS UINT32_C(0x40)
16339 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS UINT32_C(0x80)
16344 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS UINT32_C(0x100)
16349 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR UINT32_C(0x200)
16354 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN UINT32_C(0x400)
16359 #define HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_IP_ADDR UINT32_C(0x800)
16364 #define HWRM_FUNC_CFG_INPUT_ENABLES_MIN_BW UINT32_C(0x1000)
16369 #define HWRM_FUNC_CFG_INPUT_ENABLES_MAX_BW UINT32_C(0x2000)
16374 #define HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR UINT32_C(0x4000)
16379 #define HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE UINT32_C(0x8000)
16384 #define HWRM_FUNC_CFG_INPUT_ENABLES_ALLOWED_VLAN_PRIS UINT32_C(0x10000)
16389 #define HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE UINT32_C(0x20000)
16394 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MCAST_FILTERS UINT32_C(0x40000)
16399 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS UINT32_C(0x80000)
16404 #define HWRM_FUNC_CFG_INPUT_ENABLES_CACHE_LINESIZE UINT32_C(0x100000)
16409 #define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX UINT32_C(0x200000)
16414 #define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE UINT32_C(0x400000)
16419 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOT_RESET_IF_SUPPORT UINT32_C(0x800000)
16424 #define HWRM_FUNC_CFG_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1000000)
16429 #define HWRM_FUNC_CFG_INPUT_ENABLES_MPC_CHNLS UINT32_C(0x2000000)
16434 #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MIN_BW UINT32_C(0x4000000)
16439 #define HWRM_FUNC_CFG_INPUT_ENABLES_PARTITION_MAX_BW UINT32_C(0x8000000)
16445 #define HWRM_FUNC_CFG_INPUT_ENABLES_TPID UINT32_C(0x10000000)
16450 #define HWRM_FUNC_CFG_INPUT_ENABLES_HOST_MTU UINT32_C(0x20000000)
16455 #define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_TX_KEY_CTXS UINT32_C(0x40000000)
16460 #define HWRM_FUNC_CFG_INPUT_ENABLES_KTLS_RX_KEY_CTXS UINT32_C(0x80000000)
16542 * A value of 0 indicates the minimum bandwidth is not configured.
16546 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
16547 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_SFT 0
16549 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE UINT32_C(0x10000000)
16551 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
16553 #define HWRM_FUNC_CFG_INPUT_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
16556 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
16559 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
16561 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
16563 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
16565 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
16567 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
16569 #define HWRM_FUNC_CFG_INPUT_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
16574 * A value of 0 indicates that the maximum bandwidth is not configured.
16578 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
16579 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_SFT 0
16581 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE UINT32_C(0x10000000)
16583 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
16585 #define HWRM_FUNC_CFG_INPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
16588 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
16591 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
16593 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
16595 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
16597 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
16599 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
16601 #define HWRM_FUNC_CFG_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
16619 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK UINT32_C(0x0)
16621 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN UINT32_C(0x1)
16623 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE UINT32_C(0x2)
16625 #define HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN UINT32_C(0x3)
16659 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_NO_EVB UINT32_C(0x0)
16661 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEB UINT32_C(0x1)
16663 #define HWRM_FUNC_CFG_INPUT_EVB_MODE_VEPA UINT32_C(0x2)
16671 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK UINT32_C(0x3)
16672 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0
16674 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 UINT32_C(0x0)
16676 #define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128 UINT32_C(0x1)
16679 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK UINT32_C(0xc)
16682 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (UINT32_C(0x0) << 2)
16684 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (UINT32_C(0x1) << 2)
16689 #define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO (UINT32_C(0x2) << 2)
16692 #define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK UINT32_C(0xf0)
16705 * When this bit is '0', this flag has no effect.
16707 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_ENABLE UINT32_C(0x1)
16711 * When this bit is '0', this flag has no effect.
16713 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TCE_DISABLE UINT32_C(0x2)
16717 * When this bit is '0', this flag has no effect.
16719 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_ENABLE UINT32_C(0x4)
16723 * When this bit is '0', this flag has no effect.
16725 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RCE_DISABLE UINT32_C(0x8)
16729 * block. When this bit is '0', this flag has no effect.
16731 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_ENABLE UINT32_C(0x10)
16735 * block. When this bit is '0', this flag has no effect.
16737 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE UINT32_C(0x20)
16741 * block. When this bit is '0', this flag has no effect.
16743 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_ENABLE UINT32_C(0x40)
16747 * block. When this bit is '0', this flag has no effect.
16749 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE UINT32_C(0x80)
16753 * When this bit is '0', this flag has no effect.
16755 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_ENABLE UINT32_C(0x100)
16759 * When this bit is '0', this flag has no effect.
16761 #define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_PRIMATE_DISABLE UINT32_C(0x200)
16766 * of the link the partition is associated with. A value of 0
16775 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
16776 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_SFT 0
16781 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE UINT32_C(0x10000000)
16783 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
16785 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
16788 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
16791 #define HWRM_FUNC_CFG_INPUT_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
16797 * of the link the partition is associated with. A value of 0
16804 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
16805 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_SFT 0
16810 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE UINT32_C(0x10000000)
16812 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
16814 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
16817 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
16820 #define HWRM_FUNC_CFG_INPUT_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
16827 * 0x8100 will be used. This field is specified in
16855 #define HWRM_FUNC_CFG_INPUT_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST UINT32_C(0x1)
16863 #define HWRM_FUNC_CFG_INPUT_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST UINT32_C(0x2)
16869 #define HWRM_FUNC_CFG_INPUT_ENABLES2_KDNET UINT32_C(0x1)
16875 #define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2)
16880 #define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_TX_KEY_CTXS UINT32_C(0x4)
16885 #define HWRM_FUNC_CFG_INPUT_ENABLES2_QUIC_RX_KEY_CTXS UINT32_C(0x8)
16890 #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_AV_PER_VF UINT32_C(0x10)
16895 #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_CQ_PER_VF UINT32_C(0x20)
16900 #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_MRW_PER_VF UINT32_C(0x40)
16905 #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_QP_PER_VF UINT32_C(0x80)
16910 #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_SRQ_PER_VF UINT32_C(0x100)
16915 #define HWRM_FUNC_CFG_INPUT_ENABLES2_ROCE_MAX_GID_PER_VF UINT32_C(0x200)
16920 #define HWRM_FUNC_CFG_INPUT_ENABLES2_XID_PARTITION_CFG UINT32_C(0x400)
16928 #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0)
16930 #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1)
16943 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0)
16945 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1)
16947 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2)
16949 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3)
16951 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4)
16953 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5)
16955 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6)
16957 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7)
16959 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8)
16961 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9)
16963 #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa)
16995 #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_TX_CK UINT32_C(0x1)
17000 #define HWRM_FUNC_CFG_INPUT_XID_PARTITION_CFG_RX_CK UINT32_C(0x2)
17032 #define HWRM_FUNC_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
17034 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE UINT32_C(0x1)
17036 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX UINT32_C(0x2)
17041 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED UINT32_C(0x3)
17043 #define HWRM_FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT UINT32_C(0x4)
17071 * * 0x0-0xFFF8 - The function ID
17072 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17073 * * 0xFFFD - Reserved for user-space HWRM interface
17074 * * 0xFFFF - HWRM
17086 * 0xFF... (All Fs) if the query is for the requesting
17098 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
17104 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
17111 #define HWRM_FUNC_QSTATS_INPUT_FLAGS_L2_ONLY UINT32_C(0x4)
17232 * * 0x0-0xFFF8 - The function ID
17233 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17234 * * 0xFFFD - Reserved for user-space HWRM interface
17235 * * 0xFFFF - HWRM
17247 * 0xFF... (All Fs) if the query is for the requesting
17259 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1)
17265 #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2)
17272 #define HWRM_FUNC_QSTATS_EXT_INPUT_ENABLES_SCHQ_ID UINT32_C(0x1)
17277 * values are 0 through (max_configurable_queues - 1), where
17373 * * 0x0-0xFFF8 - The function ID
17374 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17375 * * 0xFFFD - Reserved for user-space HWRM interface
17376 * * 0xFFFF - HWRM
17388 * 0xFF... (All Fs) if the query is for the requesting
17440 * * 0x0-0xFFF8 - The function ID
17441 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17442 * * 0xFFFD - Reserved for user-space HWRM interface
17443 * * 0xFFFF - HWRM
17506 * * 0x0-0xFFF8 - The function ID
17507 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17508 * * 0xFFFD - Reserved for user-space HWRM interface
17509 * * 0xFFFF - HWRM
17528 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)
17537 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)
17542 * When this bit is '0', then ver_maj_8b, ver_min_8b, ver_upd_8b
17546 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4)
17560 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE UINT32_C(0x8)
17570 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT UINT32_C(0x10)
17582 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT UINT32_C(0x20)
17592 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT UINT32_C(0x40)
17604 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT UINT32_C(0x80)
17612 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT UINT32_C(0x100)
17616 * a value other than 0x8100 or 0x88a8.
17618 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT UINT32_C(0x200)
17625 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT UINT32_C(0x400)
17633 #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_TF_INGRESS_NIC_FLOW_MODE UINT32_C(0x800)
17639 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_OS_TYPE UINT32_C(0x1)
17644 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER UINT32_C(0x2)
17649 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_TIMESTAMP UINT32_C(0x4)
17654 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD UINT32_C(0x8)
17659 #define HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD UINT32_C(0x10)
17666 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
17668 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_OTHER UINT32_C(0x1)
17670 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_MSDOS UINT32_C(0xe)
17672 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
17674 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
17676 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_LINUX UINT32_C(0x24)
17678 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
17680 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_ESXI UINT32_C(0x68)
17682 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN864 UINT32_C(0x73)
17684 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
17686 #define HWRM_FUNC_DRV_RGTR_INPUT_OS_TYPE_UEFI UINT32_C(0x8000)
17726 * If all bits are set to 0 (value of 0), then the HWRM shall
17757 #define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED UINT32_C(0x1)
17792 * * 0x0-0xFFF8 - The function ID
17793 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17794 * * 0xFFFD - Reserved for user-space HWRM interface
17795 * * 0xFFFF - HWRM
17810 #define HWRM_FUNC_DRV_UNRGTR_INPUT_FLAGS_PREPARE_FOR_SHUTDOWN UINT32_C(0x1)
17859 * * 0x0-0xFFF8 - The function ID
17860 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17861 * * 0xFFFD - Reserved for user-space HWRM interface
17862 * * 0xFFFF - HWRM
17877 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
17882 #define HWRM_FUNC_BUF_RGTR_INPUT_ENABLES_ERR_BUF_ADDR UINT32_C(0x2)
17899 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_16B UINT32_C(0x4)
17901 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4K UINT32_C(0xc)
17903 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_8K UINT32_C(0xd)
17905 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_64K UINT32_C(0x10)
17907 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_2M UINT32_C(0x15)
17909 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_4M UINT32_C(0x16)
17911 #define HWRM_FUNC_BUF_RGTR_INPUT_REQ_BUF_PAGE_SIZE_1G UINT32_C(0x1e)
17918 /* This field represents the page address of page #0. */
17995 * * 0x0-0xFFF8 - The function ID
17996 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
17997 * * 0xFFFD - Reserved for user-space HWRM interface
17998 * * 0xFFFF - HWRM
18013 #define HWRM_FUNC_BUF_UNRGTR_INPUT_ENABLES_VF_ID UINT32_C(0x1)
18067 * * 0x0-0xFFF8 - The function ID
18068 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18069 * * 0xFFFD - Reserved for user-space HWRM interface
18070 * * 0xFFFF - HWRM
18084 * 0xFF... (All Fs) if the query is for the requesting
18094 #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_L2 UINT32_C(0x0)
18096 #define HWRM_FUNC_DRV_QVER_INPUT_DRIVER_TYPE_ROCE UINT32_C(0x1)
18118 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UNKNOWN UINT32_C(0x0)
18120 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_OTHER UINT32_C(0x1)
18122 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_MSDOS UINT32_C(0xe)
18124 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WINDOWS UINT32_C(0x12)
18126 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_SOLARIS UINT32_C(0x1d)
18128 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_LINUX UINT32_C(0x24)
18130 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_FREEBSD UINT32_C(0x2a)
18132 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_ESXI UINT32_C(0x68)
18134 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN864 UINT32_C(0x73)
18136 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_WIN2012R2 UINT32_C(0x74)
18138 #define HWRM_FUNC_DRV_QVER_OUTPUT_OS_TYPE_UEFI UINT32_C(0x8000)
18189 * * 0x0-0xFFF8 - The function ID
18190 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18191 * * 0xFFFD - Reserved for user-space HWRM interface
18192 * * 0xFFFF - HWRM
18204 * 0xFF... (All Fs) if the query is for the requesting
18238 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL UINT32_C(0x0)
18240 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL UINT32_C(0x1)
18245 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MINIMAL_STATIC UINT32_C(0x2)
18291 #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED UINT32_C(0x1)
18344 * * 0x0-0xFFF8 - The function ID
18345 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18346 * * 0xFFFD - Reserved for user-space HWRM interface
18347 * * 0xFFFF - HWRM
18399 #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED UINT32_C(0x1)
18489 * * 0x0-0xFFF8 - The function ID
18490 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18491 * * 0xFFFD - Reserved for user-space HWRM interface
18492 * * 0xFFFF - HWRM
18609 * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
18612 * `mrav_num_entries` is `0x02000100`, then the number of MR entries
18638 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP UINT32_C(0x1)
18643 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ UINT32_C(0x2)
18648 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ UINT32_C(0x4)
18653 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC UINT32_C(0x8)
18658 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT UINT32_C(0x10)
18663 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV UINT32_C(0x20)
18668 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_TKC UINT32_C(0x40)
18673 #define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_RKC UINT32_C(0x80)
18765 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK UINT32_C(0xf)
18766 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0
18768 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
18770 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
18775 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
18778 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
18781 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
18783 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
18785 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
18787 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
18789 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
18791 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
18823 * * 0x0-0xFFF8 - The function ID
18824 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
18825 * * 0xFFFD - Reserved for user-space HWRM interface
18826 * * 0xFFFF - HWRM
18843 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE UINT32_C(0x1)
18848 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x2)
18854 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP UINT32_C(0x1)
18859 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ UINT32_C(0x2)
18864 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ UINT32_C(0x4)
18869 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC UINT32_C(0x8)
18874 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT UINT32_C(0x10)
18879 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP UINT32_C(0x20)
18884 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING0 UINT32_C(0x40)
18889 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING1 UINT32_C(0x80)
18894 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING2 UINT32_C(0x100)
18899 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING3 UINT32_C(0x200)
18904 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING4 UINT32_C(0x400)
18909 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING5 UINT32_C(0x800)
18914 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING6 UINT32_C(0x1000)
18919 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING7 UINT32_C(0x2000)
18924 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_MRAV UINT32_C(0x4000)
18929 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM UINT32_C(0x8000)
18934 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 UINT32_C(0x10000)
18939 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 UINT32_C(0x20000)
18944 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 UINT32_C(0x40000)
18949 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TKC UINT32_C(0x80000)
18954 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_RKC UINT32_C(0x100000)
18959 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP_FAST_QPMD UINT32_C(0x200000)
18963 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_MASK UINT32_C(0xf)
18964 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_SFT 0
18966 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_0 UINT32_C(0x0)
18968 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_1 UINT32_C(0x1)
18973 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_LVL_LVL_2 UINT32_C(0x2)
18976 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_MASK UINT32_C(0xf0)
18979 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
18981 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
18983 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
18985 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
18987 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
18989 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_QPC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
18994 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_MASK UINT32_C(0xf)
18995 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_SFT 0
18997 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_0 UINT32_C(0x0)
18999 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_1 UINT32_C(0x1)
19004 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_LVL_LVL_2 UINT32_C(0x2)
19007 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_MASK UINT32_C(0xf0)
19010 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19012 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19014 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19016 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19018 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19020 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19025 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_MASK UINT32_C(0xf)
19026 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_SFT 0
19028 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_0 UINT32_C(0x0)
19030 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_1 UINT32_C(0x1)
19035 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_LVL_LVL_2 UINT32_C(0x2)
19038 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_MASK UINT32_C(0xf0)
19041 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19043 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19045 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19047 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19049 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19051 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19056 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_MASK UINT32_C(0xf)
19057 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_SFT 0
19059 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_0 UINT32_C(0x0)
19061 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_1 UINT32_C(0x1)
19066 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_LVL_LVL_2 UINT32_C(0x2)
19069 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_MASK UINT32_C(0xf0)
19072 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19074 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19076 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19078 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19080 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19082 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_VNIC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19087 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_MASK UINT32_C(0xf)
19088 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_SFT 0
19090 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_0 UINT32_C(0x0)
19092 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_1 UINT32_C(0x1)
19097 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_LVL_LVL_2 UINT32_C(0x2)
19100 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_MASK UINT32_C(0xf0)
19103 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19105 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19107 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19109 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19111 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19113 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_STAT_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19118 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_MASK UINT32_C(0xf)
19119 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_SFT 0
19121 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_0 UINT32_C(0x0)
19123 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_1 UINT32_C(0x1)
19128 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_LVL_LVL_2 UINT32_C(0x2)
19131 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_MASK UINT32_C(0xf0)
19134 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19136 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19138 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19140 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19142 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19144 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_SP_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19146 /* TQM ring 0 page size and level. */
19148 /* TQM ring 0 PBL indirect levels. */
19149 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf)
19150 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_SFT 0
19152 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0)
19154 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1)
19159 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2)
19161 /* TQM ring 0 page size. */
19162 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0)
19165 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19167 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19169 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19171 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19173 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19175 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING0_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19180 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf)
19181 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_SFT 0
19183 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0)
19185 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1)
19190 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2)
19193 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0)
19196 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19198 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19200 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19202 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19204 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19206 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING1_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19211 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf)
19212 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_SFT 0
19214 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0)
19216 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1)
19221 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2)
19224 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0)
19227 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19229 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19231 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19233 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19235 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19237 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING2_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19242 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf)
19243 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_SFT 0
19245 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0)
19247 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1)
19252 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2)
19255 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0)
19258 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19260 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19262 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19264 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19266 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19268 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING3_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19273 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf)
19274 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_SFT 0
19276 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0)
19278 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1)
19283 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2)
19286 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0)
19289 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19291 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19293 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19295 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19297 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19299 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING4_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19304 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf)
19305 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_SFT 0
19307 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0)
19309 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1)
19314 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2)
19317 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0)
19320 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19322 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19324 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19326 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19328 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19330 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING5_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19335 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf)
19336 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_SFT 0
19338 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0)
19340 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1)
19345 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2)
19348 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0)
19351 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19353 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19355 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19357 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19359 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19361 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING6_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19366 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf)
19367 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_SFT 0
19369 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0)
19371 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1)
19376 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2)
19379 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0)
19382 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19384 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19386 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19388 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19390 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19392 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TQM_RING7_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19397 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_MASK UINT32_C(0xf)
19398 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_SFT 0
19400 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_0 UINT32_C(0x0)
19402 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_1 UINT32_C(0x1)
19407 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_LVL_LVL_2 UINT32_C(0x2)
19410 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_MASK UINT32_C(0xf0)
19413 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19415 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19417 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19419 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19421 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19423 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_MRAV_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19428 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_MASK UINT32_C(0xf)
19429 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_SFT 0
19431 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_0 UINT32_C(0x0)
19433 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_1 UINT32_C(0x1)
19438 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_LVL_LVL_2 UINT32_C(0x2)
19441 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_MASK UINT32_C(0xf0)
19444 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19446 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19448 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19450 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19452 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19454 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19468 /* TQM ring 0 page directory. */
19517 * Number of TQM ring 0 entries.
19629 * represents the `mr_num_entries` and bits `[15:0]` represents
19668 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK UINT32_C(0xf)
19669 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT 0
19671 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
19673 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
19678 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
19681 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
19684 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19686 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19688 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19690 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19692 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19694 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19704 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK UINT32_C(0xf)
19705 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT 0
19707 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
19709 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
19714 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
19717 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
19720 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19722 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19724 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19726 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19728 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19730 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19740 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK UINT32_C(0xf)
19741 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT 0
19743 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
19745 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
19750 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
19753 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
19756 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19758 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19760 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19762 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19764 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19766 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19788 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_MASK UINT32_C(0xf)
19789 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_SFT 0
19791 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_0 UINT32_C(0x0)
19793 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_1 UINT32_C(0x1)
19798 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_LVL_LVL_2 UINT32_C(0x2)
19801 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_MASK UINT32_C(0xf0)
19804 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19806 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19808 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19810 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19812 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19814 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_TKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19819 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_MASK UINT32_C(0xf)
19820 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_SFT 0
19822 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_0 UINT32_C(0x0)
19824 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_1 UINT32_C(0x1)
19829 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_LVL_LVL_2 UINT32_C(0x2)
19832 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_MASK UINT32_C(0xf0)
19835 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
19837 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
19839 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
19841 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
19843 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
19845 #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
19899 * * 0x0-0xFFF8 - The function ID
19900 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
19901 * * 0xFFFD - Reserved for user-space HWRM interface
19902 * * 0xFFFF - HWRM
19932 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE UINT32_C(0x1)
19937 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x2)
19943 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP UINT32_C(0x1)
19948 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ UINT32_C(0x2)
19953 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ UINT32_C(0x4)
19958 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC UINT32_C(0x8)
19963 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT UINT32_C(0x10)
19968 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP UINT32_C(0x20)
19973 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 UINT32_C(0x40)
19978 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 UINT32_C(0x80)
19983 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 UINT32_C(0x100)
19988 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 UINT32_C(0x200)
19993 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 UINT32_C(0x400)
19998 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 UINT32_C(0x800)
20003 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 UINT32_C(0x1000)
20008 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 UINT32_C(0x2000)
20013 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV UINT32_C(0x4000)
20018 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM UINT32_C(0x8000)
20023 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 UINT32_C(0x10000)
20028 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 UINT32_C(0x20000)
20033 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 UINT32_C(0x40000)
20038 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TKC UINT32_C(0x80000)
20043 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_RKC UINT32_C(0x100000)
20048 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP_FAST_QPMD UINT32_C(0x200000)
20052 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_MASK UINT32_C(0xf)
20053 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_SFT 0
20055 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_0 UINT32_C(0x0)
20057 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_1 UINT32_C(0x1)
20062 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_LVL_LVL_2 UINT32_C(0x2)
20065 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_MASK UINT32_C(0xf0)
20068 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20070 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20072 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20074 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20076 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20078 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_QPC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20083 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_MASK UINT32_C(0xf)
20084 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_SFT 0
20086 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_0 UINT32_C(0x0)
20088 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_1 UINT32_C(0x1)
20093 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_LVL_LVL_2 UINT32_C(0x2)
20096 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_MASK UINT32_C(0xf0)
20099 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20101 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20103 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20105 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20107 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20109 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20114 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_MASK UINT32_C(0xf)
20115 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_SFT 0
20117 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_0 UINT32_C(0x0)
20119 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_1 UINT32_C(0x1)
20124 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_LVL_LVL_2 UINT32_C(0x2)
20127 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_MASK UINT32_C(0xf0)
20130 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20132 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20134 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20136 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20138 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20140 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20145 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_MASK UINT32_C(0xf)
20146 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_SFT 0
20148 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_0 UINT32_C(0x0)
20150 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_1 UINT32_C(0x1)
20155 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_LVL_LVL_2 UINT32_C(0x2)
20158 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_MASK UINT32_C(0xf0)
20161 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20163 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20165 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20167 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20169 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20171 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_VNIC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20176 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_MASK UINT32_C(0xf)
20177 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_SFT 0
20179 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_0 UINT32_C(0x0)
20181 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_1 UINT32_C(0x1)
20186 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_LVL_LVL_2 UINT32_C(0x2)
20189 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_MASK UINT32_C(0xf0)
20192 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20194 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20196 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20198 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20200 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20202 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_STAT_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20207 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_MASK UINT32_C(0xf)
20208 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_SFT 0
20210 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_0 UINT32_C(0x0)
20212 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_1 UINT32_C(0x1)
20217 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_LVL_LVL_2 UINT32_C(0x2)
20220 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_MASK UINT32_C(0xf0)
20223 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20225 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20227 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20229 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20231 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20233 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_SP_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20235 /* TQM ring 0 page size and level. */
20237 /* TQM ring 0 PBL indirect levels. */
20238 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_MASK UINT32_C(0xf)
20239 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_SFT 0
20241 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0)
20243 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1)
20248 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2)
20250 /* TQM ring 0 page size. */
20251 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0)
20254 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20256 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20258 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20260 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20262 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20264 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING0_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20269 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_MASK UINT32_C(0xf)
20270 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_SFT 0
20272 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0)
20274 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1)
20279 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2)
20282 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0)
20285 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20287 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20289 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20291 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20293 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20295 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING1_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20300 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_MASK UINT32_C(0xf)
20301 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_SFT 0
20303 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0)
20305 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1)
20310 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2)
20313 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0)
20316 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20318 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20320 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20322 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20324 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20326 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING2_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20331 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_MASK UINT32_C(0xf)
20332 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_SFT 0
20334 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0)
20336 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1)
20341 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2)
20344 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0)
20347 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20349 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20351 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20353 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20355 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20357 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING3_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20362 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_MASK UINT32_C(0xf)
20363 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_SFT 0
20365 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0)
20367 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1)
20372 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2)
20375 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0)
20378 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20380 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20382 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20384 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20386 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20388 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING4_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20393 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_MASK UINT32_C(0xf)
20394 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_SFT 0
20396 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0)
20398 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1)
20403 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2)
20406 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0)
20409 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20411 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20413 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20415 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20417 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20419 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING5_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20424 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_MASK UINT32_C(0xf)
20425 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_SFT 0
20427 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0)
20429 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1)
20434 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2)
20437 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0)
20440 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20442 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20444 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20446 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20448 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20450 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING6_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20455 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_MASK UINT32_C(0xf)
20456 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_SFT 0
20458 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0)
20460 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1)
20465 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2)
20468 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0)
20471 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20473 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20475 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20477 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20479 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20481 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TQM_RING7_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20486 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_MASK UINT32_C(0xf)
20487 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_SFT 0
20489 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_0 UINT32_C(0x0)
20491 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_1 UINT32_C(0x1)
20496 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_LVL_LVL_2 UINT32_C(0x2)
20499 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_MASK UINT32_C(0xf0)
20502 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20504 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20506 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20508 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20510 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20512 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_MRAV_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20517 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_MASK UINT32_C(0xf)
20518 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_SFT 0
20520 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_0 UINT32_C(0x0)
20522 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_1 UINT32_C(0x1)
20527 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_LVL_LVL_2 UINT32_C(0x2)
20530 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_MASK UINT32_C(0xf0)
20533 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20535 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20537 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20539 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20541 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20543 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20557 /* TQM ring 0 page directory. */
20599 /* Number of TQM ring 0 entries. */
20624 * represents the `mr_num_entries` and bits `[15:0]` represents
20635 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK UINT32_C(0xf)
20636 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT 0
20638 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
20640 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
20645 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
20648 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
20651 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20653 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20655 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20657 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20659 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20661 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20671 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK UINT32_C(0xf)
20672 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT 0
20674 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
20676 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
20681 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
20684 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
20687 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20689 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20691 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20693 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20695 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20697 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20707 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK UINT32_C(0xf)
20708 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT 0
20710 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 UINT32_C(0x0)
20712 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 UINT32_C(0x1)
20717 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 UINT32_C(0x2)
20720 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK UINT32_C(0xf0)
20723 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20725 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20727 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20729 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20731 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20733 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20751 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_MASK UINT32_C(0xf)
20752 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_SFT 0
20754 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_0 UINT32_C(0x0)
20756 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_1 UINT32_C(0x1)
20761 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_LVL_LVL_2 UINT32_C(0x2)
20764 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_MASK UINT32_C(0xf0)
20767 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20769 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20771 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20773 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20775 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20777 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_TKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20782 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_MASK UINT32_C(0xf)
20783 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_SFT 0
20785 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_0 UINT32_C(0x0)
20787 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_1 UINT32_C(0x1)
20792 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_LVL_LVL_2 UINT32_C(0x2)
20795 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_MASK UINT32_C(0xf0)
20798 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
20800 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
20802 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
20804 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
20806 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
20808 #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RKC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
20850 * * 0x0-0xFFF8 - The function ID
20851 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
20852 * * 0xFFFD - Reserved for user-space HWRM interface
20853 * * 0xFFFF - HWRM
20882 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
20887 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
20931 * A value of 0xFFFF-FFFF indicates this register does not exist.
20935 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK UINT32_C(0x3)
20936 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0
20938 * If value is 0, this register is located in PCIe config space.
20942 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
20948 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC UINT32_C(0x1)
20954 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
20961 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
20964 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK UINT32_C(0xfffffffc)
20970 * A value of 0xFFFF-FFFF indicates this register does not exist.
20974 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK UINT32_C(0x3)
20975 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0
20977 * If value is 0, this register is located in PCIe config space.
20981 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
20987 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC UINT32_C(0x1)
20993 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
20999 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
21002 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK UINT32_C(0xfffffffc)
21008 * A value of 0xFFFF-FFFF indicates this register does not exist.
21012 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK UINT32_C(0x3)
21013 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0
21015 * If value is 0, this register is located in PCIe config space.
21019 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
21025 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC UINT32_C(0x1)
21031 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
21037 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
21040 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK UINT32_C(0xfffffffc)
21046 * A value of 0xFFFF-FFFF indicates this register does not exist.
21050 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK UINT32_C(0x3)
21051 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0
21053 * If value is 0, this register is located in PCIe config space.
21057 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
21063 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC UINT32_C(0x1)
21069 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
21075 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
21078 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK UINT32_C(0xfffffffc)
21096 * A value of 0xFFFF-FFFF indicates this register does not exist.
21100 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK UINT32_C(0x3)
21101 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
21103 * If value is 0, this register is located in PCIe config space.
21107 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
21113 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC UINT32_C(0x1)
21119 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
21125 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
21128 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK UINT32_C(0xfffffffc)
21145 * A value of 0xFFFF-FFFF indicates this register does not exist.
21149 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK UINT32_C(0x3)
21150 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0
21152 * If value is 0, this register is located in PCIe config space.
21156 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
21162 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC UINT32_C(0x1)
21168 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
21174 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
21177 #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_ERR_RECOVERY_CNT_REG_ADDR_MASK UINT32_C(0xfffffffc)
21214 * * 0x0-0xFFF8 - The function ID
21215 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21216 * * 0xFFFD - Reserved for user-space HWRM interface
21217 * * 0xFFFF - HWRM
21276 * * 0x0-0xFFF8 - The function ID
21277 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21278 * * 0xFFFD - Reserved for user-space HWRM interface
21279 * * 0xFFFF - HWRM
21311 * When this bit is '1', TSIO pin 0 is enabled.
21312 * When this bit is '0', TSIO pin 0 is disabled.
21314 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN0_ENABLED UINT32_C(0x1)
21317 * When this bit is '0', TSIO pin 1 is disabled.
21319 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN1_ENABLED UINT32_C(0x2)
21322 * When this bit is '0', TSIO pin 2 is disabled.
21324 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN2_ENABLED UINT32_C(0x4)
21327 * When this bit is '0', TSIO pin 3 is disabled.
21329 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_STATE_PIN3_ENABLED UINT32_C(0x8)
21330 /* Type of function for Pin #0. */
21333 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_NONE UINT32_C(0x0)
21335 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
21337 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
21339 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
21341 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
21346 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_NONE UINT32_C(0x0)
21348 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
21350 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
21352 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
21354 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
21359 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0)
21361 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
21363 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
21365 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
21367 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
21369 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT UINT32_C(0x5)
21371 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
21376 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0)
21378 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
21380 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
21382 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
21384 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
21386 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT UINT32_C(0x5)
21388 #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
21424 * * 0x0-0xFFF8 - The function ID
21425 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21426 * * 0xFFFD - Reserved for user-space HWRM interface
21427 * * 0xFFFF - HWRM
21442 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_STATE UINT32_C(0x1)
21447 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN0_USAGE UINT32_C(0x2)
21452 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_STATE UINT32_C(0x4)
21457 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN1_USAGE UINT32_C(0x8)
21462 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_STATE UINT32_C(0x10)
21467 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN2_USAGE UINT32_C(0x20)
21472 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_STATE UINT32_C(0x40)
21477 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_ENABLES_PIN3_USAGE UINT32_C(0x80)
21478 /* Enable or disable functionality of Pin #0. */
21481 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_DISABLED UINT32_C(0x0)
21483 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_STATE_ENABLED UINT32_C(0x1)
21485 /* Configure function for TSIO pin#0. */
21488 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_NONE UINT32_C(0x0)
21490 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_IN UINT32_C(0x1)
21492 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_PPS_OUT UINT32_C(0x2)
21494 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_IN UINT32_C(0x3)
21496 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN0_USAGE_SYNC_OUT UINT32_C(0x4)
21501 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_DISABLED UINT32_C(0x0)
21503 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_STATE_ENABLED UINT32_C(0x1)
21508 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_NONE UINT32_C(0x0)
21510 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_IN UINT32_C(0x1)
21512 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_PPS_OUT UINT32_C(0x2)
21514 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_IN UINT32_C(0x3)
21516 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN1_USAGE_SYNC_OUT UINT32_C(0x4)
21521 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_DISABLED UINT32_C(0x0)
21523 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_STATE_ENABLED UINT32_C(0x1)
21528 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0)
21530 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1)
21532 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2)
21534 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3)
21536 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4)
21538 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT UINT32_C(0x5)
21540 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
21545 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_DISABLED UINT32_C(0x0)
21547 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_STATE_ENABLED UINT32_C(0x1)
21552 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0)
21554 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1)
21556 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2)
21558 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3)
21560 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4)
21562 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT UINT32_C(0x5)
21564 #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT UINT32_C(0x6)
21614 * * 0x0-0xFFF8 - The function ID
21615 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21616 * * 0xFFFD - Reserved for user-space HWRM interface
21617 * * 0xFFFF - HWRM
21632 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_PPS_EVENT UINT32_C(0x1)
21637 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE UINT32_C(0x2)
21642 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_DLL_PHASE UINT32_C(0x4)
21647 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD UINT32_C(0x8)
21652 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_UP UINT32_C(0x10)
21657 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_EXT_PHASE UINT32_C(0x20)
21659 #define HWRM_FUNC_PTP_CFG_INPUT_ENABLES_PTP_SET_TIME UINT32_C(0x40)
21668 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_INTERNAL UINT32_C(0x1)
21673 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_PPS_EVENT_EXTERNAL UINT32_C(0x2)
21680 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_NONE UINT32_C(0x0)
21681 /* TSIO Pin #0 is selected as source signal. */
21682 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 UINT32_C(0x1)
21684 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 UINT32_C(0x2)
21686 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 UINT32_C(0x3)
21688 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 UINT32_C(0x4)
21689 /* Port #0 is selected as source signal. */
21690 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 UINT32_C(0x5)
21692 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 UINT32_C(0x6)
21694 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 UINT32_C(0x7)
21696 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 UINT32_C(0x8)
21698 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_SOURCE_INVALID UINT32_C(0xff)
21706 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_NONE UINT32_C(0x0)
21708 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_4K UINT32_C(0x1)
21710 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_8K UINT32_C(0x2)
21712 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_10M UINT32_C(0x3)
21714 #define HWRM_FUNC_PTP_CFG_INPUT_PTP_FREQ_ADJ_DLL_PHASE_25M UINT32_C(0x4)
21798 * * 0x0-0xFFF8 - The function ID
21799 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21800 * * 0xFFFD - Reserved for user-space HWRM interface
21801 * * 0xFFFF - HWRM
21813 #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PPS_TIME UINT32_C(0x1)
21815 #define HWRM_FUNC_PTP_TS_QUERY_INPUT_FLAGS_PTM_TIME UINT32_C(0x2)
21885 * * 0x0-0xFFF8 - The function ID
21886 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
21887 * * 0xFFFD - Reserved for user-space HWRM interface
21888 * * 0xFFFF - HWRM
21903 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_MASTER_FID UINT32_C(0x1)
21908 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_FID UINT32_C(0x2)
21913 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_PHC_SEC_MODE UINT32_C(0x4)
21918 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_ENABLES_FAILOVER_TIMER UINT32_C(0x8)
21946 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_SWITCH UINT32_C(0x0)
21952 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_ALL UINT32_C(0x1)
21958 #define HWRM_FUNC_PTP_EXT_CFG_INPUT_PHC_SEC_MODE_PF_ONLY UINT32_C(0x2)
21965 * 0 - Failover timer is automatically selected based on the last
21972 * 0xFFFFFFFF - If driver specifies this value, then failover never
22029 * * 0x0-0xFFF8 - The function ID
22030 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22031 * * 0xFFFD - Reserved for user-space HWRM interface
22032 * * 0xFFFF - HWRM
22126 * * 0x0-0xFFF8 - The function ID
22127 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22128 * * 0xFFFD - Reserved for user-space HWRM interface
22129 * * 0xFFFF - HWRM
22165 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0)
22167 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1)
22169 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_TX UINT32_C(0x2)
22171 #define HWRM_FUNC_KEY_CTX_ALLOC_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3)
22214 #define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS UINT32_C(0x1)
22255 * * 0x0-0xFFF8 - The function ID
22256 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22257 * * 0xFFFD - Reserved for user-space HWRM interface
22258 * * 0xFFFF - HWRM
22273 #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_TX UINT32_C(0x0)
22275 #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_RX UINT32_C(0x1)
22277 #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_TX UINT32_C(0x2)
22279 #define HWRM_FUNC_KEY_CTX_FREE_INPUT_KEY_CTX_TYPE_QUIC_RX UINT32_C(0x3)
22343 * * 0x0-0xFFF8 - The function ID
22344 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22345 * * 0xFFFD - Reserved for user-space HWRM interface
22346 * * 0xFFFF - HWRM
22359 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP UINT32_C(0x0)
22361 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1)
22363 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ UINT32_C(0x2)
22365 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3)
22367 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT UINT32_C(0x4)
22369 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5)
22371 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6)
22373 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe)
22375 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM UINT32_C(0xf)
22377 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TX_CK UINT32_C(0x13)
22379 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RX_CK UINT32_C(0x14)
22381 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15)
22383 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16)
22385 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17)
22387 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18)
22389 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19)
22391 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c)
22393 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_XID_PARTITION UINT32_C(0x1d)
22395 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e)
22397 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f)
22399 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20)
22401 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21)
22403 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22)
22405 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23)
22407 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24)
22409 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_INVALID UINT32_C(0xffff)
22413 * which means "0" indicates the first instance. For backing
22414 * stores with single instance only, leave this field to 0.
22417 * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
22420 * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)
22423 * TX_CK (0), RX_CK (1)
22434 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE UINT32_C(0x1)
22443 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_CFG_ALL_DONE UINT32_C(0x2)
22457 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_EXTEND UINT32_C(0x4)
22467 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_MASK UINT32_C(0xf)
22468 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_SFT 0
22470 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_0 UINT32_C(0x0)
22472 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_1 UINT32_C(0x1)
22477 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PBL_LEVEL_LVL_2 UINT32_C(0x2)
22480 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_MASK UINT32_C(0xf0)
22483 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_4K (UINT32_C(0x0) << 4)
22485 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8K (UINT32_C(0x1) << 4)
22487 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_64K (UINT32_C(0x2) << 4)
22489 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_2M (UINT32_C(0x3) << 4)
22491 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_8M (UINT32_C(0x4) << 4)
22493 #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_PAGE_SIZE_PG_1G (UINT32_C(0x5) << 4)
22500 * | 0 | None of the split entries has valid data. |
22508 * Split entry #0. Note that the four split entries (as a group)
22577 * * 0x0-0xFFF8 - The function ID
22578 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22579 * * 0xFFFD - Reserved for user-space HWRM interface
22580 * * 0xFFFF - HWRM
22593 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_QP UINT32_C(0x0)
22595 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ UINT32_C(0x1)
22597 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ UINT32_C(0x2)
22599 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_VNIC UINT32_C(0x3)
22601 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_STAT UINT32_C(0x4)
22603 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5)
22605 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6)
22607 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MRAV UINT32_C(0xe)
22609 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TIM UINT32_C(0xf)
22611 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TX_CK UINT32_C(0x13)
22613 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RX_CK UINT32_C(0x14)
22615 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15)
22617 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16)
22619 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17)
22621 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18)
22623 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19)
22625 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c)
22627 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_XID_PARTITION_TABLE UINT32_C(0x1d)
22629 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e)
22631 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f)
22633 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20)
22635 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21)
22637 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22)
22639 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23)
22641 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24)
22643 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_INPUT_TYPE_INVALID UINT32_C(0xffff)
22647 * which means "0" indicates the first instance. For backing
22648 * stores with single instance only, leave this field to 0.
22651 * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
22654 * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)
22657 * TX_CK (0), RX_CK (1)
22677 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_QP UINT32_C(0x0)
22679 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1)
22681 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CQ UINT32_C(0x2)
22683 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3)
22685 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_STAT UINT32_C(0x4)
22687 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5)
22689 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6)
22691 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe)
22693 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TIM UINT32_C(0xf)
22695 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TX_CK UINT32_C(0x13)
22697 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RX_CK UINT32_C(0x14)
22699 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15)
22701 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_TBL_SCOPE UINT32_C(0x1c)
22703 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_XID_PARTITION UINT32_C(0x1d)
22705 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT_TRACE UINT32_C(0x1e)
22707 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_SRT2_TRACE UINT32_C(0x1f)
22709 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT_TRACE UINT32_C(0x20)
22711 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_CRT2_TRACE UINT32_C(0x21)
22713 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_RIGP0_TRACE UINT32_C(0x22)
22715 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23)
22717 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24)
22719 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_TYPE_INVALID UINT32_C(0xffff)
22723 * which means "0" indicates the first instance. For backing
22724 * stores with single instance only, leave this field to 0.
22727 * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
22730 * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)
22733 * TX_CK (0), RX_CK (1)
22745 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_MASK UINT32_C(0xf)
22746 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_SFT 0
22748 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_0 UINT32_C(0x0)
22750 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_1 UINT32_C(0x1)
22755 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PBL_LEVEL_LVL_2 UINT32_C(0x2)
22758 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_MASK UINT32_C(0xf0)
22761 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_4K (UINT32_C(0x0) << 4)
22763 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8K (UINT32_C(0x1) << 4)
22765 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_64K (UINT32_C(0x2) << 4)
22767 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_2M (UINT32_C(0x3) << 4)
22769 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_8M (UINT32_C(0x4) << 4)
22771 #define HWRM_FUNC_BACKING_STORE_QCFG_V2_OUTPUT_PAGE_SIZE_PG_1G (UINT32_C(0x5) << 4)
22778 * | 0 | None of the split entries has valid data. |
22787 * Split entry #0. Note that the four split entries (as a group)
22930 * * 0x0-0xFFF8 - The function ID
22931 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
22932 * * 0xFFFD - Reserved for user-space HWRM interface
22933 * * 0xFFFF - HWRM
22946 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_QP UINT32_C(0x0)
22948 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ UINT32_C(0x1)
22950 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ UINT32_C(0x2)
22952 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_VNIC UINT32_C(0x3)
22954 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_STAT UINT32_C(0x4)
22956 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SP_TQM_RING UINT32_C(0x5)
22958 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_FP_TQM_RING UINT32_C(0x6)
22960 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MRAV UINT32_C(0xe)
22962 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TIM UINT32_C(0xf)
22964 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TX_CK UINT32_C(0x13)
22966 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RX_CK UINT32_C(0x14)
22968 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_MP_TQM_RING UINT32_C(0x15)
22970 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16)
22972 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17)
22974 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18)
22976 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19)
22978 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_TBL_SCOPE UINT32_C(0x1c)
22980 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_XID_PARTITION UINT32_C(0x1d)
22982 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT_TRACE UINT32_C(0x1e)
22984 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1f)
22986 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT_TRACE UINT32_C(0x20)
22988 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_CRT2_TRACE UINT32_C(0x21)
22990 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x22)
22992 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23)
22994 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24)
22996 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_INPUT_TYPE_INVALID UINT32_C(0xffff)
23015 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_QP UINT32_C(0x0)
23017 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ UINT32_C(0x1)
23019 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ UINT32_C(0x2)
23021 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_VNIC UINT32_C(0x3)
23023 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_STAT UINT32_C(0x4)
23025 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SP_TQM_RING UINT32_C(0x5)
23027 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_FP_TQM_RING UINT32_C(0x6)
23029 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MRAV UINT32_C(0xe)
23031 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TIM UINT32_C(0xf)
23033 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TX_CK UINT32_C(0x13)
23035 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RX_CK UINT32_C(0x14)
23037 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_MP_TQM_RING UINT32_C(0x15)
23039 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SQ_DB_SHADOW UINT32_C(0x16)
23041 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RQ_DB_SHADOW UINT32_C(0x17)
23043 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRQ_DB_SHADOW UINT32_C(0x18)
23045 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CQ_DB_SHADOW UINT32_C(0x19)
23047 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_TBL_SCOPE UINT32_C(0x1c)
23049 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_XID_PARTITION UINT32_C(0x1d)
23051 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT_TRACE UINT32_C(0x1e)
23053 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_SRT2_TRACE UINT32_C(0x1f)
23055 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT_TRACE UINT32_C(0x20)
23057 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_CRT2_TRACE UINT32_C(0x21)
23059 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_RIGP0_TRACE UINT32_C(0x22)
23061 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x23)
23063 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x24)
23065 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_TYPE_INVALID UINT32_C(0xffff)
23075 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ENABLE_CTX_KIND_INIT UINT32_C(0x1)
23077 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID UINT32_C(0x2)
23083 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_DRIVER_MANAGED_MEMORY UINT32_C(0x4)
23100 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC UINT32_C(0x8)
23106 * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4)
23109 * RE_CFA_LKUP (0), RE_CFA_ACT (1), TE_CFA_LKUP(2), TE_CFA_ACT (3)
23112 * TX_CK (0), RX_CK (1)
23130 * this field with "0".
23139 * TQM rings. If not applicable, leave this field with "0".
23152 * | 0 | None of the split entries has valid data. |
23172 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT UINT32_C(0x1)
23177 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT UINT32_C(0x2)
23182 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT UINT32_C(0x4)
23187 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT UINT32_C(0x8)
23188 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_EXACT_CNT_BIT_MAP_UNUSED_MASK UINT32_C(0xf0)
23191 * Split entry #0. Note that the four split entries (as a group)
23246 * * 0x0-0xFFF8 - The function ID
23247 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23248 * * 0xFFFD - Reserved for user-space HWRM interface
23249 * * 0xFFFF - HWRM
23265 #define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_ENABLE UINT32_C(0x1)
23267 #define HWRM_FUNC_DBR_PACING_CFG_INPUT_FLAGS_DBR_NQ_EVENT_DISABLE UINT32_C(0x2)
23274 #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PRIMARY_NQ_ID_VALID UINT32_C(0x1)
23279 #define HWRM_FUNC_DBR_PACING_CFG_INPUT_ENABLES_PACING_THRESHOLD_VALID UINT32_C(0x2)
23339 * * 0x0-0xFFF8 - The function ID
23340 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23341 * * 0xFFFD - Reserved for user-space HWRM interface
23342 * * 0xFFFF - HWRM
23367 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_FLAGS_DBR_NQ_EVENT_ENABLED UINT32_C(0x1)
23374 * 0xFFFF-FFFF indicates this register does not exist.
23378 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK UINT32_C(0x3)
23379 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT 0
23381 * If value is 0, this register is located in PCIe config space.
23385 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
23391 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC UINT32_C(0x1)
23397 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
23404 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
23407 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_STAT_DB_FIFO_REG_ADDR_MASK UINT32_C(0xfffffffc)
23437 * address. A value of 0xFFFF-FFFF indicates this register does not
23442 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK UINT32_C(0x3)
23443 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT 0
23445 * If value is 0, this register is located in PCIe config space.
23449 …fine HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
23455 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC UINT32_C(0x1)
23461 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 UINT32_C(0x2)
23468 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 UINT32_C(0x3)
23471 #define HWRM_FUNC_DBR_PACING_QCFG_OUTPUT_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK UINT32_C(0xfffffffc)
23483 * A value of 0xFFFF FFFF indicates NQ ID is invalid.
23526 * * 0x0-0xFFF8 - The function ID
23527 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23528 * * 0xFFFD - Reserved for user-space HWRM interface
23529 * * 0xFFFF - HWRM
23587 * * 0x0-0xFFF8 - The function ID
23588 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23589 * * 0xFFFD - Reserved for user-space HWRM interface
23590 * * 0xFFFF - HWRM
23681 * * 0x0-0xFFF8 - The function ID
23682 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23683 * * 0xFFFD - Reserved for user-space HWRM interface
23684 * * 0xFFFF - HWRM
23701 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_MASK UINT32_C(0xffffff)
23702 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_SFT 0
23752 * * 0x0-0xFFF8 - The function ID
23753 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23754 * * 0xFFFD - Reserved for user-space HWRM interface
23755 * * 0xFFFF - HWRM
23770 #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_FREQ_PROFILE UINT32_C(0x1)
23775 #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_PRIMARY_CLOCK UINT32_C(0x2)
23780 #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_SECONDARY_CLOCK UINT32_C(0x4)
23784 #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)
23786 #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1)
23794 #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_DISABLE UINT32_C(0x0)
23796 #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE UINT32_C(0x1)
23804 #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_DISABLE UINT32_C(0x0)
23806 #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE UINT32_C(0x1)
23856 * * 0x0-0xFFF8 - The function ID
23857 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23858 * * 0xFFFD - Reserved for user-space HWRM interface
23859 * * 0xFFFF - HWRM
23886 #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_INVALID UINT32_C(0x0)
23888 #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1)
23894 * When this bit is '0', primary clock is disabled for this PF/port.
23896 #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_PRIMARY_CLOCK_ENABLED UINT32_C(0x1)
23900 * When this bit is '0', secondary clock is disabled for this
23903 #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_SECONDARY_CLOCK_ENABLED UINT32_C(0x2)
23938 * * 0x0-0xFFF8 - The function ID
23939 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
23940 * * 0xFFFD - Reserved for user-space HWRM interface
23941 * * 0xFFFF - HWRM
23956 #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x1)
23961 #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x2)
23963 #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_AGGR_MODE UINT32_C(0x4)
23965 #define HWRM_FUNC_LAG_CREATE_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xf8)
23970 * from 0 to n - 1 on a device with n ports. The number of front panel
23992 #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1)
23994 #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2)
23996 #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4)
23998 #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8)
24000 #define HWRM_FUNC_LAG_CREATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
24005 * from 0 to n - 1 on a device with n ports. The number of front panel
24014 #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1)
24016 #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2)
24018 #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4)
24020 #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8)
24022 #define HWRM_FUNC_LAG_CREATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
24027 #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
24029 #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
24031 #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
24033 #define HWRM_FUNC_LAG_CREATE_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4)
24088 * * 0x0-0xFFF8 - The function ID
24089 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24090 * * 0xFFFD - Reserved for user-space HWRM interface
24091 * * 0xFFFF - HWRM
24108 #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x1)
24113 #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x2)
24115 #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_AGGR_MODE UINT32_C(0x4)
24117 #define HWRM_FUNC_LAG_UPDATE_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xf8)
24122 * from 0 to n - 1 on a device with n ports. The number of front panel
24144 #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1)
24146 #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2)
24148 #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4)
24150 #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8)
24152 #define HWRM_FUNC_LAG_UPDATE_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
24157 * from 0 to n - 1 on a device with n ports. The number of front panel
24166 #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1)
24168 #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2)
24170 #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4)
24172 #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8)
24174 #define HWRM_FUNC_LAG_UPDATE_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
24179 #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
24181 #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
24183 #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
24185 #define HWRM_FUNC_LAG_UPDATE_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4)
24235 * * 0x0-0xFFF8 - The function ID
24236 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24237 * * 0xFFFD - Reserved for user-space HWRM interface
24238 * * 0xFFFF - HWRM
24298 * * 0x0-0xFFF8 - The function ID
24299 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24300 * * 0xFFFD - Reserved for user-space HWRM interface
24301 * * 0xFFFF - HWRM
24330 * from 0 to n - 1 on a device with n ports. The number of front panel
24352 #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1)
24354 #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2)
24356 #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4)
24358 #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8)
24360 #define HWRM_FUNC_LAG_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
24365 * from 0 to n - 1 on a device with n ports. The number of front panel
24374 #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1)
24376 #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2)
24378 #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4)
24380 #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8)
24382 #define HWRM_FUNC_LAG_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
24387 #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
24389 #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
24391 #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
24393 #define HWRM_FUNC_LAG_QCFG_OUTPUT_AGGR_MODE_802_3_AD UINT32_C(0x4)
24429 * * 0x0-0xFFF8 - The function ID
24430 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24431 * * 0xFFFD - Reserved for user-space HWRM interface
24432 * * 0xFFFF - HWRM
24447 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_FLAGS UINT32_C(0x1)
24452 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_ACTIVE_PORT_MAP UINT32_C(0x2)
24457 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_MEMBER_PORT_MAP UINT32_C(0x4)
24459 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_AGGR_MODE UINT32_C(0x8)
24461 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_LAG_ID UINT32_C(0x10)
24463 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ENABLES_RSVD1_MASK UINT32_C(0xe0)
24470 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_DISABLE UINT32_C(0x1)
24475 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_AGGR_ENABLE UINT32_C(0x2)
24477 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_FLAGS_RSVD2_MASK UINT32_C(0xfc)
24481 * represents a front panel port of the device starting from port 0.
24499 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1)
24501 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2)
24503 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4)
24505 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8)
24507 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_ACTIVE_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
24511 * represents a front panel port of the device starting from port 0.
24528 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1)
24530 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2)
24532 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4)
24534 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8)
24536 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_MEMBER_PORT_MAP_RSVD4_MASK UINT32_C(0xf0)
24541 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
24543 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
24545 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
24547 #define HWRM_FUNC_LAG_MODE_CFG_INPUT_AGGR_MODE_802_3_AD UINT32_C(0x4)
24601 * * 0x0-0xFFF8 - The function ID
24602 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24603 * * 0xFFFD - Reserved for user-space HWRM interface
24604 * * 0xFFFF - HWRM
24633 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_ENABLED UINT32_C(0x1)
24635 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_RSVD1_MASK UINT32_C(0xfe)
24639 * represents a front panel port of the device starting from port 0.
24657 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_0 UINT32_C(0x1)
24659 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_1 UINT32_C(0x2)
24661 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_2 UINT32_C(0x4)
24663 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_PORT_3 UINT32_C(0x8)
24665 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_ACTIVE_PORT_MAP_RSVD2_MASK UINT32_C(0xf0)
24669 * represents a front panel port of the device starting from port 0.
24686 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_0 UINT32_C(0x1)
24688 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_1 UINT32_C(0x2)
24690 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_2 UINT32_C(0x4)
24692 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_PORT_3 UINT32_C(0x8)
24694 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_MEMBER_PORT_MAP_RSVD3_MASK UINT32_C(0xf0)
24699 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
24701 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
24703 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
24705 #define HWRM_FUNC_LAG_MODE_QCFG_OUTPUT_AGGR_MODE_802_3_AD UINT32_C(0x4)
24741 * * 0x0-0xFFF8 - The function ID
24742 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24743 * * 0xFFFD - Reserved for user-space HWRM interface
24744 * * 0xFFFF - HWRM
24757 * If set to 0xFF... (All Fs), then the configuration is
24834 * * 0x0-0xFFF8 - The function ID
24835 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24836 * * 0xFFFD - Reserved for user-space HWRM interface
24837 * * 0xFFFF - HWRM
24850 * If set to 0xFF... (All Fs), then the configuration is
24860 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)
24865 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)
24870 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)
24875 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)
24880 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)
24885 #define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)
24958 * * 0x0-0xFFF8 - The function ID
24959 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
24960 * * 0xFFFD - Reserved for user-space HWRM interface
24961 * * 0xFFFF - HWRM
25034 * * 0x0-0xFFF8 - The function ID
25035 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25036 * * 0xFFFD - Reserved for user-space HWRM interface
25037 * * 0xFFFF - HWRM
25056 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
25057 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0
25062 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)
25064 /* 0% of the max tx rate */
25065 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 (UINT32_C(0x0) << 12)
25067 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 (UINT32_C(0x1) << 12)
25069 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 (UINT32_C(0x2) << 12)
25071 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 (UINT32_C(0x3) << 12)
25073 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 (UINT32_C(0x4) << 12)
25075 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 (UINT32_C(0x5) << 12)
25077 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 (UINT32_C(0x6) << 12)
25079 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 (UINT32_C(0x7) << 12)
25081 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 (UINT32_C(0x8) << 12)
25083 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 (UINT32_C(0x9) << 12)
25085 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 (UINT32_C(0xa) << 12)
25087 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 (UINT32_C(0xb) << 12)
25089 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 (UINT32_C(0xc) << 12)
25091 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 (UINT32_C(0xd) << 12)
25093 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 (UINT32_C(0xe) << 12)
25095 #define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 (UINT32_C(0xf) << 12)
25144 * * 0x0-0xFFF8 - The function ID
25145 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25146 * * 0xFFFD - Reserved for user-space HWRM interface
25147 * * 0xFFFF - HWRM
25167 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)
25168 #define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0
25192 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)
25193 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0
25198 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)
25200 /* 0% of the max tx rate */
25201 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 (UINT32_C(0x0) << 12)
25203 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 (UINT32_C(0x1) << 12)
25205 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 (UINT32_C(0x2) << 12)
25207 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 (UINT32_C(0x3) << 12)
25209 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 (UINT32_C(0x4) << 12)
25211 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 (UINT32_C(0x5) << 12)
25213 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 (UINT32_C(0x6) << 12)
25215 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 (UINT32_C(0x7) << 12)
25217 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 (UINT32_C(0x8) << 12)
25219 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 (UINT32_C(0x9) << 12)
25221 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 (UINT32_C(0xa) << 12)
25223 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 (UINT32_C(0xb) << 12)
25225 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 (UINT32_C(0xc) << 12)
25227 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 (UINT32_C(0xd) << 12)
25229 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 (UINT32_C(0xe) << 12)
25231 #define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 (UINT32_C(0xf) << 12)
25267 * * 0x0-0xFFF8 - The function ID
25268 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25269 * * 0xFFFD - Reserved for user-space HWRM interface
25270 * * 0xFFFF - HWRM
25294 #define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)
25316 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE UINT32_C(0x1)
25322 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE UINT32_C(0x2)
25331 #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_CAPS_CHANGE UINT32_C(0x4)
25366 * * 0x0-0xFFF8 - The function ID
25367 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25368 * * 0xFFFD - Reserved for user-space HWRM interface
25369 * * 0xFFFF - HWRM
25384 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_SOC UINT32_C(0x1)
25389 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_0 UINT32_C(0x2)
25394 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_1 UINT32_C(0x4)
25399 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_2 UINT32_C(0x8)
25404 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_HOST_EP_3 UINT32_C(0x10)
25414 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ALL UINT32_C(0x0)
25419 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_L2 UINT32_C(0x1)
25424 #define HWRM_FUNC_HOST_PF_IDS_QUERY_INPUT_FILTER_ROCE UINT32_C(0x2)
25447 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_0 UINT32_C(0x1)
25452 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_1 UINT32_C(0x2)
25457 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_2 UINT32_C(0x4)
25462 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_3 UINT32_C(0x8)
25467 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_4 UINT32_C(0x10)
25472 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_5 UINT32_C(0x20)
25477 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_6 UINT32_C(0x40)
25482 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_7 UINT32_C(0x80)
25487 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_8 UINT32_C(0x100)
25492 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_9 UINT32_C(0x200)
25497 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_10 UINT32_C(0x400)
25502 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_11 UINT32_C(0x800)
25507 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_12 UINT32_C(0x1000)
25512 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_13 UINT32_C(0x2000)
25517 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_14 UINT32_C(0x4000)
25522 #define HWRM_FUNC_HOST_PF_IDS_QUERY_OUTPUT_PF_ORDINAL_MASK_FUNC_15 UINT32_C(0x8000)
25557 * * 0x0-0xFFF8 - The function ID
25558 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25559 * * 0xFFFD - Reserved for user-space HWRM interface
25560 * * 0xFFFF - HWRM
25572 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE UINT32_C(0x1)
25574 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE UINT32_C(0x2)
25579 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE UINT32_C(0x4)
25584 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE UINT32_C(0x8)
25589 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE UINT32_C(0x10)
25594 #define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE UINT32_C(0x20)
25600 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE UINT32_C(0x1)
25605 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS UINT32_C(0x2)
25610 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE UINT32_C(0x4)
25615 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR UINT32_C(0x8)
25620 #define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR UINT32_C(0x10)
25625 * value of 0xffff is used if there is no user specified value.
25634 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1)
25642 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2)
25649 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4)
25657 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8)
25664 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10)
25672 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
25678 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
25684 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
25690 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
25696 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
25702 #define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
25754 * * 0x0-0xFFF8 - The function ID
25755 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25756 * * 0xFFFD - Reserved for user-space HWRM interface
25757 * * 0xFFFF - HWRM
25785 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED UINT32_C(0x1)
25790 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED UINT32_C(0x2)
25795 #define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED UINT32_C(0x4)
25802 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
25808 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
25814 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
25820 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
25826 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
25832 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
25841 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1)
25849 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2)
25856 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4)
25864 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8)
25871 #define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10)
25877 * value of 0xffff is used if there is no user specified value.
25914 * * 0x0-0xFFF8 - The function ID
25915 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
25916 * * 0xFFFD - Reserved for user-space HWRM interface
25917 * * 0xFFFF - HWRM
25942 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)
25944 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED UINT32_C(0x2)
25947 * bit in the 'enables' field is '0', the link shall be forced
25964 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE UINT32_C(0x4)
25969 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG UINT32_C(0x8)
25976 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE UINT32_C(0x10)
25983 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE UINT32_C(0x20)
25992 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE UINT32_C(0x40)
26001 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE UINT32_C(0x80)
26013 * When set to 0, then this flag shall be ignored.
26017 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE UINT32_C(0x100)
26022 * When set to 0, then this flag shall be ignored.
26026 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE UINT32_C(0x200)
26031 * When set to 0, then this flag shall be ignored.
26035 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE UINT32_C(0x400)
26040 * When set to 0, then this flag shall be ignored.
26044 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE UINT32_C(0x800)
26053 * When set to 0, then this flag shall be ignored.
26057 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE UINT32_C(0x1000)
26062 * force disabled otherwise. When set to 0, then this flag shall be
26066 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE UINT32_C(0x2000)
26076 * to '0'.
26077 * # If this flag is set to '0', then the link shall be
26085 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN UINT32_C(0x4000)
26093 * When set to 0, then this flag shall be ignored.
26097 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_ENABLE UINT32_C(0x8000)
26102 * When set to 0, then this flag shall be ignored.
26106 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_1XN_DISABLE UINT32_C(0x10000)
26114 * When set to 0, then this flag shall be ignored.
26118 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_ENABLE UINT32_C(0x20000)
26123 * When set to 0, then this flag shall be ignored.
26127 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS544_IEEE_DISABLE UINT32_C(0x40000)
26136 * When set to 0, then this flag shall be ignored.
26140 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_ENABLE UINT32_C(0x80000)
26145 * When set to 0, then this flag shall be ignored.
26149 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_1XN_DISABLE UINT32_C(0x100000)
26158 * When set to 0, then this flag shall be ignored.
26162 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_ENABLE UINT32_C(0x200000)
26167 * When set to 0, then this flag shall be ignored.
26171 #define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_RS272_IEEE_DISABLE UINT32_C(0x400000)
26177 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)
26182 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX UINT32_C(0x2)
26187 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE UINT32_C(0x4)
26192 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED UINT32_C(0x8)
26197 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK UINT32_C(0x10)
26202 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED UINT32_C(0x20)
26207 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK UINT32_C(0x40)
26212 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS UINT32_C(0x80)
26217 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE UINT32_C(0x100)
26222 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK UINT32_C(0x200)
26227 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER UINT32_C(0x400)
26232 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAM4_LINK_SPEED UINT32_C(0x800)
26237 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAM4_LINK_SPEED_MASK UINT32_C(0x1000)
26242 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_LINK_SPEEDS2 UINT32_C(0x2000)
26247 #define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEEDS2_MASK UINT32_C(0x4000)
26257 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
26259 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
26261 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
26263 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
26265 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
26267 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
26269 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
26271 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
26273 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
26275 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
26277 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
26285 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)
26287 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
26292 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
26298 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
26304 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
26312 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)
26314 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)
26316 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)
26328 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX UINT32_C(0x1)
26333 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX UINT32_C(0x2)
26341 * flag is set to 0, the pause is forced as indicated in
26346 * 1, auto_pause bits should be ignored and should be set to 0.
26348 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
26361 * When set to 0, management firmware is using the given port.
26363 #define HWRM_PORT_PHY_CFG_INPUT_MGMT_FLAG_LINK_RELEASE UINT32_C(0x1)
26368 #define HWRM_PORT_PHY_CFG_INPUT_MGMT_FLAG_MGMT_VALID UINT32_C(0x80)
26376 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
26378 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
26380 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
26382 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
26384 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
26386 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
26388 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
26390 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
26392 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
26394 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
26396 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
26405 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD UINT32_C(0x1)
26407 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB UINT32_C(0x2)
26409 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD UINT32_C(0x4)
26411 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB UINT32_C(0x8)
26413 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB UINT32_C(0x10)
26415 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB UINT32_C(0x20)
26417 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB UINT32_C(0x40)
26419 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB UINT32_C(0x80)
26421 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB UINT32_C(0x100)
26423 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB UINT32_C(0x200)
26425 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB UINT32_C(0x400)
26427 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB UINT32_C(0x800)
26429 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD UINT32_C(0x1000)
26431 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB UINT32_C(0x2000)
26435 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)
26437 #define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)
26442 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
26447 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
26453 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
26460 #define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)
26471 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
26476 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
26481 * enable.preemphasis = 0) unless driver is sure of setting.
26496 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
26498 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
26500 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
26502 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
26504 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10)
26506 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20)
26508 #define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40)
26516 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_50GB UINT32_C(0x1f4)
26518 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_100GB UINT32_C(0x3e8)
26520 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAM4_LINK_SPEED_200GB UINT32_C(0x7d0)
26528 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
26529 #define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
26532 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_50G UINT32_C(0x1)
26533 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_100G UINT32_C(0x2)
26534 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_PAM4_SPEED_MASK_200G UINT32_C(0x4)
26542 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_1GB UINT32_C(0xa)
26544 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_10GB UINT32_C(0x64)
26546 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_25GB UINT32_C(0xfa)
26548 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_40GB UINT32_C(0x190)
26550 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB UINT32_C(0x1f4)
26552 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB UINT32_C(0x3e8)
26554 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x1f5)
26556 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x3e9)
26558 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x7d1)
26560 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0xfa1)
26562 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x3ea)
26564 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x7d2)
26566 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0xfa2)
26568 #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x1f42)
26577 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_1GB UINT32_C(0x1)
26579 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_10GB UINT32_C(0x2)
26581 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_25GB UINT32_C(0x4)
26583 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_40GB UINT32_C(0x8)
26585 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB UINT32_C(0x10)
26587 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB UINT32_C(0x20)
26589 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 UINT32_C(0x40)
26591 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 UINT32_C(0x80)
26593 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 UINT32_C(0x100)
26595 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 UINT32_C(0x200)
26597 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 UINT32_C(0x400)
26599 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 UINT32_C(0x800)
26601 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 UINT32_C(0x1000)
26603 #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 UINT32_C(0x2000)
26638 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
26640 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)
26646 * but if a 0 is returned at any time then this should
26653 #define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)
26681 * * 0x0-0xFFF8 - The function ID
26682 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
26683 * * 0xFFFD - Reserved for user-space HWRM interface
26684 * * 0xFFFF - HWRM
26713 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)
26715 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)
26717 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)
26724 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_MASK UINT32_C(0xf)
26725 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_SFT 0
26727 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ UINT32_C(0x0)
26729 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 UINT32_C(0x1)
26731 #define HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4_112 UINT32_C(0x2)
26734 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_MASK UINT32_C(0xf0)
26737 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_NONE_ACTIVE (UINT32_C(0x0) << 4)
26739 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (UINT32_C(0x1) << 4)
26741 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (UINT32_C(0x2) << 4)
26743 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (UINT32_C(0x3) << 4)
26745 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (UINT32_C(0x4) << 4)
26747 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (UINT32_C(0x5) << 4)
26749 #define HWRM_PORT_PHY_QCFG_OUTPUT_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (UINT32_C(0x6) << 4)
26758 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)
26760 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)
26762 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)
26764 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)
26766 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)
26768 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)
26770 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)
26772 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)
26774 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
26776 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
26778 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
26780 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_400GB UINT32_C(0xfa0)
26782 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_800GB UINT32_C(0x1f40)
26784 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
26792 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)
26794 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)
26806 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)
26811 #define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)
26819 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD UINT32_C(0x1)
26821 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB UINT32_C(0x2)
26823 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD UINT32_C(0x4)
26825 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB UINT32_C(0x8)
26827 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB UINT32_C(0x10)
26829 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB UINT32_C(0x20)
26831 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB UINT32_C(0x40)
26833 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB UINT32_C(0x80)
26835 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB UINT32_C(0x100)
26837 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB UINT32_C(0x200)
26839 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB UINT32_C(0x400)
26841 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB UINT32_C(0x800)
26843 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD UINT32_C(0x1000)
26845 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB UINT32_C(0x2000)
26849 * value shall be set to 0.
26853 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)
26855 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)
26857 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)
26859 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)
26861 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)
26863 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)
26865 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)
26867 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)
26869 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
26871 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
26873 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
26878 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)
26880 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
26885 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
26891 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
26896 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
26907 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX UINT32_C(0x1)
26912 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX UINT32_C(0x2)
26920 * flag is set to 0, the pause is forced as indicated in
26925 * 1, auto_pause bits should be ignored and should be set to 0.
26927 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
26934 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)
26936 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)
26938 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)
26940 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)
26942 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)
26944 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)
26946 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)
26948 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)
26950 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
26952 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
26954 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
26965 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD UINT32_C(0x1)
26967 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB UINT32_C(0x2)
26969 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD UINT32_C(0x4)
26971 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB UINT32_C(0x8)
26973 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB UINT32_C(0x10)
26975 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB UINT32_C(0x20)
26977 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB UINT32_C(0x40)
26979 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB UINT32_C(0x80)
26981 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB UINT32_C(0x100)
26983 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB UINT32_C(0x200)
26985 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB UINT32_C(0x400)
26987 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB UINT32_C(0x800)
26989 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD UINT32_C(0x1000)
26991 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB UINT32_C(0x2000)
26995 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)
26997 #define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)
27002 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
27007 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
27013 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
27020 #define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)
27025 * this value shall be set to 0.
27032 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)
27037 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)
27044 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE UINT32_C(0x0)
27046 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX UINT32_C(0x1)
27048 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG UINT32_C(0x2)
27050 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN UINT32_C(0x3)
27052 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED UINT32_C(0x4)
27054 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_CURRENTFAULT UINT32_C(0x5)
27056 #define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE UINT32_C(0xff)
27069 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN UINT32_C(0x0)
27071 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR UINT32_C(0x1)
27073 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 UINT32_C(0x2)
27075 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR UINT32_C(0x3)
27077 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR UINT32_C(0x4)
27079 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 UINT32_C(0x5)
27081 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX UINT32_C(0x6)
27083 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR UINT32_C(0x7)
27085 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET UINT32_C(0x8)
27087 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE UINT32_C(0x9)
27089 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY UINT32_C(0xa)
27091 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L UINT32_C(0xb)
27093 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S UINT32_C(0xc)
27095 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N UINT32_C(0xd)
27097 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR UINT32_C(0xe)
27099 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 UINT32_C(0xf)
27101 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 UINT32_C(0x10)
27103 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 UINT32_C(0x11)
27105 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 UINT32_C(0x12)
27107 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 UINT32_C(0x13)
27109 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 UINT32_C(0x14)
27111 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 UINT32_C(0x15)
27113 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 UINT32_C(0x16)
27115 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 UINT32_C(0x17)
27117 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE UINT32_C(0x18)
27119 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET UINT32_C(0x19)
27121 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX UINT32_C(0x1a)
27123 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX UINT32_C(0x1b)
27125 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 UINT32_C(0x1c)
27127 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 UINT32_C(0x1d)
27129 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 UINT32_C(0x1e)
27131 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 UINT32_C(0x1f)
27133 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASECR UINT32_C(0x20)
27135 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASESR UINT32_C(0x21)
27137 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASELR UINT32_C(0x22)
27139 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_50G_BASEER UINT32_C(0x23)
27141 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR2 UINT32_C(0x24)
27143 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR2 UINT32_C(0x25)
27145 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR2 UINT32_C(0x26)
27147 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER2 UINT32_C(0x27)
27149 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR UINT32_C(0x28)
27151 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR UINT32_C(0x29)
27153 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR UINT32_C(0x2a)
27155 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER UINT32_C(0x2b)
27157 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR2 UINT32_C(0x2c)
27159 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR2 UINT32_C(0x2d)
27161 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR2 UINT32_C(0x2e)
27163 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER2 UINT32_C(0x2f)
27165 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR8 UINT32_C(0x30)
27167 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR8 UINT32_C(0x31)
27169 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR8 UINT32_C(0x32)
27171 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER8 UINT32_C(0x33)
27173 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASECR4 UINT32_C(0x34)
27175 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASESR4 UINT32_C(0x35)
27177 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASELR4 UINT32_C(0x36)
27179 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_400G_BASEER4 UINT32_C(0x37)
27181 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASECR8 UINT32_C(0x38)
27183 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASESR8 UINT32_C(0x39)
27185 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASELR8 UINT32_C(0x3a)
27187 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEER8 UINT32_C(0x3b)
27189 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEFR8 UINT32_C(0x3c)
27191 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_800G_BASEDR8 UINT32_C(0x3d)
27196 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)
27198 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)
27200 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)
27202 #define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)
27207 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL UINT32_C(0x1)
27209 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL UINT32_C(0x2)
27213 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK UINT32_C(0x1f)
27214 #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0
27221 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK UINT32_C(0xe0)
27228 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED UINT32_C(0x20)
27232 * # If eee_enabled is set to 0, then EEE mode is disabled
27237 * # If eee_enabled is set to 1 and this flag is set to 0,
27241 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE UINT32_C(0x40)
27245 * # If eee_enabled is set to 0, then EEE mode is disabled
27250 * # If eee_enabled is set to 1 and this flag is set to 0,
27254 #define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI UINT32_C(0x80)
27272 #define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)
27279 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD UINT32_C(0x1)
27281 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB UINT32_C(0x2)
27283 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD UINT32_C(0x4)
27285 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB UINT32_C(0x8)
27287 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB UINT32_C(0x10)
27289 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB UINT32_C(0x20)
27291 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB UINT32_C(0x40)
27293 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB UINT32_C(0x80)
27295 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB UINT32_C(0x100)
27297 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB UINT32_C(0x200)
27299 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB UINT32_C(0x400)
27301 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB UINT32_C(0x800)
27303 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD UINT32_C(0x1000)
27305 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB UINT32_C(0x2000)
27308 * This field is deprecated and should be set to 0.
27312 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE UINT32_C(0x0)
27314 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)
27319 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED UINT32_C(0x2)
27325 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)
27330 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK UINT32_C(0x4)
27338 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX UINT32_C(0x1)
27343 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX UINT32_C(0x2)
27353 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
27355 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
27357 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
27359 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
27361 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10)
27363 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20)
27365 #define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40)
27373 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
27375 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
27377 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
27379 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
27381 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 UINT32_C(0x10)
27383 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 UINT32_C(0x20)
27385 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB UINT32_C(0x40)
27392 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)
27393 #define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0
27395 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK UINT32_C(0xff000000)
27398 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN (UINT32_C(0x0) << 24)
27400 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP (UINT32_C(0x3) << 24)
27402 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP (UINT32_C(0xc) << 24)
27404 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS (UINT32_C(0xd) << 24)
27406 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 (UINT32_C(0x11) << 24)
27408 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPDD (UINT32_C(0x18) << 24)
27410 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP112 (UINT32_C(0x1e) << 24)
27412 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFPDD (UINT32_C(0x1f) << 24)
27414 #define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_CSFP (UINT32_C(0x20) << 24)
27424 * ignored. When set to 0, then FEC is supported as indicated by
27427 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED UINT32_C(0x1)
27430 * When set to 0, then FEC autonegotiation is not supported on this
27433 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED UINT32_C(0x2)
27436 * When set to 0, then FEC autonegotiation is disabled if supported.
27440 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED UINT32_C(0x4)
27443 * port. When set to 0, then FEC CLAUSE 74 (Fire Code) is not
27446 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED UINT32_C(0x8)
27451 * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if
27455 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED UINT32_C(0x10)
27459 * When set to 0, then FEC RS(528,418) is not supported on this port.
27461 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED UINT32_C(0x20)
27466 * RS(528,514) is force enabled. When set to 0, then FEC RS(528,514)
27471 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED UINT32_C(0x40)
27474 * When set to 0, then FEC RS544_1XN is not supported on this port.
27476 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_SUPPORTED UINT32_C(0x80)
27481 * When set to 0, then FEC RS544_1XN is disabled if supported.
27485 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_1XN_ENABLED UINT32_C(0x100)
27488 * When set to 0, then FEC RS(544,514) is not supported on this port.
27490 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_SUPPORTED UINT32_C(0x200)
27495 * enabled. When set to 0, then FEC RS(544,514) is disabled if
27499 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS544_IEEE_ENABLED UINT32_C(0x400)
27502 * When set to 0, then FEC RS272_1XN is not supported on this port.
27504 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_SUPPORTED UINT32_C(0x800)
27509 * enabled. When set to 0, then FEC RS272_1XN is disabled if
27514 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_1XN_ENABLED UINT32_C(0x1000)
27517 * When set to 0, then FEC RS(272,514) is not supported on this port.
27519 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_SUPPORTED UINT32_C(0x2000)
27524 * enabled. When set to 0, then FEC RS(272,257) is disabled if
27529 #define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_RS272_IEEE_ENABLED UINT32_C(0x4000)
27536 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)
27538 #define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)
27543 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT UINT32_C(0x1)
27548 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN UINT32_C(0x2)
27553 #define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SPEEDS2_SUPPORTED UINT32_C(0x4)
27574 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G UINT32_C(0x1)
27575 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G UINT32_C(0x2)
27576 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G UINT32_C(0x4)
27580 * value shall be set to 0.
27584 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_50GB UINT32_C(0x1f4)
27586 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_100GB UINT32_C(0x3e8)
27588 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAM4_LINK_SPEED_200GB UINT32_C(0x7d0)
27598 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_50G UINT32_C(0x1)
27599 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_100G UINT32_C(0x2)
27600 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAM4_LINK_SPEED_MASK_200G UINT32_C(0x4)
27607 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB UINT32_C(0x1)
27609 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB UINT32_C(0x2)
27611 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB UINT32_C(0x4)
27614 * This field is set to 0, if the link down reason is unknown.
27618 #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF UINT32_C(0x1)
27627 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_1GB UINT32_C(0x1)
27629 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_10GB UINT32_C(0x2)
27631 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_25GB UINT32_C(0x4)
27633 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_40GB UINT32_C(0x8)
27635 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB UINT32_C(0x10)
27637 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB UINT32_C(0x20)
27639 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_50GB_PAM4_56 UINT32_C(0x40)
27641 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_56 UINT32_C(0x80)
27643 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_56 UINT32_C(0x100)
27645 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_56 UINT32_C(0x200)
27647 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_100GB_PAM4_112 UINT32_C(0x400)
27649 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_200GB_PAM4_112 UINT32_C(0x800)
27651 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_400GB_PAM4_112 UINT32_C(0x1000)
27653 #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS2_800GB_PAM4_112 UINT32_C(0x2000)
27656 * being forced, this value shall be set to 0.
27662 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_1GB UINT32_C(0xa)
27664 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_10GB UINT32_C(0x64)
27666 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_25GB UINT32_C(0xfa)
27668 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_40GB UINT32_C(0x190)
27670 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB UINT32_C(0x1f4)
27672 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB UINT32_C(0x3e8)
27674 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x1f5)
27676 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x3e9)
27678 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x7d1)
27680 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0xfa1)
27682 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x3ea)
27684 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x7d2)
27686 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0xfa2)
27688 #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x1f42)
27700 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_1GB UINT32_C(0x1)
27702 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_10GB UINT32_C(0x2)
27704 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_25GB UINT32_C(0x4)
27706 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_40GB UINT32_C(0x8)
27708 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB UINT32_C(0x10)
27710 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB UINT32_C(0x20)
27712 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_50GB_PAM4_56 UINT32_C(0x40)
27714 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_56 UINT32_C(0x80)
27716 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_56 UINT32_C(0x100)
27718 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_56 UINT32_C(0x200)
27720 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_100GB_PAM4_112 UINT32_C(0x400)
27722 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_200GB_PAM4_112 UINT32_C(0x800)
27724 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_400GB_PAM4_112 UINT32_C(0x1000)
27726 #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEEDS2_800GB_PAM4_112 UINT32_C(0x2000)
27766 * * 0x0-0xFFF8 - The function ID
27767 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
27768 * * 0xFFFD - Reserved for user-space HWRM interface
27769 * * 0xFFFF - HWRM
27810 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK UINT32_C(0x1)
27815 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE UINT32_C(0x2)
27820 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE UINT32_C(0x4)
27825 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE UINT32_C(0x8)
27831 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE UINT32_C(0x10)
27837 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE UINT32_C(0x20)
27843 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE UINT32_C(0x40)
27849 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE UINT32_C(0x80)
27854 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE UINT32_C(0x100)
27859 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE UINT32_C(0x200)
27864 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE UINT32_C(0x400)
27869 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE UINT32_C(0x800)
27874 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE UINT32_C(0x1000)
27880 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS UINT32_C(0x2000)
27886 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_ENABLE UINT32_C(0x4000)
27892 #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_ALL_RX_TS_CAPTURE_DISABLE UINT32_C(0x8000)
27898 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG UINT32_C(0x1)
27903 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK UINT32_C(0x2)
27908 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI UINT32_C(0x4)
27913 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI UINT32_C(0x10)
27918 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI UINT32_C(0x20)
27923 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x40)
27928 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE UINT32_C(0x80)
27933 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG UINT32_C(0x100)
27938 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB UINT32_C(0x200)
27943 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_ADJ_PHASE UINT32_C(0x400)
27948 #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_LOAD_CONTROL UINT32_C(0x800)
27959 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)
27964 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)
27970 #define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)
27981 * For example, a value of 0-3 is returned where 0 is being
27997 * For example, a value of 0-3 is returned where 0 is being
28010 * For example, a value of 0-3 is returned where 0 is being
28041 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 UINT32_C(0x1)
28052 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK UINT32_C(0x6)
28058 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 1)
28066 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 1)
28071 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 1)
28073 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 1)
28084 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK UINT32_C(0x18)
28090 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 3)
28098 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 3)
28103 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 3)
28105 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 3)
28115 #define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK UINT32_C(0xe0)
28130 #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_NONE UINT32_C(0x0)
28135 #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_IMMEDIATE UINT32_C(0x1)
28140 #define HWRM_PORT_MAC_CFG_INPUT_PTP_LOAD_CONTROL_PPS_EVENT UINT32_C(0x2)
28180 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
28185 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
28191 #define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
28227 * * 0x0-0xFFF8 - The function ID
28228 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28229 * * 0xFFFD - Reserved for user-space HWRM interface
28230 * * 0xFFFF - HWRM
28278 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)
28283 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)
28289 #define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)
28297 * For example, a value of 0-3 is returned where 0 is being
28314 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE UINT32_C(0x1)
28319 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE UINT32_C(0x2)
28324 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE UINT32_C(0x4)
28329 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE UINT32_C(0x8)
28331 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE UINT32_C(0x10)
28333 #define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE UINT32_C(0x20)
28340 * For example, a value of 0-3 is returned where 0 is being
28354 * For example, a value of 0-3 is returned where 0 is being
28370 * If all bits are set to 0 (i.e. field value set 0),
28386 * If all bits are set to 0 (i.e. field value set 0),
28397 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD UINT32_C(0x1)
28404 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK UINT32_C(0x6)
28410 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 1)
28418 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 1)
28423 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 1)
28425 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 1)
28433 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK UINT32_C(0x18)
28439 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (UINT32_C(0x0) << 3)
28447 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (UINT32_C(0x1) << 3)
28452 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (UINT32_C(0x2) << 3)
28454 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (UINT32_C(0x3) << 3)
28460 #define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK UINT32_C(0xe0)
28469 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK UINT32_C(0x7fff)
28470 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_SFT 0
28472 #define HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID UINT32_C(0x8000)
28479 #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_NONE UINT32_C(0x0)
28481 #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_IMMEDIATE UINT32_C(0x1)
28486 #define HWRM_PORT_MAC_QCFG_OUTPUT_PTP_LOAD_CONTROL_PPS_EVENT UINT32_C(0x2)
28522 * * 0x0-0xFFF8 - The function ID
28523 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
28524 * * 0xFFFD - Reserved for user-space HWRM interface
28525 * * 0xFFFF - HWRM
28560 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS UINT32_C(0x1)
28565 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS UINT32_C(0x4)
28570 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS UINT32_C(0x8)
28576 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK UINT32_C(0x10)
28581 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_RTC_CONFIGURED UINT32_C(0x20)
28586 #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_64B_PHC_TIME UINT32_C(0x40)
28726 * Pri 0 transmitted
28854 * and RXD is 0xE. The event is reported along with the
28885 * XON to XOFF on Pri 0
28925 * bit for Pri 0
29026 * * 0x0-0xFFF8 - The function ID
29027 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29028 * * 0xFFFD - Reserved for user-space HWRM interface
29029 * * 0xFFFF - HWRM
29047 #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
29091 /* Total number of tx bytes count on cos queue 0 */
29107 /* Total number of tx packets count on cos queue 0 */
29123 /* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
29125 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
29171 /* Total number of rx bytes count on cos queue 0 */
29187 /* Total number of rx packets count on cos queue 0 */
29203 /* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */
29205 /* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */
29246 /* Total number of rx discard bytes count on cos queue 0 */
29262 /* Total number of rx discard packets count on cos queue 0 */
29321 * for Pri 0
29361 * for Pri 0
29401 * for pri 0
29441 * for pri 0
29481 * for pri 0
29521 * for pri 0
29561 * for pri 0
29601 * for pri 0
29641 * for pri 0
29681 * for pri 0
29744 * * 0x0-0xFFF8 - The function ID
29745 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29746 * * 0xFFFD - Reserved for user-space HWRM interface
29747 * * 0xFFFF - HWRM
29775 #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
29811 #define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED UINT32_C(0x1)
29845 * * 0x0-0xFFF8 - The function ID
29846 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29847 * * 0xFFFD - Reserved for user-space HWRM interface
29848 * * 0xFFFF - HWRM
29923 * * 0x0-0xFFF8 - The function ID
29924 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
29925 * * 0xFFFD - Reserved for user-space HWRM interface
29926 * * 0xFFFF - HWRM
29950 #define HWRM_PORT_LPBK_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
30038 * * 0x0-0xFFF8 - The function ID
30039 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30040 * * 0xFFFD - Reserved for user-space HWRM interface
30041 * * 0xFFFF - HWRM
30067 #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
30110 * Number of packets marked in CoS queue 0.
30182 * * 0x0-0xFFF8 - The function ID
30183 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30184 * * 0xFFFD - Reserved for user-space HWRM interface
30185 * * 0xFFFF - HWRM
30208 #define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)
30257 * * 0x0-0xFFF8 - The function ID
30258 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30259 * * 0xFFFD - Reserved for user-space HWRM interface
30260 * * 0xFFFF - HWRM
30320 * * 0x0-0xFFF8 - The function ID
30321 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30322 * * 0xFFFD - Reserved for user-space HWRM interface
30323 * * 0xFFFF - HWRM
30339 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1)
30341 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
30343 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
30349 #define HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME UINT32_C(0x2)
30358 #define HWRM_PORT_TS_QUERY_INPUT_ENABLES_TS_REQ_TIMEOUT UINT32_C(0x1)
30363 #define HWRM_PORT_TS_QUERY_INPUT_ENABLES_PTP_SEQ_ID UINT32_C(0x2)
30368 #define HWRM_PORT_TS_QUERY_INPUT_ENABLES_PTP_HDR_OFFSET UINT32_C(0x4)
30446 * * 0x0-0xFFF8 - The function ID
30447 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30448 * * 0xFFFD - Reserved for user-space HWRM interface
30449 * * 0xFFFF - HWRM
30481 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED UINT32_C(0x1)
30486 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED UINT32_C(0x2)
30491 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED UINT32_C(0x4)
30499 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED UINT32_C(0x8)
30505 * If set to 0, the state of the counters is unspecified when
30508 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET UINT32_C(0x10)
30513 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED UINT32_C(0x20)
30523 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN UINT32_C(0x40)
30529 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS UINT32_C(0x80)
30533 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)
30535 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)
30537 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)
30539 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)
30541 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)
30543 #define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_12 UINT32_C(0xc)
30553 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD UINT32_C(0x1)
30555 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB UINT32_C(0x2)
30557 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD UINT32_C(0x4)
30559 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB UINT32_C(0x8)
30561 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB UINT32_C(0x10)
30563 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB UINT32_C(0x20)
30565 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB UINT32_C(0x40)
30567 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB UINT32_C(0x80)
30569 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB UINT32_C(0x100)
30571 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB UINT32_C(0x200)
30573 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB UINT32_C(0x400)
30575 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB UINT32_C(0x800)
30577 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD UINT32_C(0x1000)
30579 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB UINT32_C(0x2000)
30588 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD UINT32_C(0x1)
30590 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB UINT32_C(0x2)
30592 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD UINT32_C(0x4)
30594 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB UINT32_C(0x8)
30596 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB UINT32_C(0x10)
30598 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB UINT32_C(0x20)
30600 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB UINT32_C(0x40)
30602 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB UINT32_C(0x80)
30604 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB UINT32_C(0x100)
30606 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB UINT32_C(0x200)
30608 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB UINT32_C(0x400)
30610 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB UINT32_C(0x800)
30612 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD UINT32_C(0x1000)
30614 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB UINT32_C(0x2000)
30624 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 UINT32_C(0x1)
30626 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB UINT32_C(0x2)
30628 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 UINT32_C(0x4)
30630 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB UINT32_C(0x8)
30632 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 UINT32_C(0x10)
30634 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 UINT32_C(0x20)
30636 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB UINT32_C(0x40)
30643 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK UINT32_C(0xffffff)
30644 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0
30646 * Reserved field. The HWRM shall set this field to 0.
30649 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK UINT32_C(0xff000000)
30657 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK UINT32_C(0xffffff)
30658 #define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0
30660 * Reserved field. The HWRM shall set this field to 0.
30663 #define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD_MASK UINT32_C(0xff000000)
30670 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G UINT32_C(0x1)
30671 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G UINT32_C(0x2)
30672 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G UINT32_C(0x4)
30678 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G UINT32_C(0x1)
30679 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G UINT32_C(0x2)
30680 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G UINT32_C(0x4)
30687 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED UINT32_C(0x1)
30692 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED UINT32_C(0x2)
30697 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED UINT32_C(0x4)
30703 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_SPEEDS2_SUPPORTED UINT32_C(0x8)
30708 #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_REMOTE_LPBK_UNSUPPORTED UINT32_C(0x10)
30713 * the PRBS test run on them. This field always return 0 unless NVM
30727 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_1GB UINT32_C(0x1)
30729 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_10GB UINT32_C(0x2)
30731 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_25GB UINT32_C(0x4)
30733 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_40GB UINT32_C(0x8)
30735 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB UINT32_C(0x10)
30737 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB UINT32_C(0x20)
30739 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 UINT32_C(0x40)
30741 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 UINT32_C(0x80)
30743 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 UINT32_C(0x100)
30745 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 UINT32_C(0x200)
30747 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 UINT32_C(0x400)
30749 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 UINT32_C(0x800)
30751 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 UINT32_C(0x1000)
30753 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 UINT32_C(0x2000)
30763 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_1GB UINT32_C(0x1)
30765 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_10GB UINT32_C(0x2)
30767 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_25GB UINT32_C(0x4)
30769 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_40GB UINT32_C(0x8)
30771 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB UINT32_C(0x10)
30773 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB UINT32_C(0x20)
30775 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 UINT32_C(0x40)
30777 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 UINT32_C(0x80)
30779 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 UINT32_C(0x100)
30781 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 UINT32_C(0x200)
30783 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 UINT32_C(0x400)
30785 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 UINT32_C(0x800)
30787 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 UINT32_C(0x1000)
30789 #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 UINT32_C(0x2000)
30824 * * 0x0-0xFFF8 - The function ID
30825 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30826 * * 0xFFFD - Reserved for user-space HWRM interface
30827 * * 0xFFFF - HWRM
30843 #define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET UINT32_C(0x1)
30848 #define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_BANK_NUMBER UINT32_C(0x2)
30915 * * 0x0-0xFFF8 - The function ID
30916 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
30917 * * 0xFFFD - Reserved for user-space HWRM interface
30918 * * 0xFFFF - HWRM
30934 #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET UINT32_C(0x1)
30939 #define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_BANK_NUMBER UINT32_C(0x2)
31006 * * 0x0-0xFFF8 - The function ID
31007 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31008 * * 0xFFFD - Reserved for user-space HWRM interface
31009 * * 0xFFFF - HWRM
31023 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
31033 * when this bit is set to 0 a Clause 22 mdio access is done.
31085 * * 0x0-0xFFF8 - The function ID
31086 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31087 * * 0xFFFD - Reserved for user-space HWRM interface
31088 * * 0xFFFF - HWRM
31102 /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
31110 * when this bit is set to 0 a Clause 22 mdio access is done.
31164 * * 0x0-0xFFF8 - The function ID
31165 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31166 * * 0xFFFD - Reserved for user-space HWRM interface
31167 * * 0xFFFF - HWRM
31182 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID UINT32_C(0x1)
31187 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE UINT32_C(0x2)
31192 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR UINT32_C(0x4)
31197 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON UINT32_C(0x8)
31202 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF UINT32_C(0x10)
31207 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID UINT32_C(0x20)
31212 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID UINT32_C(0x40)
31217 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE UINT32_C(0x80)
31222 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR UINT32_C(0x100)
31227 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON UINT32_C(0x200)
31232 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF UINT32_C(0x400)
31237 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID UINT32_C(0x800)
31242 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID UINT32_C(0x1000)
31247 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE UINT32_C(0x2000)
31252 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR UINT32_C(0x4000)
31257 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON UINT32_C(0x8000)
31262 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF UINT32_C(0x10000)
31267 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID UINT32_C(0x20000)
31272 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID UINT32_C(0x40000)
31277 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE UINT32_C(0x80000)
31282 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR UINT32_C(0x100000)
31287 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON UINT32_C(0x200000)
31292 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF UINT32_C(0x400000)
31297 #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID UINT32_C(0x800000)
31307 /* An identifier for the LED #0. */
31309 /* The requested state of the LED #0. */
31312 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
31314 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)
31316 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)
31318 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)
31320 #define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
31322 /* The requested color of LED #0. */
31325 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
31327 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)
31329 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)
31331 #define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
31335 * If the LED #0 state is "blink" or "blinkalt", then
31341 * If the LED #0 state is "blink" or "blinkalt", then
31347 * An identifier for the group of LEDs that LED #0 belongs
31349 * If set to 0, then the LED #0 shall not be grouped and
31351 * For all other non-zero values of this field, LED #0 shall
31363 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
31365 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)
31367 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)
31369 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)
31371 #define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
31376 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
31378 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)
31380 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)
31382 #define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
31400 * If set to 0, then the LED #1 shall not be grouped and
31414 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
31416 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)
31418 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)
31420 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)
31422 #define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
31427 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
31429 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)
31431 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)
31433 #define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
31451 * If set to 0, then the LED #2 shall not be grouped and
31465 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
31467 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)
31469 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)
31471 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)
31473 #define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
31478 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
31480 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)
31482 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)
31484 #define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
31502 * If set to 0, then the LED #3 shall not be grouped and
31558 * * 0x0-0xFFF8 - The function ID
31559 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31560 * * 0xFFFD - Reserved for user-space HWRM interface
31561 * * 0xFFFF - HWRM
31592 /* An identifier for the LED #0. */
31594 /* The type of LED #0. */
31597 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
31599 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
31601 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
31603 /* The current state of the LED #0. */
31606 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)
31608 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)
31610 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)
31612 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)
31614 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)
31616 /* The color of LED #0. */
31619 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)
31621 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)
31623 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)
31625 #define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)
31629 * If the LED #0 state is "blink" or "blinkalt", then
31635 * If the LED #0 state is "blink" or "blinkalt", then
31641 * An identifier for the group of LEDs that LED #0 belongs
31643 * If set to 0, then the LED #0 is not grouped.
31644 * For all other non-zero values of this field, LED #0 is
31654 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
31656 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
31658 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
31663 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)
31665 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)
31667 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)
31669 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)
31671 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)
31676 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)
31678 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)
31680 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)
31682 #define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)
31700 * If set to 0, then the LED #1 is not grouped.
31711 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
31713 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
31715 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
31720 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)
31722 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)
31724 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)
31726 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)
31728 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)
31733 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)
31735 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)
31737 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)
31739 #define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)
31757 * If set to 0, then the LED #2 is not grouped.
31768 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
31770 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
31772 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
31777 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)
31779 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)
31781 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)
31783 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)
31785 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)
31790 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)
31792 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)
31794 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)
31796 #define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)
31814 * If set to 0, then the LED #3 is not grouped.
31854 * * 0x0-0xFFF8 - The function ID
31855 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
31856 * * 0xFFFD - Reserved for user-space HWRM interface
31857 * * 0xFFFF - HWRM
31890 /* An identifier for the LED #0. */
31892 /* The type of LED #0. */
31895 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)
31897 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)
31899 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)
31902 * An identifier for the group of LEDs that LED #0 belongs
31904 * If set to 0, then the LED #0 cannot be grouped.
31905 * For all other non-zero values of this field, LED #0 is
31911 /* The states supported by LED #0. */
31915 * If set to 0, this LED is disabled.
31917 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED UINT32_C(0x1)
31920 * If set to 0, off state is not supported on this LED.
31922 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
31925 * If set to 0, on state is not supported on this LED.
31927 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
31930 * If set to 0, blink state is not supported on this LED.
31932 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
31935 * If set to 0, blink_alt state is not supported on this LED.
31937 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
31938 /* The colors supported by LED #0. */
31941 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD UINT32_C(0x1)
31944 * If set to 0, Amber color is not supported on this LED.
31946 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
31949 * If set to 0, Green color is not supported on this LED.
31951 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
31957 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)
31959 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)
31961 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)
31966 * If set to 0, then the LED #0 cannot be grouped.
31967 * For all other non-zero values of this field, LED #0 is
31977 * If set to 0, this LED is disabled.
31979 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED UINT32_C(0x1)
31982 * If set to 0, off state is not supported on this LED.
31984 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
31987 * If set to 0, on state is not supported on this LED.
31989 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
31992 * If set to 0, blink state is not supported on this LED.
31994 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
31997 * If set to 0, blink_alt state is not supported on this LED.
31999 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
32003 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD UINT32_C(0x1)
32006 * If set to 0, Amber color is not supported on this LED.
32008 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
32011 * If set to 0, Green color is not supported on this LED.
32013 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
32019 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)
32021 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)
32023 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)
32026 * An identifier for the group of LEDs that LED #0 belongs
32028 * If set to 0, then the LED #0 cannot be grouped.
32029 * For all other non-zero values of this field, LED #0 is
32039 * If set to 0, this LED is disabled.
32041 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED UINT32_C(0x1)
32044 * If set to 0, off state is not supported on this LED.
32046 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
32049 * If set to 0, on state is not supported on this LED.
32051 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
32054 * If set to 0, blink state is not supported on this LED.
32056 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
32059 * If set to 0, blink_alt state is not supported on this LED.
32061 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
32065 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD UINT32_C(0x1)
32068 * If set to 0, Amber color is not supported on this LED.
32070 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
32073 * If set to 0, Green color is not supported on this LED.
32075 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
32081 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)
32083 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)
32085 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)
32090 * If set to 0, then the LED #0 cannot be grouped.
32091 * For all other non-zero values of this field, LED #0 is
32101 * If set to 0, this LED is disabled.
32103 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED UINT32_C(0x1)
32106 * If set to 0, off state is not supported on this LED.
32108 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED UINT32_C(0x2)
32111 * If set to 0, on state is not supported on this LED.
32113 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED UINT32_C(0x4)
32116 * If set to 0, blink state is not supported on this LED.
32118 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED UINT32_C(0x8)
32121 * If set to 0, blink_alt state is not supported on this LED.
32123 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED UINT32_C(0x10)
32127 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD UINT32_C(0x1)
32130 * If set to 0, Amber color is not supported on this LED.
32132 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED UINT32_C(0x2)
32135 * If set to 0, Green color is not supported on this LED.
32137 #define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED UINT32_C(0x4)
32172 * * 0x0-0xFFF8 - The function ID
32173 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32174 * * 0xFFFD - Reserved for user-space HWRM interface
32175 * * 0xFFFF - HWRM
32199 #define HWRM_PORT_PRBS_TEST_INPUT_FLAGS_INTERNAL UINT32_C(0x1)
32206 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
32208 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
32210 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
32212 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
32214 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
32216 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
32218 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
32220 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS49 UINT32_C(0x7)
32222 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS10 UINT32_C(0x8)
32224 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS20 UINT32_C(0x9)
32226 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS13 UINT32_C(0xa)
32228 #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
32234 * if set to 0 test will be run on all lanes.
32238 * Set 0 to stop test currently in progress
32241 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP UINT32_C(0x1)
32244 * If set to 0, test will be run on all lanes for this port.
32246 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID UINT32_C(0x2)
32249 * If set to 0, test will be run on all lanes for this port.
32251 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID UINT32_C(0x4)
32252 /* If set to 1, FEC stat t-code 0-7 registers are enabled. */
32253 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T0_T7 UINT32_C(0x8)
32258 #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T8_T15 UINT32_C(0x10)
32291 #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_PRBS UINT32_C(0x0)
32293 #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC UINT32_C(0x1)
32330 * * 0x0-0xFFF8 - The function ID
32331 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32332 * * 0xFFFD - Reserved for user-space HWRM interface
32333 * * 0xFFFF - HWRM
32365 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE UINT32_C(0x0)
32367 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_CORE UINT32_C(0x1)
32369 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT UINT32_C(0x2)
32371 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EYE UINT32_C(0x3)
32373 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_CORE UINT32_C(0x4)
32375 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_REG_LANE UINT32_C(0x5)
32377 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_CORE UINT32_C(0x6)
32379 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_UC_LANE UINT32_C(0x7)
32381 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_LANE_DEBUG UINT32_C(0x8)
32383 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_VERT UINT32_C(0x9)
32385 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_BER_HORZ UINT32_C(0xa)
32387 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_EVENT_SAFE UINT32_C(0xb)
32389 #define HWRM_PORT_DSC_DUMP_INPUT_DIAG_LEVEL_SRDS_DIAG_TIMESTAMP UINT32_C(0xc)
32393 * If this is 0xFFFF, the dsc dump will be collected for all lanes,
32400 * Set 0 to retrieve the dsc dump
32406 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_START_RETRIEVE UINT32_C(0x1)
32408 * Set 0 to limit the report size to 65535 bytes.
32411 * If this is set 0 in the start operation, the firmware will
32421 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_BIG_BUFFER UINT32_C(0x2)
32423 * Set 0 on the last 'retrieve' to release the firmware buffer
32433 #define HWRM_PORT_DSC_DUMP_INPUT_DSC_DUMP_CONFIG_DEFER_CLOSE UINT32_C(0x4)
32484 #define HWRM_PORT_DSC_DUMP_OUTPUT_FLAGS_BIG_BUFFER UINT32_C(0x1)
32518 * * 0x0-0xFFF8 - The function ID
32519 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32520 * * 0xFFFD - Reserved for user-space HWRM interface
32521 * * 0xFFFF - HWRM
32540 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS0 UINT32_C(0x1)
32542 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RS1 UINT32_C(0x2)
32544 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_TX_DIS UINT32_C(0x4)
32549 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_MOD_SEL UINT32_C(0x8)
32551 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_RESET_L UINT32_C(0x10)
32553 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_LP_MODE UINT32_C(0x20)
32555 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_ENABLES_PWR_DIS UINT32_C(0x40)
32567 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS0 UINT32_C(0x1)
32573 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RS1 UINT32_C(0x2)
32579 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_TX_DIS UINT32_C(0x4)
32584 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_MOD_SEL UINT32_C(0x8)
32586 * If reset_l is set to 0, Module will be taken out of reset
32591 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_RESET_L UINT32_C(0x10)
32597 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_LP_MODE UINT32_C(0x20)
32599 #define HWRM_PORT_SFP_SIDEBAND_CFG_INPUT_FLAGS_PWR_DIS UINT32_C(0x40)
32647 * * 0x0-0xFFF8 - The function ID
32648 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32649 * * 0xFFFD - Reserved for user-space HWRM interface
32650 * * 0xFFFF - HWRM
32683 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_ABS UINT32_C(0x1)
32688 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RX_LOS UINT32_C(0x2)
32694 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS0 UINT32_C(0x4)
32700 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RS1 UINT32_C(0x8)
32706 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_DIS UINT32_C(0x10)
32708 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_TX_FAULT UINT32_C(0x20)
32713 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_MOD_SEL UINT32_C(0x40)
32715 * When this bit is set to '0', the module is held in reset.
32720 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_RESET_L UINT32_C(0x80)
32725 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_LP_MODE UINT32_C(0x100)
32727 #define HWRM_PORT_SFP_SIDEBAND_QCFG_OUTPUT_SIDEBAND_SIGNALS_PWR_DIS UINT32_C(0x200)
32762 * * 0x0-0xFFF8 - The function ID
32763 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32764 * * 0xFFFD - Reserved for user-space HWRM interface
32765 * * 0xFFFF - HWRM
32779 * Any value from 0x10 to 0xFFFF can be used.
32782 * 0-0xF are reserved for internal use.
32789 * A 0xFFFF will hold the bus until this bus is released.
32809 * 0-0xF are reserved for internal use.
32846 * * 0x0-0xFFF8 - The function ID
32847 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32848 * * 0xFFFD - Reserved for user-space HWRM interface
32849 * * 0xFFFF - HWRM
32917 * * 0x0-0xFFF8 - The function ID
32918 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
32919 * * 0xFFFD - Reserved for user-space HWRM interface
32920 * * 0xFFFF - HWRM
32933 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
32935 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
32937 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_NRZ UINT32_C(0x2)
32939 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_PAM4 UINT32_C(0x3)
32941 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_PAM4_112 UINT32_C(0x4)
32943 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_C2M_PAM4_112G UINT32_C(0x5)
32945 #define HWRM_PORT_TX_FIR_CFG_INPUT_MOD_TYPE_LPO_PAM4_112G UINT32_C(0x6)
33006 * * 0x0-0xFFF8 - The function ID
33007 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33008 * * 0xFFFD - Reserved for user-space HWRM interface
33009 * * 0xFFFF - HWRM
33022 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_NRZ UINT32_C(0x0)
33024 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4 UINT32_C(0x1)
33026 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_NRZ UINT32_C(0x2)
33028 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_PAM4 UINT32_C(0x3)
33030 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_PAM4_112 UINT32_C(0x4)
33032 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_C2M_PAM4_112 UINT32_C(0x5)
33034 #define HWRM_PORT_TX_FIR_QCFG_INPUT_MOD_TYPE_LPO_PAM4_112 UINT32_C(0x6)
33094 * * 0x0-0xFFF8 - The function ID
33095 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33096 * * 0xFFFD - Reserved for user-space HWRM interface
33097 * * 0xFFFF - HWRM
33109 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MIN_BW UINT32_C(0x1)
33111 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP0_MAX_BW UINT32_C(0x2)
33113 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MIN_BW UINT32_C(0x4)
33115 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP1_MAX_BW UINT32_C(0x8)
33117 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MIN_BW UINT32_C(0x10)
33119 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP2_MAX_BW UINT32_C(0x20)
33121 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MIN_BW UINT32_C(0x40)
33123 #define HWRM_PORT_EP_TX_CFG_INPUT_ENABLES_EP3_MAX_BW UINT32_C(0x80)
33124 /* A port index, from 0 to the number of front panel ports, minus 1. */
33129 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
33130 * the specified port. The range is 0 to 100. A value of 0 indicates no
33138 * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
33139 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33146 * the specified port. The range is 0 to 100. A value of 0 indicates no
33155 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33162 * the specified port. The range is 0 to 100. A value of 0 indicates no
33171 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33178 * the specified port. The range is 0 to 100. A value of 0 indicates no
33187 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33226 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
33228 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_PORT_ID_INVALID UINT32_C(0x1)
33230 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_EP_INACTIVE UINT32_C(0x2)
33232 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_RANGE UINT32_C(0x3)
33237 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_MORE_THAN_MAX UINT32_C(0x4)
33239 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_SUM UINT32_C(0x5)
33244 #define HWRM_PORT_EP_TX_CFG_CMD_ERR_CODE_MIN_BW_UNSUPPORTED UINT32_C(0x6)
33272 * * 0x0-0xFFF8 - The function ID
33273 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33274 * * 0xFFFD - Reserved for user-space HWRM interface
33275 * * 0xFFFF - HWRM
33303 * port bandwidth, for the set of PFs and VFs on PCIe endpoint 0 for
33304 * the specified port. The range is 0 to 100. A value of 0 indicates no
33312 * of PFs and VFs on PCIe endpoint 0 may use. The value is a percentage
33313 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33320 * the specified port. The range is 0 to 100. A value of 0 indicates no
33329 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33336 * the specified port. The range is 0 to 100. A value of 0 indicates no
33345 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33352 * the specified port. The range is 0 to 100. A value of 0 indicates no
33361 * of the link bandwidth, from 0 to 100. A value of 0 indicates no
33400 * * 0x0-0xFFF8 - The function ID
33401 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33402 * * 0xFFFD - Reserved for user-space HWRM interface
33403 * * 0xFFFF - HWRM
33419 #define HWRM_PORT_CFG_INPUT_ENABLES_TX_RATE_LIMIT UINT32_C(0x1)
33425 * tx_rate_limit = 0 will cancel the rate limit if any.
33477 * * 0x0-0xFFF8 - The function ID
33478 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33479 * * 0xFFFD - Reserved for user-space HWRM interface
33480 * * 0xFFFF - HWRM
33511 #define HWRM_PORT_QCFG_OUTPUT_SUPPORTED_TX_RATE_LIMIT UINT32_C(0x1)
33517 #define HWRM_PORT_QCFG_OUTPUT_ENABLED_TX_RATE_LIMIT UINT32_C(0x1)
33558 * * 0x0-0xFFF8 - The function ID
33559 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33560 * * 0xFFFD - Reserved for user-space HWRM interface
33561 * * 0xFFFF - HWRM
33593 #define HWRM_PORT_MAC_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED UINT32_C(0x1)
33598 #define HWRM_PORT_MAC_QCAPS_OUTPUT_FLAGS_REMOTE_LPBK_SUPPORTED UINT32_C(0x2)
33633 * * 0x0-0xFFF8 - The function ID
33634 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
33635 * * 0xFFFD - Reserved for user-space HWRM interface
33636 * * 0xFFFF - HWRM
33652 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
33654 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
33656 #define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
33669 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)
33671 #define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)
33696 * Valid values range from 0 through 8.
33703 * Each bit represents a specific queue where bit 0 represents
33704 * queue 0 and bit 7 represents queue 7.
33705 * # A value of 0 indicates that the queue is not configurable
33717 * If this flag is set to '0', then the queues are
33724 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
33730 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_USE_PROFILE_TYPE UINT32_C(0x2)
33735 * Each bit represents a specific priority where bit 0 represents
33736 * priority 0 and bit 7 represents priority 7.
33737 * # A value of 0 indicates that the priority is not configurable by
33748 * Each bit represents a specific queue where bit 0 represents
33749 * queue 0 and bit 7 represents queue 7.
33750 * # A value of 0 indicates that the queue is not configurable
33761 * Each bit represents a specific queue where bit 0 represents
33762 * queue 0 and bit 7 represents queue 7.
33763 * # A value of 0 indicates that the queue is not configurable
33771 * ID of CoS Queue 0.
33779 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
33782 * # A value of 0xff indicates that the queue is not available.
33789 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
33791 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
33793 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
33795 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
33797 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
33798 /* Set to 0xFF... (All Fs) if there is no service profile specified */
33799 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
33810 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
33813 * # A value of 0xff indicates that the queue is not available.
33820 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
33822 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
33824 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
33826 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
33828 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
33829 /* Set to 0xFF... (All Fs) if there is no service profile specified */
33830 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
33841 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
33844 * # A value of 0xff indicates that the queue is not available.
33851 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
33853 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
33855 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
33857 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
33859 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
33860 /* Set to 0xFF... (All Fs) if there is no service profile specified */
33861 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
33872 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
33875 * # A value of 0xff indicates that the queue is not available.
33882 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
33884 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
33886 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
33888 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
33890 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
33891 /* Set to 0xFF... (All Fs) if there is no service profile specified */
33892 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
33903 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
33906 * # A value of 0xff indicates that the queue is not available.
33913 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
33915 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
33917 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
33919 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
33921 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
33922 /* Set to 0xFF... (All Fs) if there is no service profile specified */
33923 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
33934 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
33937 * # A value of 0xff indicates that the queue is not available.
33944 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
33946 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
33948 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
33950 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
33952 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
33953 /* Set to 0xFF... (All Fs) if there is no service profile specified */
33954 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
33965 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
33968 * # A value of 0xff indicates that the queue is not available.
33975 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
33977 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
33979 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
33981 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
33983 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
33984 /* Set to 0xFF... (All Fs) if there is no service profile specified */
33985 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
33996 * CoS queue ID. Valid CoS queue indexes are in the range of 0 to 7.
33999 * # A value of 0xff indicates that the queue is not available.
34006 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
34008 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
34010 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE UINT32_C(0x1)
34012 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP UINT32_C(0x2)
34014 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC UINT32_C(0x3)
34015 /* Set to 0xFF... (All Fs) if there is no service profile specified */
34016 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
34021 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34026 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
34028 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
34030 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
34054 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34059 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
34061 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
34063 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
34067 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34072 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
34074 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
34076 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
34080 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34085 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
34087 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
34089 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
34093 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34098 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
34100 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
34102 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
34106 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34111 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
34113 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
34115 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
34119 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34124 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
34126 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
34128 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
34132 * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).
34137 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE UINT32_C(0x1)
34139 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC UINT32_C(0x2)
34141 #define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP UINT32_C(0x4)
34175 * * 0x0-0xFFF8 - The function ID
34176 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34177 * * 0xFFFD - Reserved for user-space HWRM interface
34178 * * 0xFFFF - HWRM
34194 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
34196 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
34198 #define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
34223 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
34225 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
34226 /* Set to 0xFF... (All Fs) if there is no service profile specified */
34227 #define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
34234 * If this flag is set to '0', then this queue is
34237 #define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
34272 * * 0x0-0xFFF8 - The function ID
34273 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34274 * * 0xFFFD - Reserved for user-space HWRM interface
34275 * * 0xFFFF - HWRM
34291 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
34292 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0
34294 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
34296 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
34298 #define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
34305 #define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)
34310 #define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)
34316 * Set to 0xFF... (All Fs) to not adjust this value.
34322 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)
34324 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)
34325 /* Set to 0xFF... (All Fs) if there is no service profile specified */
34326 #define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)
34376 * * 0x0-0xFFF8 - The function ID
34377 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34378 * * 0xFFFD - Reserved for user-space HWRM interface
34379 * * 0xFFFF - HWRM
34410 /* If set to 1, then PFC is enabled on PRI 0. */
34411 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED UINT32_C(0x1)
34413 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED UINT32_C(0x2)
34415 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED UINT32_C(0x4)
34417 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED UINT32_C(0x8)
34419 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED UINT32_C(0x10)
34421 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED UINT32_C(0x20)
34423 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED UINT32_C(0x40)
34425 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED UINT32_C(0x80)
34427 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED UINT32_C(0x100)
34429 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED UINT32_C(0x200)
34431 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED UINT32_C(0x400)
34433 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED UINT32_C(0x800)
34435 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED UINT32_C(0x1000)
34437 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED UINT32_C(0x2000)
34439 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED UINT32_C(0x4000)
34441 #define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED UINT32_C(0x8000)
34476 * * 0x0-0xFFF8 - The function ID
34477 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34478 * * 0xFFFD - Reserved for user-space HWRM interface
34479 * * 0xFFFF - HWRM
34490 /* If set to 1, then PFC is requested to be enabled on PRI 0. */
34491 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED UINT32_C(0x1)
34493 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED UINT32_C(0x2)
34495 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED UINT32_C(0x4)
34497 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED UINT32_C(0x8)
34499 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED UINT32_C(0x10)
34501 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED UINT32_C(0x20)
34503 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED UINT32_C(0x40)
34505 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED UINT32_C(0x80)
34507 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_WATCHDOG_ENABLED UINT32_C(0x100)
34509 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_WATCHDOG_ENABLED UINT32_C(0x200)
34511 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_WATCHDOG_ENABLED UINT32_C(0x400)
34513 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_WATCHDOG_ENABLED UINT32_C(0x800)
34515 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_WATCHDOG_ENABLED UINT32_C(0x1000)
34517 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_WATCHDOG_ENABLED UINT32_C(0x2000)
34519 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_WATCHDOG_ENABLED UINT32_C(0x4000)
34521 #define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_WATCHDOG_ENABLED UINT32_C(0x8000)
34576 * * 0x0-0xFFF8 - The function ID
34577 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34578 * * 0xFFFD - Reserved for user-space HWRM interface
34579 * * 0xFFFF - HWRM
34595 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
34597 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
34599 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
34602 * When this bit is set to '0', the query is
34607 #define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)
34629 * CoS Queue assigned to priority 0. This value can only
34631 * A value of 0xff indicates that no CoS queue is assigned to the
34638 * A value of 0xff indicates that no CoS queue is assigned to the
34645 * A value of 0xff indicates that no CoS queue is assigned to the
34652 * A value of 0xff indicates that no CoS queue is assigned to the
34659 * A value of 0xff indicates that no CoS queue is assigned to the
34666 * A value of 0xff indicates that no CoS queue is assigned to the
34673 * A value of 0xff indicates that no CoS queue is assigned to the
34680 * A value of 0xff indicates that no CoS queue is assigned to the
34689 * If this flag is set to '0', then PRI to CoS configuration
34692 #define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG UINT32_C(0x1)
34727 * * 0x0-0xFFF8 - The function ID
34728 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34729 * * 0xFFFD - Reserved for user-space HWRM interface
34730 * * 0xFFFF - HWRM
34746 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)
34747 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0
34749 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
34751 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
34753 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)
34756 * When this bit is set to '0', the mapping is requested
34761 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)
34767 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID UINT32_C(0x1)
34772 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID UINT32_C(0x2)
34777 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID UINT32_C(0x4)
34782 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID UINT32_C(0x8)
34787 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID UINT32_C(0x10)
34792 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID UINT32_C(0x20)
34797 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID UINT32_C(0x40)
34802 #define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID UINT32_C(0x80)
34810 * CoS Queue assigned to priority 0. This value can only
34897 * * 0x0-0xFFF8 - The function ID
34898 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
34899 * * 0xFFFD - Reserved for user-space HWRM interface
34900 * * 0xFFFF - HWRM
34930 /* ID of CoS Queue 0. */
34941 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
34942 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
34944 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE UINT32_C(0x10000000)
34946 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
34948 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
34951 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
34954 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
34956 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
34958 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
34960 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
34962 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
34964 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
34973 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
34974 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
34976 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE UINT32_C(0x10000000)
34978 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
34980 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
34983 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
34986 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
34988 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
34990 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
34992 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
34994 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
34996 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35001 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP UINT32_C(0x0)
35003 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS UINT32_C(0x1)
35005 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35007 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35010 * tsa_assign is 0 - Strict Priority (SP)
35011 * 0..7 - Valid values.
35029 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35030 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
35032 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE UINT32_C(0x10000000)
35034 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35036 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35039 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35042 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35044 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35046 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35048 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35050 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35052 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35061 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35062 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
35064 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE UINT32_C(0x10000000)
35066 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35068 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35071 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35074 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35076 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35078 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35080 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35082 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35084 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35089 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP UINT32_C(0x0)
35091 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS UINT32_C(0x1)
35093 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35095 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35098 * tsa_assign is 0 - Strict Priority (SP)
35099 * 0..7 - Valid values.
35117 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35118 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
35120 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE UINT32_C(0x10000000)
35122 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35124 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35127 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35130 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35132 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35134 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35136 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35138 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35140 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35149 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35150 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
35152 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE UINT32_C(0x10000000)
35154 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35156 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35159 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35162 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35164 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35166 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35168 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35170 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35172 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35177 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP UINT32_C(0x0)
35179 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS UINT32_C(0x1)
35181 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35183 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35186 * tsa_assign is 0 - Strict Priority (SP)
35187 * 0..7 - Valid values.
35205 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35206 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
35208 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE UINT32_C(0x10000000)
35210 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35212 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35215 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35218 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35220 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35222 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35224 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35226 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35228 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35237 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35238 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
35240 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE UINT32_C(0x10000000)
35242 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35244 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35247 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35250 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35252 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35254 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35256 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35258 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35260 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35265 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP UINT32_C(0x0)
35267 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS UINT32_C(0x1)
35269 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35271 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35274 * tsa_assign is 0 - Strict Priority (SP)
35275 * 0..7 - Valid values.
35293 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35294 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
35296 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE UINT32_C(0x10000000)
35298 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35300 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35303 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35306 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35308 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35310 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35312 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35314 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35316 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35325 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35326 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
35328 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE UINT32_C(0x10000000)
35330 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35332 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35335 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35338 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35340 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35342 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35344 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35346 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35348 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35353 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP UINT32_C(0x0)
35355 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS UINT32_C(0x1)
35357 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35359 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35362 * tsa_assign is 0 - Strict Priority (SP)
35363 * 0..7 - Valid values.
35381 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35382 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
35384 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE UINT32_C(0x10000000)
35386 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35388 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35391 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35394 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35396 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35398 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35400 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35402 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35404 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35413 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35414 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
35416 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE UINT32_C(0x10000000)
35418 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35420 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35423 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35426 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35428 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35430 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35432 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35434 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35436 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35441 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP UINT32_C(0x0)
35443 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS UINT32_C(0x1)
35445 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35447 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35450 * tsa_assign is 0 - Strict Priority (SP)
35451 * 0..7 - Valid values.
35469 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35470 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
35472 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE UINT32_C(0x10000000)
35474 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35476 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35479 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35482 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35484 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35486 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35488 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35490 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35492 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35501 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35502 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
35504 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE UINT32_C(0x10000000)
35506 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35508 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35511 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35514 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35516 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35518 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35520 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35522 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35524 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35529 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP UINT32_C(0x0)
35531 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS UINT32_C(0x1)
35533 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35535 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35538 * tsa_assign is 0 - Strict Priority (SP)
35539 * 0..7 - Valid values.
35557 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35558 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
35560 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE UINT32_C(0x10000000)
35562 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35564 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35567 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35570 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35572 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35574 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35576 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35578 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35580 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35589 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35590 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
35592 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE UINT32_C(0x10000000)
35594 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35596 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35599 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35602 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35604 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35606 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35608 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35610 …#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
35612 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35617 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP UINT32_C(0x0)
35619 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS UINT32_C(0x1)
35621 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35623 #define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35626 * tsa_assign is 0 - Strict Priority (SP)
35627 * 0..7 - Valid values.
35670 * * 0x0-0xFFF8 - The function ID
35671 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
35672 * * 0xFFFD - Reserved for user-space HWRM interface
35673 * * 0xFFFF - HWRM
35689 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID UINT32_C(0x1)
35694 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID UINT32_C(0x2)
35699 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID UINT32_C(0x4)
35704 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID UINT32_C(0x8)
35709 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID UINT32_C(0x10)
35714 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID UINT32_C(0x20)
35719 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID UINT32_C(0x40)
35724 #define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID UINT32_C(0x80)
35731 /* ID of CoS Queue 0. */
35741 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35742 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0
35744 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE UINT32_C(0x10000000)
35746 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35748 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35751 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35754 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35756 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35758 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35760 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35762 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
35764 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35773 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35774 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0
35776 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE UINT32_C(0x10000000)
35778 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35780 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35783 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35786 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35788 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35790 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35792 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35794 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
35796 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35801 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP UINT32_C(0x0)
35803 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS UINT32_C(0x1)
35805 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35807 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35810 * tsa_assign is 0 - Strict Priority (SP)
35811 * 0..7 - Valid values.
35829 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35830 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0
35832 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE UINT32_C(0x10000000)
35834 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35836 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35839 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35842 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35844 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35846 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35848 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35850 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
35852 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35861 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35862 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0
35864 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE UINT32_C(0x10000000)
35866 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35868 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35871 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35874 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35876 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35878 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35880 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35882 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
35884 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35889 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP UINT32_C(0x0)
35891 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS UINT32_C(0x1)
35893 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35895 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35898 * tsa_assign is 0 - Strict Priority (SP)
35899 * 0..7 - Valid values.
35917 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35918 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0
35920 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE UINT32_C(0x10000000)
35922 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35924 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35927 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35930 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35932 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35934 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35936 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35938 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
35940 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35949 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
35950 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0
35952 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE UINT32_C(0x10000000)
35954 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
35956 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
35959 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
35962 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
35964 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
35966 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
35968 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
35970 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
35972 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
35977 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP UINT32_C(0x0)
35979 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS UINT32_C(0x1)
35981 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
35983 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
35986 * tsa_assign is 0 - Strict Priority (SP)
35987 * 0..7 - Valid values.
36005 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
36006 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0
36008 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE UINT32_C(0x10000000)
36010 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
36012 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
36015 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
36018 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
36020 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
36022 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
36024 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
36026 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
36028 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
36037 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
36038 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0
36040 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE UINT32_C(0x10000000)
36042 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
36044 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
36047 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
36050 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
36052 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
36054 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
36056 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
36058 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
36060 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
36065 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP UINT32_C(0x0)
36067 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS UINT32_C(0x1)
36069 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36071 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
36074 * tsa_assign is 0 - Strict Priority (SP)
36075 * 0..7 - Valid values.
36093 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
36094 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0
36096 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE UINT32_C(0x10000000)
36098 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
36100 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
36103 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
36106 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
36108 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
36110 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
36112 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
36114 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
36116 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
36125 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
36126 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0
36128 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE UINT32_C(0x10000000)
36130 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
36132 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
36135 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
36138 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
36140 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
36142 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
36144 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
36146 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
36148 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
36153 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP UINT32_C(0x0)
36155 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS UINT32_C(0x1)
36157 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36159 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
36162 * tsa_assign is 0 - Strict Priority (SP)
36163 * 0..7 - Valid values.
36181 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
36182 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0
36184 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE UINT32_C(0x10000000)
36186 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
36188 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
36191 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
36194 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
36196 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
36198 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
36200 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
36202 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
36204 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
36213 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
36214 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0
36216 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE UINT32_C(0x10000000)
36218 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
36220 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
36223 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
36226 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
36228 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
36230 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
36232 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
36234 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
36236 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
36241 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP UINT32_C(0x0)
36243 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS UINT32_C(0x1)
36245 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36247 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
36250 * tsa_assign is 0 - Strict Priority (SP)
36251 * 0..7 - Valid values.
36269 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
36270 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0
36272 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE UINT32_C(0x10000000)
36274 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
36276 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
36279 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
36282 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
36284 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
36286 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
36288 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
36290 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
36292 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
36301 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
36302 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0
36304 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE UINT32_C(0x10000000)
36306 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
36308 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
36311 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
36314 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
36316 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
36318 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
36320 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
36322 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
36324 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
36329 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP UINT32_C(0x0)
36331 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS UINT32_C(0x1)
36333 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36335 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
36338 * tsa_assign is 0 - Strict Priority (SP)
36339 * 0..7 - Valid values.
36357 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
36358 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0
36360 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE UINT32_C(0x10000000)
36362 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS (UINT32_C(0x0) << 28)
36364 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
36367 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
36370 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
36372 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
36374 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
36376 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
36378 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
36380 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
36389 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
36390 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0
36392 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE UINT32_C(0x10000000)
36394 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
36396 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
36399 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
36402 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
36404 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
36406 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
36408 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
36410 …#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
36412 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
36417 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP UINT32_C(0x0)
36419 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS UINT32_C(0x1)
36421 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST UINT32_C(0x2)
36423 #define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST UINT32_C(0xff)
36426 * tsa_assign is 0 - Strict Priority (SP)
36427 * 0..7 - Valid values.
36484 * * 0x0-0xFFF8 - The function ID
36485 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36486 * * 0xFFFD - Reserved for user-space HWRM interface
36487 * * 0xFFFF - HWRM
36556 * * 0x0-0xFFF8 - The function ID
36557 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36558 * * 0xFFFD - Reserved for user-space HWRM interface
36559 * * 0xFFFF - HWRM
36641 * * 0x0-0xFFF8 - The function ID
36642 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36643 * * 0xFFFD - Reserved for user-space HWRM interface
36644 * * 0xFFFF - HWRM
36657 * a mask equal to 0 triggers the firmware to remove a tuple.
36659 * prior to Thor a mask can be 0 - 0x3f, while on Thor it can
36660 * be 0 or 0x3f.
36665 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI UINT32_C(0x1)
36671 #define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI UINT32_C(0x1)
36736 * * 0x0-0xFFF8 - The function ID
36737 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36738 * * 0xFFFD - Reserved for user-space HWRM interface
36739 * * 0xFFFF - HWRM
36773 * Each bit represents a specific pri where bit 0 represents
36774 * pri 0 and bit 7 represents pri 7.
36775 * # A value of 0 indicates that the pri is not configurable
36821 * * 0x0-0xFFF8 - The function ID
36822 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36823 * * 0xFFFD - Reserved for user-space HWRM interface
36824 * * 0xFFFF - HWRM
36855 * pri assigned to MPLS TC(EXP) 0. This value can only be changed
36857 * A value of 0xff indicates that no pri is assigned to the
36858 * MPLS TC(EXP) 0.
36864 * A value of 0xff indicates that no pri is assigned to the
36871 * A value of 0xff indicates that no pri is assigned to the
36878 * A value of 0xff indicates that no pri is assigned to the
36885 * A value of 0xff indicates that no pri is assigned to the
36892 * A value of 0xff indicates that no pri is assigned to the
36899 * A value of 0xff indicates that no pri is assigned to the
36906 * A value of 0xff indicates that no pri is assigned to the
36944 * * 0x0-0xFFF8 - The function ID
36945 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
36946 * * 0xFFFD - Reserved for user-space HWRM interface
36947 * * 0xFFFF - HWRM
36962 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID UINT32_C(0x1)
36967 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID UINT32_C(0x2)
36972 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID UINT32_C(0x4)
36977 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID UINT32_C(0x8)
36982 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID UINT32_C(0x10)
36987 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID UINT32_C(0x20)
36992 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID UINT32_C(0x40)
36997 #define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID UINT32_C(0x80)
37006 * pri assigned to MPLS TC(EXP) 0. This value can only
37092 * * 0x0-0xFFF8 - The function ID
37093 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37094 * * 0xFFFD - Reserved for user-space HWRM interface
37095 * * 0xFFFF - HWRM
37164 * * 0x0-0xFFF8 - The function ID
37165 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37166 * * 0xFFFD - Reserved for user-space HWRM interface
37167 * * 0xFFFF - HWRM
37198 * User priority assigned to VLAN priority 0. A value of 0xff
37204 * User priority assigned to VLAN priority 1. A value of 0xff
37210 * User priority assigned to VLAN priority 2. A value of 0xff
37216 * User priority assigned to VLAN priority 3. A value of 0xff
37222 * User priority assigned to VLAN priority 4. A value of 0xff
37228 * User priority assigned to VLAN priority 5. A value of 0xff
37234 * User priority assigned to VLAN priority 6. A value of 0xff
37240 * User priority assigned to VLAN priority 7. A value of 0xff
37279 * * 0x0-0xFFF8 - The function ID
37280 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37281 * * 0xFFFD - Reserved for user-space HWRM interface
37282 * * 0xFFFF - HWRM
37297 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID UINT32_C(0x1)
37302 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID UINT32_C(0x2)
37307 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID UINT32_C(0x4)
37312 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID UINT32_C(0x8)
37317 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID UINT32_C(0x10)
37322 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID UINT32_C(0x20)
37327 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID UINT32_C(0x40)
37332 #define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID UINT32_C(0x80)
37341 * User priority assigned to VLAN priority 0. This value can only
37427 * * 0x0-0xFFF8 - The function ID
37428 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37429 * * 0xFFFD - Reserved for user-space HWRM interface
37430 * * 0xFFFF - HWRM
37447 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_SHARED UINT32_C(0x0)
37452 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_MODE_INDEPENDENT UINT32_C(0x1)
37457 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_MODE UINT32_C(0x1)
37459 * This bit must be '1' when the maximum bandwidth for queue group 0
37462 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G0_MAX_BW UINT32_C(0x2)
37467 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G1_MAX_BW UINT32_C(0x4)
37472 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G2_MAX_BW UINT32_C(0x8)
37477 #define HWRM_QUEUE_GLOBAL_CFG_INPUT_ENABLES_G3_MAX_BW UINT32_C(0x10)
37480 * bandwidth, of the receive traffic through queue group 0. A value
37481 * of 0 indicates no rate limit.
37486 * through port 0. In multi-root or multi-host mode, each PCIe endpoint
37489 * endpoints, in this case endpoint 0.
37496 * value of 0 indicates no rate limit.
37503 * value of 0 indicates no rate limit.
37508 * through queue group 3 (for port 3 or PCIe endpoint 3). A value of 0
37559 * * 0x0-0xFFF8 - The function ID
37560 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37561 * * 0xFFFD - Reserved for user-space HWRM interface
37562 * * 0xFFFF - HWRM
37585 /* Port or PCIe endpoint id to be mapped for buffer pool 0. */
37593 /* Size of buffer pool 0 (KBytes). */
37606 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING UINT32_C(0x1)
37608 * The buffer_pool_id[0-3]_map field represents mapping of rx
37611 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_PORT UINT32_C(0x0)
37613 * The buffer_pool_id[0-3]_map field represents mapping of rx
37616 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_FLAGS_MAPPING_MAPPING_PER_ENDPOINT UINT32_C(0x1)
37625 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_SHARED UINT32_C(0x0)
37630 #define HWRM_QUEUE_GLOBAL_QCFG_OUTPUT_MODE_INDEPENDENT UINT32_C(0x1)
37635 * group 0. The rate limit is a percentage of total link bandwidth. A
37636 * value of 0 indicates no rate limit.
37641 * through port 0. In multi-root or multi-host mode, each PCIe endpoint
37644 * endpoints, in this case endpoint 0.
37650 * percentage of total link bandwidth. A value of 0 indicates no rate
37657 * percentage of total link bandwidth. A value of 0 indicates no rate
37664 * percentage of total link bandwidth. A value of 0 indicates no rate
37702 * * 0x0-0xFFF8 - The function ID
37703 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37704 * * 0xFFFD - Reserved for user-space HWRM interface
37705 * * 0xFFFF - HWRM
37731 * Each bit represents a specific queue where bit 0 represents
37732 * queue 0 and bit 7 represents queue 7.
37733 * A value of 0 indicates that the queue is not enabled.
37738 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1)
37740 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x…
37742 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x…
37745 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2)
37747 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1)
37749 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1)
37752 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4)
37754 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2)
37756 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2)
37759 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8)
37761 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3)
37763 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3)
37766 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10)
37768 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4)
37770 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4)
37773 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20)
37775 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5)
37777 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5)
37780 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40)
37782 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6)
37784 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6)
37787 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80)
37789 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7)
37791 …HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7)
37797 * where bit 0 represents queue 0 and bit 7 represents queue 7.
37798 * A value of 0 indicates that the queue is lossy.
37802 /* If set to 0, then the queue is lossy, else lossless. */
37803 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE UINT32_C(0x1)
37805 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSY UINT32_C(0x0)
37807 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID0_MODE_LOSSLESS UINT32_C(0x1)
37809 /* If set to 0, then the queue is lossy, else lossless. */
37810 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE UINT32_C(0x2)
37812 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSY (UINT32_C(0x0) << 1)
37814 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID1_MODE_LOSSLESS (UINT32_C(0x1) …
37816 /* If set to 0, then the queue is lossy, else lossless. */
37817 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE UINT32_C(0x4)
37819 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSY (UINT32_C(0x0) << 2)
37821 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID2_MODE_LOSSLESS (UINT32_C(0x1) …
37823 /* If set to 0, then the queue is lossy, else lossless. */
37824 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE UINT32_C(0x8)
37826 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSY (UINT32_C(0x0) << 3)
37828 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID3_MODE_LOSSLESS (UINT32_C(0x1) …
37830 /* If set to 0, then the queue is lossy, else lossless. */
37831 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE UINT32_C(0x10)
37833 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSY (UINT32_C(0x0) << 4)
37835 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID4_MODE_LOSSLESS (UINT32_C(0x1) …
37837 /* If set to 0, then the queue is lossy, else lossless. */
37838 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE UINT32_C(0x20)
37840 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSY (UINT32_C(0x0) << 5)
37842 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID5_MODE_LOSSLESS (UINT32_C(0x1) …
37844 /* If set to 0, then the queue is lossy, else lossless. */
37845 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE UINT32_C(0x40)
37847 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSY (UINT32_C(0x0) << 6)
37849 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID6_MODE_LOSSLESS (UINT32_C(0x1) …
37851 /* If set to 0, then the queue is lossy, else lossless. */
37852 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE UINT32_C(0x80)
37854 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSY (UINT32_C(0x0) << 7)
37856 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG_OUTPUT_QUEUE_MODE_QID7_MODE_LOSSLESS (UINT32_C(0x1) …
37892 * * 0x0-0xFFF8 - The function ID
37893 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
37894 * * 0xFFFD - Reserved for user-space HWRM interface
37895 * * 0xFFFF - HWRM
37907 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_ENABLES_QUEUE_ENABLE UINT32_C(0x1)
37909 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_ENABLES_QUEUE_MODE UINT32_C(0x2)
37913 * Each bit represents a specific queue where bit 0 represents
37914 * queue 0 and bit 7 represents queue 7.
37915 * A value of 0 indicates that the queue is not enabled.
37920 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1)
37922 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0)
37924 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1)
37927 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2)
37929 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0…
37931 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1…
37934 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4)
37936 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0…
37938 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1…
37941 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8)
37943 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0…
37945 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1…
37948 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10)
37950 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0…
37952 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1…
37955 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20)
37957 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0…
37959 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1…
37962 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40)
37964 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0…
37966 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1…
37969 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80)
37971 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0…
37973 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1…
37978 * Each bit represents a specific queue where bit 0 represents
37979 * queue 0 and bit 7 represents queue 7.
37980 * A value of 0 indicates that the queue is lossy.
37984 /* If set to 0, then the queue is lossy, else lossless. */
37985 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE UINT32_C(0x1)
37987 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSY UINT32_C(0x0)
37989 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID0_MODE_LOSSLESS UINT32_C(0x1)
37991 /* If set to 0, then the queue is lossy, else lossless. */
37992 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE UINT32_C(0x2)
37994 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSY (UINT32_C(0x0) << 1)
37996 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID1_MODE_LOSSLESS (UINT32_C(0x1) <<…
37998 /* If set to 0, then the queue is lossy, else lossless. */
37999 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE UINT32_C(0x4)
38001 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSY (UINT32_C(0x0) << 2)
38003 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID2_MODE_LOSSLESS (UINT32_C(0x1) <<…
38005 /* If set to 0, then the queue is lossy, else lossless. */
38006 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE UINT32_C(0x8)
38008 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSY (UINT32_C(0x0) << 3)
38010 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID3_MODE_LOSSLESS (UINT32_C(0x1) <<…
38012 /* If set to 0, then the queue is lossy, else lossless. */
38013 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE UINT32_C(0x10)
38015 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSY (UINT32_C(0x0) << 4)
38017 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID4_MODE_LOSSLESS (UINT32_C(0x1) <<…
38019 /* If set to 0, then the queue is lossy, else lossless. */
38020 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE UINT32_C(0x20)
38022 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSY (UINT32_C(0x0) << 5)
38024 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID5_MODE_LOSSLESS (UINT32_C(0x1) <<…
38026 /* If set to 0, then the queue is lossy, else lossless. */
38027 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE UINT32_C(0x40)
38029 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSY (UINT32_C(0x0) << 6)
38031 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID6_MODE_LOSSLESS (UINT32_C(0x1) <<…
38033 /* If set to 0, then the queue is lossy, else lossless. */
38034 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE UINT32_C(0x80)
38036 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSY (UINT32_C(0x0) << 7)
38038 …#define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG_INPUT_QUEUE_MODE_QID7_MODE_LOSSLESS (UINT32_C(0x1) <<…
38088 * * 0x0-0xFFF8 - The function ID
38089 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38090 * * 0xFFFD - Reserved for user-space HWRM interface
38091 * * 0xFFFF - HWRM
38117 * Each bit represents a specific queue where bit 0 represents
38118 * queue 0 and bit 7 represents queue 7.
38119 * A value of 0 indicates that the queue is not enabled.
38124 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1)
38126 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x…
38128 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x…
38131 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2)
38133 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0) << 1)
38135 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1) << 1)
38138 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4)
38140 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0) << 2)
38142 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1) << 2)
38145 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8)
38147 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0) << 3)
38149 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1) << 3)
38152 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10)
38154 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0) << 4)
38156 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1) << 4)
38159 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20)
38161 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0) << 5)
38163 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1) << 5)
38166 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40)
38168 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0) << 6)
38170 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1) << 6)
38173 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80)
38175 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0) << 7)
38177 …HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG_OUTPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1) << 7)
38213 * * 0x0-0xFFF8 - The function ID
38214 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38215 * * 0xFFFD - Reserved for user-space HWRM interface
38216 * * 0xFFFF - HWRM
38228 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_ENABLES_QUEUE_ENABLE UINT32_C(0x1)
38232 * Each bit represents a specific queue where bit 0 represents
38233 * queue 0 and bit 7 represents queue 7.
38234 * A value of 0 indicates that the queue is not enabled.
38239 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE UINT32_C(0x1)
38241 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_DISABLED UINT32_C(0x0)
38243 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID0_ENABLE_ENABLED UINT32_C(0x1)
38246 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE UINT32_C(0x2)
38248 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_DISABLED (UINT32_C(0x0…
38250 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID1_ENABLE_ENABLED (UINT32_C(0x1…
38253 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE UINT32_C(0x4)
38255 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_DISABLED (UINT32_C(0x0…
38257 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID2_ENABLE_ENABLED (UINT32_C(0x1…
38260 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE UINT32_C(0x8)
38262 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_DISABLED (UINT32_C(0x0…
38264 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID3_ENABLE_ENABLED (UINT32_C(0x1…
38267 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE UINT32_C(0x10)
38269 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_DISABLED (UINT32_C(0x0…
38271 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID4_ENABLE_ENABLED (UINT32_C(0x1…
38274 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE UINT32_C(0x20)
38276 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_DISABLED (UINT32_C(0x0…
38278 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID5_ENABLE_ENABLED (UINT32_C(0x1…
38281 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE UINT32_C(0x40)
38283 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_DISABLED (UINT32_C(0x0…
38285 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID6_ENABLE_ENABLED (UINT32_C(0x1…
38288 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE UINT32_C(0x80)
38290 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_DISABLED (UINT32_C(0x0…
38292 …#define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG_INPUT_QUEUE_ENABLE_QID7_ENABLE_ENABLED (UINT32_C(0x1…
38342 * * 0x0-0xFFF8 - The function ID
38343 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38344 * * 0xFFFD - Reserved for user-space HWRM interface
38345 * * 0xFFFF - HWRM
38373 * If set to '0', then the capability to configure queue_enable
38376 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_FEATURE_PARAMS_QUEUE_ENABLE_CAP UINT32_C(0x1)
38380 * If set to '0', then the capability to configure queue_mode
38383 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_FEATURE_PARAMS_QUEUE_MODE_CAP UINT32_C(0x2)
38389 * If set to '0', then the capability to configure queue_enable
38392 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_FEATURE_PARAMS_QUEUE_ENABLE_CAP UINT32_C(0x1)
38404 * If set to '0', then the capability to configure the option
38407 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_WFQ_COST_CAP UINT32_C(0x1)
38411 * If set to '0', then the capability to configure the option
38414 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_WFQ_UPPER_FACTOR_CAP UINT32_C(0x2)
38418 * If set to '0', then the capability to configure the option
38421 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_HYST_WINDOW_SIZE_FACTOR_CAP UINT32_C(0x4)
38425 * If set to '0', then the capability to configure the option
38428 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_PCIE_BW_EFF_CAP UINT32_C(0x8)
38432 * If set to '0', then the capability to configure the option
38435 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_XOFF_HEADROOM_FACTOR_CAP UINT32_C(0x10)
38439 * If set to '0', then the capability to configure the option
38442 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_MIN_LATENCY_CAP UINT32_C(0x20)
38446 * If set to '0', then the capability to configure the option
38449 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_MAX_LATENCY_CAP UINT32_C(0x40)
38453 * If set to '0', then the capability to configure the option
38456 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_MIN_LATENCY_CAP UINT32_C(0x80)
38460 * If set to '0', then the capability to configure the option
38463 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_MAX_LATENCY_CAP UINT32_C(0x100)
38467 * If set to '0', then the capability to configure the option
38470 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_L2_PIPE_COS_LATENCY_CAP UINT32_C(0x200)
38474 * If set to '0', then the capability to configure the option
38477 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_ROCE_PIPE_COS_LATENCY_CAP UINT32_C(0x400)
38481 * If set to '0', then the capability to configure the option
38484 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_COS_SHARED_MIN_RATIO_CAP UINT32_C(0x800)
38488 * If set to '0', then the capability to configure the option
38491 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_RSVD_CELLS_LIMIT_RATIO_CAP UINT32_C(0x1000)
38495 * If set to '0', then the capability to configure the option
38498 #define HWRM_QUEUE_QCAPS_OUTPUT_RX_TUNING_PARAMS_SHAPER_REFILL_TIMER_CAP UINT32_C(0x2000)
38504 * If set to '0', then the capability to configure the option
38507 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_WFQ_COST_CAP UINT32_C(0x1)
38511 * If set to '0', then the capability to configure the option
38514 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_WFQ_UPPER_FACTOR_CAP UINT32_C(0x2)
38518 * If set to '0', then the capability to configure the option
38521 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_HYST_WINDOW_SIZE_FACTOR_CAP UINT32_C(0x4)
38525 * If set to '0', then the capability to configure the option
38528 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_RSVD_CELLS_LIMIT_RATIO_CAP UINT32_C(0x8)
38532 * If set to '0', then the capability to configure the option
38535 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_L2_MIN_LATENCY_CAP UINT32_C(0x10)
38539 * If set to '0', then the capability to configure the option
38542 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_L2_MAX_LATENCY_CAP UINT32_C(0x20)
38546 * If set to '0', then the capability to configure the option
38549 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_ROCE_MIN_LATENCY_CAP UINT32_C(0x40)
38553 * If set to '0', then the capability to configure the option
38556 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_ROCE_MAX_LATENCY_CAP UINT32_C(0x80)
38560 * If set to '0', then the capability to configure the option
38563 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_MAX_TBM_CELLS_PRERESERVED_CAP UINT32_C(0x100)
38567 * If set to '0', then the capability to configure the option
38570 #define HWRM_QUEUE_QCAPS_OUTPUT_TX_TUNING_PARAMS_SHAPER_REFILL_TIMER_CAP UINT32_C(0x200)
38605 * * 0x0-0xFFF8 - The function ID
38606 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38607 * * 0xFFFD - Reserved for user-space HWRM interface
38608 * * 0xFFFF - HWRM
38645 * Specifies PCIe BW efficiency in the range of 0-100%. System
38698 * value. Its range of values is 0-50%.
38740 * * 0x0-0xFFF8 - The function ID
38741 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38742 * * 0xFFFD - Reserved for user-space HWRM interface
38743 * * 0xFFFF - HWRM
38755 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_WFQ_COST UINT32_C(0x1)
38757 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_WFQ_UPPER_FACTOR UINT32_C(0x2)
38759 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_HYST_WINDOW_SIZE_FACTOR UINT32_C(0x4)
38761 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_PCIE_BW_EFF UINT32_C(0x8)
38763 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_XOFF_HEADROOM_FACTOR UINT32_C(0x10)
38765 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_MIN_LATENCY UINT32_C(0x20)
38767 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_MAX_LATENCY UINT32_C(0x40)
38769 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_MIN_LATENCY UINT32_C(0x80)
38771 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_MAX_LATENCY UINT32_C(0x100)
38773 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_L2_PIPE_COS_LATENCY UINT32_C(0x200)
38775 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_ROCE_PIPE_COS_LATENCY UINT32_C(0x400)
38777 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_COS_SHARED_MIN_RATIO UINT32_C(0x800)
38779 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_RSVD_CELLS_LIMIT_RATIO UINT32_C(0x1000)
38781 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG_INPUT_ENABLES_SHAPER_REFILL_TIMER UINT32_C(0x2000)
38796 * Specifies PCIe BW efficiency in the range of 0-100%. System
38849 * value. Its range of values is 0-50%.
38905 * * 0x0-0xFFF8 - The function ID
38906 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
38907 * * 0xFFFD - Reserved for user-space HWRM interface
38908 * * 0xFFFF - HWRM
38948 * value. Its range of values is 0-50%.
39016 * * 0x0-0xFFF8 - The function ID
39017 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39018 * * 0xFFFD - Reserved for user-space HWRM interface
39019 * * 0xFFFF - HWRM
39031 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_WFQ_COST UINT32_C(0x1)
39033 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_WFQ_UPPER_FACTOR UINT32_C(0x2)
39035 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_HYST_WINDOW_SIZE_FACTOR UINT32_C(0x4)
39037 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_RSVD_CELLS_LIMIT_RATIO UINT32_C(0x8)
39039 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_L2_MIN_LATENCY UINT32_C(0x10)
39041 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_L2_MAX_LATENCY UINT32_C(0x20)
39043 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_ROCE_MIN_LATENCY UINT32_C(0x40)
39045 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_ROCE_MAX_LATENCY UINT32_C(0x80)
39047 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_MAX_TBM_CELLS_PRERESERVED UINT32_C(0x100)
39049 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG_INPUT_ENABLES_SHAPER_REFILL_TIMER UINT32_C(0x200)
39067 * value. Its range of values is 0-50%.
39149 * * 0x0-0xFFF8 - The function ID
39150 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39151 * * 0xFFFD - Reserved for user-space HWRM interface
39152 * * 0xFFFF - HWRM
39211 * * 0x0-0xFFF8 - The function ID
39212 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39213 * * 0xFFFD - Reserved for user-space HWRM interface
39214 * * 0xFFFF - HWRM
39274 * * 0x0-0xFFF8 - The function ID
39275 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39276 * * 0xFFFD - Reserved for user-space HWRM interface
39277 * * 0xFFFF - HWRM
39336 * * 0x0-0xFFF8 - The function ID
39337 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39338 * * 0xFFFD - Reserved for user-space HWRM interface
39339 * * 0xFFFF - HWRM
39354 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
39360 #define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID UINT32_C(0x2)
39417 * * 0x0-0xFFF8 - The function ID
39418 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39419 * * 0xFFFD - Reserved for user-space HWRM interface
39420 * * 0xFFFF - HWRM
39437 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID UINT32_C(0x1)
39442 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID UINT32_C(0x2)
39447 #define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID UINT32_C(0x4)
39454 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
39456 #define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP UINT32_C(0x1)
39466 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)
39467 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)
39468 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)
39469 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)
39470 #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)
39530 * * 0x0-0xFFF8 - The function ID
39531 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39532 * * 0xFFFD - Reserved for user-space HWRM interface
39533 * * 0xFFFF - HWRM
39593 * * 0x0-0xFFF8 - The function ID
39594 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39595 * * 0xFFFD - Reserved for user-space HWRM interface
39596 * * 0xFFFF - HWRM
39611 #define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT UINT32_C(0x1)
39615 * If set to '0', then VLAN stripping is disabled on
39618 #define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2)
39623 * If set to '0', then bd_stall is being configured to be
39626 #define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4)
39630 * If set to '0', then this VNIC is not configured to be
39633 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8)
39637 * If this flag is set to '0', then this flag shall be
39643 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10)
39661 #define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20)
39668 #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE UINT32_C(0x40)
39673 #define HWRM_VNIC_CFG_INPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x80)
39679 #define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP UINT32_C(0x1)
39684 #define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE UINT32_C(0x2)
39689 #define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE UINT32_C(0x4)
39694 #define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE UINT32_C(0x8)
39699 #define HWRM_VNIC_CFG_INPUT_ENABLES_MRU UINT32_C(0x10)
39704 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID UINT32_C(0x20)
39709 #define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID UINT32_C(0x40)
39711 #define HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID UINT32_C(0x80)
39716 #define HWRM_VNIC_CFG_INPUT_ENABLES_RX_CSUM_V2_MODE UINT32_C(0x100)
39718 #define HWRM_VNIC_CFG_INPUT_ENABLES_L2_CQE_MODE UINT32_C(0x200)
39728 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
39733 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
39739 * 0xFF... (All Fs) if there is no LB rule.
39793 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
39803 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
39808 #define HWRM_VNIC_CFG_INPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
39820 #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0)
39830 #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1)
39837 #define HWRM_VNIC_CFG_INPUT_L2_CQE_MODE_MIXED UINT32_C(0x2)
39887 * * 0x0-0xFFF8 - The function ID
39888 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
39889 * * 0xFFFD - Reserved for user-space HWRM interface
39890 * * 0xFFFF - HWRM
39905 #define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
39927 * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if
39932 * RSS ID for COS rule/table structure. 0xFF... (All Fs) if
39938 * 0xFF... (All Fs) if there is no LB rule.
39949 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT UINT32_C(0x1)
39953 * If set to '0', then VLAN stripping is disabled on
39956 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE UINT32_C(0x2)
39961 * If set to '0', then bd_stall is disabled on
39964 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE UINT32_C(0x4)
39968 * If set to '0', then this VNIC is not configured to
39971 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE UINT32_C(0x8)
39975 * When this flag is set to '0', the VNIC is not configured
39982 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE UINT32_C(0x10)
39996 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE UINT32_C(0x20)
40003 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE UINT32_C(0x40)
40005 * When this bit is '0', VNIC is in normal operation state.
40008 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE UINT32_C(0x80)
40010 #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x100)
40013 * association is valid. Otherwise it will return 0xFFFF to indicate no
40029 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_DEFAULT UINT32_C(0x0)
40035 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_ALL_OK UINT32_C(0x1)
40040 #define HWRM_VNIC_QCFG_OUTPUT_RX_CSUM_V2_MODE_MAX UINT32_C(0x2)
40052 #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_DEFAULT UINT32_C(0x0)
40057 #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_COMPRESSED UINT32_C(0x1)
40063 #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2)
40073 #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0)
40074 #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1)
40075 #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2)
40076 #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3)
40077 #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4)
40082 #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_NORMAL UINT32_C(0x0)
40084 #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP UINT32_C(0x1)
40120 * * 0x0-0xFFF8 - The function ID
40121 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40122 * * 0xFFFD - Reserved for user-space HWRM interface
40123 * * 0xFFFF - HWRM
40153 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED UINT32_C(0x1)
40157 * If set to '0', then VLAN stripping capability is
40160 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP UINT32_C(0x2)
40165 * If set to '0', then bd_stall capability is not supported
40168 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP UINT32_C(0x4)
40173 * If set to '0', then the capability to receive
40177 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP UINT32_C(0x8)
40181 * When this flag is set to '0', the VNIC capability to
40184 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP UINT32_C(0x10)
40189 * When this bit is set to '0', then a VNIC can not be configured
40193 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP UINT32_C(0x20)
40197 * If set to '0', then the capability to mirror the
40200 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP UINT32_C(0x40)
40203 * is supported. If set to '0', then the outermost RSS hashing
40206 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP UINT32_C(0x80)
40213 * to 1. If set to '0', firmware does not support this feature.
40215 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP UINT32_C(0x100)
40222 * configured using the HWRM_VNIC_CFG on a VNIC. If set to '0', the
40225 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP UINT32_C(0x200)
40229 * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not
40232 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP UINT32_C(0x400)
40237 * This capability is available only on Proxy VEE PF. If set to '0',
40240 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP UINT32_C(0x800)
40244 * When this bit is set to '0', then the capability to configure
40248 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP UINT32_C(0x1000)
40254 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_STRICT_HASH_TYPE_CAP UINT32_C(0x2000)
40259 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_HASH_TYPE_DELTA_CAP UINT32_C(0x4000)
40268 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP UINT32_C(0x8000)
40277 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_XOR_CAP UINT32_C(0x10000)
40289 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP UINT32_C(0x20000)
40294 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPV6_FLOW_LABEL_CAP UINT32_C(0x40000)
40299 * be used for the RX rings of the VNIC. If set to '0', the
40302 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V3_CAP UINT32_C(0x80000)
40308 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP UINT32_C(0x100000)
40313 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP UINT32_C(0x200000)
40318 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP UINT32_C(0x400000)
40323 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP UINT32_C(0x800000)
40328 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP UINT32_C(0x1000000)
40332 * When outermost_rss_cap is '1' and this bit is '0', the outermost
40335 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP UINT32_C(0x2000000)
40340 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE UINT32_C(0x4000000)
40345 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED UINT32_C(0x8000000)
40347 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP UINT32_C(0x10000000)
40349 #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_HW_TUNNEL_TPA_CAP UINT32_C(0x20000000)
40353 * '0' means that both the TPA v2 and v3 are not supported.
40390 * * 0x0-0xFFF8 - The function ID
40391 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40392 * * 0xFFFD - Reserved for user-space HWRM interface
40393 * * 0xFFFF - HWRM
40409 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA UINT32_C(0x1)
40415 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA UINT32_C(0x2)
40421 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4)
40427 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO UINT32_C(0x8)
40433 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10)
40440 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20)
40451 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40)
40459 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80)
40463 * When this bit is '0', the VNIC shall DMA payload data
40467 #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO UINT32_C(0x100)
40473 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)
40478 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)
40483 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
40485 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
40490 #define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_TNL_TPA_EN UINT32_C(0x10)
40497 * valid values are > 0 and <= 63.
40501 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
40503 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
40505 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
40507 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
40509 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
40514 * supporting TPA v2, this is in unit of 1 and must be > 0
40520 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)
40522 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)
40524 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)
40526 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)
40528 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)
40530 #define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)
40541 * should be set to 0. The minimum length is set by firmware
40557 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN UINT32_C(0x1)
40562 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GENEVE UINT32_C(0x2)
40567 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_NVGRE UINT32_C(0x4)
40572 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE UINT32_C(0x8)
40577 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV4 UINT32_C(0x10)
40582 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_IPV6 UINT32_C(0x20)
40587 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE UINT32_C(0x40)
40592 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1 UINT32_C(0x80)
40597 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_GRE_CUST1 UINT32_C(0x100)
40602 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR1 UINT32_C(0x200)
40607 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR2 UINT32_C(0x400)
40612 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR3 UINT32_C(0x800)
40617 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR4 UINT32_C(0x1000)
40622 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR5 UINT32_C(0x2000)
40627 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR6 UINT32_C(0x4000)
40632 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR7 UINT32_C(0x8000)
40637 #define HWRM_VNIC_TPA_CFG_INPUT_TNL_TPA_EN_BITMAP_UPAR8 UINT32_C(0x10000)
40686 * * 0x0-0xFFF8 - The function ID
40687 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40688 * * 0xFFFD - Reserved for user-space HWRM interface
40689 * * 0xFFFF - HWRM
40721 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA UINT32_C(0x1)
40727 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA UINT32_C(0x2)
40733 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE UINT32_C(0x4)
40739 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO UINT32_C(0x8)
40745 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN UINT32_C(0x10)
40752 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ UINT32_C(0x20)
40763 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK UINT32_C(0x40)
40771 #define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK UINT32_C(0x80)
40778 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)
40780 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)
40782 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)
40784 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)
40786 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)
40794 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0)
40796 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1)
40798 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2)
40800 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3)
40802 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4)
40804 #define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7)
40828 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN UINT32_C(0x1)
40833 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GENEVE UINT32_C(0x2)
40838 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_NVGRE UINT32_C(0x4)
40843 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE UINT32_C(0x8)
40848 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV4 UINT32_C(0x10)
40853 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_IPV6 UINT32_C(0x20)
40858 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_GPE UINT32_C(0x40)
40863 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_VXLAN_CUST1 UINT32_C(0x80)
40868 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_GRE_CUST1 UINT32_C(0x100)
40873 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR1 UINT32_C(0x200)
40878 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR2 UINT32_C(0x400)
40883 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR3 UINT32_C(0x800)
40888 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR4 UINT32_C(0x1000)
40893 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR5 UINT32_C(0x2000)
40898 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR6 UINT32_C(0x4000)
40903 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR7 UINT32_C(0x8000)
40908 #define HWRM_VNIC_TPA_QCFG_OUTPUT_TNL_TPA_EN_BITMAP_UPAR8 UINT32_C(0x10000)
40943 * * 0x0-0xFFF8 - The function ID
40944 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
40945 * * 0xFFFD - Reserved for user-space HWRM interface
40946 * * 0xFFFF - HWRM
40962 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
40968 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
40974 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
40980 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
40986 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
40992 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
41002 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL UINT32_C(0x40)
41009 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 UINT32_C(0x80)
41016 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 UINT32_C(0x100)
41023 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 UINT32_C(0x200)
41030 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 UINT32_C(0x400)
41035 * Valid values range from 0 to 7.
41041 * 0xffff. Only PF can initiate global RSS hash mode setting changes.
41058 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1)
41066 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2)
41073 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4)
41081 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8)
41088 #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10)
41107 #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_INCLUDE UINT32_C(0x1)
41119 #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_HASH_TYPE_EXCLUDE UINT32_C(0x2)
41124 #define HWRM_VNIC_RSS_CFG_INPUT_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT UINT32_C(0x4)
41133 #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ UINT32_C(0x0)
41141 #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_XOR UINT32_C(0x1)
41151 #define HWRM_VNIC_RSS_CFG_INPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM UINT32_C(0x2)
41187 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
41192 #define HWRM_VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY UINT32_C(0x1)
41220 * * 0x0-0xFFF8 - The function ID
41221 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41222 * * 0xFFFD - Reserved for user-space HWRM interface
41223 * * 0xFFFF - HWRM
41263 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)
41269 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
41275 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
41281 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)
41287 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
41293 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
41300 * udp_ipv6 hash types. This bit will be '0' if
41301 * rss_ipv6_flow_label_cap is '0'.
41303 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6_FLOW_LABEL UINT32_C(0x40)
41307 * AH/IPv4 packets. This bit will be '0' if rss_ipsec_ah_spi_ipv4_cap
41308 * is '0'.
41310 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV4 UINT32_C(0x80)
41314 * ESP/IPv4 packets. This bit will be '0' if
41315 * rss_ipsec_esp_spi_ipv4_cap is '0'.
41317 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV4 UINT32_C(0x100)
41321 * AH/IPv6 packets. This bit will be '0' if
41322 * rss_ipsec_ah_spi_ipv6_cap is '0'.
41324 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV6 UINT32_C(0x200)
41328 * ESP/IPv6 packets. This bit will be '0' if
41329 * rss_ipsec_esp_spi_ipv6_cap is '0'.
41331 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV6 UINT32_C(0x400)
41337 * the value of 0xffff implies a global RSS configuration query.
41341 * and rss_ctx_idx is 0xffff.
41351 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT UINT32_C(0x1)
41359 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 UINT32_C(0x2)
41366 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 UINT32_C(0x4)
41374 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 UINT32_C(0x8)
41381 #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 UINT32_C(0x10)
41390 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ UINT32_C(0x0)
41398 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_XOR UINT32_C(0x1)
41408 #define HWRM_VNIC_RSS_QCFG_OUTPUT_RING_SELECT_MODE_TOEPLITZ_CHECKSUM UINT32_C(0x2)
41444 * * 0x0-0xFFF8 - The function ID
41445 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41446 * * 0xFFFD - Reserved for user-space HWRM interface
41447 * * 0xFFFF - HWRM
41464 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1)
41469 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2)
41483 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 UINT32_C(0x4)
41497 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 UINT32_C(0x8)
41503 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE UINT32_C(0x10)
41509 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE UINT32_C(0x20)
41515 #define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_VIRTIO_PLACEMENT UINT32_C(0x40)
41521 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID UINT32_C(0x1)
41526 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID UINT32_C(0x2)
41531 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID UINT32_C(0x4)
41536 #define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_MAX_BDS_VALID UINT32_C(0x8)
41627 * * 0x0-0xFFF8 - The function ID
41628 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41629 * * 0xFFFD - Reserved for user-space HWRM interface
41630 * * 0xFFFF - HWRM
41661 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT UINT32_C(0x1)
41666 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT UINT32_C(0x2)
41671 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 UINT32_C(0x4)
41676 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 UINT32_C(0x8)
41681 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE UINT32_C(0x10)
41686 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE UINT32_C(0x20)
41691 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC UINT32_C(0x40)
41697 #define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_VIRTIO_PLACEMENT UINT32_C(0x80)
41772 * * 0x0-0xFFF8 - The function ID
41773 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41774 * * 0xFFFD - Reserved for user-space HWRM interface
41775 * * 0xFFFF - HWRM
41834 * * 0x0-0xFFF8 - The function ID
41835 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41836 * * 0xFFFD - Reserved for user-space HWRM interface
41837 * * 0xFFFF - HWRM
41897 * * 0x0-0xFFF8 - The function ID
41898 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
41899 * * 0xFFFD - Reserved for user-space HWRM interface
41900 * * 0xFFFF - HWRM
41915 #define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG UINT32_C(0x2)
41920 #define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID UINT32_C(0x8)
41925 #define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID UINT32_C(0x20)
41930 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID UINT32_C(0x40)
41935 #define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID UINT32_C(0x80)
41940 #define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID UINT32_C(0x100)
41945 #define HWRM_RING_ALLOC_INPUT_ENABLES_SCHQ_ID UINT32_C(0x200)
41950 #define HWRM_RING_ALLOC_INPUT_ENABLES_MPC_CHNLS_TYPE UINT32_C(0x400)
41955 #define HWRM_RING_ALLOC_INPUT_ENABLES_STEERING_TAG_VALID UINT32_C(0x800)
41959 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
41961 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)
41963 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)
41965 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
41967 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
41969 #define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)
41979 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_OFF UINT32_C(0x0)
41981 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_4 UINT32_C(0x1)
41983 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_8 UINT32_C(0x2)
41985 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_12 UINT32_C(0x3)
41987 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_16 UINT32_C(0x4)
41989 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_24 UINT32_C(0x5)
41991 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_32 UINT32_C(0x6)
41993 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_48 UINT32_C(0x7)
41995 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_64 UINT32_C(0x8)
41997 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_96 UINT32_C(0x9)
41999 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_128 UINT32_C(0xa)
42001 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_192 UINT32_C(0xb)
42003 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_256 UINT32_C(0xc)
42005 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_320 UINT32_C(0xd)
42007 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_384 UINT32_C(0xe)
42009 #define HWRM_RING_ALLOC_INPUT_CMPL_COAL_CNT_COAL_MAX UINT32_C(0xf)
42015 * a 0B or 2B offset from the start of the Rx packet buffer. When
42021 #define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)
42032 #define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x2)
42038 #define HWRM_RING_ALLOC_INPUT_FLAGS_NQ_DBR_PACING UINT32_C(0x4)
42051 #define HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE UINT32_C(0x8)
42080 * For this version of the specification, value other than 0 or
42082 * When the page_tbl_depth = 0, then it is treated as a
42140 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK UINT32_C(0xf)
42141 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0
42146 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP UINT32_C(0x1)
42151 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ UINT32_C(0x2)
42154 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK UINT32_C(0xf0)
42159 * represents a priority value. If set to 0, then the priority
42163 * represents a weight value. If set to 0, then the weight
42167 #define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK UINT32_C(0xff00)
42173 * It shall be set to 0.
42184 * It shall be set to 0.
42195 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK UINT32_C(0xfffffff)
42196 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0
42198 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE UINT32_C(0x10000000)
42200 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS (UINT32_C(0x0) << 28)
42202 #define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES (UINT32_C(0x1) << 28)
42205 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
42208 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
42210 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
42212 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
42214 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
42216 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
42218 #define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
42229 #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)
42231 #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)
42233 #define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)
42235 #define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)
42243 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TCE UINT32_C(0x0)
42248 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RCE UINT32_C(0x1)
42253 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_TE_CFA UINT32_C(0x2)
42258 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_RE_CFA UINT32_C(0x3)
42263 #define HWRM_RING_ALLOC_INPUT_MPC_CHNLS_TYPE_PRIMATE UINT32_C(0x4)
42299 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER UINT32_C(0x0)
42301 #define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER UINT32_C(0x1)
42337 * * 0x0-0xFFF8 - The function ID
42338 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42339 * * 0xFFFD - Reserved for user-space HWRM interface
42340 * * 0xFFFF - HWRM
42353 #define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
42355 #define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)
42357 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)
42359 #define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
42361 #define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)
42363 #define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)
42375 * If this bit is '0', firmware will not treat ring_id as virtio
42380 #define HWRM_RING_FREE_INPUT_FLAGS_VIRTIO_RING_VALID UINT32_C(0x1)
42442 * * 0x0-0xFFF8 - The function ID
42443 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42444 * * 0xFFFD - Reserved for user-space HWRM interface
42445 * * 0xFFFF - HWRM
42458 #define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
42460 #define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)
42462 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)
42464 #define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)
42470 #define HWRM_RING_RESET_INPUT_RING_TYPE_RX_RING_GRP UINT32_C(0x6)
42498 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER UINT32_C(0x0)
42500 #define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER UINT32_C(0x1)
42538 * * 0x0-0xFFF8 - The function ID
42539 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42540 * * 0xFFFD - Reserved for user-space HWRM interface
42541 * * 0xFFFF - HWRM
42554 #define HWRM_RING_CFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
42556 #define HWRM_RING_CFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
42565 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
42570 * When '0', the received packet will not be padded.
42574 #define HWRM_RING_CFG_INPUT_ENABLES_RX_SOP_PAD_ENABLE UINT32_C(0x1)
42583 * When set to '0', the PCI function on which driver issues
42588 #define HWRM_RING_CFG_INPUT_ENABLES_PROXY_MODE_ENABLE UINT32_C(0x2)
42597 #define HWRM_RING_CFG_INPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE UINT32_C(0x4)
42599 #define HWRM_RING_CFG_INPUT_ENABLES_SCHQ_ID UINT32_C(0x8)
42601 #define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE UINT32_C(0x10)
42605 * QP context field. When set to '0', no change done to metadata.
42610 #define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA UINT32_C(0x20)
42694 * * 0x0-0xFFF8 - The function ID
42695 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42696 * * 0xFFFD - Reserved for user-space HWRM interface
42697 * * 0xFFFF - HWRM
42710 #define HWRM_RING_QCFG_INPUT_RING_TYPE_TX UINT32_C(0x1)
42712 #define HWRM_RING_QCFG_INPUT_RING_TYPE_RX UINT32_C(0x2)
42734 * a 0B, 2B, 10B or 12B offset from the start of the Rx packet
42739 * When '0', the received packet will not be padded.
42743 #define HWRM_RING_QCFG_OUTPUT_ENABLES_RX_SOP_PAD_ENABLE UINT32_C(0x1)
42752 * When set to '0', the PCI function on which driver issues
42757 #define HWRM_RING_QCFG_OUTPUT_ENABLES_PROXY_MODE_ENABLE UINT32_C(0x2)
42766 #define HWRM_RING_QCFG_OUTPUT_ENABLES_TX_PROXY_SRC_INTF_OVERRIDE UINT32_C(0x4)
42834 * * 0x0-0xFFF8 - The function ID
42835 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42836 * * 0xFFFD - Reserved for user-space HWRM interface
42837 * * 0xFFFF - HWRM
42865 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN UINT32_C(0x1)
42870 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX UINT32_C(0x2)
42875 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET UINT32_C(0x4)
42880 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE UINT32_C(0x8)
42885 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR UINT32_C(0x10)
42890 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT UINT32_C(0x20)
42895 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR UINT32_C(0x40)
42900 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT UINT32_C(0x80)
42905 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT UINT32_C(0x100)
42911 #define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN UINT32_C(0x1)
42976 * * 0x0-0xFFF8 - The function ID
42977 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
42978 * * 0xFFFD - Reserved for user-space HWRM interface
42979 * * 0xFFFF - HWRM
42992 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_MASK UINT32_C(0x3)
42993 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_UNUSED_0_SFT 0
42996 * queue. Set this flag to 0 when querying parameters on a
42999 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_INPUT_FLAGS_IS_NQ UINT32_C(0x4)
43019 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET UINT32_C(0x1)
43024 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE UINT32_C(0x2)
43092 * * 0x0-0xFFF8 - The function ID
43093 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43094 * * 0xFFFD - Reserved for user-space HWRM interface
43095 * * 0xFFFF - HWRM
43112 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET UINT32_C(0x1)
43117 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE UINT32_C(0x2)
43120 * notification queue. Set this flag to 0 when configuring
43123 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ UINT32_C(0x4)
43168 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR UINT32_C(0x1)
43173 …fine HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT UINT32_C(0x2)
43178 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR UINT32_C(0x4)
43183 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN UINT32_C(0x8)
43188 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX UINT32_C(0x10)
43193 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT UINT32_C(0x20)
43242 * * 0x0-0xFFF8 - The function ID
43243 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43244 * * 0xFFFD - Reserved for user-space HWRM interface
43245 * * 0xFFFF - HWRM
43267 * the ring group. If this value is 0xFF... (All Fs), then no
43329 * * 0x0-0xFFF8 - The function ID
43330 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43331 * * 0xFFFD - Reserved for user-space HWRM interface
43332 * * 0xFFFF - HWRM
43392 * * 0x0-0xFFF8 - The function ID
43393 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43394 * * 0xFFFD - Reserved for user-space HWRM interface
43395 * * 0xFFFF - HWRM
43410 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING0 UINT32_C(0x1)
43415 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING1 UINT32_C(0x2)
43420 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING2 UINT32_C(0x4)
43425 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING3 UINT32_C(0x8)
43430 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING4 UINT32_C(0x10)
43435 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING5 UINT32_C(0x20)
43440 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING6 UINT32_C(0x40)
43445 #define HWRM_RING_SCHQ_ALLOC_INPUT_ENABLES_TQM_RING7 UINT32_C(0x80)
43448 /* TQM ring 0 page size and level. */
43450 /* TQM ring 0 PBL indirect levels. */
43451 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_MASK UINT32_C(0xf)
43452 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_SFT 0
43454 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_0 UINT32_C(0x0)
43456 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_1 UINT32_C(0x1)
43461 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_LVL_LVL_2 UINT32_C(0x2)
43463 /* TQM ring 0 page size. */
43464 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_MASK UINT32_C(0xf0)
43467 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
43469 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
43471 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
43473 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
43475 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
43477 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING0_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
43482 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_MASK UINT32_C(0xf)
43483 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_SFT 0
43485 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_0 UINT32_C(0x0)
43487 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_1 UINT32_C(0x1)
43492 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_LVL_LVL_2 UINT32_C(0x2)
43495 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_MASK UINT32_C(0xf0)
43498 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
43500 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
43502 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
43504 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
43506 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
43508 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING1_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
43513 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_MASK UINT32_C(0xf)
43514 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_SFT 0
43516 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_0 UINT32_C(0x0)
43518 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_1 UINT32_C(0x1)
43523 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_LVL_LVL_2 UINT32_C(0x2)
43526 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_MASK UINT32_C(0xf0)
43529 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
43531 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
43533 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
43535 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
43537 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
43539 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING2_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
43544 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_MASK UINT32_C(0xf)
43545 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_SFT 0
43547 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_0 UINT32_C(0x0)
43549 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_1 UINT32_C(0x1)
43554 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_LVL_LVL_2 UINT32_C(0x2)
43557 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_MASK UINT32_C(0xf0)
43560 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
43562 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
43564 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
43566 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
43568 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
43570 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING3_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
43575 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_MASK UINT32_C(0xf)
43576 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_SFT 0
43578 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_0 UINT32_C(0x0)
43580 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_1 UINT32_C(0x1)
43585 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_LVL_LVL_2 UINT32_C(0x2)
43588 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_MASK UINT32_C(0xf0)
43591 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
43593 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
43595 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
43597 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
43599 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
43601 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING4_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
43606 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_MASK UINT32_C(0xf)
43607 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_SFT 0
43609 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_0 UINT32_C(0x0)
43611 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_1 UINT32_C(0x1)
43616 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_LVL_LVL_2 UINT32_C(0x2)
43619 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_MASK UINT32_C(0xf0)
43622 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
43624 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
43626 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
43628 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
43630 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
43632 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING5_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
43637 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_MASK UINT32_C(0xf)
43638 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_SFT 0
43640 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_0 UINT32_C(0x0)
43642 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_1 UINT32_C(0x1)
43647 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_LVL_LVL_2 UINT32_C(0x2)
43650 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_MASK UINT32_C(0xf0)
43653 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
43655 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
43657 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
43659 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
43661 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
43663 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING6_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
43668 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_MASK UINT32_C(0xf)
43669 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_SFT 0
43671 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_0 UINT32_C(0x0)
43673 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_1 UINT32_C(0x1)
43678 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_LVL_LVL_2 UINT32_C(0x2)
43681 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_MASK UINT32_C(0xf0)
43684 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
43686 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
43688 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
43690 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
43692 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
43694 #define HWRM_RING_SCHQ_ALLOC_INPUT_TQM_RING7_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
43696 /* TQM ring 0 page directory. */
43713 * Number of TQM ring 0 entries.
43864 * * 0x0-0xFFF8 - The function ID
43865 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
43866 * * 0xFFFD - Reserved for user-space HWRM interface
43867 * * 0xFFFF - HWRM
43884 * in this SCHQ. Bit 0 represents traffic class 0 and bit 7 represents
43891 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_MAX_BW_ENABLED UINT32_C(0x1)
43893 #define HWRM_RING_SCHQ_CFG_INPUT_FLAGS_TC_RESERVATION_ENABLED UINT32_C(0x2)
44019 * * 0x0-0xFFF8 - The function ID
44020 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44021 * * 0xFFFD - Reserved for user-space HWRM interface
44022 * * 0xFFFF - HWRM
44063 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL
44068 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL
44073 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL
44078 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
44103 * * 0x0-0xFFF8 - The function ID
44104 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44105 * * 0xFFFD - Reserved for user-space HWRM interface
44106 * * 0xFFFF - HWRM
44122 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
44124 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
44126 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
44132 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x2)
44137 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x4)
44144 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST UINT32_C(0x8)
44149 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK UINT32_C(0x30)
44152 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 (UINT32_C(0x0) << 4)
44154 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 (UINT32_C(0x1) << 4)
44156 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE (UINT32_C(0x2) << 4)
44161 * 0 - legacy behavior, XDP filter is created with L2 filter
44164 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE UINT32_C(0x40)
44167 * pertain to source fields. Setting this flag to 0 indicate the
44171 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID UINT32_C(0x80)
44177 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x1)
44182 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK UINT32_C(0x2)
44187 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN UINT32_C(0x4)
44192 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK UINT32_C(0x8)
44197 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x10)
44202 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK UINT32_C(0x20)
44207 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR UINT32_C(0x40)
44212 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK UINT32_C(0x80)
44217 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN UINT32_C(0x100)
44222 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK UINT32_C(0x200)
44227 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN UINT32_C(0x400)
44232 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK UINT32_C(0x800)
44237 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE UINT32_C(0x1000)
44242 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID UINT32_C(0x2000)
44247 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4000)
44252 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000)
44257 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000)
44262 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS UINT32_C(0x20000)
44267 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS UINT32_C(0x40000)
44283 * A value of 0 will mask the corresponding bit from
44291 * A value of 0 will mask the corresponding bit from
44299 * A value of 0 will mask the corresponding bit from
44315 * A value of 0 will mask the corresponding bit from
44323 * A value of 0 will mask the corresponding bit from
44331 * A value of 0 will mask the corresponding bit from
44338 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)
44340 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)
44342 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)
44344 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)
44346 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)
44348 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)
44350 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)
44352 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)
44371 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
44373 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
44375 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
44377 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
44379 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
44381 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
44383 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
44385 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
44387 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
44389 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
44394 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
44395 /* Use fixed layer 2 ether type of 0xFFFF */
44396 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
44401 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
44403 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
44405 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
44426 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0)
44428 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER UINT32_C(0x1)
44430 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER UINT32_C(0x2)
44432 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX UINT32_C(0x3)
44434 #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN UINT32_C(0x4)
44466 * The flow id value in bit 0-29 is the actual ID of the flow
44469 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
44474 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
44475 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
44477 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
44479 * If this bit set to 0, then it indicates that the flow is
44482 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
44487 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
44490 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
44491 /* If this bit set to 0, then it indicates rx flow. */
44492 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
44494 #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
44531 * * 0x0-0xFFF8 - The function ID
44532 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44533 * * 0xFFFD - Reserved for user-space HWRM interface
44534 * * 0xFFFF - HWRM
44597 * * 0x0-0xFFF8 - The function ID
44598 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44599 * * 0xFFFD - Reserved for user-space HWRM interface
44600 * * 0xFFFF - HWRM
44616 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
44618 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
44620 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
44626 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2)
44631 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK UINT32_C(0xc)
44634 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 (UINT32_C(0x0) << 2)
44636 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 (UINT32_C(0x1) << 2)
44638 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE (UINT32_C(0x2) << 2)
44644 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_MASK UINT32_C(0x30)
44647 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_NO_UPDATE (UINT32_C(0x0) << 4)
44649 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_BYPASS_LKUP (UINT32_C(0x1) << 4)
44651 #define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_REMAP_OP_ENABLE_LKUP (UINT32_C(0x2) << 4)
44658 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID UINT32_C(0x1)
44663 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
44668 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_PROF_FUNC UINT32_C(0x4)
44673 #define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_L2_CONTEXT_ID UINT32_C(0x8)
44751 * * 0x0-0xFFF8 - The function ID
44752 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44753 * * 0xFFFD - Reserved for user-space HWRM interface
44754 * * 0xFFFF - HWRM
44771 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST UINT32_C(0x2)
44776 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST UINT32_C(0x4)
44781 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST UINT32_C(0x8)
44818 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS UINT32_C(0x10)
44825 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST UINT32_C(0x20)
44833 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY UINT32_C(0x40)
44841 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN UINT32_C(0x80)
44858 #define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN UINT32_C(0x100)
44914 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
44916 #define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR UINT32_C(0x1)
44944 * * 0x0-0xFFF8 - The function ID
44945 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
44946 * * 0xFFFD - Reserved for user-space HWRM interface
44947 * * 0xFFFF - HWRM
44968 * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,
44970 * For an individual VLAN entry, the mask value should be 0xfff
45022 * * 0x0-0xFFF8 - The function ID
45023 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45024 * * 0xFFFD - Reserved for user-space HWRM interface
45025 * * 0xFFFF - HWRM
45049 * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),
45052 * the mask value should be 0xfff for the 12-bit VLAN ID.
45105 * * 0x0-0xFFF8 - The function ID
45106 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45107 * * 0xFFFD - Reserved for user-space HWRM interface
45108 * * 0xFFFF - HWRM
45123 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1)
45129 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
45134 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR UINT32_C(0x2)
45139 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN UINT32_C(0x4)
45144 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR UINT32_C(0x8)
45149 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE UINT32_C(0x10)
45154 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE UINT32_C(0x20)
45159 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR UINT32_C(0x40)
45164 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x80)
45169 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI UINT32_C(0x100)
45174 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID UINT32_C(0x200)
45179 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400)
45224 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
45226 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
45228 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
45230 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
45232 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
45234 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
45236 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
45238 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
45240 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
45242 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
45247 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
45248 /* Use fixed layer 2 ether type of 0xFFFF */
45249 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
45254 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
45256 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
45258 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
45273 …#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR UINT32_C(0x…
45283 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 UINT32_C(0x2)
45294 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 UINT32_C(0x4)
45325 * The flow id value in bit 0-29 is the actual ID of the flow
45328 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
45333 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
45334 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
45336 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
45338 * If this bit set to 0, then it indicates that the flow is
45341 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
45346 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
45349 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
45350 /* If this bit set to 0, then it indicates rx flow. */
45351 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
45353 #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
45390 * * 0x0-0xFFF8 - The function ID
45391 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45392 * * 0xFFFD - Reserved for user-space HWRM interface
45393 * * 0xFFFF - HWRM
45453 * * 0x0-0xFFF8 - The function ID
45454 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45455 * * 0xFFFD - Reserved for user-space HWRM interface
45456 * * 0xFFFF - HWRM
45471 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
45473 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
45475 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
45477 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
45479 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
45481 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
45483 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
45485 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
45487 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
45489 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
45494 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
45495 /* Use fixed layer 2 ether type of 0xFFFF */
45496 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
45501 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
45503 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
45505 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
45513 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST UINT32_C(0x1)
45563 * * 0x0-0xFFF8 - The function ID
45564 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45565 * * 0xFFFD - Reserved for user-space HWRM interface
45566 * * 0xFFFF - HWRM
45581 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
45583 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
45585 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
45587 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
45589 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
45591 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
45593 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
45595 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
45597 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
45599 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
45604 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
45605 /* Use fixed layer 2 ether type of 0xFFFF */
45606 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
45611 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
45613 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
45615 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
45666 * * 0x0-0xFFF8 - The function ID
45667 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45668 * * 0xFFFD - Reserved for user-space HWRM interface
45669 * * 0xFFFF - HWRM
45684 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
45686 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
45688 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
45690 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
45692 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
45694 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
45696 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
45698 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
45700 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
45702 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
45707 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
45708 /* Use fixed layer 2 ether type of 0xFFFF */
45709 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
45714 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
45716 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
45718 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
45754 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)
45755 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0
45757 #define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)
45781 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT UINT32_C(0x1c)
45783 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK UINT32_C(0xf0000000)
45785 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT UINT32_C(0x14)
45787 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK UINT32_C(0xff00000)
45789 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT UINT32_C(0x0)
45791 #define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK UINT32_C(0xfffff)
45829 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)
45831 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)
45833 #define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)
45876 * * 0x0-0xFFF8 - The function ID
45877 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45878 * * 0xFFFD - Reserved for user-space HWRM interface
45879 * * 0xFFFF - HWRM
45894 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1)
45900 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL UINT32_C(0x2)
45904 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN UINT32_C(0x1)
45906 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE UINT32_C(0x2)
45908 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE UINT32_C(0x3)
45910 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP UINT32_C(0x4)
45912 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE UINT32_C(0x5)
45914 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS UINT32_C(0x6)
45916 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN UINT32_C(0x7)
45918 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE UINT32_C(0x8)
45920 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
45925 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
45926 /* Use fixed layer 2 ether type of 0xFFFF */
45927 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
45932 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
45934 #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE UINT32_C(0x10)
45989 * * 0x0-0xFFF8 - The function ID
45990 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
45991 * * 0xFFFD - Reserved for user-space HWRM interface
45992 * * 0xFFFF - HWRM
46053 * * 0x0-0xFFF8 - The function ID
46054 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46055 * * 0xFFFD - Reserved for user-space HWRM interface
46056 * * 0xFFFF - HWRM
46071 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK UINT32_C(0x1)
46076 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x2)
46082 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER UINT32_C(0x4)
46088 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID UINT32_C(0x8)
46091 * is 0x0806. If this is not set it indicates no specific arp opcode
46094 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY UINT32_C(0x10)
46104 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX UINT32_C(0x20)
46111 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_NO_L2_CONTEXT UINT32_C(0x40)
46117 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
46122 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2)
46127 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x4)
46132 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8)
46137 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x10)
46142 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x20)
46147 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK UINT32_C(0x40)
46152 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x80)
46157 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK UINT32_C(0x100)
46162 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x200)
46167 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x400)
46172 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK UINT32_C(0x800)
46177 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x1000)
46182 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK UINT32_C(0x2000)
46187 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT UINT32_C(0x4000)
46192 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID UINT32_C(0x8000)
46197 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x10000)
46199 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x20000)
46204 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x40000)
46209 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX UINT32_C(0x80000)
46230 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
46232 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
46234 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
46247 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
46249 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
46251 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
46253 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMP UINT32_C(0x1)
46255 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMPV6 UINT32_C(0x3a)
46257 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD UINT32_C(0xff)
46283 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
46285 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
46287 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
46289 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
46291 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
46293 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
46295 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
46297 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
46299 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
46301 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
46306 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
46307 /* Use fixed layer 2 ether type of 0xFFFF */
46308 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
46313 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
46315 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
46317 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
46325 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER UINT32_C(0x0)
46327 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE UINT32_C(0x1)
46329 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW UINT32_C(0x2)
46331 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST UINT32_C(0x3)
46333 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST UINT32_C(0x4)
46399 * The flow id value in bit 0-29 is the actual ID of the flow
46402 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
46407 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
46408 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
46410 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
46412 * If this bit set to 0, then it indicates that the flow is
46415 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
46420 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
46423 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
46424 /* If this bit set to 0, then it indicates rx flow. */
46425 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
46427 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
46450 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
46452 #define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR UINT32_C(0x1)
46480 * * 0x0-0xFFF8 - The function ID
46481 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46482 * * 0xFFFD - Reserved for user-space HWRM interface
46483 * * 0xFFFF - HWRM
46543 * * 0x0-0xFFF8 - The function ID
46544 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46545 * * 0xFFFD - Reserved for user-space HWRM interface
46546 * * 0xFFFF - HWRM
46561 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1)
46566 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
46571 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4)
46575 * Setting this to 0 indicates that dest_id field contains VNIC or
46578 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID UINT32_C(0x1)
46585 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX UINT32_C(0x2)
46592 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_NO_L2_CONTEXT UINT32_C(0x4)
46614 * A value of 0xfff is considered invalid and implies the
46617 #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
46668 * * 0x0-0xFFF8 - The function ID
46669 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
46670 * * 0xFFFD - Reserved for user-space HWRM interface
46671 * * 0xFFFF - HWRM
46687 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
46689 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
46691 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
46697 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)
46702 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)
46707 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)
46712 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)
46717 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)
46723 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)
46729 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
46734 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x2)
46739 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x4)
46744 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x8)
46749 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x10)
46754 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x20)
46759 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x40)
46764 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x80)
46769 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x100)
46774 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x200)
46779 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x400)
46784 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x800)
46789 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x1000)
46794 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x2000)
46799 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x4000)
46804 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x8000)
46809 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID UINT32_C(0x10000)
46814 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID UINT32_C(0x20000)
46823 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
46825 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
46827 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
46829 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
46831 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
46833 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
46835 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
46837 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
46839 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
46841 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
46846 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
46847 /* Use fixed layer 2 ether type of 0xFFFF */
46848 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
46853 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
46855 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
46857 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
46876 * A value of 0xfff is considered invalid and implies the
46879 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
46906 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
46908 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
46910 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
46920 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
46922 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
46924 #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
46979 * The flow id value in bit 0-29 is the actual ID of the flow
46982 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
46987 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
46988 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
46990 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
46992 * If this bit set to 0, then it indicates that the flow is
46995 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
47000 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
47003 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
47004 /* If this bit set to 0, then it indicates rx flow. */
47005 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
47007 #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
47044 * * 0x0-0xFFF8 - The function ID
47045 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47046 * * 0xFFFD - Reserved for user-space HWRM interface
47047 * * 0xFFFF - HWRM
47107 * * 0x0-0xFFF8 - The function ID
47108 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47109 * * 0xFFFD - Reserved for user-space HWRM interface
47110 * * 0xFFFF - HWRM
47125 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID UINT32_C(0x1)
47130 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID UINT32_C(0x2)
47135 #define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID UINT32_C(0x4)
47158 * A value of 0xfff is considered invalid and implies the
47161 #define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
47212 * * 0x0-0xFFF8 - The function ID
47213 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47214 * * 0xFFFD - Reserved for user-space HWRM interface
47215 * * 0xFFFF - HWRM
47244 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
47245 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
47247 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
47249 #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
47327 * * 0x0-0xFFF8 - The function ID
47328 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47329 * * 0xFFFD - Reserved for user-space HWRM interface
47330 * * 0xFFFF - HWRM
47346 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
47348 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
47350 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
47355 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0)
47357 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1)
47359 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2)
47363 * It shall be set to 0.
47368 * It shall be set to 0.
47374 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
47375 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT 0
47377 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000)
47379 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
47381 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
47384 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
47387 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
47389 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
47391 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
47393 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
47395 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) …
47397 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29)
47402 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
47403 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT 0
47405 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000)
47407 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
47409 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
47412 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
47415 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
47417 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
47419 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
47421 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
47423 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1)…
47425 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
47430 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
47431 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT 0
47433 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000)
47435 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
47437 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
47440 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
47443 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 2…
47445 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 2…
47447 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 2…
47449 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 2…
47451 …RM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
47453 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29)
47458 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
47459 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT 0
47461 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000)
47463 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
47465 #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
47468 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe000000…
47471 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << …
47473 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << …
47475 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << …
47477 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << …
47479 …M_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
47481 …#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) …
47499 * A value of 0xfff is considered invalid and implies the
47502 #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
47539 * * 0x0-0xFFF8 - The function ID
47540 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47541 * * 0xFFFD - Reserved for user-space HWRM interface
47542 * * 0xFFFF - HWRM
47558 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
47560 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
47562 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
47568 * A value of 0xfff is considered invalid and implies the
47571 #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
47622 * * 0x0-0xFFF8 - The function ID
47623 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47624 * * 0xFFFD - Reserved for user-space HWRM interface
47625 * * 0xFFFF - HWRM
47641 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
47643 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
47645 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
47650 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 UINT32_C(0x0)
47652 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 UINT32_C(0x1)
47654 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 UINT32_C(0x2)
47659 * A value of 0xfff is considered invalid and implies the
47662 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
47666 * It shall be set to 0.
47672 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
47673 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT 0
47675 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE UINT32_C(0x10000000)
47677 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
47679 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
47682 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
47685 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
47687 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
47689 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
47691 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
47693 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <<…
47695 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29)
47700 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
47701 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT 0
47703 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE UINT32_C(0x10000000)
47705 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
47707 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
47710 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
47713 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
47715 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
47717 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
47719 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
47721 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) <…
47723 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) << 29)
47728 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK UINT32_C(0xfffffff)
47729 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT 0
47731 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE UINT32_C(0x10000000)
47733 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS (UINT32_C(0x0) << 28)
47735 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES (UINT32_C(0x1) << 28)
47738 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
47741 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
47743 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
47745 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
47747 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
47749 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x…
47751 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW (UINT32_C(0x7) << 29)
47756 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK UINT32_C(0xfffffff)
47757 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT 0
47759 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE UINT32_C(0x10000000)
47761 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS (UINT32_C(0x0) << 28)
47763 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES (UINT32_C(0x1) << 28)
47766 #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK UINT32_C(0xe0000000)
47769 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA (UINT32_C(0x0) << 29)
47771 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO (UINT32_C(0x2) << 29)
47773 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE (UINT32_C(0x4) << 29)
47775 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA (UINT32_C(0x6) << 29)
47777 …WRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 (UINT32_C(0x1) << 29)
47779 …#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID (UINT32_C(0x7) <<…
47829 * * 0x0-0xFFF8 - The function ID
47830 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47831 * * 0xFFFD - Reserved for user-space HWRM interface
47832 * * 0xFFFF - HWRM
47848 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
47850 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
47852 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
47858 * A value of 0xffff is considered invalid and implies the
47861 #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
47880 * A value of 0xffff is considered invalid and implies the
47883 #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
47920 * * 0x0-0xFFF8 - The function ID
47921 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
47922 * * 0xFFFD - Reserved for user-space HWRM interface
47923 * * 0xFFFF - HWRM
47939 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
47941 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
47943 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
47952 * A value of 0xffff is considered invalid and implies the
47955 #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID UINT32_C(0xffff)
48011 * * 0x0-0xFFF8 - The function ID
48012 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48013 * * 0xFFFD - Reserved for user-space HWRM interface
48014 * * 0xFFFF - HWRM
48030 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
48032 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
48034 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
48040 * A value of 0xfff is considered invalid and implies the
48043 #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID UINT32_C(0xffff)
48094 * * 0x0-0xFFF8 - The function ID
48095 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48096 * * 0xFFFD - Reserved for user-space HWRM interface
48097 * * 0xFFFF - HWRM
48109 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL UINT32_C(0x1)
48115 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE UINT32_C(0x1)
48120 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID UINT32_C(0x2)
48125 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR UINT32_C(0x4)
48130 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR UINT32_C(0x8)
48135 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID UINT32_C(0x10)
48140 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID UINT32_C(0x20)
48145 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID UINT32_C(0x40)
48150 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID UINT32_C(0x80)
48155 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x100)
48160 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x200)
48165 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x400)
48170 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x800)
48175 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x1000)
48180 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x2000)
48185 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x4000)
48190 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x8000)
48195 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x10000)
48207 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
48209 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
48211 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
48213 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
48215 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
48217 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
48219 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
48221 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
48223 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
48225 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
48230 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
48231 /* Use fixed layer 2 ether type of 0xFFFF */
48232 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
48237 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
48239 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
48241 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
48286 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
48288 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
48290 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
48300 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
48302 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
48304 #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
48389 * * 0x0-0xFFF8 - The function ID
48390 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48391 * * 0xFFFD - Reserved for user-space HWRM interface
48392 * * 0xFFFF - HWRM
48453 * * 0x0-0xFFF8 - The function ID
48454 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48455 * * 0xFFFD - Reserved for user-space HWRM interface
48456 * * 0xFFFF - HWRM
48468 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1)
48470 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6)
48473 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE (UINT32_C(0x0) << 1)
48475 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE (UINT32_C(0x1) << 1)
48477 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO (UINT32_C(0x2) << 1)
48480 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38)
48483 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 (UINT32_C(0x0) << 3)
48485 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 (UINT32_C(0x1) << 3)
48487 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 (UINT32_C(0x2) << 3)
48499 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x40)
48504 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x80)
48511 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI UINT32_C(0x100)
48516 #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN UINT32_C(0x200)
48529 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD UINT32_C(0x1)
48531 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE UINT32_C(0x2)
48536 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP UINT32_C(0x4)
48538 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER UINT32_C(0x8)
48540 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL UINT32_C(0x10)
48542 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC UINT32_C(0x20)
48544 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST UINT32_C(0x40)
48546 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS UINT32_C(0x80)
48548 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE UINT32_C(0x100)
48550 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT UINT32_C(0x200)
48557 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP UINT32_C(0x400)
48559 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED UINT32_C(0x800)
48562 * to the most optimal flow table resource. If set to 0, the flow
48565 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT UINT32_C(0x1000)
48568 * to offload this flow. If set to 0, which will keep compatibility
48574 #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC UINT32_C(0x2000)
48628 * 0 values are ignored.
48636 * 0 values are ignored.
48646 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
48648 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
48650 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
48652 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
48654 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
48656 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
48658 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
48660 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
48662 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
48664 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
48669 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
48670 /* Use fixed layer 2 ether type of 0xFFFF */
48671 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
48676 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
48678 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
48680 #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
48699 * The flow id value in bit 0-29 is the actual ID of the flow
48702 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
48707 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
48708 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
48710 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
48712 * If this bit set to 0, then it indicates that the flow is
48715 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
48720 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
48723 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
48724 /* If this bit set to 0, then it indicates rx flow. */
48725 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
48727 #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
48753 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
48755 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
48757 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
48759 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
48761 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
48763 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
48765 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
48767 #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
48795 * * 0x0-0xFFF8 - The function ID
48796 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
48797 * * 0xFFFD - Reserved for user-space HWRM interface
48798 * * 0xFFFF - HWRM
48849 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD UINT32_C(0x1)
48851 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE UINT32_C(0x2)
48853 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP UINT32_C(0x4)
48855 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER UINT32_C(0x8)
48857 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL UINT32_C(0x10)
48863 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP UINT32_C(0x20)
48865 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT UINT32_C(0x40)
48867 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED UINT32_C(0x80)
48869 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP UINT32_C(0x100)
48871 #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP UINT32_C(0x200)
48886 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
48888 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
48890 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
48892 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
48894 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
48896 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
48898 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
48900 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
48902 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
48907 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
48908 /* Use fixed layer 2 ether type of 0xFFFF */
48909 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
48914 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
48916 #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE UINT32_C(0x10)
48929 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
48931 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
48933 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
48935 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
48937 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP UINT32_C(0x4)
48939 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
48941 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS UINT32_C(0x6)
48943 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT UINT32_C(0x7)
48945 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
48947 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
48952 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
48953 /* Use fixed layer 2 ether type of 0xFFFF */
48954 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
48959 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
48961 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
48963 #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
49086 * * 0x0-0xFFF8 - The function ID
49087 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49088 * * 0xFFFD - Reserved for user-space HWRM interface
49089 * * 0xFFFF - HWRM
49102 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK UINT32_C(0xfff)
49104 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT UINT32_C(0x1000)
49106 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT UINT32_C(0x2000)
49108 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_TX UINT32_C(0x3000)
49110 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT UINT32_C(0x4000)
49112 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX UINT32_C(0x8000)
49114 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT_RX UINT32_C(0x9000)
49116 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT_RX UINT32_C(0xa000)
49118 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_RX UINT32_C(0xb000)
49120 #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX UINT32_C(0xc000)
49140 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
49142 #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
49205 * * 0x0-0xFFF8 - The function ID
49206 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49207 * * 0xFFFD - Reserved for user-space HWRM interface
49208 * * 0xFFFF - HWRM
49224 * specified. This flag is set to 0 by older driver. For older
49227 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID UINT32_C(0x1)
49231 * 0 by older driver. For older firmware, setting this flag has no
49234 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL UINT32_C(0x2)
49237 * flows by the caller. This flag is set to 0 by older driver. For
49240 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT UINT32_C(0x4)
49245 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC UINT32_C(0x8000000)
49251 #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK UINT32_C(0xc0000000)
49254 …#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT (UINT32_C(0x0) << 3…
49256 …#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT (UINT32_C(0x1) << 3…
49261 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
49263 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
49265 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
49267 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
49269 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
49271 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
49273 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
49275 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
49280 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
49282 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
49287 #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
49341 * * 0x0-0xFFF8 - The function ID
49342 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49343 * * 0xFFFD - Reserved for user-space HWRM interface
49344 * * 0xFFFF - HWRM
49493 * will be 0. Mapping will match flow numbers where bitX is for flowX
49494 * (ex: bit 0 is flow0). This only applies for NIC flows. Upon
49534 * * 0x0-0xFFF8 - The function ID
49535 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49536 * * 0xFFFD - Reserved for user-space HWRM interface
49537 * * 0xFFFF - HWRM
49605 * * 0x0-0xFFF8 - The function ID
49606 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49607 * * 0xFFFD - Reserved for user-space HWRM interface
49608 * * 0xFFFF - HWRM
49624 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER UINT32_C(0x1)
49629 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER UINT32_C(0x2)
49634 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER UINT32_C(0x4)
49639 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL UINT32_C(0x8)
49644 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL UINT32_C(0x10)
49649 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES UINT32_C(0x20)
49654 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID UINT32_C(0x40)
49659 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE UINT32_C(0x80)
49662 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
49664 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
49666 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
49672 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
49674 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE (UINT32_C(0x0) << 1)
49676 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE (UINT32_C(0x1) << 1)
49713 #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA UINT32_C(0x0)
49764 * * 0x0-0xFFF8 - The function ID
49765 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49766 * * 0xFFFD - Reserved for user-space HWRM interface
49767 * * 0xFFFF - HWRM
49783 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
49785 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
49787 #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
49869 * * 0x0-0xFFF8 - The function ID
49870 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49871 * * 0xFFFD - Reserved for user-space HWRM interface
49872 * * 0xFFFF - HWRM
49888 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
49890 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
49892 #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
49960 * * 0x0-0xFFF8 - The function ID
49961 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
49962 * * 0xFFFD - Reserved for user-space HWRM interface
49963 * * 0xFFFF - HWRM
49986 /* The port 0 RX mirror action record ID. */
49991 * The port 0 RX action record ID for TX TCP flag packets from
50035 * * 0x0-0xFFF8 - The function ID
50036 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50037 * * 0xFFFD - Reserved for user-space HWRM interface
50038 * * 0xFFFF - HWRM
50048 /* Logical VF number (range: 0 -> MAX_VFS -1). */
50050 /* Logical VF number (range: 0 -> MAX_VFS -1). */
50103 * * 0x0-0xFFF8 - The function ID
50104 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50105 * * 0xFFFD - Reserved for user-space HWRM interface
50106 * * 0xFFFF - HWRM
50166 * * 0x0-0xFFF8 - The function ID
50167 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50168 * * 0xFFFD - Reserved for user-space HWRM interface
50169 * * 0xFFFF - HWRM
50181 #define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
50213 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
50215 #define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
50255 * * 0x0-0xFFF8 - The function ID
50256 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50257 * * 0xFFFD - Reserved for user-space HWRM interface
50258 * * 0xFFFF - HWRM
50269 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
50277 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
50282 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
50287 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
50289 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
50291 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
50293 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
50298 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
50303 #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
50305 /* Logical VF number (range: 0 -> MAX_VFS -1). */
50307 /* Logical Host (0xff-local host). */
50309 /* Logical PF (0xff-PF for command channel). */
50311 /* Logical VF number (range: 0 -> MAX_VFS -1). */
50313 /* Loopback port (0xff-internal loopback), valid for mode-3. */
50324 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)
50329 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)
50334 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)
50339 #define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)
50345 * the interface pair. The default value is 0.
50355 * Specifies whether RX ring flow control is disabled (0) or enabled
50356 * (1) in the A to B direction. The default value is 0, meaning that
50361 * Specifies whether RX ring flow control is disabled (0) or enabled
50424 * * 0x0-0xFFF8 - The function ID
50425 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50426 * * 0xFFFD - Reserved for user-space HWRM interface
50427 * * 0xFFFF - HWRM
50439 /* Logical PF (0xff-PF for command channel). */
50442 /* Logical VF number (range: 0 -> MAX_VFS -1). */
50445 * Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair,
50453 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
50458 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
50463 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
50465 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)
50467 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
50469 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)
50474 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)
50479 #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)
50529 * * 0x0-0xFFF8 - The function ID
50530 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50531 * * 0xFFFD - Reserved for user-space HWRM interface
50532 * * 0xFFFF - HWRM
50544 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
50546 #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
50594 /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */
50600 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)
50605 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)
50610 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)
50612 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)
50614 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)
50619 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)
50621 #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)
50660 * * 0x0-0xFFF8 - The function ID
50661 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50662 * * 0xFFFD - Reserved for user-space HWRM interface
50663 * * 0xFFFF - HWRM
50673 /* Logical VF number (range: 0 -> MAX_VFS -1). */
50677 * It shall be set to 0.
50735 * * 0x0-0xFFF8 - The function ID
50736 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50737 * * 0xFFFD - Reserved for user-space HWRM interface
50738 * * 0xFFFF - HWRM
50750 /* Logical VF number (range: 0 -> MAX_VFS -1). */
50754 * It shall be set to 0.
50806 * * 0x0-0xFFF8 - The function ID
50807 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50808 * * 0xFFFD - Reserved for user-space HWRM interface
50809 * * 0xFFFF - HWRM
50838 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL UINT32_C(0x1)
50840 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN UINT32_C(0x2)
50842 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE UINT32_C(0x4)
50844 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE UINT32_C(0x8)
50846 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP UINT32_C(0x10)
50848 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE UINT32_C(0x20)
50850 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS UINT32_C(0x40)
50852 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT UINT32_C(0x80)
50854 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE UINT32_C(0x100)
50856 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 UINT32_C(0x200)
50861 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 UINT32_C(0x400)
50863 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL UINT32_C(0x800)
50864 /* Use fixed layer 2 ether type of 0xFFFF */
50865 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE UINT32_C(0x1000)
50870 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 UINT32_C(0x2000)
50872 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE UINT32_C(0x4000)
50908 * * 0x0-0xFFF8 - The function ID
50909 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
50910 * * 0xFFFD - Reserved for user-space HWRM interface
50911 * * 0xFFFF - HWRM
50925 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
50927 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
50932 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
50937 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
50939 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
50941 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
50943 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
50945 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
50947 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
50949 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
50951 #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
51009 * * 0x0-0xFFF8 - The function ID
51010 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51011 * * 0xFFFD - Reserved for user-space HWRM interface
51012 * * 0xFFFF - HWRM
51076 * * 0x0-0xFFF8 - The function ID
51077 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51078 * * 0xFFFD - Reserved for user-space HWRM interface
51079 * * 0xFFFF - HWRM
51112 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
51114 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
51119 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
51124 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
51126 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
51128 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
51130 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
51132 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
51134 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
51136 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
51138 #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
51178 * * 0x0-0xFFF8 - The function ID
51179 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51180 * * 0xFFFD - Reserved for user-space HWRM interface
51181 * * 0xFFFF - HWRM
51244 * * 0x0-0xFFF8 - The function ID
51245 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51246 * * 0xFFFD - Reserved for user-space HWRM interface
51247 * * 0xFFFF - HWRM
51272 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT UINT32_C(0x1)
51274 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_NONE UINT32_C(0x0)
51276 #define HWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT UINT32_C(0x1)
51379 * * 0x0-0xFFF8 - The function ID
51380 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51381 * * 0xFFFD - Reserved for user-space HWRM interface
51382 * * 0xFFFF - HWRM
51394 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE UINT32_C(0x1)
51396 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE UINT32_C(0x0)
51398 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE UINT32_C(0x1)
51401 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x2)
51403 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX (UINT32_C(0x0) << 1)
51405 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX (UINT32_C(0x1) << 1)
51408 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK UINT32_C(0xc)
51411 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH (UINT32_C(0x0) << 2)
51413 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL (UINT32_C(0x1) << 2)
51415 #define HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC (UINT32_C(0x2) << 2)
51419 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_FC UINT32_C(0x0)
51421 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_EFC UINT32_C(0x1)
51423 #define HWRM_CFA_COUNTER_CFG_INPUT_COUNTER_TYPE_MDC UINT32_C(0x2)
51480 * * 0x0-0xFFF8 - The function ID
51481 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51482 * * 0xFFFD - Reserved for user-space HWRM interface
51483 * * 0xFFFF - HWRM
51495 #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
51497 #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
51499 #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
51502 #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_MASK UINT32_C(0x6)
51505 #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PUSH (UINT32_C(0x0) << 1)
51507 #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL (UINT32_C(0x1) << 1)
51509 #define HWRM_CFA_COUNTER_QCFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL_ASYNC (UINT32_C(0x2) << 1)
51564 * * 0x0-0xFFF8 - The function ID
51565 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51566 * * 0xFFFD - Reserved for user-space HWRM interface
51567 * * 0xFFFF - HWRM
51579 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH UINT32_C(0x1)
51581 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
51583 #define HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
51641 * * 0x0-0xFFF8 - The function ID
51642 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51643 * * 0xFFFD - Reserved for user-space HWRM interface
51644 * * 0xFFFF - HWRM
51660 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
51666 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
51668 #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4)
51689 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
51695 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
51701 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x4)
51709 #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED UINT32_C(0x8)
51714 * If set to 0, EEM KEY0 table is not supported.
51716 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE UINT32_C(0x1)
51719 * If set to 0, EEM KEY1 table is not supported.
51721 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE UINT32_C(0x2)
51724 * If set to 0, EEM External Record table is not supported.
51727 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE UINT32_C(0x4)
51730 * If set to 0, EEM External Flow Counters table is not supported.
51732 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE UINT32_C(0x8)
51736 * If set to 0, then FID table used for implicit flow flush is
51739 #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE UINT32_C(0x10)
51793 * * 0x0-0xFFF8 - The function ID
51794 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51795 * * 0xFFFD - Reserved for user-space HWRM interface
51796 * * 0xFFFF - HWRM
51812 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
51818 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
51820 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4)
51821 /* When set to 1, secondary, 0 means primary. */
51822 #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF UINT32_C(0x8)
51897 * * 0x0-0xFFF8 - The function ID
51898 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51899 * * 0xFFFD - Reserved for user-space HWRM interface
51900 * * 0xFFFF - HWRM
51912 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
51914 #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
51931 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
51933 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
51935 #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD UINT32_C(0x4)
51983 * * 0x0-0xFFF8 - The function ID
51984 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
51985 * * 0xFFFD - Reserved for user-space HWRM interface
51986 * * 0xFFFF - HWRM
52002 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
52008 #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
52013 #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
52020 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
52027 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
52032 #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
52082 * * 0x0-0xFFF8 - The function ID
52083 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52084 * * 0xFFFD - Reserved for user-space HWRM interface
52085 * * 0xFFFF - HWRM
52112 * Value of 0 to indicate firmware not support 16-bit flow handle.
52114 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED UINT32_C(0x1)
52117 * Value of 0 to indicate firmware not support 64-bit flow handle.
52119 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED UINT32_C(0x2)
52123 * Value of 0 to indicate that the firmware does not support flow
52126 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED UINT32_C(0x4)
52130 * Value of 0 indicates firmware does not support flow reset all
52133 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED UINT32_C(0x8)
52137 * Value of 0 indicates firmware does not support use of FID as
52140 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED UINT32_C(0x10)
52143 * Value of 0 indicates firmware does not support TX EEM flows.
52146 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED UINT32_C(0x20)
52149 * Value of 0 indicates firmware does not support RX EEM flows.
52152 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED UINT32_C(0x40)
52156 * flows. Value of 0 indicates firmware does not support the dynamic
52160 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED UINT32_C(0x80)
52164 * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
52166 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED UINT32_C(0x100)
52169 * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
52172 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED UINT32_C(0x200)
52175 * of 0 indicates firmware does not support XDP filter.
52177 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED UINT32_C(0x400)
52181 * Value of 0 indicates firmware does not support L2 header source
52184 …#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED UINT32_C(0x80…
52188 * RX direction. By default, this flag should be 0 for older version
52191 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED UINT32_C(0x1000)
52195 * command. Value of 0 indicates firmware does not support
52198 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED UINT32_C(0x2000)
52202 * direction. By default, this flag should be 0 for older version
52205 …#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED UINT32_C(0…
52211 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE UINT32_C(0x8000)
52215 * By default, this flag should be 0 for older version of firmware.
52217 …WRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED UINT32_C(0x10000)
52222 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_LAG_SUPPORTED UINT32_C(0x20000)
52227 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED UINT32_C(0x40000)
52230 * in cfa_flow_stats command where flow_handle value 0xF000.
52232 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED UINT32_C(0x80000)
52236 * this flag should be 0 for older version of firmware.
52238 …#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED UINT32_C(0…
52242 * Value of 0 indicates ring tbl idx should be passed using dst_id.
52244 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED UINT32_C(0x200000)
52280 * * 0x0-0xFFF8 - The function ID
52281 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52282 * * 0xFFFD - Reserved for user-space HWRM interface
52283 * * 0xFFFF - HWRM
52358 * * 0x0-0xFFF8 - The function ID
52359 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52360 * * 0xFFFD - Reserved for user-space HWRM interface
52361 * * 0xFFFF - HWRM
52376 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_ACTIVE_BACKUP UINT32_C(0x1)
52387 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BALANCE_XOR UINT32_C(0x2)
52389 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR_INPUT_MODE_BROADCAST UINT32_C(0x3)
52392 * Supports up to 5 ports. bit0 = port 0, bit1 = port 1,
52449 * * 0x0-0xFFF8 - The function ID
52450 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52451 * * 0xFFFD - Reserved for user-space HWRM interface
52452 * * 0xFFFF - HWRM
52513 * * 0x0-0xFFF8 - The function ID
52514 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52515 * * 0xFFFD - Reserved for user-space HWRM interface
52516 * * 0xFFFF - HWRM
52532 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID UINT32_C(0x1)
52537 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE UINT32_C(0x2)
52542 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE UINT32_C(0x4)
52547 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR UINT32_C(0x8)
52552 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR UINT32_C(0x10)
52557 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL UINT32_C(0x20)
52562 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT UINT32_C(0x40)
52567 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_PORT UINT32_C(0x80)
52572 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_KID UINT32_C(0x100)
52577 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_DST_ID UINT32_C(0x200)
52582 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID UINT32_C(0x400)
52587 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_ENABLES_QUIC_DST_CONNECT_ID UINT32_C(0x800)
52604 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)
52606 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)
52608 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)
52618 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)
52620 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)
52622 #define HWRM_CFA_TLS_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)
52680 * The flow id value in bit 0-29 is the actual ID of the flow
52683 * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
52688 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK UINT32_C(0x3fffffff)
52689 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
52691 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE UINT32_C(0x40000000)
52693 * If this bit set to 0, then it indicates that the flow is
52696 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT (UINT32_C(0x0) << 30)
52701 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT (UINT32_C(0x1) << 30)
52704 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR UINT32_C(0x80000000)
52705 /* If this bit set to 0, then it indicates rx flow. */
52706 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX (UINT32_C(0x0) << 31)
52708 #define HWRM_CFA_TLS_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX (UINT32_C(0x1) << 31)
52745 * * 0x0-0xFFF8 - The function ID
52746 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52747 * * 0xFFFD - Reserved for user-space HWRM interface
52748 * * 0xFFFF - HWRM
52808 * * 0x0-0xFFF8 - The function ID
52809 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52810 * * 0xFFFD - Reserved for user-space HWRM interface
52811 * * 0xFFFF - HWRM
52828 #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_EFID UINT32_C(0x1)
52830 #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_RFID UINT32_C(0x2)
52832 #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_TYPE_DFID UINT32_C(0x3)
52841 #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_BC_REM UINT32_C(0x1)
52843 #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_MC_REM UINT32_C(0x2)
52845 #define HWRM_CFA_RELEASE_AFM_FUNC_INPUT_FLAGS_PROMISC_REM UINT32_C(0x4)
52895 * * 0x0-0xFFF8 - The function ID
52896 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52897 * * 0xFFFD - Reserved for user-space HWRM interface
52898 * * 0xFFFF - HWRM
52973 * * 0x0-0xFFF8 - The function ID
52974 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
52975 * * 0xFFFD - Reserved for user-space HWRM interface
52976 * * 0xFFFF - HWRM
53048 * * 0x0-0xFFF8 - The function ID
53049 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53050 * * 0xFFFD - Reserved for user-space HWRM interface
53051 * * 0xFFFF - HWRM
53091 * should be 1. The AFM session's fw_rm_client_id is 0.
53093 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION UINT32_C(0x1)
53095 * If this bit set to 0, then it indicates the shared session
53098 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_NOT_CREATOR UINT32_C(0x0)
53103 #define HWRM_TF_SESSION_OPEN_OUTPUT_FLAGS_SHARED_SESSION_CREATOR UINT32_C(0x1)
53141 * * 0x0-0xFFF8 - The function ID
53142 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53143 * * 0xFFFD - Reserved for user-space HWRM interface
53144 * * 0xFFFF - HWRM
53222 * * 0x0-0xFFF8 - The function ID
53223 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53224 * * 0xFFFD - Reserved for user-space HWRM interface
53225 * * 0xFFFF - HWRM
53294 * * 0x0-0xFFF8 - The function ID
53295 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53296 * * 0xFFFD - Reserved for user-space HWRM interface
53297 * * 0xFFFF - HWRM
53360 * * 0x0-0xFFF8 - The function ID
53361 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53362 * * 0xFFFD - Reserved for user-space HWRM interface
53363 * * 0xFFFF - HWRM
53396 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_GFID_EN UINT32_C(0x1)
53402 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_ABCR_VTAG_DLT_BOTH UINT32_C(0x2)
53408 #define HWRM_TF_SESSION_QCFG_OUTPUT_RX_ACT_FLAGS_TECT_SMAC_OVR_RUTNSL2 UINT32_C(0x4)
53412 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_ABCR_VEB_EN UINT32_C(0x1)
53417 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_GRE_SET_K UINT32_C(0x2)
53424 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV6_TC_IH UINT32_C(0x4)
53430 #define HWRM_TF_SESSION_QCFG_OUTPUT_TX_ACT_FLAGS_TECT_IPV4_TOS_IH UINT32_C(0x8)
53467 * * 0x0-0xFFF8 - The function ID
53468 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53469 * * 0xFFFD - Reserved for user-space HWRM interface
53470 * * 0xFFFF - HWRM
53485 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR UINT32_C(0x1)
53486 /* If this bit set to 0, then it indicates rx flow. */
53487 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
53489 #define HWRM_TF_SESSION_RESC_QCAPS_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
53521 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_MASK UINT32_C(0x3)
53522 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_SFT 0
53524 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_STATIC UINT32_C(0x0)
53526 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_1 UINT32_C(0x1)
53528 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_2 UINT32_C(0x2)
53530 #define HWRM_TF_SESSION_RESC_QCAPS_OUTPUT_FLAGS_SESS_RESV_STRATEGY_3 UINT32_C(0x3)
53581 * * 0x0-0xFFF8 - The function ID
53582 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53583 * * 0xFFFD - Reserved for user-space HWRM interface
53584 * * 0xFFFF - HWRM
53599 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
53600 /* If this bit set to 0, then it indicates rx flow. */
53601 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
53603 #define HWRM_TF_SESSION_RESC_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
53681 * * 0x0-0xFFF8 - The function ID
53682 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53683 * * 0xFFFD - Reserved for user-space HWRM interface
53684 * * 0xFFFF - HWRM
53699 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR UINT32_C(0x1)
53700 /* If this bit set to 0, then it indicates rx flow. */
53701 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
53703 #define HWRM_TF_SESSION_RESC_FLUSH_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
53766 * * 0x0-0xFFF8 - The function ID
53767 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53768 * * 0xFFFD - Reserved for user-space HWRM interface
53769 * * 0xFFFF - HWRM
53784 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR UINT32_C(0x1)
53785 /* If this bit set to 0, then it indicates rx flow. */
53786 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
53788 #define HWRM_TF_SESSION_RESC_INFO_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
53890 * * 0x0-0xFFF8 - The function ID
53891 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53892 * * 0xFFFD - Reserved for user-space HWRM interface
53893 * * 0xFFFF - HWRM
53908 #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
53909 /* If this bit set to 0, then it indicates rx flow. */
53910 #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
53912 #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
53917 #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
53919 #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
53921 #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
53923 #define HWRM_TF_TBL_TYPE_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
53987 * * 0x0-0xFFF8 - The function ID
53988 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
53989 * * 0xFFFD - Reserved for user-space HWRM interface
53990 * * 0xFFFF - HWRM
54005 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
54006 /* If this bit set to 0, then it indicates rx flow. */
54007 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54009 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
54015 #define HWRM_TF_TBL_TYPE_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2)
54019 #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
54021 #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
54023 #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
54025 #define HWRM_TF_TBL_TYPE_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
54093 * * 0x0-0xFFF8 - The function ID
54094 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54095 * * 0xFFFD - Reserved for user-space HWRM interface
54096 * * 0xFFFF - HWRM
54111 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
54112 /* If this bit set to 0, then it indicates rx flow. */
54113 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54115 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
54118 #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
54122 #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
54124 #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
54126 #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
54128 #define HWRM_TF_TBL_TYPE_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
54194 * * 0x0-0xFFF8 - The function ID
54195 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54196 * * 0xFFFD - Reserved for user-space HWRM interface
54197 * * 0xFFFF - HWRM
54212 #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
54213 /* If this bit set to 0, then it indicates rx flow. */
54214 #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54216 #define HWRM_TF_TBL_TYPE_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
54221 #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
54223 #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
54225 #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
54227 #define HWRM_TF_TBL_TYPE_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
54289 * * 0x0-0xFFF8 - The function ID
54290 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54291 * * 0xFFFD - Reserved for user-space HWRM interface
54292 * * 0xFFFF - HWRM
54307 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
54308 /* If this bit set to 0, then it indicates rx flow. */
54309 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54311 #define HWRM_TF_EM_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
54340 /* EM record offset 0~3. */
54380 * * 0x0-0xFFF8 - The function ID
54381 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54382 * * 0xFFFD - Reserved for user-space HWRM interface
54383 * * 0xFFFF - HWRM
54398 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR UINT32_C(0x1)
54399 /* If this bit set to 0, then it indicates rx flow. */
54400 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54402 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
54405 #define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DMA UINT32_C(0x2)
54433 /* EM record offset 0~3. */
54473 * * 0x0-0xFFF8 - The function ID
54474 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54475 * * 0xFFFD - Reserved for user-space HWRM interface
54476 * * 0xFFFF - HWRM
54491 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR UINT32_C(0x1)
54492 /* If this bit set to 0, then it indicates rx flow. */
54493 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54495 #define HWRM_TF_EM_DELETE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
54558 * * 0x0-0xFFF8 - The function ID
54559 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54560 * * 0xFFFD - Reserved for user-space HWRM interface
54561 * * 0xFFFF - HWRM
54576 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
54577 /* If this bit set to 0, then it indicates rx flow. */
54578 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54580 #define HWRM_TF_EM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
54641 * * 0x0-0xFFF8 - The function ID
54642 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54643 * * 0xFFFD - Reserved for user-space HWRM interface
54644 * * 0xFFFF - HWRM
54659 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
54660 /* If this bit set to 0, then it indicates rx flow. */
54661 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54663 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
54669 #define HWRM_TF_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
54683 * array, key offset is always 0.
54691 * TCAM key located at offset 0, mask located at mask_offset
54744 * * 0x0-0xFFF8 - The function ID
54745 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54746 * * 0xFFFD - Reserved for user-space HWRM interface
54747 * * 0xFFFF - HWRM
54762 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
54763 /* If this bit set to 0, then it indicates rx flow. */
54764 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54766 #define HWRM_TF_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
54801 * TCAM key located at offset 0, mask located at mask_offset
54841 * * 0x0-0xFFF8 - The function ID
54842 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54843 * * 0xFFFD - Reserved for user-space HWRM interface
54844 * * 0xFFFF - HWRM
54859 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR UINT32_C(0x1)
54860 /* If this bit set to 0, then it indicates rx flow. */
54861 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54863 #define HWRM_TF_TCAM_MOVE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
54925 * * 0x0-0xFFF8 - The function ID
54926 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
54927 * * 0xFFFD - Reserved for user-space HWRM interface
54928 * * 0xFFFF - HWRM
54943 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
54944 /* If this bit set to 0, then it indicates rx flow. */
54945 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
54947 #define HWRM_TF_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
55009 * * 0x0-0xFFF8 - The function ID
55010 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55011 * * 0xFFFD - Reserved for user-space HWRM interface
55012 * * 0xFFFF - HWRM
55027 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
55028 /* If this bit set to 0, then it indicates rx flow. */
55029 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
55031 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
55034 #define HWRM_TF_GLOBAL_CFG_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
55045 /* Mask of data to set, 0 indicates no mask */
55096 * * 0x0-0xFFF8 - The function ID
55097 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55098 * * 0xFFFD - Reserved for user-space HWRM interface
55099 * * 0xFFFF - HWRM
55114 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
55115 /* If this bit set to 0, then it indicates rx flow. */
55116 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
55118 #define HWRM_TF_GLOBAL_CFG_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
55183 * * 0x0-0xFFF8 - The function ID
55184 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55185 * * 0xFFFD - Reserved for user-space HWRM interface
55186 * * 0xFFFF - HWRM
55201 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
55202 /* If this bit set to 0, then it indicates rx flow. */
55203 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
55205 #define HWRM_TF_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
55273 * * 0x0-0xFFF8 - The function ID
55274 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55275 * * 0xFFFD - Reserved for user-space HWRM interface
55276 * * 0xFFFF - HWRM
55291 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
55292 /* If this bit set to 0, then it indicates rx flow. */
55293 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
55295 #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
55361 * * 0x0-0xFFF8 - The function ID
55362 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55363 * * 0xFFFD - Reserved for user-space HWRM interface
55364 * * 0xFFFF - HWRM
55379 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
55380 /* If this bit set to 0, then it indicates rx flow. */
55381 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
55383 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
55389 #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2)
55458 * * 0x0-0xFFF8 - The function ID
55459 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55460 * * 0xFFFD - Reserved for user-space HWRM interface
55461 * * 0xFFFF - HWRM
55478 #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
55479 /* If this bit set to 0, then it indicates rx flow. */
55480 #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
55482 #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
55533 * * 0x0-0xFFF8 - The function ID
55534 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55535 * * 0xFFFD - Reserved for user-space HWRM interface
55536 * * 0xFFFF - HWRM
55551 #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
55552 /* If this bit set to 0, then it indicates rx flow. */
55553 #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
55555 #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
55612 * * 0x0-0xFFF8 - The function ID
55613 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55614 * * 0xFFFD - Reserved for user-space HWRM interface
55615 * * 0xFFFF - HWRM
55630 #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
55631 /* If this bit set to 0, then it indicates rx flow. */
55632 #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
55634 #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
55637 #define HWRM_TF_RESC_USAGE_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
55641 #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_WC_TCAM UINT32_C(0x1)
55643 #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_EM UINT32_C(0x2)
55645 #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_METER UINT32_C(0x4)
55647 #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_COUNTER UINT32_C(0x8)
55649 #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACTION UINT32_C(0x10)
55651 #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ACT_MOD_ENCAP UINT32_C(0x20)
55653 #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_SP_SMAC UINT32_C(0x40)
55655 #define HWRM_TF_RESC_USAGE_SET_INPUT_TYPES_ALL UINT32_C(0x80)
55711 * * 0x0-0xFFF8 - The function ID
55712 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55713 * * 0xFFFD - Reserved for user-space HWRM interface
55714 * * 0xFFFF - HWRM
55729 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR UINT32_C(0x1)
55730 /* If this bit set to 0, then it indicates rx flow. */
55731 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
55733 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
55740 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_WC_TCAM UINT32_C(0x1)
55742 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_EM UINT32_C(0x2)
55744 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_METER UINT32_C(0x4)
55746 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_COUNTER UINT32_C(0x8)
55748 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACTION UINT32_C(0x10)
55750 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ACT_MOD_ENCAP UINT32_C(0x20)
55752 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_SP_SMAC UINT32_C(0x40)
55754 #define HWRM_TF_RESC_USAGE_QUERY_INPUT_TYPES_ALL UINT32_C(0x80)
55818 * * 0x0-0xFFF8 - The function ID
55819 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55820 * * 0xFFFD - Reserved for user-space HWRM interface
55821 * * 0xFFFF - HWRM
55885 * a fid_cnt of 0 that also means that the table scope ID has
55906 * * 0x0-0xFFF8 - The function ID
55907 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
55908 * * 0xFFFD - Reserved for user-space HWRM interface
55909 * * 0xFFFF - HWRM
55924 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
55946 /* Application type. 0 (AFM), 1 (TF) */
56007 * * 0x0-0xFFF8 - The function ID
56008 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56009 * * 0xFFFD - Reserved for user-space HWRM interface
56010 * * 0xFFFF - HWRM
56118 * * 0x0-0xFFF8 - The function ID
56119 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56120 * * 0xFFFD - Reserved for user-space HWRM interface
56121 * * 0xFFFF - HWRM
56185 * * 0x0-0xFFF8 - The function ID
56186 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56187 * * 0xFFFD - Reserved for user-space HWRM interface
56188 * * 0xFFFF - HWRM
56203 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
56263 * * 0x0-0xFFF8 - The function ID
56264 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56265 * * 0xFFFD - Reserved for user-space HWRM interface
56266 * * 0xFFFF - HWRM
56281 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
56327 * to 0), will result in this session id being freed automatically.
56347 * * 0x0-0xFFF8 - The function ID
56348 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56349 * * 0xFFFD - Reserved for user-space HWRM interface
56350 * * 0xFFFF - HWRM
56365 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
56429 * * 0x0-0xFFF8 - The function ID
56430 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56431 * * 0xFFFD - Reserved for user-space HWRM interface
56432 * * 0xFFFF - HWRM
56447 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
56495 * (fid_cnt goes to 0), will result in this session id being freed
56516 * * 0x0-0xFFF8 - The function ID
56517 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56518 * * 0xFFFD - Reserved for user-space HWRM interface
56519 * * 0xFFFF - HWRM
56534 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
56603 * * 0x0-0xFFF8 - The function ID
56604 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56605 * * 0xFFFD - Reserved for user-space HWRM interface
56606 * * 0xFFFF - HWRM
56621 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
56633 #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
56634 /* If this bit set to 0, then it indicates rx flow. */
56635 #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
56637 #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
56647 #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
56649 #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
56651 #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
56715 * * 0x0-0xFFF8 - The function ID
56716 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56717 * * 0xFFFD - Reserved for user-space HWRM interface
56718 * * 0xFFFF - HWRM
56733 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
56750 #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
56751 /* If this bit set to 0, then it indicates rx flow. */
56752 #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
56754 #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
56807 * * 0x0-0xFFF8 - The function ID
56808 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56809 * * 0xFFFD - Reserved for user-space HWRM interface
56810 * * 0xFFFF - HWRM
56825 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
56838 #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
56839 /* If this bit set to 0, then it indicates rx flow. */
56840 #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
56842 #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
56857 #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
56859 #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
56861 #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
56866 #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
56868 #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
56870 #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
56872 #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
56928 * * 0x0-0xFFF8 - The function ID
56929 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
56930 * * 0xFFFD - Reserved for user-space HWRM interface
56931 * * 0xFFFF - HWRM
56946 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
56959 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
56960 /* If this bit set to 0, then it indicates rx flow. */
56961 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
56963 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
56969 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
56983 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
56985 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
56987 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
56992 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
56994 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
56996 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
56998 #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
57007 * Index table data located at offset 0. If dma bit is set,
57065 * * 0x0-0xFFF8 - The function ID
57066 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57067 * * 0xFFFD - Reserved for user-space HWRM interface
57068 * * 0xFFFF - HWRM
57081 #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
57082 /* If this bit set to 0, then it indicates rx flow. */
57083 #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
57085 #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
57091 #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
57102 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57121 #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
57123 #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
57125 #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
57127 #define HWRM_TFC_IDX_TBL_SET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
57134 * Index table data located at offset 0. If dma bit is set,
57187 * * 0x0-0xFFF8 - The function ID
57188 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57189 * * 0xFFFD - Reserved for user-space HWRM interface
57190 * * 0xFFFF - HWRM
57203 #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
57204 /* If this bit set to 0, then it indicates rx flow. */
57205 #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
57207 #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
57213 #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_CLEAR_ON_READ UINT32_C(0x2)
57224 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57243 #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
57245 #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
57247 #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
57249 #define HWRM_TFC_IDX_TBL_GET_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
57306 * * 0x0-0xFFF8 - The function ID
57307 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57308 * * 0xFFFD - Reserved for user-space HWRM interface
57309 * * 0xFFFF - HWRM
57322 #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
57323 /* If this bit set to 0, then it indicates rx flow. */
57324 #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
57326 #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
57338 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57352 #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_CFA UINT32_C(0x0)
57354 #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_RXP UINT32_C(0x1)
57356 #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_RE_GPARSE UINT32_C(0x2)
57358 #define HWRM_TFC_IDX_TBL_FREE_INPUT_BLKTYPE_BLKTYPE_TE_GPARSE UINT32_C(0x3)
57439 * * 0x0-0xFFF8 - The function ID
57440 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57441 * * 0xFFFD - Reserved for user-space HWRM interface
57442 * * 0xFFFF - HWRM
57457 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57543 * * 0x0-0xFFF8 - The function ID
57544 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57545 * * 0xFFFD - Reserved for user-space HWRM interface
57546 * * 0xFFFF - HWRM
57561 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57579 #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
57580 /* If this bit set to 0, then it indicates rx flow. */
57581 #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
57583 #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
57586 #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
57597 * TCAM key located at offset 0, mask located at mask_offset
57650 * * 0x0-0xFFF8 - The function ID
57651 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57652 * * 0xFFFD - Reserved for user-space HWRM interface
57653 * * 0xFFFF - HWRM
57666 #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
57667 /* If this bit set to 0, then it indicates rx flow. */
57668 #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
57670 #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
57682 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57713 * TCAM key located at offset 0, mask located at key_size
57753 * * 0x0-0xFFF8 - The function ID
57754 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57755 * * 0xFFFD - Reserved for user-space HWRM interface
57756 * * 0xFFFF - HWRM
57769 #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1)
57770 /* If this bit set to 0, then it indicates rx flow. */
57771 #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
57773 #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
57785 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57802 #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
57804 #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
57806 #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
57864 * * 0x0-0xFFF8 - The function ID
57865 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57866 * * 0xFFFD - Reserved for user-space HWRM interface
57867 * * 0xFFFF - HWRM
57880 #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
57881 /* If this bit set to 0, then it indicates rx flow. */
57882 #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
57884 #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
57887 #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2)
57898 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
57917 #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
57919 #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
57921 #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
57928 * Index table data located at offset 0. If dma bit is set,
57983 * * 0x0-0xFFF8 - The function ID
57984 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
57985 * * 0xFFFD - Reserved for user-space HWRM interface
57986 * * 0xFFFF - HWRM
57999 #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1)
58000 /* If this bit set to 0, then it indicates rx flow. */
58001 #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
58003 #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
58015 * set to 0xffff. A non-trusted VF cannot specify a valid FID in this
58075 * * 0x0-0xFFF8 - The function ID
58076 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58077 * * 0xFFFD - Reserved for user-space HWRM interface
58078 * * 0xFFFF - HWRM
58100 #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1)
58101 /* If this bit set to 0, then it indicates rx flow. */
58102 #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
58104 #define HWRM_TFC_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
58163 * * 0x0-0xFFF8 - The function ID
58164 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58165 * * 0xFFFD - Reserved for user-space HWRM interface
58166 * * 0xFFFF - HWRM
58188 #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR UINT32_C(0x1)
58189 /* If this bit set to 0, then it indicates rx flow. */
58190 #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
58192 #define HWRM_TFC_IF_TBL_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
58225 #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR UINT32_C(0x1)
58226 /* If this bit set to 0, then it indicates rx flow. */
58227 #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_RX UINT32_C(0x0)
58229 #define HWRM_TFC_IF_TBL_GET_OUTPUT_FLAGS_DIR_TX UINT32_C(0x1)
58276 * * 0x0-0xFFF8 - The function ID
58277 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58278 * * 0xFFFD - Reserved for user-space HWRM interface
58279 * * 0xFFFF - HWRM
58344 * * 0x0-0xFFF8 - The function ID
58345 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58346 * * 0xFFFD - Reserved for user-space HWRM interface
58347 * * 0xFFFF - HWRM
58364 #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR UINT32_C(0x1)
58365 /* If this bit set to 0, then it indicates rx flow. */
58366 #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_RX UINT32_C(0x0)
58368 #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_FLAGS_DIR_TX UINT32_C(0x1)
58373 #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID UINT32_C(0x0)
58375 #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_SID UINT32_C(0x1)
58377 #define HWRM_TFC_RESC_USAGE_QUERY_INPUT_TRACK_TYPE_TRACK_TYPE_FID UINT32_C(0x2)
58440 * * 0x0-0xFFF8 - The function ID
58441 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58442 * * 0xFFFD - Reserved for user-space HWRM interface
58443 * * 0xFFFF - HWRM
58456 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
58458 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
58460 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
58465 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
58466 /* Use fixed layer 2 ether type of 0xFFFF */
58467 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
58472 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
58474 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd)
58476 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe)
58478 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf)
58480 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
58482 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11)
58484 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12)
58486 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13)
58488 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14)
58490 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15)
58492 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16)
58494 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17)
58496 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18)
58498 #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19)
58533 * A value of 0 means that the destination port is not
58545 #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR0 UINT32_C(0x1)
58547 #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR1 UINT32_C(0x2)
58549 #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR2 UINT32_C(0x4)
58551 #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR3 UINT32_C(0x8)
58553 #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR4 UINT32_C(0x10)
58555 #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR5 UINT32_C(0x20)
58557 #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6 UINT32_C(0x40)
58559 #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 UINT32_C(0x80)
58566 #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_CHIP_LEVEL UINT32_C(0x1)
58571 #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_STATUS_FUNC_LEVEL UINT32_C(0x2)
58606 * * 0x0-0xFFF8 - The function ID
58607 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58608 * * 0xFFFD - Reserved for user-space HWRM interface
58609 * * 0xFFFF - HWRM
58622 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
58624 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
58626 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
58631 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
58632 /* Use fixed layer 2 ether type of 0xFFFF */
58633 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
58638 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
58643 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd)
58645 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe)
58647 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf)
58649 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
58651 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11)
58653 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12)
58655 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13)
58657 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14)
58659 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15)
58661 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16)
58663 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17)
58665 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18)
58667 #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19)
58682 * A value of 0 shall fail the command.
58707 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_SUCCESS UINT32_C(0x0)
58709 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED UINT32_C(0x1)
58711 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE UINT32_C(0x2)
58713 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ENABLED UINT32_C(0x3)
58723 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR0 UINT32_C(0x1)
58725 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR1 UINT32_C(0x2)
58727 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR2 UINT32_C(0x4)
58729 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR3 UINT32_C(0x8)
58731 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR4 UINT32_C(0x10)
58733 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR5 UINT32_C(0x20)
58735 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR6 UINT32_C(0x40)
58737 #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR7 UINT32_C(0x80)
58772 * * 0x0-0xFFF8 - The function ID
58773 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
58774 * * 0xFFFD - Reserved for user-space HWRM interface
58775 * * 0xFFFF - HWRM
58788 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
58790 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
58792 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
58797 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 UINT32_C(0xa)
58798 /* Use fixed layer 2 ether type of 0xFFFF */
58799 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE UINT32_C(0xb)
58804 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
58809 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE UINT32_C(0xd)
58811 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI UINT32_C(0xe)
58813 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 UINT32_C(0xf)
58815 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE UINT32_C(0x10)
58817 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GRE UINT32_C(0x11)
58819 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR UINT32_C(0x12)
58821 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 UINT32_C(0x13)
58823 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 UINT32_C(0x14)
58825 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 UINT32_C(0x15)
58827 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 UINT32_C(0x16)
58829 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 UINT32_C(0x17)
58831 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 UINT32_C(0x18)
58833 #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 UINT32_C(0x19)
58862 #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_SUCCESS UINT32_C(0x0)
58864 #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_OWNER UINT32_C(0x1)
58866 #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED UINT32_C(0x2)
59049 * * 0x0-0xFFF8 - The function ID
59050 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59051 * * 0xFFFD - Reserved for user-space HWRM interface
59052 * * 0xFFFF - HWRM
59071 * If update_period_ms is 0, then the stats update
59076 * if tpa v2 supported (hwrm_vnic_qcaps[max_aggs_supported]>0),
59092 * When this bit is set to '0', the statistics context shall be
59095 #define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
59105 #define HWRM_STAT_CTX_ALLOC_INPUT_FLAGS_STEERING_TAG_VALID UINT32_C(0x1)
59163 * * 0x0-0xFFF8 - The function ID
59164 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59165 * * 0xFFFD - Reserved for user-space HWRM interface
59166 * * 0xFFFF - HWRM
59228 * * 0x0-0xFFF8 - The function ID
59229 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59230 * * 0xFFFD - Reserved for user-space HWRM interface
59231 * * 0xFFFF - HWRM
59249 #define HWRM_STAT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
59338 * * 0x0-0xFFF8 - The function ID
59339 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59340 * * 0xFFFD - Reserved for user-space HWRM interface
59341 * * 0xFFFF - HWRM
59359 #define HWRM_STAT_EXT_CTX_QUERY_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
59452 * * 0x0-0xFFF8 - The function ID
59453 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59454 * * 0xFFFD - Reserved for user-space HWRM interface
59455 * * 0xFFFF - HWRM
59556 * * 0x0-0xFFF8 - The function ID
59557 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59558 * * 0xFFFD - Reserved for user-space HWRM interface
59559 * * 0xFFFF - HWRM
59619 * * 0x0-0xFFF8 - The function ID
59620 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59621 * * 0xFFFD - Reserved for user-space HWRM interface
59622 * * 0xFFFF - HWRM
59730 * * 0x0-0xFFF8 - The function ID
59731 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59732 * * 0xFFFD - Reserved for user-space HWRM interface
59733 * * 0xFFFF - HWRM
59757 #define HWRM_STAT_GENERIC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1)
59917 * * 0x0-0xFFF8 - The function ID
59918 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
59919 * * 0xFFFD - Reserved for user-space HWRM interface
59920 * * 0xFFFF - HWRM
60010 * * 0x0-0xFFF8 - The function ID
60011 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60012 * * 0xFFFD - Reserved for user-space HWRM interface
60013 * * 0xFFFF - HWRM
60026 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0)
60028 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1)
60030 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)
60032 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3)
60037 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4)
60042 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP UINT32_C(0x5)
60044 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP UINT32_C(0x6)
60049 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT UINT32_C(0x7)
60055 * status is set to a non-0x8000 value to disambiguate reset pending
60059 #define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION UINT32_C(0x8)
60064 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0)
60066 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)
60068 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
60070 #define HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTIMMEDIATE UINT32_C(0x3)
60073 * Indicate which host is being reset. 0 means first host.
60085 #define HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL UINT32_C(0x1)
60092 #define HWRM_FW_RESET_INPUT_FLAGS_FW_ACTIVATION UINT32_C(0x2)
60110 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0)
60112 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)
60114 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
60116 #define HWRM_FW_RESET_OUTPUT_SELFRST_STATUS_SELFRSTIMMEDIATE UINT32_C(0x3)
60152 * * 0x0-0xFFF8 - The function ID
60153 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60154 * * 0xFFFD - Reserved for user-space HWRM interface
60155 * * 0xFFFF - HWRM
60168 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_BOOT UINT32_C(0x0)
60170 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_MGMT UINT32_C(0x1)
60172 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_NETCTRL UINT32_C(0x2)
60174 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_ROCE UINT32_C(0x3)
60179 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_HOST UINT32_C(0x4)
60184 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_AP UINT32_C(0x5)
60186 #define HWRM_FW_QSTATUS_INPUT_EMBEDDED_PROC_TYPE_CHIP UINT32_C(0x6)
60205 #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTNONE UINT32_C(0x0)
60207 #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTASAP UINT32_C(0x1)
60209 #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPCIERST UINT32_C(0x2)
60211 #define HWRM_FW_QSTATUS_OUTPUT_SELFRST_STATUS_SELFRSTPOWER UINT32_C(0x3)
60220 #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE UINT32_C(0x0)
60222 #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET UINT32_C(0x1)
60224 #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT UINT32_C(0x2)
60226 #define HWRM_FW_QSTATUS_OUTPUT_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT UINT32_C(0x3)
60262 * * 0x0-0xFFF8 - The function ID
60263 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60264 * * 0xFFFD - Reserved for user-space HWRM interface
60265 * * 0xFFFF - HWRM
60278 #define HWRM_FW_SET_TIME_INPUT_YEAR_UNKNOWN UINT32_C(0x0)
60284 /* Current hour (0-23) */
60286 /* Current minute (0-59) */
60288 /* Current second (0-59) */
60291 /* Current millisecond (0-999) */
60293 /* Minutes east of UTC, 0xffff if TZ is not known */
60296 #define HWRM_FW_SET_TIME_INPUT_ZONE_UTC 0
60348 * * 0x0-0xFFF8 - The function ID
60349 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60350 * * 0xFFFD - Reserved for user-space HWRM interface
60351 * * 0xFFFF - HWRM
60377 #define HWRM_FW_GET_TIME_OUTPUT_YEAR_UNKNOWN UINT32_C(0x0)
60383 /* Current hour (0-23) */
60385 /* Current minute (0-59) */
60387 /* Current second (0-59) */
60390 /* Current millisecond (0-999) */
60392 /* Minutes east of UTC, 0xffff if TZ is not known */
60395 #define HWRM_FW_GET_TIME_OUTPUT_ZONE_UTC 0
60416 #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_CFG UINT32_C(0x41b)
60418 #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_ETS UINT32_C(0x41d)
60420 #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_PFC UINT32_C(0x41f)
60422 #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_APP UINT32_C(0x421)
60424 #define HWRM_STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE UINT32_C(0x422)
60429 #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_GENERIC UINT32_C(0x424)
60434 #define HWRM_STRUCT_HDR_STRUCT_ID_LLDP_DEVICE UINT32_C(0x426)
60436 #define HWRM_STRUCT_HDR_STRUCT_ID_POWER_BKUP UINT32_C(0x427)
60438 #define HWRM_STRUCT_HDR_STRUCT_ID_AFM_OPAQUE UINT32_C(0x1)
60440 #define HWRM_STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION UINT32_C(0xa)
60442 #define HWRM_STRUCT_HDR_STRUCT_ID_RSS_V2 UINT32_C(0x64)
60444 #define HWRM_STRUCT_HDR_STRUCT_ID_MSIX_PER_VF UINT32_C(0xc8)
60456 * header. A value of 0 means that this is the last element. The value is
60461 #define HWRM_STRUCT_HDR_NEXT_OFFSET_LAST UINT32_C(0x0)
60475 #define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_CONFIGURATION UINT32_C(0x1)
60477 #define HWRM_STRUCT_DATA_DCBX_ETS_DESTINATION_RECOMMMENDATION UINT32_C(0x2)
60483 /* ETS priority 0 to TC map. */
60499 /* ETS TC 0 to bandwidth map. */
60515 /* ETS TC 0 to TSA map. */
60518 #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_SP UINT32_C(0x0)
60520 #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_CBS UINT32_C(0x1)
60522 #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_ETS UINT32_C(0x2)
60524 #define HWRM_STRUCT_DATA_DCBX_ETS_TC0_TO_TSA_MAP_TSA_TYPE_VENDOR_SPECIFIC UINT32_C(0xff)
60547 * This field indicates PFC priority bit map. A value of '0' indicates
60559 * of '1' indicates MBC is enabled. A value of '0' indicates MBC is
60580 #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE UINT32_C(0x1)
60582 #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT UINT32_C(0x2)
60584 #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT UINT32_C(0x3)
60586 #define HWRM_STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT UINT32_C(0x4)
60601 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_DISABLED UINT32_C(0x0)
60603 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_IEEE UINT32_C(0x1)
60605 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_DCBX_MODE_DCBX_CEE UINT32_C(0x2)
60614 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ENABLE_BIT_POS UINT32_C(0x7)
60616 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_WILLING_BIT_POS UINT32_C(0x6)
60618 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_APP_STATE_ADVERTISE_BIT_POS UINT32_C(0x5)
60628 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_ETS UINT32_C(0x1)
60630 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_PFC UINT32_C(0x2)
60632 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_APP UINT32_C(0x4)
60634 #define HWRM_STRUCT_DATA_DCBX_FEATURE_STATE_RESETS_RESET_STATE UINT32_C(0x8)
60644 #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_DISABLE UINT32_C(0x0)
60646 #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_TX UINT32_C(0x1)
60648 #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_RX UINT32_C(0x2)
60650 #define HWRM_STRUCT_DATA_LLDP_ADMIN_STATE_ENABLE UINT32_C(0x3)
60652 /* Port description TLV transmit state (enable(1)/disable(0)). */
60655 #define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_DISABLE UINT32_C(0x0)
60657 #define HWRM_STRUCT_DATA_LLDP_PORT_DESCRIPTION_STATE_ENABLE UINT32_C(0x1)
60659 /* System name TLV transmit state (enable(1)/disable(0)). */
60662 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_DISABLE UINT32_C(0x0)
60664 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_NAME_STATE_ENABLE UINT32_C(0x1)
60666 /* System description TLV transmit state (enable(1)/disable(0)). */
60669 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_DISABLE UINT32_C(0x0)
60671 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_DESC_STATE_ENABLE UINT32_C(0x1)
60673 /* System capabilities TLV transmit state (enable(1)/disable(0)). */
60676 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_DISABLE UINT32_C(0x0)
60678 #define HWRM_STRUCT_DATA_LLDP_SYSTEM_CAP_STATE_ENABLE UINT32_C(0x1)
60680 /* Management address TLV transmit state (enable(1)/disable(0)). */
60683 #define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_DISABLE UINT32_C(0x0)
60685 #define HWRM_STRUCT_DATA_LLDP_MGMT_ADDR_STATE_ENABLE UINT32_C(0x1)
60687 /* Async event notification state (enable(1)/disable(0)). */
60690 #define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_DISABLE UINT32_C(0x0)
60692 #define HWRM_STRUCT_DATA_LLDP_ASYNC_EVENT_NOTIFICATION_STATE_ENABLE UINT32_C(0x1)
60703 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_CHASSIS UINT32_C(0x1)
60705 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT UINT32_C(0x2)
60707 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_NAME UINT32_C(0x3)
60709 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_SYSTEM_DESCRIPTION UINT32_C(0x4)
60711 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_NAME UINT32_C(0x5)
60713 #define HWRM_STRUCT_DATA_LLDP_GENERIC_TLV_TYPE_PORT_DESCRIPTION UINT32_C(0x6)
60755 * Port #. Port number starts at 0 and anything greater than number of
60767 #define HWRM_STRUCT_DATA_RSS_V2_FLAGS_HASH_VALID UINT32_C(0x1)
60778 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV4 UINT32_C(0x1)
60784 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)
60790 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)
60796 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_IPV6 UINT32_C(0x8)
60802 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)
60808 #define HWRM_STRUCT_DATA_RSS_V2_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)
60838 /* Starting VF for row 0 */
60840 /* MSI-X vectors per VF for row 0 */
60895 * * 0x0-0xFFF8 - The function ID
60896 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60897 * * 0xFFFD - Reserved for user-space HWRM interface
60898 * * 0xFFFF - HWRM
60954 #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
60956 #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT UINT32_C(0x1)
60958 #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT UINT32_C(0x2)
60960 #define HWRM_FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
60988 * * 0x0-0xFFF8 - The function ID
60989 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
60990 * * 0xFFFD - Reserved for user-space HWRM interface
60991 * * 0xFFFF - HWRM
61028 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_UNUSED UINT32_C(0x0)
61029 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_ALL UINT32_C(0xffff)
61030 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_ADMIN UINT32_C(0x100)
61031 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_PEER UINT32_C(0x101)
61032 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NEAR_BRIDGE_OPERATIONAL UINT32_C(0x102)
61033 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_ADMIN UINT32_C(0x200)
61034 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_PEER UINT32_C(0x201)
61035 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_NON_TPMR_OPERATIONAL UINT32_C(0x202)
61036 #define HWRM_FW_GET_STRUCTURED_DATA_INPUT_SUBTYPE_HOST_OPERATIONAL UINT32_C(0x300)
61079 #define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
61081 #define HWRM_FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
61109 * * 0x0-0xFFF8 - The function ID
61110 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61111 * * 0xFFFD - Reserved for user-space HWRM interface
61112 * * 0xFFFF - HWRM
61127 #define HWRM_FW_IPC_MSG_INPUT_ENABLES_COMMAND_ID UINT32_C(0x1)
61132 #define HWRM_FW_IPC_MSG_INPUT_ENABLES_SRC_PROCESSOR UINT32_C(0x2)
61137 #define HWRM_FW_IPC_MSG_INPUT_ENABLES_DATA_OFFSET UINT32_C(0x4)
61142 #define HWRM_FW_IPC_MSG_INPUT_ENABLES_LENGTH UINT32_C(0x8)
61146 #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_LAG UINT32_C(0x1)
61148 #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_MHB_HOST UINT32_C(0x2)
61150 #define HWRM_FW_IPC_MSG_INPUT_COMMAND_ID_ROCE_DRVR_VERSION UINT32_C(0x3)
61155 #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_CFW UINT32_C(0x1)
61157 #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_BONO UINT32_C(0x2)
61159 #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_APE UINT32_C(0x3)
61161 #define HWRM_FW_IPC_MSG_INPUT_SRC_PROCESSOR_KONG UINT32_C(0x4)
61221 * * 0x0-0xFFF8 - The function ID
61222 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61223 * * 0xFFFD - Reserved for user-space HWRM interface
61224 * * 0xFFFF - HWRM
61279 #define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
61281 #define HWRM_FW_IPC_MAILBOX_CMD_ERR_CODE_BAD_ID UINT32_C(0x3)
61309 * * 0x0-0xFFF8 - The function ID
61310 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61311 * * 0xFFFD - Reserved for user-space HWRM interface
61312 * * 0xFFFF - HWRM
61332 * Setting this bit to '0' disables ECN immediately.
61334 #define HWRM_FW_ECN_CFG_INPUT_FLAGS_ENABLE_ECN UINT32_C(0x1)
61383 * * 0x0-0xFFF8 - The function ID
61384 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61385 * * 0xFFFD - Reserved for user-space HWRM interface
61386 * * 0xFFFF - HWRM
61411 #define HWRM_FW_ECN_QCFG_OUTPUT_FLAGS_ENABLE_ECN UINT32_C(0x1)
61446 * * 0x0-0xFFF8 - The function ID
61447 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61448 * * 0xFFFD - Reserved for user-space HWRM interface
61449 * * 0xFFFF - HWRM
61474 * This bit is '0' if the primary SBI was used this boot,
61477 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SBI_BOOTED UINT32_C(0x1)
61479 * This bit is '0' if the primary and secondary SBI images
61482 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SBI_MISMATCH UINT32_C(0x2)
61484 * This bit is '0' if the primary SRT was used this boot,
61487 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT_BOOTED UINT32_C(0x4)
61489 * This bit is '0' if the primary and secondary SRT images
61492 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SRT_MISMATCH UINT32_C(0x8)
61494 * This bit is '0' if the primary CRT (or second stage SRT)
61498 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT_BOOTED UINT32_C(0x10)
61500 * This bit is '0' if the primary and secondary CRT images
61504 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT_MISMATCH UINT32_C(0x20)
61506 * This bit is '0' if the second stage RT image is a CRT,
61509 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_SECOND_RT UINT32_C(0x40)
61511 * This bit is '0' if the image was loaded from flash,
61514 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FASTBOOTED UINT32_C(0x80)
61516 * This bit is '0' if the primary dir_hdr was used to locate
61519 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_DIR_HDR_BOOTED UINT32_C(0x100)
61521 * This bit is '0' if the primary and secondary dir_hdr match,
61524 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_DIR_HDR_MISMATCH UINT32_C(0x200)
61526 * This bit is '0' if the Master Boot Record is in good condition,
61529 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_MBR_CORRUPT UINT32_C(0x400)
61531 * This bit is '0' if the configuration is in good condition,
61534 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CFG_MISMATCH UINT32_C(0x800)
61536 * This bit is '0' if both FRU entries match,
61539 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_FRU_MISMATCH UINT32_C(0x1000)
61541 * This bit is '0' if the primary CRT2 was used this boot,
61544 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT2_BOOTED UINT32_C(0x2000)
61546 * This bit is '0' if the primary and secondary CRT2 images
61549 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_CRT2_MISMATCH UINT32_C(0x4000)
61551 * This bit is '0' if the primary GXRT was used this boot,
61554 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_GXRT_BOOTED UINT32_C(0x8000)
61556 * This bit is '0' if the primary and secondary GXRT images
61559 #define HWRM_FW_HEALTH_CHECK_OUTPUT_FW_STATUS_GXRT_MISMATCH UINT32_C(0x10000)
61594 * * 0x0-0xFFF8 - The function ID
61595 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61596 * * 0xFFFD - Reserved for user-space HWRM interface
61597 * * 0xFFFF - HWRM
61610 #define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_COMMON_FW UINT32_C(0x1)
61612 #define HWRM_FW_LIVEPATCH_QUERY_INPUT_FW_TARGET_SECURE_FW UINT32_C(0x2)
61640 #define HWRM_FW_LIVEPATCH_QUERY_OUTPUT_STATUS_FLAGS_INSTALL UINT32_C(0x1)
61642 #define HWRM_FW_LIVEPATCH_QUERY_OUTPUT_STATUS_FLAGS_ACTIVE UINT32_C(0x2)
61677 * * 0x0-0xFFF8 - The function ID
61678 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61679 * * 0xFFFD - Reserved for user-space HWRM interface
61680 * * 0xFFFF - HWRM
61698 #define HWRM_FW_LIVEPATCH_INPUT_OPCODE_ACTIVATE UINT32_C(0x1)
61703 #define HWRM_FW_LIVEPATCH_INPUT_OPCODE_DEACTIVATE UINT32_C(0x2)
61708 #define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_COMMON_FW UINT32_C(0x1)
61710 #define HWRM_FW_LIVEPATCH_INPUT_FW_TARGET_SECURE_FW UINT32_C(0x2)
61715 #define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_NVM_INSTALL UINT32_C(0x1)
61720 #define HWRM_FW_LIVEPATCH_INPUT_LOADTYPE_MEMORY_DIRECT UINT32_C(0x2)
61761 #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
61763 #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE UINT32_C(0x1)
61765 #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET UINT32_C(0x2)
61767 #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED UINT32_C(0x3)
61769 #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED UINT32_C(0x4)
61771 #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED UINT32_C(0x5)
61773 #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL UINT32_C(0x6)
61775 #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER UINT32_C(0x7)
61777 #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE UINT32_C(0x8)
61782 #define HWRM_FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED UINT32_C(0x9)
61810 * * 0x0-0xFFF8 - The function ID
61811 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61812 * * 0xFFFD - Reserved for user-space HWRM interface
61813 * * 0xFFFF - HWRM
61830 #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SBI UINT32_C(0x1)
61837 #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_SRT UINT32_C(0x2)
61845 #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CRT UINT32_C(0x4)
61852 #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_DIR_HDR UINT32_C(0x8)
61857 #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_WRITE_MBR UINT32_C(0x10)
61862 #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CFG UINT32_C(0x20)
61868 #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_FRU UINT32_C(0x40)
61875 #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_CRT2 UINT32_C(0x80)
61882 #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_SYNC_GXRT UINT32_C(0x100)
61886 * sync_sbi, sync_srt, sync_crt, sync_crt2 bits. A value of '0' just
61890 #define HWRM_FW_SYNC_INPUT_SYNC_ACTION_ACTION UINT32_C(0x80000000)
61907 #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_MASK UINT32_C(0xff)
61908 #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_SFT 0
61910 #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0)
61915 #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_IN_PROGRESS UINT32_C(0x1)
61917 #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_TIMEOUT UINT32_C(0x2)
61919 #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_ERR_CODE_GENERAL UINT32_C(0x3)
61926 #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_SYNC_ERR UINT32_C(0x40000000)
61928 * This bit is '0' if the previously requested synchronization
61934 #define HWRM_FW_SYNC_OUTPUT_SYNC_STATUS_SYNC_COMPLETE UINT32_C(0x80000000)
61969 * * 0x0-0xFFF8 - The function ID
61970 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
61971 * * 0xFFFD - Reserved for user-space HWRM interface
61972 * * 0xFFFF - HWRM
62025 * for status 0x8000.
62030 * 0x8000 before assuming a reset failure occurred. This time does
62070 * * 0x0-0xFFF8 - The function ID
62071 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62072 * * 0xFFFD - Reserved for user-space HWRM interface
62073 * * 0xFFFF - HWRM
62097 #define HWRM_FW_STATE_QUIESCE_INPUT_FLAGS_ERROR_RECOVERY UINT32_C(0x1)
62117 #define HWRM_FW_STATE_QUIESCE_OUTPUT_QUIESCE_STATUS_INITIATED UINT32_C(0x80000000)
62154 * * 0x0-0xFFF8 - The function ID
62155 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62156 * * 0xFFFD - Reserved for user-space HWRM interface
62157 * * 0xFFFF - HWRM
62182 #define HWRM_FW_STATE_UNQUIESCE_OUTPUT_UNQUIESCE_STATUS_COMPLETE UINT32_C(0x80000000)
62218 * * 0x0-0xFFF8 - The function ID
62219 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62220 * * 0xFFFD - Reserved for user-space HWRM interface
62221 * * 0xFFFF - HWRM
62234 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_MASK UINT32_C(0xf)
62235 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_SFT 0
62237 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_0 UINT32_C(0x0)
62239 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_1 UINT32_C(0x1)
62244 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_LVL_LVL_2 UINT32_C(0x2)
62247 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_MASK UINT32_C(0xf0)
62250 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
62252 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
62254 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
62256 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
62258 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
62260 #define HWRM_FW_STATE_BACKUP_INPUT_BACKUP_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
62283 #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_MASK UINT32_C(0xff)
62284 #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_SFT 0
62286 #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0)
62288 #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_QUIESCE_ERROR UINT32_C(0x1)
62290 #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_ERR_CODE_GENERAL UINT32_C(0x3)
62293 * This bit is '0' if the backout was done in a way that firmware
62301 #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_RESET_REQUIRED UINT32_C(0x40000000)
62303 #define HWRM_FW_STATE_BACKUP_OUTPUT_BACKUP_STATUS_COMPLETE UINT32_C(0x80000000)
62339 * * 0x0-0xFFF8 - The function ID
62340 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62341 * * 0xFFFD - Reserved for user-space HWRM interface
62342 * * 0xFFFF - HWRM
62355 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_MASK UINT32_C(0xf)
62356 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_SFT 0
62358 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_0 UINT32_C(0x0)
62360 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_1 UINT32_C(0x1)
62365 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_LVL_LVL_2 UINT32_C(0x2)
62368 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_MASK UINT32_C(0xf0)
62371 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
62373 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
62375 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
62377 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
62379 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
62381 #define HWRM_FW_STATE_RESTORE_INPUT_RESTORE_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
62404 #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_MASK UINT32_C(0xff)
62405 #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_SFT 0
62407 #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_SUCCESS UINT32_C(0x0)
62409 #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_GENERAL UINT32_C(0x1)
62411 #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_FORMAT_PARSE UINT32_C(0x2)
62413 #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_ERR_CODE_INTEGRITY_CHECK UINT32_C(0x3)
62416 * If a failure occurs (complete is 0), restore attempts to
62421 #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_FAILURE_ROLLBACK_COMPLETED UINT32_C(0x40000000)
62423 #define HWRM_FW_STATE_RESTORE_OUTPUT_RESTORE_STATUS_COMPLETE UINT32_C(0x80000000)
62458 * * 0x0-0xFFF8 - The function ID
62459 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62460 * * 0xFFFD - Reserved for user-space HWRM interface
62461 * * 0xFFFF - HWRM
62474 #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_NVRAM UINT32_C(0x1)
62476 #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_GRC UINT32_C(0x2)
62478 #define HWRM_FW_SECURE_CFG_INPUT_ENABLE_UART UINT32_C(0x3)
62486 #define HWRM_FW_SECURE_CFG_INPUT_CONFIG_MODE_PERSISTENT UINT32_C(0x1)
62488 #define HWRM_FW_SECURE_CFG_INPUT_CONFIG_MODE_RUNTIME UINT32_C(0x2)
62495 #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_NONE UINT32_C(0x0)
62500 #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_PARTIAL UINT32_C(0x1)
62505 #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_FULL UINT32_C(0x2)
62511 #define HWRM_FW_SECURE_CFG_INPUT_NVM_LOCK_MODE_CHIP UINT32_C(0x3)
62519 #define HWRM_FW_SECURE_CFG_INPUT_NVM_PARTIAL_LOCK_MASK_EXE UINT32_C(0x1)
62521 #define HWRM_FW_SECURE_CFG_INPUT_NVM_PARTIAL_LOCK_MASK_CFG UINT32_C(0x2)
62525 #define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RO UINT32_C(0x0)
62527 #define HWRM_FW_SECURE_CFG_INPUT_GRC_CTRL_RW UINT32_C(0x1)
62532 #define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_DISABLE UINT32_C(0x0)
62534 #define HWRM_FW_SECURE_CFG_INPUT_UART_CTRL_ENABLE UINT32_C(0x1)
62586 * * 0x0-0xFFF8 - The function ID
62587 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62588 * * 0xFFFD - Reserved for user-space HWRM interface
62589 * * 0xFFFF - HWRM
62609 * 0x0 - 0xFFF8 - Used for function ids
62610 * 0xFFF8 - 0xFFFE - Reserved for internal processors
62611 * 0xFFFF - HWRM
62662 * * 0x0-0xFFF8 - The function ID
62663 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62664 * * 0xFFFD - Reserved for user-space HWRM interface
62665 * * 0xFFFF - HWRM
62685 * 0x0 - 0xFFF8 - Used for function ids
62686 * 0xFFF8 - 0xFFFE - Reserved for internal processors
62687 * 0xFFFF - HWRM
62738 * * 0x0-0xFFF8 - The function ID
62739 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62740 * * 0xFFFD - Reserved for user-space HWRM interface
62741 * * 0xFFFF - HWRM
62754 * 0x0 - 0xFFF8 - Used for function ids
62755 * 0xFFF8 - 0xFFFE - Reserved for internal processors
62756 * 0xFFFF - HWRM
62829 * * 0x0-0xFFF8 - The function ID
62830 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62831 * * 0xFFFD - Reserved for user-space HWRM interface
62832 * * 0xFFFF - HWRM
62845 * 0x0 - 0xFFF8 - Used for function ids
62846 * 0xFFF8 - 0xFFFE - Reserved for internal processors
62847 * 0xFFFF - Broadcast to all children VFs (only applicable when
62901 * * 0x0-0xFFF8 - The function ID
62902 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
62903 * * 0xFFFD - Reserved for user-space HWRM interface
62904 * * 0xFFFF - HWRM
62949 #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_TEMP_NOT_AVAILABLE UINT32_C(0x1)
62954 #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_PHY_TEMP_NOT_AVAILABLE UINT32_C(0x2)
62956 #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_OM_NOT_PRESENT UINT32_C(0x4)
62961 #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_OM_TEMP_NOT_AVAILABLE UINT32_C(0x8)
62966 #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_EXT_TEMP_FIELDS_AVAILABLE UINT32_C(0x10)
62971 #define HWRM_TEMP_MONITOR_QUERY_OUTPUT_FLAGS_THRESHOLD_VALUES_AVAILABLE UINT32_C(0x20)
62974 * This field is unsigned and the value range of 0 to 255 is used to
62977 * Example: A value of 0 represents a temperature of -64, a value of
62983 * field is unsigned and the value range of 0 to 255 is used to
62986 * Example: A value of 0 represents a temperature of -64, a value of
62992 * This field is unsigned and the value range of 0 to 255 is used to
62995 * Example: A value of 0 represents a temperature of -64, a value of
63055 * * 0x0-0xFFF8 - The function ID
63056 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63057 * * 0xFFFD - Reserved for user-space HWRM interface
63058 * * 0xFFFF - HWRM
63084 #define HWRM_REG_POWER_QUERY_OUTPUT_FLAGS_IN_POWER_AVAILABLE UINT32_C(0x1)
63086 #define HWRM_REG_POWER_QUERY_OUTPUT_FLAGS_OUT_POWER_AVAILABLE UINT32_C(0x2)
63131 * * 0x0-0xFFF8 - The function ID
63132 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63133 * * 0xFFFD - Reserved for user-space HWRM interface
63134 * * 0xFFFF - HWRM
63193 * * 0x0-0xFFF8 - The function ID
63194 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63195 * * 0xFFFD - Reserved for user-space HWRM interface
63196 * * 0xFFFF - HWRM
63212 #define HWRM_REG_POWER_HISTOGRAM_INPUT_FLAGS_CLEAR_HISTOGRAM UINT32_C(0x1)
63236 #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT UINT32_C(0x1)
63241 #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_INPUT UINT32_C(0x0)
63246 #define HWRM_REG_POWER_HISTOGRAM_OUTPUT_FLAGS_POWER_IN_OUT_OUTPUT UINT32_C(0x1)
63270 * value, 0xFFFFFFFF, and do not roll over. Clients should use the
63295 #define BUCKET_NO_DATA_FOR_SAMPLE UINT32_C(0x0)
63297 #define BUCKET_RANGE_8W_OR_LESS UINT32_C(0x1)
63299 #define BUCKET_RANGE_8W_TO_9W UINT32_C(0x2)
63301 #define BUCKET_RANGE_9W_TO_10W UINT32_C(0x3)
63303 #define BUCKET_RANGE_10W_TO_11W UINT32_C(0x4)
63305 #define BUCKET_RANGE_11W_TO_12W UINT32_C(0x5)
63307 #define BUCKET_RANGE_12W_TO_13W UINT32_C(0x6)
63309 #define BUCKET_RANGE_13W_TO_14W UINT32_C(0x7)
63311 #define BUCKET_RANGE_14W_TO_15W UINT32_C(0x8)
63313 #define BUCKET_RANGE_15W_TO_16W UINT32_C(0x9)
63315 #define BUCKET_RANGE_16W_TO_18W UINT32_C(0xa)
63317 #define BUCKET_RANGE_18W_TO_20W UINT32_C(0xb)
63319 #define BUCKET_RANGE_20W_TO_22W UINT32_C(0xc)
63321 #define BUCKET_RANGE_22W_TO_24W UINT32_C(0xd)
63323 #define BUCKET_RANGE_24W_TO_26W UINT32_C(0xe)
63325 #define BUCKET_RANGE_26W_TO_28W UINT32_C(0xf)
63327 #define BUCKET_RANGE_28W_TO_30W UINT32_C(0x10)
63329 #define BUCKET_RANGE_30W_TO_32W UINT32_C(0x11)
63331 #define BUCKET_RANGE_32W_TO_34W UINT32_C(0x12)
63333 #define BUCKET_RANGE_34W_TO_36W UINT32_C(0x13)
63335 #define BUCKET_RANGE_36W_TO_38W UINT32_C(0x14)
63337 #define BUCKET_RANGE_38W_TO_40W UINT32_C(0x15)
63339 #define BUCKET_RANGE_40W_TO_42W UINT32_C(0x16)
63341 #define BUCKET_RANGE_42W_TO_44W UINT32_C(0x17)
63343 #define BUCKET_RANGE_44W_TO_50W UINT32_C(0x18)
63345 #define BUCKET_RANGE_OVER_50W UINT32_C(0x19)
63372 * * 0x0-0xFFF8 - The function ID
63373 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63374 * * 0xFFFD - Reserved for user-space HWRM interface
63375 * * 0xFFFF - HWRM
63391 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_MAC_ADDRESS UINT32_C(0x1)
63396 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_OFFSET UINT32_C(0x2)
63401 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_SIZE UINT32_C(0x4)
63406 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_BUF_ADDR UINT32_C(0x8)
63411 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_ADDR UINT32_C(0x10)
63416 #define HWRM_WOL_FILTER_ALLOC_INPUT_ENABLES_PATTERN_MASK_SIZE UINT32_C(0x20)
63422 #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0)
63424 #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_BMP UINT32_C(0x1)
63426 #define HWRM_WOL_FILTER_ALLOC_INPUT_WOL_TYPE_INVALID UINT32_C(0xff)
63436 * 0xFF in this command, then the HWRM
63441 * 0xFF in this command, then the HWRM
63521 * * 0x0-0xFFF8 - The function ID
63522 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63523 * * 0xFFFD - Reserved for user-space HWRM interface
63524 * * 0xFFFF - HWRM
63542 #define HWRM_WOL_FILTER_FREE_INPUT_FLAGS_FREE_ALL_WOL_FILTERS UINT32_C(0x1)
63548 #define HWRM_WOL_FILTER_FREE_INPUT_ENABLES_WOL_FILTER_ID UINT32_C(0x1)
63604 * * 0x0-0xFFF8 - The function ID
63605 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63606 * * 0xFFFD - Reserved for user-space HWRM interface
63607 * * 0xFFFF - HWRM
63621 * # The HWRM client shall set this field to 0x0000 to begin
63632 * # Value of 0 indicates an invalid buffer address.
63633 * If this field is set to 0, then HWRM shall ignore
63650 * # Value of 0 indicates an invalid pattern mask address.
63651 * If this field is set to 0, then HWRM shall ignore
63680 * # If this field is set to 0x0000, then no WoL filters are
63683 * # If this field is set to neither 0x0000 nor 0xFFFF, then the
63686 * # If this field is set to 0xFFFF, then there are no remaining
63703 #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_MAGICPKT UINT32_C(0x0)
63705 #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_BMP UINT32_C(0x1)
63707 #define HWRM_WOL_FILTER_QCFG_OUTPUT_WOL_TYPE_INVALID UINT32_C(0xff)
63765 * * 0x0-0xFFF8 - The function ID
63766 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63767 * * 0xFFFD - Reserved for user-space HWRM interface
63768 * * 0xFFFF - HWRM
63817 #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_MAGICPKT UINT32_C(0x0)
63819 #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_BMP UINT32_C(0x1)
63821 #define HWRM_WOL_REASON_QCFG_OUTPUT_WOL_REASON_INVALID UINT32_C(0xff)
63859 * * 0x0-0xFFF8 - The function ID
63860 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63861 * * 0xFFFD - Reserved for user-space HWRM interface
63862 * * 0xFFFF - HWRM
63934 * * 0x0-0xFFF8 - The function ID
63935 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
63936 * * 0xFFFD - Reserved for user-space HWRM interface
63937 * * 0xFFFF - HWRM
64000 * * 0x0-0xFFF8 - The function ID
64001 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64002 * * 0xFFFD - Reserved for user-space HWRM interface
64003 * * 0xFFFF - HWRM
64023 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 UINT32_C(0x0)
64025 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 UINT32_C(0x1)
64027 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 UINT32_C(0x2)
64029 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 UINT32_C(0x3)
64031 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS UINT32_C(0x4)
64033 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM UINT32_C(0x5)
64035 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM UINT32_C(0x6)
64037 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM UINT32_C(0x7)
64039 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM UINT32_C(0x8)
64041 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9)
64043 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa)
64045 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM UINT32_C(0xb)
64047 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc)
64049 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd)
64051 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM UINT32_C(0xe)
64053 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM UINT32_C(0xf)
64055 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB UINT32_C(0x10)
64057 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL UINT32_C(0x11)
64059 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC UINT32_C(0x12)
64061 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_PRIVATE UINT32_C(0x13)
64063 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_HOST_DMA UINT32_C(0x14)
64067 * in the opaque[0] field.
64068 * 1) sub-type CHECK(0) if ELOG is available in media.
64074 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_SOC_ELOG UINT32_C(0x15)
64076 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CTX UINT32_C(0x16)
64078 #define HWRM_DBG_READ_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS UINT32_C(0x17)
64137 * * 0x0-0xFFF8 - The function ID
64138 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64139 * * 0xFFFD - Reserved for user-space HWRM interface
64140 * * 0xFFFF - HWRM
64153 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L2 UINT32_C(0x0)
64155 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_TE_MGMT_FILTERS_L3L4 UINT32_C(0x1)
64157 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L2 UINT32_C(0x2)
64159 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_RE_MGMT_FILTERS_L3L4 UINT32_C(0x3)
64161 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STAT_CTXS UINT32_C(0x4)
64163 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_L2_TCAM UINT32_C(0x5)
64165 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_L2_TCAM UINT32_C(0x6)
64167 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_IPV6_SUBNET_TCAM UINT32_C(0x7)
64169 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_IPV6_SUBNET_TCAM UINT32_C(0x8)
64171 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_SRC_PROPERTIES_TCAM UINT32_C(0x9)
64173 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_SRC_PROPERTIES_TCAM UINT32_C(0xa)
64175 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_VEB_LOOKUP_TCAM UINT32_C(0xb)
64177 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_PROFILE_LOOKUP_TCAM UINT32_C(0xc)
64179 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_PROFILE_LOOKUP_TCAM UINT32_C(0xd)
64181 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_TX_LOOKUP_TCAM UINT32_C(0xe)
64183 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CFA_RX_LOOKUP_TCAM UINT32_C(0xf)
64185 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MHB UINT32_C(0x10)
64187 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_GBL UINT32_C(0x11)
64189 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_MULTI_HOST_SOC UINT32_C(0x12)
64191 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_PCIE_PRIVATE UINT32_C(0x13)
64193 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_HOST_DMA UINT32_C(0x14)
64195 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_SOC_ELOG UINT32_C(0x15)
64197 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_CTX UINT32_C(0x16)
64199 #define HWRM_DBG_WRITE_INDIRECT_INPUT_INDIRECT_ACCESS_TYPE_STATS UINT32_C(0x17)
64258 * * 0x0-0xFFF8 - The function ID
64259 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64260 * * 0xFFFD - Reserved for user-space HWRM interface
64261 * * 0xFFFF - HWRM
64273 * handle = 0 indicates the beginning of the dump.
64274 * handle != 0 indicates the request to dump the next part.
64301 * nexthandle = 0 indicates that there is no more debug data
64303 * nexthandle != 0 indicates the handle value that should be used
64346 * * 0x0-0xFFF8 - The function ID
64347 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64348 * * 0xFFFD - Reserved for user-space HWRM interface
64349 * * 0xFFFF - HWRM
64361 #define HWRM_DBG_ERASE_NVM_INPUT_FLAGS_ERASE_ALL UINT32_C(0x1)
64410 * * 0x0-0xFFF8 - The function ID
64411 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64412 * * 0xFFFD - Reserved for user-space HWRM interface
64413 * * 0xFFFF - HWRM
64428 #define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG UINT32_C(0x1)
64434 #define HWRM_DBG_CFG_INPUT_FLAGS_UART_LOG_SECONDARY UINT32_C(0x2)
64439 #define HWRM_DBG_CFG_INPUT_FLAGS_FW_TRACE UINT32_C(0x4)
64444 #define HWRM_DBG_CFG_INPUT_FLAGS_FW_TRACE_SECONDARY UINT32_C(0x8)
64449 #define HWRM_DBG_CFG_INPUT_FLAGS_DEBUG_NOTIFY UINT32_C(0x10)
64456 #define HWRM_DBG_CFG_INPUT_FLAGS_JTAG_DEBUG UINT32_C(0x20)
64511 * * 0x0-0xFFF8 - The function ID
64512 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64513 * * 0xFFFD - Reserved for user-space HWRM interface
64514 * * 0xFFFF - HWRM
64556 #define HWRM_DBG_CRASHDUMP_HEADER_OUTPUT_UTC_OFFSET_UTC 0
64614 * have '\0' character.
64656 * * 0x0-0xFFF8 - The function ID
64657 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64658 * * 0xFFFD - Reserved for user-space HWRM interface
64659 * * 0xFFFF - HWRM
64675 #define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_INVALIDATE UINT32_C(0x0)
64683 #define HWRM_DBG_CRASHDUMP_ERASE_INPUT_SCOPE_REINIT UINT32_C(0x1)
64734 * * 0x0-0xFFF8 - The function ID
64735 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64736 * * 0xFFFD - Reserved for user-space HWRM interface
64737 * * 0xFFFF - HWRM
64749 * 0xFF... (All Fs) if the query is for the requesting
64782 #define HWRM_DBG_QCAPS_OUTPUT_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM UINT32_C(0x1)
64785 #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_NVM UINT32_C(0x1)
64787 #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_HOST_DDR UINT32_C(0x2)
64789 #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_CRASHDUMP_SOC_DDR UINT32_C(0x4)
64791 #define HWRM_DBG_QCAPS_OUTPUT_FLAGS_USEQ UINT32_C(0x8)
64826 * * 0x0-0xFFF8 - The function ID
64827 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64828 * * 0xFFFD - Reserved for user-space HWRM interface
64829 * * 0xFFFF - HWRM
64841 * 0xFF... (All Fs) if the query is for the requesting
64850 #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK UINT32_C(0x3)
64851 #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0
64853 #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM UINT32_C(0x0)
64855 #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR UINT32_C(0x1)
64857 #define HWRM_DBG_QCFG_INPUT_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR UINT32_C(0x2)
64868 #define HWRM_DBG_QCFG_INPUT_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM UINT32_C(0x1)
64899 #define HWRM_DBG_QCFG_OUTPUT_FLAGS_UART_LOG UINT32_C(0x1)
64904 #define HWRM_DBG_QCFG_OUTPUT_FLAGS_UART_LOG_SECONDARY UINT32_C(0x2)
64909 #define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE UINT32_C(0x4)
64914 #define HWRM_DBG_QCFG_OUTPUT_FLAGS_FW_TRACE_SECONDARY UINT32_C(0x8)
64919 #define HWRM_DBG_QCFG_OUTPUT_FLAGS_DEBUG_NOTIFY UINT32_C(0x10)
64926 #define HWRM_DBG_QCFG_OUTPUT_FLAGS_JTAG_DEBUG UINT32_C(0x20)
64973 * * 0x0-0xFFF8 - The function ID
64974 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
64975 * * 0xFFFD - Reserved for user-space HWRM interface
64976 * * 0xFFFF - HWRM
64988 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_TYPE_DDR UINT32_C(0x1)
64991 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_MASK UINT32_C(0x3)
64992 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_SFT 0
64994 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_0 UINT32_C(0x0)
64996 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_1 UINT32_C(0x1)
65001 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_LVL_LVL_2 UINT32_C(0x2)
65004 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_MASK UINT32_C(0x1c)
65007 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
65009 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
65011 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
65013 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
65015 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
65017 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
65020 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_UNUSED11_MASK UINT32_C(0xffe0)
65033 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG_INPUT_NVRAM UINT32_C(0x1)
65075 * bit 0: live data
65085 #define SFLAG_COMPRESSED_ZLIB UINT32_C(0x1)
65117 * * 0x0-0xFFF8 - The function ID
65118 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65119 * * 0xFFFD - Reserved for user-space HWRM interface
65120 * * 0xFFFF - HWRM
65137 /* Sequence number of the request. Starts at 0. */
65143 * If set to 0, both live core and crash dump are requested.
65145 #define HWRM_DBG_COREDUMP_LIST_INPUT_FLAGS_CRASHDUMP UINT32_C(0x1)
65165 #define HWRM_DBG_COREDUMP_LIST_OUTPUT_FLAGS_MORE UINT32_C(0x1)
65205 * * 0x0-0xFFF8 - The function ID
65206 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65207 * * 0xFFFD - Reserved for user-space HWRM interface
65208 * * 0xFFFF - HWRM
65227 * bit 0: live data
65263 * length: 0 - 23 bits represents the actual data without the pad.
65269 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK UINT32_C(0xffffff)
65270 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0
65272 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS UINT32_C(0x1000000)
65302 * * 0x0-0xFFF8 - The function ID
65303 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65304 * * 0xFFFD - Reserved for user-space HWRM interface
65305 * * 0xFFFF - HWRM
65333 * bit 0: live data
65341 /* Sequence number is used per segment request. Starts at 0. */
65362 #define HWRM_DBG_COREDUMP_RETRIEVE_OUTPUT_FLAGS_MORE UINT32_C(0x1)
65400 * * 0x0-0xFFF8 - The function ID
65401 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65402 * * 0xFFFD - Reserved for user-space HWRM interface
65403 * * 0xFFFF - HWRM
65440 #define HWRM_DBG_I2C_CMD_INPUT_OPTIONS_10_BIT_ADDRESSING UINT32_C(0x1)
65445 #define HWRM_DBG_I2C_CMD_INPUT_OPTIONS_FAST_MODE UINT32_C(0x2)
65451 #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_READ UINT32_C(0x0)
65453 #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE UINT32_C(0x1)
65455 #define HWRM_DBG_I2C_CMD_INPUT_XFER_MODE_MASTER_WRITE_READ UINT32_C(0x2)
65505 * * 0x0-0xFFF8 - The function ID
65506 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65507 * * 0xFFFD - Reserved for user-space HWRM interface
65508 * * 0xFFFF - HWRM
65579 * * 0x0-0xFFF8 - The function ID
65580 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65581 * * 0xFFFD - Reserved for user-space HWRM interface
65582 * * 0xFFFF - HWRM
65595 #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)
65597 #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_TX UINT32_C(0x1)
65599 #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_RX UINT32_C(0x2)
65601 #define HWRM_DBG_RING_INFO_GET_INPUT_RING_TYPE_NQ UINT32_C(0x3)
65668 * * 0x0-0xFFF8 - The function ID
65669 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65670 * * 0xFFFD - Reserved for user-space HWRM interface
65671 * * 0xFFFF - HWRM
65684 #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_FATAL UINT32_C(0x0)
65686 #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_ERROR UINT32_C(0x1)
65688 #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_WARNING UINT32_C(0x2)
65690 #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_INFO UINT32_C(0x3)
65692 #define HWRM_DBG_DRV_TRACE_INPUT_SEVERITY_TRACE_LEVEL_DEBUG UINT32_C(0x4)
65749 * * 0x0-0xFFF8 - The function ID
65750 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65751 * * 0xFFFD - Reserved for user-space HWRM interface
65752 * * 0xFFFF - HWRM
65796 #define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
65798 #define HWRM_DBG_USEQ_ALLOC_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
65841 * * 0x0-0xFFF8 - The function ID
65842 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65843 * * 0xFFFD - Reserved for user-space HWRM interface
65844 * * 0xFFFF - HWRM
65880 #define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
65882 #define HWRM_DBG_USEQ_FREE_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
65923 * * 0x0-0xFFF8 - The function ID
65924 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
65925 * * 0xFFFD - Reserved for user-space HWRM interface
65926 * * 0xFFFF - HWRM
65939 #define HWRM_DBG_USEQ_FLUSH_INPUT_USEQ_CODE_WORDS UINT32_C(0x1)
65941 #define HWRM_DBG_USEQ_FLUSH_INPUT_BUFFERS UINT32_C(0x2)
65967 #define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
65969 #define HWRM_DBG_USEQ_FLUSH_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
66010 * * 0x0-0xFFF8 - The function ID
66011 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66012 * * 0xFFFD - Reserved for user-space HWRM interface
66013 * * 0xFFFF - HWRM
66050 #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USID_CTRL_PRESENT UINT32_C(0x1)
66056 #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_USE_DMA UINT32_C(0x2)
66061 #define HWRM_DBG_USEQ_CW_CFG_INPUT_FLAGS_END UINT32_C(0x8000)
66087 #define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
66089 #define HWRM_DBG_USEQ_CW_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
66120 * * 0x0-0xFFF8 - The function ID
66121 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66122 * * 0xFFFD - Reserved for user-space HWRM interface
66123 * * 0xFFFF - HWRM
66155 #define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
66157 #define HWRM_DBG_USEQ_QCAPS_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
66206 * * 0x0-0xFFF8 - The function ID
66207 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66208 * * 0xFFFD - Reserved for user-space HWRM interface
66209 * * 0xFFFF - HWRM
66222 #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_NO_CHANGE UINT32_C(0x0)
66227 #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_DISABLE UINT32_C(0x1)
66232 #define HWRM_DBG_USEQ_SCHED_CFG_INPUT_ENABLE UINT32_C(0x2)
66265 #define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
66267 …#define HWRM_DBG_USEQ_SCHED_CFG_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x…
66308 * * 0x0-0xFFF8 - The function ID
66309 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66310 * * 0xFFFD - Reserved for user-space HWRM interface
66311 * * 0xFFFF - HWRM
66326 #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_SINGLE UINT32_C(0x0)
66332 #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_CNT UINT32_C(0x1)
66339 #define HWRM_DBG_USEQ_RUN_INPUT_RUN_TYPE_FILL_BUF UINT32_C(0x2)
66388 #define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x1)
66390 #define HWRM_DBG_USEQ_RUN_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
66435 * * 0x0-0xFFF8 - The function ID
66436 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66437 * * 0xFFFD - Reserved for user-space HWRM interface
66438 * * 0xFFFF - HWRM
66450 * deliver USEQ output details. A value of 0x0 for the address can be
66482 …#define HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_AVAIL UINT32_C(0x…
66484 …ine HWRM_DBG_USEQ_DELIVERY_REQ_OUTPUT_HWRM_DBG_USEQ_RESP_HDR_USEQ_RESP_FLAGS_OVERFLOW UINT32_C(0x2)
66531 * * 0x0-0xFFF8 - The function ID
66532 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66533 * * 0xFFFD - Reserved for user-space HWRM interface
66534 * * 0xFFFF - HWRM
66547 #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT_TRACE UINT32_C(0x0)
66549 #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_SRT2_TRACE UINT32_C(0x1)
66551 #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT_TRACE UINT32_C(0x2)
66553 #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_CRT2_TRACE UINT32_C(0x3)
66555 #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_RIGP0_TRACE UINT32_C(0x4)
66557 #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_L2_HWRM_TRACE UINT32_C(0x5)
66559 #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_TYPE_ROCE_HWRM_TRACE UINT32_C(0x6)
66568 #define HWRM_DBG_LOG_BUFFER_FLUSH_INPUT_FLAGS_FLUSH_ALL_BUFFERS UINT32_C(0x1)
66624 * * 0x0-0xFFF8 - The function ID
66625 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66626 * * 0xFFFD - Reserved for user-space HWRM interface
66627 * * 0xFFFF - HWRM
66658 #define HWRM_NVM_RAW_WRITE_BLK_INPUT_FLAGS_SECURITY_SOC_NVM UINT32_C(0x1)
66707 * * 0x0-0xFFF8 - The function ID
66708 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66709 * * 0xFFFD - Reserved for user-space HWRM interface
66710 * * 0xFFFF - HWRM
66725 /* The 0-based index of the directory entry. */
66780 * * 0x0-0xFFF8 - The function ID
66781 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66782 * * 0xFFFD - Reserved for user-space HWRM interface
66783 * * 0xFFFF - HWRM
66810 #define HWRM_NVM_RAW_DUMP_INPUT_FLAGS_SECURITY_SOC_NVM UINT32_C(0x1)
66859 * * 0x0-0xFFF8 - The function ID
66860 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66861 * * 0xFFFD - Reserved for user-space HWRM interface
66862 * * 0xFFFF - HWRM
66924 * * 0x0-0xFFF8 - The function ID
66925 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66926 * * 0xFFFD - Reserved for user-space HWRM interface
66927 * * 0xFFFF - HWRM
66988 * * 0x0-0xFFF8 - The function ID
66989 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
66990 * * 0xFFFD - Reserved for user-space HWRM interface
66991 * * 0xFFFF - HWRM
67013 * The 0-based instance of the combined Directory Entry Type and
67041 #define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG UINT32_C(0x1)
67052 #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_MODE UINT32_C(0x2)
67057 #define HWRM_NVM_WRITE_INPUT_FLAGS_BATCH_LAST UINT32_C(0x4)
67126 #define HWRM_NVM_WRITE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
67128 #define HWRM_NVM_WRITE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
67130 #define HWRM_NVM_WRITE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
67158 * * 0x0-0xFFF8 - The function ID
67159 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67160 * * 0xFFFD - Reserved for user-space HWRM interface
67161 * * 0xFFFF - HWRM
67189 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_MODE UINT32_C(0x1)
67194 #define HWRM_NVM_MODIFY_INPUT_FLAGS_BATCH_LAST UINT32_C(0x2)
67250 * * 0x0-0xFFF8 - The function ID
67251 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67252 * * 0xFFFD - Reserved for user-space HWRM interface
67253 * * 0xFFFF - HWRM
67268 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_ENABLES_DIR_IDX_VALID UINT32_C(0x1)
67283 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_MASK UINT32_C(0x3)
67284 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_SFT 0
67286 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_EQ UINT32_C(0x0)
67288 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GE UINT32_C(0x1)
67290 #define HWRM_NVM_FIND_DIR_ENTRY_INPUT_OPT_ORDINAL_GT UINT32_C(0x2)
67354 * * 0x0-0xFFF8 - The function ID
67355 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67356 * * 0xFFFD - Reserved for user-space HWRM interface
67357 * * 0xFFFF - HWRM
67417 * * 0x0-0xFFF8 - The function ID
67418 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67419 * * 0xFFFD - Reserved for user-space HWRM interface
67420 * * 0xFFFF - HWRM
67468 #define HWRM_NVM_GET_DEV_INFO_OUTPUT_FLAGS_FW_VER_VALID UINT32_C(0x1)
67592 * * 0x0-0xFFF8 - The function ID
67593 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67594 * * 0xFFFD - Reserved for user-space HWRM interface
67595 * * 0xFFFF - HWRM
67610 #define HWRM_NVM_MOD_DIR_ENTRY_INPUT_ENABLES_CHECKSUM UINT32_C(0x1)
67615 * The (0-based) instance of this Directory Type.
67680 * * 0x0-0xFFF8 - The function ID
67681 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67682 * * 0xFFFD - Reserved for user-space HWRM interface
67683 * * 0xFFFF - HWRM
67758 * * 0x0-0xFFF8 - The function ID
67759 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67760 * * 0xFFFD - Reserved for user-space HWRM interface
67761 * * 0xFFFF - HWRM
67772 * Installation type. If the value 3 through 0xffff is used,
67784 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_NORMAL UINT32_C(0x0)
67790 #define HWRM_NVM_INSTALL_UPDATE_INPUT_INSTALL_TYPE_ALL UINT32_C(0xffffffff)
67797 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE UINT32_C(0x1)
67804 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG UINT32_C(0x2)
67811 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG UINT32_C(0x4)
67817 #define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_VERIFY_ONLY UINT32_C(0x8)
67834 * Bit-0 corresponding to the first packaged item, Bit-1 for the second
67835 * item, etc. A value of 0 indicates that no items were successfully
67842 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_SUCCESS UINT32_C(0x0)
67844 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_FAILURE UINT32_C(0xff)
67846 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_MALLOC_FAILURE UINT32_C(0xfd)
67848 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_INDEX_PARAMETER UINT32_C(0xfb)
67850 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TYPE_PARAMETER UINT32_C(0xf3)
67852 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PREREQUISITE UINT32_C(0xf2)
67854 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_FILE_HEADER UINT32_C(0xec)
67856 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_SIGNATURE UINT32_C(0xeb)
67858 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_STREAM UINT32_C(0xea)
67860 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_PROP_LENGTH UINT32_C(0xe9)
67862 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_MANIFEST UINT32_C(0xe8)
67864 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_TRAILER UINT32_C(0xe7)
67866 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_CHECKSUM UINT32_C(0xe6)
67868 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_ITEM_CHECKSUM UINT32_C(0xe5)
67870 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DATA_LENGTH UINT32_C(0xe4)
67872 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INVALID_DIRECTIVE UINT32_C(0xe1)
67874 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_CHIP_REV UINT32_C(0xce)
67876 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_DEVICE_ID UINT32_C(0xcd)
67878 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_VENDOR UINT32_C(0xcc)
67880 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_SUBSYS_ID UINT32_C(0xcb)
67882 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_UNSUPPORTED_PLATFORM UINT32_C(0xc5)
67884 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_DUPLICATE_ITEM UINT32_C(0xc4)
67886 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ZERO_LENGTH_ITEM UINT32_C(0xc3)
67888 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_CHECKSUM_ERROR UINT32_C(0xb9)
67890 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_DATA_ERROR UINT32_C(0xb8)
67892 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_INSTALL_AUTHENTICATION_ERROR UINT32_C(0xb7)
67894 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_NOT_FOUND UINT32_C(0xb0)
67896 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESULT_ITEM_LOCKED UINT32_C(0xa7)
67901 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_NONE UINT32_C(0x0)
67903 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_PROBLEM_ITEM_PACKAGE UINT32_C(0xff)
67911 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_NONE UINT32_C(0x0)
67917 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_PCI UINT32_C(0x1)
67925 #define HWRM_NVM_INSTALL_UPDATE_OUTPUT_RESET_REQUIRED_POWER UINT32_C(0x2)
67947 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
67949 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR UINT32_C(0x1)
67951 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE UINT32_C(0x2)
67953 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK UINT32_C(0x3)
67955 #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT UINT32_C(0x4)
67983 * * 0x0-0xFFF8 - The function ID
67984 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
67985 * * 0xFFFD - Reserved for user-space HWRM interface
67986 * * 0xFFFF - HWRM
68029 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
68031 #define HWRM_NVM_FLUSH_CMD_ERR_CODE_FAIL UINT32_C(0x1)
68059 * * 0x0-0xFFF8 - The function ID
68060 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68061 * * 0xFFFD - Reserved for user-space HWRM interface
68062 * * 0xFFFF - HWRM
68082 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
68084 #define HWRM_NVM_GET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
68089 * A value of 0 means that none of the indexN values are valid.
68105 * returned, 0 returns the operational value.
68107 #define HWRM_NVM_GET_VARIABLE_INPUT_FLAGS_FACTORY_DFLT UINT32_C(0x1)
68135 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
68137 #define HWRM_NVM_GET_VARIABLE_OUTPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
68159 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
68161 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
68163 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
68165 #define HWRM_NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT UINT32_C(0x3)
68193 * * 0x0-0xFFF8 - The function ID
68194 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68195 * * 0xFFFD - Reserved for user-space HWRM interface
68196 * * 0xFFFF - HWRM
68216 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
68218 #define HWRM_NVM_SET_VARIABLE_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
68223 * A value of 0 means that none of the indexN values are valid.
68241 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH UINT32_C(0x1)
68243 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_MASK UINT32_C(0xe)
68246 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_NONE (UINT32_C(0x0) << 1)
68248 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (UINT32_C(0x1) << 1)
68250 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_AES256 (UINT32_C(0x2) << 1)
68252 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (UINT32_C(0x3) << 1)
68254 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FLAGS_UNUSED_0_MASK UINT32_C(0x70)
68257 #define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FACTORY_DEFAULT UINT32_C(0x80)
68292 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
68294 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST UINT32_C(0x1)
68296 #define HWRM_NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR UINT32_C(0x2)
68324 * * 0x0-0xFFF8 - The function ID
68325 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68326 * * 0xFFFD - Reserved for user-space HWRM interface
68327 * * 0xFFFF - HWRM
68347 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_0 UINT32_C(0x0)
68349 #define HWRM_NVM_VALIDATE_OPTION_INPUT_OPTION_NUM_RSVD_FFFF UINT32_C(0xffff)
68354 * A value of 0 means that none of the indexN values are valid.
68386 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_NOT_MATCH UINT32_C(0x0)
68391 #define HWRM_NVM_VALIDATE_OPTION_OUTPUT_RESULT_MATCH UINT32_C(0x1)
68413 #define HWRM_NVM_VALIDATE_OPTION_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
68441 * * 0x0-0xFFF8 - The function ID
68442 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68443 * * 0xFFFD - Reserved for user-space HWRM interface
68444 * * 0xFFFF - HWRM
68462 #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0)
68469 #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1)
68474 * If it is '0', the operation applies to all data. If it is not '0',
68479 #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_SELECTION_CFG_OPTION UINT32_C(0x1)
68481 #define HWRM_NVM_FACTORY_DEFAULTS_INPUT_SELECTION_CRASHDUMP UINT32_C(0x2)
68498 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK UINT32_C(0x0)
68500 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK UINT32_C(0x1)
68502 #define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY UINT32_C(0x2)
68524 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
68526 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG UINT32_C(0x1)
68528 #define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG UINT32_C(0x2)
68556 * * 0x0-0xFFF8 - The function ID
68557 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68558 * * 0xFFFD - Reserved for user-space HWRM interface
68559 * * 0xFFFF - HWRM
68572 #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_STATUS UINT32_C(0x0)
68574 #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_ACQUIRE UINT32_C(0x1)
68576 #define HWRM_NVM_REQ_ARBITRATION_INPUT_TYPE_RELEASE UINT32_C(0x2)
68628 * * 0x0-0xFFF8 - The function ID
68629 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68630 * * 0xFFFD - Reserved for user-space HWRM interface
68631 * * 0xFFFF - HWRM
68643 #define HWRM_NVM_DEFRAG_INPUT_FLAGS_DEFRAG UINT32_C(0x1)
68678 #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
68680 #define HWRM_NVM_DEFRAG_CMD_ERR_CODE_FAIL UINT32_C(0x1)
68708 * * 0x0-0xFFF8 - The function ID
68709 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68710 * * 0xFFFD - Reserved for user-space HWRM interface
68711 * * 0xFFFF - HWRM
68723 * a value of [0x00, 0x82] should be used. All other fields
68726 * in tag_id[0] and the next letter in tag_id[1].
68781 * * 0x0-0xFFF8 - The function ID
68782 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
68783 * * 0xFFFD - Reserved for user-space HWRM interface
68784 * * 0xFFFF - HWRM
68801 * a value of [0x00, 0x82] should be used. All other fields
68804 * in tag_id[0] and the next letter in tag_id[1].
68852 #define CMDQ_INIT_CMDQ_LVL_MASK UINT32_C(0x3)
68853 #define CMDQ_INIT_CMDQ_LVL_SFT 0
68855 #define CMDQ_INIT_CMDQ_SIZE_MASK UINT32_C(0xfffc)
68883 #define CMDQ_BASE_OPCODE_CREATE_QP UINT32_C(0x1)
68888 #define CMDQ_BASE_OPCODE_DESTROY_QP UINT32_C(0x2)
68893 #define CMDQ_BASE_OPCODE_MODIFY_QP UINT32_C(0x3)
68895 #define CMDQ_BASE_OPCODE_QUERY_QP UINT32_C(0x4)
68897 #define CMDQ_BASE_OPCODE_CREATE_SRQ UINT32_C(0x5)
68899 #define CMDQ_BASE_OPCODE_DESTROY_SRQ UINT32_C(0x6)
68901 #define CMDQ_BASE_OPCODE_QUERY_SRQ UINT32_C(0x8)
68903 #define CMDQ_BASE_OPCODE_CREATE_CQ UINT32_C(0x9)
68905 #define CMDQ_BASE_OPCODE_DESTROY_CQ UINT32_C(0xa)
68907 #define CMDQ_BASE_OPCODE_RESIZE_CQ UINT32_C(0xc)
68912 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW UINT32_C(0xd)
68917 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY UINT32_C(0xe)
68919 #define CMDQ_BASE_OPCODE_REGISTER_MR UINT32_C(0xf)
68921 #define CMDQ_BASE_OPCODE_DEREGISTER_MR UINT32_C(0x10)
68923 #define CMDQ_BASE_OPCODE_ADD_GID UINT32_C(0x11)
68925 #define CMDQ_BASE_OPCODE_DELETE_GID UINT32_C(0x12)
68927 #define CMDQ_BASE_OPCODE_MODIFY_GID UINT32_C(0x17)
68929 #define CMDQ_BASE_OPCODE_QUERY_GID UINT32_C(0x18)
68931 #define CMDQ_BASE_OPCODE_CREATE_QP1 UINT32_C(0x13)
68933 #define CMDQ_BASE_OPCODE_DESTROY_QP1 UINT32_C(0x14)
68935 #define CMDQ_BASE_OPCODE_CREATE_AH UINT32_C(0x15)
68937 #define CMDQ_BASE_OPCODE_DESTROY_AH UINT32_C(0x16)
68942 #define CMDQ_BASE_OPCODE_INITIALIZE_FW UINT32_C(0x80)
68944 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW UINT32_C(0x81)
68946 #define CMDQ_BASE_OPCODE_STOP_FUNC UINT32_C(0x82)
68948 #define CMDQ_BASE_OPCODE_QUERY_FUNC UINT32_C(0x83)
68954 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84)
68959 #define CMDQ_BASE_OPCODE_READ_CONTEXT UINT32_C(0x85)
68964 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86)
68969 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY UINT32_C(0x87)
68975 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88)
68981 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRAY_DEPRECATED UINT32_C(0x89)
68983 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a)
68985 #define CMDQ_BASE_OPCODE_QUERY_VERSION UINT32_C(0x8b)
68987 #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
68989 #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
68991 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e)
68993 #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f)
68995 #define CMDQ_BASE_OPCODE_MODIFY_CQ UINT32_C(0x90)
69000 #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
69002 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92)
69009 #define CMDQ_BASE_OPCODE_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93)
69014 #define CMDQ_BASE_OPCODE_CREATE_QP_BATCH UINT32_C(0x94)
69020 #define CMDQ_BASE_OPCODE_DESTROY_QP_BATCH UINT32_C(0x95)
69029 #define CMDQ_BASE_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96)
69031 #define CMDQ_BASE_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97)
69036 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
69062 #define CREQ_BASE_TYPE_MASK UINT32_C(0x3f)
69063 #define CREQ_BASE_TYPE_SFT 0
69065 #define CREQ_BASE_TYPE_QP_EVENT UINT32_C(0x38)
69067 #define CREQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
69074 * will write 1. The odd passes will write 0.
69076 #define CREQ_BASE_V UINT32_C(0x1)
69088 #define CREQ_RESP_SB_HDR_OPCODE_QUERY_QP UINT32_C(0x4)
69090 #define CREQ_RESP_SB_HDR_OPCODE_QUERY_SRQ UINT32_C(0x8)
69092 #define CREQ_RESP_SB_HDR_OPCODE_QUERY_GID UINT32_C(0x18)
69094 #define CREQ_RESP_SB_HDR_OPCODE_QUERY_FUNC UINT32_C(0x83)
69096 #define CREQ_RESP_SB_HDR_OPCODE_QUERY_VERSION UINT32_C(0x8b)
69098 #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
69100 #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e)
69102 #define CREQ_RESP_SB_HDR_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
69104 #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92)
69106 #define CREQ_RESP_SB_HDR_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
69134 #define CREATE_QP_BATCH_DATA_QP_FLAGS_SRQ_USED UINT32_C(0x1)
69136 #define CREATE_QP_BATCH_DATA_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2)
69138 #define CREATE_QP_BATCH_DATA_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
69140 #define CREATE_QP_BATCH_DATA_QP_FLAGS_FR_PMR_ENABLED UINT32_C(0x8)
69142 #define CREATE_QP_BATCH_DATA_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED UINT32_C(0x10)
69149 #define CREATE_QP_BATCH_DATA_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x20)
69155 #define CREATE_QP_BATCH_DATA_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA UINT32_C(0x40)
69160 #define CREATE_QP_BATCH_DATA_QP_FLAGS_EXT_STATS_ENABLED UINT32_C(0x80)
69162 #define CREATE_QP_BATCH_DATA_QP_FLAGS_EXPRESS_MODE_ENABLED UINT32_C(0x100)
69164 #define CREATE_QP_BATCH_DATA_QP_FLAGS_STEERING_TAG_VALID UINT32_C(0x200)
69170 #define CREATE_QP_BATCH_DATA_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED UINT32_C(0x400)
69175 #define CREATE_QP_BATCH_DATA_QP_FLAGS_EXT_STATS_CTX_VALID UINT32_C(0x800)
69177 #define CREATE_QP_BATCH_DATA_QP_FLAGS_SCHQ_ID_VALID UINT32_C(0x1000)
69182 #define CREATE_QP_BATCH_DATA_TYPE_RC UINT32_C(0x2)
69184 #define CREATE_QP_BATCH_DATA_TYPE_UD UINT32_C(0x4)
69186 #define CREATE_QP_BATCH_DATA_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
69188 #define CREATE_QP_BATCH_DATA_TYPE_GSI UINT32_C(0x7)
69195 #define CREATE_QP_BATCH_DATA_SQ_LVL_MASK UINT32_C(0xf)
69196 #define CREATE_QP_BATCH_DATA_SQ_LVL_SFT 0
69198 #define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_0 UINT32_C(0x0)
69200 #define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_1 UINT32_C(0x1)
69205 #define CREATE_QP_BATCH_DATA_SQ_LVL_LVL_2 UINT32_C(0x2)
69211 #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_MASK UINT32_C(0xf0)
69214 #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
69216 #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
69218 #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
69220 #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
69222 #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
69224 #define CREATE_QP_BATCH_DATA_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
69231 #define CREATE_QP_BATCH_DATA_RQ_LVL_MASK UINT32_C(0xf)
69232 #define CREATE_QP_BATCH_DATA_RQ_LVL_SFT 0
69234 #define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_0 UINT32_C(0x0)
69236 #define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_1 UINT32_C(0x1)
69241 #define CREATE_QP_BATCH_DATA_RQ_LVL_LVL_2 UINT32_C(0x2)
69247 #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_MASK UINT32_C(0xf0)
69250 #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
69252 #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
69254 #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
69256 #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
69258 #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
69260 #define CREATE_QP_BATCH_DATA_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
69278 #define CREATE_QP_BATCH_DATA_SQ_SGE_MASK UINT32_C(0xf)
69279 #define CREATE_QP_BATCH_DATA_SQ_SGE_SFT 0
69284 #define CREATE_QP_BATCH_DATA_SQ_FWO_MASK UINT32_C(0xfff0)
69292 #define CREATE_QP_BATCH_DATA_RQ_SGE_MASK UINT32_C(0xf)
69293 #define CREATE_QP_BATCH_DATA_RQ_SGE_SFT 0
69298 #define CREATE_QP_BATCH_DATA_RQ_FWO_MASK UINT32_C(0xfff0)
69477 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION UINT32_C(0x8b)
69503 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK UINT32_C(0x3f)
69504 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0
69506 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT UINT32_C(0x38)
69524 * will write 1. The odd passes will write 0.
69526 #define CREQ_QUERY_VERSION_RESP_V UINT32_C(0x1)
69530 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION UINT32_C(0x8b)
69557 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW UINT32_C(0x80)
69567 #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x1)
69572 #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED UINT32_C(0x2)
69574 #define CMDQ_INITIALIZE_FW_FLAGS_DRV_VERSION UINT32_C(0x4)
69576 #define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED UINT32_C(0x8)
69581 #define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT UINT32_C(0x10)
69591 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK UINT32_C(0xf)
69592 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0
69594 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 UINT32_C(0x0)
69596 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 UINT32_C(0x1)
69601 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 UINT32_C(0x2)
69604 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK UINT32_C(0xf0)
69607 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
69609 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
69611 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
69613 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
69615 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
69617 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
69621 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK UINT32_C(0xf)
69622 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0
69624 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 UINT32_C(0x0)
69626 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 UINT32_C(0x1)
69631 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 UINT32_C(0x2)
69634 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK UINT32_C(0xf0)
69637 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
69639 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
69641 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
69643 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
69645 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
69647 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
69651 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK UINT32_C(0xf)
69652 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0
69654 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 UINT32_C(0x0)
69656 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 UINT32_C(0x1)
69661 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 UINT32_C(0x2)
69664 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK UINT32_C(0xf0)
69667 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
69669 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
69671 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
69673 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
69675 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
69677 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
69681 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK UINT32_C(0xf)
69682 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0
69684 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 UINT32_C(0x0)
69686 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 UINT32_C(0x1)
69691 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 UINT32_C(0x2)
69694 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK UINT32_C(0xf0)
69697 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
69699 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
69701 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
69703 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
69705 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
69707 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
69711 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK UINT32_C(0xf)
69712 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0
69714 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 UINT32_C(0x0)
69716 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 UINT32_C(0x1)
69721 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 UINT32_C(0x2)
69724 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK UINT32_C(0xf0)
69727 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
69729 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
69731 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
69733 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
69735 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
69737 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
69741 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK UINT32_C(0xf)
69742 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0
69744 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 UINT32_C(0x0)
69746 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 UINT32_C(0x1)
69751 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 UINT32_C(0x2)
69754 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK UINT32_C(0xf0)
69757 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
69759 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
69761 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
69763 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
69765 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
69767 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
69771 * Log base 2 of DBR page size - 12. 0 for 4KB. HW supported values
69774 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK UINT32_C(0xf)
69775 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0
69777 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K UINT32_C(0x0)
69779 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K UINT32_C(0x1)
69781 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K UINT32_C(0x2)
69783 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K UINT32_C(0x3)
69785 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K UINT32_C(0x4)
69787 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K UINT32_C(0x5)
69789 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K UINT32_C(0x6)
69791 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K UINT32_C(0x7)
69793 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M UINT32_C(0x8)
69795 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M UINT32_C(0x9)
69797 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M UINT32_C(0xa)
69799 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M UINT32_C(0xb)
69801 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M UINT32_C(0xc)
69803 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M UINT32_C(0xd)
69805 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M UINT32_C(0xe)
69807 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M UINT32_C(0xf)
69810 #define CMDQ_INITIALIZE_FW_RSVD_MASK UINT32_C(0xfff0)
69858 * represents the `max_mr_per_vf` and bits `[15:0]` represents
69913 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f)
69914 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0
69916 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
69927 * will write 1. The odd passes will write 0.
69929 #define CREQ_INITIALIZE_FW_RESP_V UINT32_C(0x1)
69933 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW UINT32_C(0x80)
69949 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW UINT32_C(0x81)
69975 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK UINT32_C(0x3f)
69976 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0
69978 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
69989 * will write 1. The odd passes will write 0.
69991 #define CREQ_DEINITIALIZE_FW_RESP_V UINT32_C(0x1)
69995 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW UINT32_C(0x81)
70014 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP UINT32_C(0x1)
70035 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED UINT32_C(0x1)
70037 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2)
70039 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
70041 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED UINT32_C(0x8)
70043 #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED UINT32_C(0x10)
70050 #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x20)
70056 #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA UINT32_C(0x40)
70061 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED UINT32_C(0x80)
70063 #define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED UINT32_C(0x100)
70065 #define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID UINT32_C(0x200)
70071 #define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED UINT32_C(0x400)
70076 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_CTX_VALID UINT32_C(0x800)
70078 #define CMDQ_CREATE_QP_QP_FLAGS_SCHQ_ID_VALID UINT32_C(0x1000)
70083 #define CMDQ_CREATE_QP_TYPE_RC UINT32_C(0x2)
70085 #define CMDQ_CREATE_QP_TYPE_UD UINT32_C(0x4)
70087 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
70089 #define CMDQ_CREATE_QP_TYPE_GSI UINT32_C(0x7)
70096 #define CMDQ_CREATE_QP_SQ_LVL_MASK UINT32_C(0xf)
70097 #define CMDQ_CREATE_QP_SQ_LVL_SFT 0
70099 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 UINT32_C(0x0)
70101 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 UINT32_C(0x1)
70106 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 UINT32_C(0x2)
70112 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK UINT32_C(0xf0)
70115 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
70117 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
70119 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
70121 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
70123 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
70125 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
70132 #define CMDQ_CREATE_QP_RQ_LVL_MASK UINT32_C(0xf)
70133 #define CMDQ_CREATE_QP_RQ_LVL_SFT 0
70135 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 UINT32_C(0x0)
70137 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 UINT32_C(0x1)
70142 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 UINT32_C(0x2)
70148 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK UINT32_C(0xf0)
70151 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
70153 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
70155 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
70157 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
70159 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
70161 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
70179 #define CMDQ_CREATE_QP_SQ_SGE_MASK UINT32_C(0xf)
70180 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0
70185 #define CMDQ_CREATE_QP_SQ_FWO_MASK UINT32_C(0xfff0)
70193 #define CMDQ_CREATE_QP_RQ_SGE_MASK UINT32_C(0xf)
70194 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0
70199 #define CMDQ_CREATE_QP_RQ_FWO_MASK UINT32_C(0xfff0)
70279 #define CREQ_CREATE_QP_RESP_TYPE_MASK UINT32_C(0x3f)
70280 #define CREQ_CREATE_QP_RESP_TYPE_SFT 0
70282 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
70294 * will write 1. The odd passes will write 0.
70296 #define CREQ_CREATE_QP_RESP_V UINT32_C(0x1)
70300 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP UINT32_C(0x1)
70324 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP UINT32_C(0x2)
70353 #define CREQ_DESTROY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
70354 #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0
70356 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
70368 * will write 1. The odd passes will write 0.
70370 #define CREQ_DESTROY_QP_RESP_V UINT32_C(0x1)
70374 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP UINT32_C(0x2)
70393 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP UINT32_C(0x3)
70405 #define CMDQ_MODIFY_QP_FLAGS_SRQ_USED UINT32_C(0x1)
70417 #define CMDQ_MODIFY_QP_QP_TYPE_RC UINT32_C(0x2)
70419 #define CMDQ_MODIFY_QP_QP_TYPE_UD UINT32_C(0x4)
70421 #define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE UINT32_C(0x6)
70423 #define CMDQ_MODIFY_QP_QP_TYPE_GSI UINT32_C(0x7)
70430 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE UINT32_C(0x1)
70432 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY UINT32_C(0x2)
70434 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS UINT32_C(0x4)
70436 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY UINT32_C(0x8)
70438 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY UINT32_C(0x10)
70440 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID UINT32_C(0x20)
70442 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL UINT32_C(0x40)
70444 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX UINT32_C(0x80)
70446 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT UINT32_C(0x100)
70448 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS UINT32_C(0x200)
70450 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC UINT32_C(0x400)
70452 #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE UINT32_C(0x800)
70454 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU UINT32_C(0x1000)
70456 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT UINT32_C(0x2000)
70458 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT UINT32_C(0x4000)
70460 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY UINT32_C(0x8000)
70462 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN UINT32_C(0x10000)
70464 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC UINT32_C(0x20000)
70466 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER UINT32_C(0x40000)
70468 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN UINT32_C(0x80000)
70470 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC UINT32_C(0x100000)
70472 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE UINT32_C(0x200000)
70474 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE UINT32_C(0x400000)
70476 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE UINT32_C(0x800000)
70478 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE UINT32_C(0x1000000)
70480 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA UINT32_C(0x2000000)
70482 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID UINT32_C(0x4000000)
70484 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC UINT32_C(0x8000000)
70486 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID UINT32_C(0x10000000)
70488 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC UINT32_C(0x20000000)
70490 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN UINT32_C(0x40000000)
70492 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP UINT32_C(0x80000000)
70497 #define CMDQ_MODIFY_QP_NEW_STATE_MASK UINT32_C(0xf)
70498 #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0
70500 #define CMDQ_MODIFY_QP_NEW_STATE_RESET UINT32_C(0x0)
70502 #define CMDQ_MODIFY_QP_NEW_STATE_INIT UINT32_C(0x1)
70504 #define CMDQ_MODIFY_QP_NEW_STATE_RTR UINT32_C(0x2)
70506 #define CMDQ_MODIFY_QP_NEW_STATE_RTS UINT32_C(0x3)
70508 #define CMDQ_MODIFY_QP_NEW_STATE_SQD UINT32_C(0x4)
70510 #define CMDQ_MODIFY_QP_NEW_STATE_SQE UINT32_C(0x5)
70512 #define CMDQ_MODIFY_QP_NEW_STATE_ERR UINT32_C(0x6)
70515 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10)
70517 #define CMDQ_MODIFY_QP_UNUSED1 UINT32_C(0x20)
70519 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK UINT32_C(0xc0)
70522 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (UINT32_C(0x0) << 6)
70524 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (UINT32_C(0x2) << 6)
70526 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (UINT32_C(0x3) << 6)
70530 …#define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK UINT32_C(0x…
70531 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0
70533 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE UINT32_C(0x1)
70535 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE UINT32_C(0x2)
70537 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ UINT32_C(0x4)
70542 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
70561 #define CMDQ_MODIFY_QP_TOS_ECN_MASK UINT32_C(0x3)
70562 #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0
70564 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK UINT32_C(0xfc)
70572 #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE UINT32_C(0x1)
70574 #define CMDQ_MODIFY_QP_UNUSED3_MASK UINT32_C(0xe)
70577 #define CMDQ_MODIFY_QP_PATH_MTU_MASK UINT32_C(0xf0)
70580 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (UINT32_C(0x0) << 4)
70582 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (UINT32_C(0x1) << 4)
70584 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 4)
70586 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 4)
70588 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 4)
70590 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 4)
70610 #define CMDQ_MODIFY_QP_ENABLE_CC UINT32_C(0x1)
70612 #define CMDQ_MODIFY_QP_UNUSED15_MASK UINT32_C(0xfffe)
70632 #define CMDQ_MODIFY_QP_VLAN_ID_MASK UINT32_C(0xfff)
70633 #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0
70635 #define CMDQ_MODIFY_QP_VLAN_DEI UINT32_C(0x1000)
70637 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK UINT32_C(0xe000)
70649 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX UINT32_C(0x1)
70651 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID UINT32_C(0x2)
70679 #define CREQ_MODIFY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
70680 #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0
70682 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
70694 * will write 1. The odd passes will write 0.
70696 #define CREQ_MODIFY_QP_RESP_V UINT32_C(0x1)
70700 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP UINT32_C(0x3)
70707 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED UINT32_C(0x1)
70712 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK UINT32_C(0xe)
70716 * for first push operation. 0 - ping buffer, 1 - pong buffer.
70718 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE UINT32_C(0x10)
70735 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP UINT32_C(0x4)
70764 #define CREQ_QUERY_QP_RESP_TYPE_MASK UINT32_C(0x3f)
70765 #define CREQ_QUERY_QP_RESP_TYPE_SFT 0
70767 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT UINT32_C(0x38)
70779 * will write 1. The odd passes will write 0.
70781 #define CREQ_QUERY_QP_RESP_V UINT32_C(0x1)
70785 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP UINT32_C(0x4)
70797 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP UINT32_C(0x4)
70812 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK UINT32_C(0xf)
70813 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0
70815 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET UINT32_C(0x0)
70817 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT UINT32_C(0x1)
70819 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR UINT32_C(0x2)
70821 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS UINT32_C(0x3)
70823 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD UINT32_C(0x4)
70825 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE UINT32_C(0x5)
70827 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR UINT32_C(0x6)
70830 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY UINT32_C(0x10)
70832 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK UINT32_C(0xe0)
70836 …REQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK UINT32_C(0xff)
70837 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0
70839 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE UINT32_C(0x1)
70841 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE UINT32_C(0x2)
70843 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ UINT32_C(0x4)
70845 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
70870 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK UINT32_C(0xfff)
70871 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0
70873 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK UINT32_C(0xf000)
70876 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (UINT32_C(0x0) << 12)
70878 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (UINT32_C(0x1) << 12)
70880 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (UINT32_C(0x2) << 12)
70882 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (UINT32_C(0x3) << 12)
70884 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (UINT32_C(0x4) << 12)
70886 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (UINT32_C(0x5) << 12)
70906 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK UINT32_C(0x3)
70907 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0
70909 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc)
70913 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC UINT32_C(0x1)
70935 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK UINT32_C(0xfff)
70936 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0
70938 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI UINT32_C(0x1000)
70940 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK UINT32_C(0xe000)
70958 #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
70978 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK UINT32_C(0xff)
70979 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0
70981 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK UINT32_C(0xffff00)
70984 #define CMDQ_QUERY_QP_EXTEND_VF_VALID UINT32_C(0x1000000)
71003 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK UINT32_C(0x3f)
71004 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0
71006 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT UINT32_C(0x38)
71018 * will write 1. The odd passes will write 0.
71020 #define CREQ_QUERY_QP_EXTEND_RESP_V UINT32_C(0x1)
71024 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND UINT32_C(0x91)
71041 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
71056 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK UINT32_C(0xf)
71057 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0
71059 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET UINT32_C(0x0)
71061 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT UINT32_C(0x1)
71063 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR UINT32_C(0x2)
71065 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS UINT32_C(0x3)
71067 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD UINT32_C(0x4)
71069 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE UINT32_C(0x5)
71071 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR UINT32_C(0x6)
71074 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK UINT32_C(0xf0)
71086 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 UINT32_C(0x0)
71088 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 UINT32_C(0x2)
71090 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 UINT32_C(0x3)
71115 * For TLV encapsulated messages this field must be 0x8000.
71124 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
71126 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
71128 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
71135 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
71137 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
71139 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
71150 * Global TLV range: `0 - (63k-1)`
71170 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND UINT32_C(0x91)
71185 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK UINT32_C(0xf)
71186 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0
71188 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET UINT32_C(0x0)
71190 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT UINT32_C(0x1)
71192 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR UINT32_C(0x2)
71194 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS UINT32_C(0x3)
71196 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD UINT32_C(0x4)
71198 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE UINT32_C(0x5)
71200 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR UINT32_C(0x6)
71203 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK UINT32_C(0xf0)
71215 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 UINT32_C(0x0)
71217 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 UINT32_C(0x2)
71219 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 UINT32_C(0x3)
71243 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ UINT32_C(0x5)
71250 #define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID UINT32_C(0x1)
71262 #define CMDQ_CREATE_SRQ_LVL_MASK UINT32_C(0x3)
71263 #define CMDQ_CREATE_SRQ_LVL_SFT 0
71265 #define CMDQ_CREATE_SRQ_LVL_LVL_0 UINT32_C(0x0)
71267 #define CMDQ_CREATE_SRQ_LVL_LVL_1 UINT32_C(0x1)
71272 #define CMDQ_CREATE_SRQ_LVL_LVL_2 UINT32_C(0x2)
71275 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK UINT32_C(0x1c)
71278 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
71280 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
71282 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
71284 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
71286 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
71288 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
71291 #define CMDQ_CREATE_SRQ_UNUSED11_MASK UINT32_C(0xffe0)
71295 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK UINT32_C(0xfff)
71296 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0
71298 #define CMDQ_CREATE_SRQ_UNUSED4_MASK UINT32_C(0xf000)
71304 #define CMDQ_CREATE_SRQ_SRQ_FWO_MASK UINT32_C(0xfff)
71305 #define CMDQ_CREATE_SRQ_SRQ_FWO_SFT 0
71310 #define CMDQ_CREATE_SRQ_SRQ_SGE_MASK UINT32_C(0xf000)
71336 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
71337 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0
71339 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
71351 * will write 1. The odd passes will write 0.
71353 #define CREQ_CREATE_SRQ_RESP_V UINT32_C(0x1)
71357 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ UINT32_C(0x5)
71373 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ UINT32_C(0x6)
71402 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
71403 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0
71405 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
71417 * will write 1. The odd passes will write 0.
71419 #define CREQ_DESTROY_SRQ_RESP_V UINT32_C(0x1)
71423 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ UINT32_C(0x6)
71426 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK UINT32_C(0xffff)
71427 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0
71432 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK UINT32_C(0x30000)
71447 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ UINT32_C(0x8)
71476 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK UINT32_C(0x3f)
71477 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0
71479 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
71491 * will write 1. The odd passes will write 0.
71493 #define CREQ_QUERY_SRQ_RESP_V UINT32_C(0x1)
71497 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ UINT32_C(0x8)
71509 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ UINT32_C(0x8)
71540 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ UINT32_C(0x9)
71556 #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x1)
71558 #define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID UINT32_C(0x2)
71570 #define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE UINT32_C(0x4)
71575 #define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID UINT32_C(0x8)
71587 #define CMDQ_CREATE_CQ_LVL_MASK UINT32_C(0x3)
71588 #define CMDQ_CREATE_CQ_LVL_SFT 0
71590 #define CMDQ_CREATE_CQ_LVL_LVL_0 UINT32_C(0x0)
71592 #define CMDQ_CREATE_CQ_LVL_LVL_1 UINT32_C(0x1)
71597 #define CMDQ_CREATE_CQ_LVL_LVL_2 UINT32_C(0x2)
71600 #define CMDQ_CREATE_CQ_PG_SIZE_MASK UINT32_C(0x1c)
71603 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
71605 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
71607 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
71609 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
71611 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
71613 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
71616 #define CMDQ_CREATE_CQ_UNUSED27_MASK UINT32_C(0xffffffe0)
71620 #define CMDQ_CREATE_CQ_CNQ_ID_MASK UINT32_C(0xfff)
71621 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0
71623 #define CMDQ_CREATE_CQ_CQ_FCO_MASK UINT32_C(0xfffff000)
71641 #define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK UINT32_C(0x1ff)
71642 #define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT 0
71648 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK UINT32_C(0x3e00)
71655 #define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK UINT32_C(0x7c000)
71664 #define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE UINT32_C(0x80000)
71666 #define CMDQ_CREATE_CQ_UNUSED12_MASK UINT32_C(0xfff00000)
71683 #define CREQ_CREATE_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
71684 #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0
71686 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
71698 * will write 1. The odd passes will write 0.
71700 #define CREQ_CREATE_CQ_RESP_V UINT32_C(0x1)
71704 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ UINT32_C(0x9)
71720 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ UINT32_C(0xa)
71749 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
71750 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0
71752 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
71764 * will write 1. The odd passes will write 0.
71766 #define CREQ_DESTROY_CQ_RESP_V UINT32_C(0x1)
71770 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ UINT32_C(0xa)
71775 * 0 ? Not Armed
71779 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK UINT32_C(0x3)
71780 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0
71801 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ UINT32_C(0xc)
71818 #define CMDQ_RESIZE_CQ_LVL_MASK UINT32_C(0x3)
71819 #define CMDQ_RESIZE_CQ_LVL_SFT 0
71821 #define CMDQ_RESIZE_CQ_LVL_LVL_0 UINT32_C(0x0)
71823 #define CMDQ_RESIZE_CQ_LVL_LVL_1 UINT32_C(0x1)
71828 #define CMDQ_RESIZE_CQ_LVL_LVL_2 UINT32_C(0x2)
71831 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK UINT32_C(0x1c)
71834 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 2)
71836 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 2)
71838 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 2)
71840 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 2)
71842 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 2)
71844 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 2)
71847 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK UINT32_C(0x1fffffe0)
71867 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
71868 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0
71870 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
71882 * will write 1. The odd passes will write 0.
71884 #define CREQ_RESIZE_CQ_RESP_V UINT32_C(0x1)
71888 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ UINT32_C(0xc)
71904 #define CMDQ_MODIFY_CQ_OPCODE_MODIFY_CQ UINT32_C(0x90)
71920 #define CMDQ_MODIFY_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION UINT32_C(0x1)
71931 #define CMDQ_MODIFY_CQ_MODIFY_MASK_CQ_HANDLE UINT32_C(0x1)
71933 #define CMDQ_MODIFY_CQ_MODIFY_MASK_CNQ_ID UINT32_C(0x2)
71935 #define CMDQ_MODIFY_CQ_MODIFY_MASK_FCO UINT32_C(0x4)
71937 #define CMDQ_MODIFY_CQ_MODIFY_MASK_DPI UINT32_C(0x8)
71939 #define CMDQ_MODIFY_CQ_MODIFY_MASK_CQ_SIZE UINT32_C(0x10)
71941 #define CMDQ_MODIFY_CQ_MODIFY_MASK_PBL UINT32_C(0x20)
71948 #define CMDQ_MODIFY_CQ_CNQ_ID_MASK UINT32_C(0xfff)
71949 #define CMDQ_MODIFY_CQ_CNQ_ID_SFT 0
71951 #define CMDQ_MODIFY_CQ_CQ_FCO_MASK UINT32_C(0xfffff000)
71976 #define CREQ_MODIFY_CQ_RESP_TYPE_MASK UINT32_C(0x3f)
71977 #define CREQ_MODIFY_CQ_RESP_TYPE_SFT 0
71979 #define CREQ_MODIFY_CQ_RESP_TYPE_QP_EVENT UINT32_C(0x38)
71991 * will write 1. The odd passes will write 0.
71993 #define CREQ_MODIFY_CQ_RESP_V UINT32_C(0x1)
71997 #define CREQ_MODIFY_CQ_RESP_EVENT_MODIFY_CQ UINT32_C(0x9)
72016 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW UINT32_C(0xd)
72033 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK UINT32_C(0xf)
72034 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0
72036 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR UINT32_C(0x0)
72038 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR UINT32_C(0x1)
72040 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2)
72042 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3)
72044 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4)
72050 #define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID UINT32_C(0x10)
72052 #define CMDQ_ALLOCATE_MRW_UNUSED3_MASK UINT32_C(0xe0)
72057 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY UINT32_C(0x20)
72075 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK UINT32_C(0x3f)
72076 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0
72078 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT UINT32_C(0x38)
72090 * will write 1. The odd passes will write 0.
72092 #define CREQ_ALLOCATE_MRW_RESP_V UINT32_C(0x1)
72096 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW UINT32_C(0xd)
72115 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY UINT32_C(0xe)
72130 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK UINT32_C(0xf)
72131 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0
72133 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR UINT32_C(0x0)
72135 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR UINT32_C(0x1)
72137 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 UINT32_C(0x2)
72139 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A UINT32_C(0x3)
72141 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B UINT32_C(0x4)
72144 #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK UINT32_C(0xf0)
72163 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK UINT32_C(0x3f)
72164 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0
72166 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT UINT32_C(0x38)
72178 * will write 1. The odd passes will write 0.
72180 #define CREQ_DEALLOCATE_KEY_RESP_V UINT32_C(0x1)
72184 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY UINT32_C(0xe)
72213 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR UINT32_C(0xf)
72225 #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR UINT32_C(0x1)
72231 #define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID UINT32_C(0x2)
72233 #define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO UINT32_C(0x4)
72243 #define CMDQ_REGISTER_MR_LVL_MASK UINT32_C(0x3)
72244 #define CMDQ_REGISTER_MR_LVL_SFT 0
72246 #define CMDQ_REGISTER_MR_LVL_LVL_0 UINT32_C(0x0)
72248 #define CMDQ_REGISTER_MR_LVL_LVL_1 UINT32_C(0x1)
72253 #define CMDQ_REGISTER_MR_LVL_LVL_2 UINT32_C(0x2)
72259 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK UINT32_C(0x7c)
72262 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (UINT32_C(0xc) << 2)
72264 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (UINT32_C(0xd) << 2)
72266 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (UINT32_C(0x10) << 2)
72268 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (UINT32_C(0x12) << 2)
72270 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (UINT32_C(0x14) << 2)
72272 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (UINT32_C(0x15) << 2)
72274 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (UINT32_C(0x16) << 2)
72276 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (UINT32_C(0x1e) << 2)
72279 #define CMDQ_REGISTER_MR_UNUSED1 UINT32_C(0x80)
72283 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE UINT32_C(0x1)
72285 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ UINT32_C(0x2)
72287 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE UINT32_C(0x4)
72289 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC UINT32_C(0x8)
72291 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND UINT32_C(0x10)
72293 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED UINT32_C(0x20)
72299 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK UINT32_C(0x1f)
72300 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0
72302 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K UINT32_C(0xc)
72304 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K UINT32_C(0xd)
72306 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K UINT32_C(0x10)
72308 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K UINT32_C(0x12)
72310 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M UINT32_C(0x14)
72312 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M UINT32_C(0x15)
72314 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M UINT32_C(0x16)
72316 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G UINT32_C(0x1e)
72319 #define CMDQ_REGISTER_MR_UNUSED11_MASK UINT32_C(0xffe0)
72352 #define CREQ_REGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f)
72353 #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0
72355 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38)
72367 * will write 1. The odd passes will write 0.
72369 #define CREQ_REGISTER_MR_RESP_V UINT32_C(0x1)
72373 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR UINT32_C(0xf)
72389 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR UINT32_C(0x10)
72418 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK UINT32_C(0x3f)
72419 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0
72421 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT UINT32_C(0x38)
72433 * will write 1. The odd passes will write 0.
72435 #define CREQ_DEREGISTER_MR_RESP_V UINT32_C(0x1)
72439 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR UINT32_C(0x10)
72463 #define CMDQ_ADD_GID_OPCODE_ADD_GID UINT32_C(0x11)
72482 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK UINT32_C(0xffff)
72483 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0
72485 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
72486 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0
72488 #define CMDQ_ADD_GID_VLAN_TPID_MASK UINT32_C(0x7000)
72490 /* TPID = 0x88A8. */
72491 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
72492 /* TPID = 0x8100. */
72493 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
72494 /* TPID = 0x9100. */
72495 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
72496 /* TPID = 0x9200. */
72497 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
72498 /* TPID = 0x9300. */
72499 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
72501 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
72503 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
72505 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
72511 #define CMDQ_ADD_GID_VLAN_VLAN_EN UINT32_C(0x8000)
72516 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK UINT32_C(0xffff)
72517 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0
72519 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff)
72520 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0
72525 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000)
72540 #define CREQ_ADD_GID_RESP_TYPE_MASK UINT32_C(0x3f)
72541 #define CREQ_ADD_GID_RESP_TYPE_SFT 0
72543 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
72555 * will write 1. The odd passes will write 0.
72557 #define CREQ_ADD_GID_RESP_V UINT32_C(0x1)
72561 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID UINT32_C(0x11)
72577 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID UINT32_C(0x12)
72606 #define CREQ_DELETE_GID_RESP_TYPE_MASK UINT32_C(0x3f)
72607 #define CREQ_DELETE_GID_RESP_TYPE_SFT 0
72609 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
72621 * will write 1. The odd passes will write 0.
72623 #define CREQ_DELETE_GID_RESP_V UINT32_C(0x1)
72627 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID UINT32_C(0x12)
72643 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID UINT32_C(0x17)
72663 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
72664 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0
72666 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK UINT32_C(0x7000)
72668 /* TPID = 0x88A8. */
72669 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
72670 /* TPID = 0x8100. */
72671 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
72672 /* TPID = 0x9100. */
72673 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
72674 /* TPID = 0x9200. */
72675 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
72676 /* TPID = 0x9300. */
72677 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
72679 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
72681 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
72683 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
72689 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN UINT32_C(0x8000)
72697 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK UINT32_C(0x7fff)
72698 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0
72703 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID UINT32_C(0x8000)
72718 #define CREQ_MODIFY_GID_RESP_TYPE_MASK UINT32_C(0x3f)
72719 #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0
72721 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
72733 * will write 1. The odd passes will write 0.
72735 #define CREQ_MODIFY_GID_RESP_V UINT32_C(0x1)
72739 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID UINT32_C(0x11)
72755 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID UINT32_C(0x18)
72785 #define CREQ_QUERY_GID_RESP_TYPE_MASK UINT32_C(0x3f)
72786 #define CREQ_QUERY_GID_RESP_TYPE_SFT 0
72788 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT UINT32_C(0x38)
72800 * will write 1. The odd passes will write 0.
72802 #define CREQ_QUERY_GID_RESP_V UINT32_C(0x1)
72806 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID UINT32_C(0x18)
72818 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID UINT32_C(0x18)
72835 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK UINT32_C(0xffff)
72836 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0
72838 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK UINT32_C(0xfff)
72839 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0
72841 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK UINT32_C(0x7000)
72843 /* TPID = 0x88A8. */
72844 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (UINT32_C(0x0) << 12)
72845 /* TPID = 0x8100. */
72846 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (UINT32_C(0x1) << 12)
72847 /* TPID = 0x9100. */
72848 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (UINT32_C(0x2) << 12)
72849 /* TPID = 0x9200. */
72850 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (UINT32_C(0x3) << 12)
72851 /* TPID = 0x9300. */
72852 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (UINT32_C(0x4) << 12)
72854 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (UINT32_C(0x5) << 12)
72856 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (UINT32_C(0x6) << 12)
72858 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (UINT32_C(0x7) << 12)
72864 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN UINT32_C(0x8000)
72883 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 UINT32_C(0x13)
72901 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED UINT32_C(0x1)
72903 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION UINT32_C(0x2)
72905 #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE UINT32_C(0x4)
72910 #define CMDQ_CREATE_QP1_TYPE_GSI UINT32_C(0x1)
72914 #define CMDQ_CREATE_QP1_SQ_LVL_MASK UINT32_C(0xf)
72915 #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0
72917 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 UINT32_C(0x0)
72919 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 UINT32_C(0x1)
72924 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 UINT32_C(0x2)
72927 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK UINT32_C(0xf0)
72930 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
72932 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
72934 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
72936 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
72938 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
72940 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
72944 #define CMDQ_CREATE_QP1_RQ_LVL_MASK UINT32_C(0xf)
72945 #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0
72947 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 UINT32_C(0x0)
72949 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 UINT32_C(0x1)
72954 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 UINT32_C(0x2)
72957 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK UINT32_C(0xf0)
72960 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (UINT32_C(0x0) << 4)
72962 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (UINT32_C(0x1) << 4)
72964 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (UINT32_C(0x2) << 4)
72966 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (UINT32_C(0x3) << 4)
72968 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (UINT32_C(0x4) << 4)
72970 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (UINT32_C(0x5) << 4)
72981 #define CMDQ_CREATE_QP1_SQ_SGE_MASK UINT32_C(0xf)
72982 #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0
72984 #define CMDQ_CREATE_QP1_SQ_FWO_MASK UINT32_C(0xfff0)
72988 #define CMDQ_CREATE_QP1_RQ_SGE_MASK UINT32_C(0xf)
72989 #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0
72991 #define CMDQ_CREATE_QP1_RQ_FWO_MASK UINT32_C(0xfff0)
73018 #define CREQ_CREATE_QP1_RESP_TYPE_MASK UINT32_C(0x3f)
73019 #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0
73021 #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38)
73033 * will write 1. The odd passes will write 0.
73035 #define CREQ_CREATE_QP1_RESP_V UINT32_C(0x1)
73039 #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 UINT32_C(0x13)
73055 #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 UINT32_C(0x14)
73084 #define CREQ_DESTROY_QP1_RESP_TYPE_MASK UINT32_C(0x3f)
73085 #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0
73087 #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT UINT32_C(0x38)
73099 * will write 1. The odd passes will write 0.
73101 #define CREQ_DESTROY_QP1_RESP_V UINT32_C(0x1)
73105 #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 UINT32_C(0x14)
73121 #define CMDQ_CREATE_AH_OPCODE_CREATE_AH UINT32_C(0x15)
73141 #define CMDQ_CREATE_AH_TYPE_V1 UINT32_C(0x0)
73143 #define CMDQ_CREATE_AH_TYPE_V2IPV4 UINT32_C(0x2)
73145 #define CMDQ_CREATE_AH_TYPE_V2IPV6 UINT32_C(0x3)
73153 #define CMDQ_CREATE_AH_FLOW_LABEL_MASK UINT32_C(0xfffff)
73154 #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0
73156 #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK UINT32_C(0xfff00000)
73167 #define CMDQ_CREATE_AH_ENABLE_CC UINT32_C(0x1)
73181 #define CREQ_CREATE_AH_RESP_TYPE_MASK UINT32_C(0x3f)
73182 #define CREQ_CREATE_AH_RESP_TYPE_SFT 0
73184 #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
73196 * will write 1. The odd passes will write 0.
73198 #define CREQ_CREATE_AH_RESP_V UINT32_C(0x1)
73202 #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH UINT32_C(0x15)
73218 #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH UINT32_C(0x16)
73247 #define CREQ_DESTROY_AH_RESP_TYPE_MASK UINT32_C(0x3f)
73248 #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0
73250 #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
73262 * will write 1. The odd passes will write 0.
73264 #define CREQ_DESTROY_AH_RESP_V UINT32_C(0x1)
73268 #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH UINT32_C(0x16)
73284 #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e)
73296 #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID UINT32_C(0x1)
73303 #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID UINT32_C(0x2)
73315 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK UINT32_C(0xff)
73316 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0
73318 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK UINT32_C(0xffff00)
73321 #define CMDQ_QUERY_ROCE_STATS_VF_VALID UINT32_C(0x1000000)
73336 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK UINT32_C(0x3f)
73337 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0
73339 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT UINT32_C(0x38)
73351 * will write 1. The odd passes will write 0.
73353 #define CREQ_QUERY_ROCE_STATS_RESP_V UINT32_C(0x1)
73357 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS UINT32_C(0x8e)
73369 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS UINT32_C(0x8e)
73485 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS UINT32_C(0x92)
73497 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID UINT32_C(0x1)
73504 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID UINT32_C(0x2)
73516 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK UINT32_C(0xff)
73517 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0
73519 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK UINT32_C(0xffff00)
73522 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID UINT32_C(0x1000000)
73537 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK UINT32_C(0x3f)
73538 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0
73540 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT UINT32_C(0x38)
73552 * will write 1. The odd passes will write 0.
73554 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V UINT32_C(0x1)
73558 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT UINT32_C(0x92)
73570 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT UINT32_C(0x92)
73740 #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC UINT32_C(0x83)
73766 #define CREQ_QUERY_FUNC_RESP_TYPE_MASK UINT32_C(0x3f)
73767 #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0
73769 #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
73781 * will write 1. The odd passes will write 0.
73783 #define CREQ_QUERY_FUNC_RESP_V UINT32_C(0x1)
73787 #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC UINT32_C(0x83)
73799 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC UINT32_C(0x83)
73828 #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP UINT32_C(0x1)
73830 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK UINT32_C(0xe)
73836 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (UINT32_C(0x0) << 1)
73845 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (UINT32_C(0x1) << 1)
73851 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (UINT32_C(0x2) << 1)
73859 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN2 (UINT32_C(0x3) << 1)
73866 #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS UINT32_C(0x10)
73873 #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC UINT32_C(0x20)
73878 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED UINT32_C(0x40)
73884 #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 UINT32_C(0x80)
73886 #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE UINT32_C(0x100)
73888 #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED UINT32_C(0x200)
73890 #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED UINT32_C(0x400)
73892 #define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED UINT32_C(0x800)
73894 #define CREQ_QUERY_FUNC_RESP_SB_LINK_AGGR_SUPPORTED_VALID UINT32_C(0x1000)
73905 #define CREQ_QUERY_FUNC_RESP_SB_PSEUDO_STATIC_QP_ALLOC_SUPPORTED UINT32_C(0x2000)
73912 #define CREQ_QUERY_FUNC_RESP_SB_EXPRESS_MODE_SUPPORTED UINT32_C(0x4000)
73917 #define CREQ_QUERY_FUNC_RESP_SB_INTERNAL_QUEUE_MEMORY UINT32_C(0x8000)
73969 * space: 0x00000000, 0x01000000, 0x02000000, etc.
73985 #define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED UINT32_C(0x1)
73987 #define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED UINT32_C(0x2)
73989 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED UINT32_C(0x4)
73991 #define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED UINT32_C(0x8)
74003 #define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED UINT32_C(0x10)
74008 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED UINT32_C(0x20)
74010 #define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED UINT32_C(0x40)
74012 #define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED UINT32_C(0x80)
74034 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED UINT32_C(0x1)
74039 #define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED UINT32_C(0x2)
74041 #define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED UINT32_C(0x4)
74046 #define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED UINT32_C(0x8)
74048 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK UINT32_C(0x30)
74051 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (UINT32_C(0x0) << 4)
74053 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (UINT32_C(0x1) << 4)
74058 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (UINT32_C(0x2) << 4)
74095 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES UINT32_C(0x84)
74105 #define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT UINT32_C(0x1)
74151 * represents the `max_mr_per_vf` and bits `[15:0]` represents
74190 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK UINT32_C(0x3f)
74191 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0
74193 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT UINT32_C(0x38)
74204 * will write 1. The odd passes will write 0.
74206 #define CREQ_SET_FUNC_RESOURCES_RESP_V UINT32_C(0x1)
74210 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84)
74226 #define CMDQ_STOP_FUNC_OPCODE_STOP_FUNC UINT32_C(0x82)
74252 #define CREQ_STOP_FUNC_RESP_TYPE_MASK UINT32_C(0x3f)
74253 #define CREQ_STOP_FUNC_RESP_TYPE_SFT 0
74255 #define CREQ_STOP_FUNC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
74266 * will write 1. The odd passes will write 0.
74268 #define CREQ_STOP_FUNC_RESP_V UINT32_C(0x1)
74272 #define CREQ_STOP_FUNC_RESP_EVENT_STOP_FUNC UINT32_C(0x82)
74291 #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT UINT32_C(0x85)
74313 #define CMDQ_READ_CONTEXT_TYPE_QPC UINT32_C(0x0)
74318 #define CMDQ_READ_CONTEXT_TYPE_CQ UINT32_C(0x1)
74323 #define CMDQ_READ_CONTEXT_TYPE_MRW UINT32_C(0x2)
74328 #define CMDQ_READ_CONTEXT_TYPE_SRQ UINT32_C(0x3)
74344 #define CREQ_READ_CONTEXT_TYPE_MASK UINT32_C(0x3f)
74345 #define CREQ_READ_CONTEXT_TYPE_SFT 0
74347 #define CREQ_READ_CONTEXT_TYPE_QP_EVENT UINT32_C(0x38)
74358 * will write 1. The odd passes will write 0.
74360 #define CREQ_READ_CONTEXT_V UINT32_C(0x1)
74367 #define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT UINT32_C(0x85)
74384 #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS UINT32_C(0x8a)
74400 #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE UINT32_C(0xffff)
74405 #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE UINT32_C(0x8000)
74407 #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE UINT32_C(0xffff)
74423 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK UINT32_C(0x3f)
74424 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0
74426 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT UINT32_C(0x38)
74437 * will write 1. The odd passes will write 0.
74439 #define CREQ_MAP_TC_TO_COS_RESP_V UINT32_C(0x1)
74443 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS UINT32_C(0x8a)
74459 #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
74485 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f)
74486 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0
74488 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
74500 * will write 1. The odd passes will write 0.
74502 #define CREQ_QUERY_ROCE_CC_RESP_V UINT32_C(0x1)
74506 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC UINT32_C(0x8d)
74518 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
74531 #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC UINT32_C(0x1)
74533 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK UINT32_C(0xfe)
74537 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK UINT32_C(0x3)
74538 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0
74540 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK UINT32_C(0xfc)
74552 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK UINT32_C(0x7)
74553 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0
74555 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK UINT32_C(0xf8)
74559 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
74560 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0
74562 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK UINT32_C(0xc0)
74566 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP UINT32_C(0x0)
74568 * Probabilistic marking CC algorithm. On chips with CC Gen 0
74571 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC UINT32_C(0x1)
74577 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK UINT32_C(0x3fff)
74578 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0
74580 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK UINT32_C(0xc000)
74584 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK UINT32_C(0x3ff)
74585 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0
74587 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK UINT32_C(0xfc00)
74611 * For TLV encapsulated messages this field must be 0x8000.
74620 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
74622 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
74624 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
74631 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
74633 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
74635 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
74646 * Global TLV range: `0 - (63k-1)`
74666 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC UINT32_C(0x8d)
74679 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC UINT32_C(0x1)
74681 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK UINT32_C(0xfe)
74685 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK UINT32_C(0x3)
74686 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0
74688 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK UINT32_C(0xfc)
74700 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK UINT32_C(0x7)
74701 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0
74703 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK UINT32_C(0xf8)
74707 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
74708 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0
74710 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK UINT32_C(0xc0)
74714 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP UINT32_C(0x0)
74716 * Probabilistic marking CC algorithm. On chips with CC Gen 0
74719 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC UINT32_C(0x1)
74725 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK UINT32_C(0x3fff)
74726 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0
74728 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK UINT32_C(0xc000)
74732 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK UINT32_C(0x3ff)
74733 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0
74735 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK UINT32_C(0xfc00)
74754 * For TLV encapsulated messages this field must be 0x8000.
74763 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
74765 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
74767 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
74774 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
74776 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
74778 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
74789 * Global TLV range: `0 - (63k-1)`
74810 * is 0 - 1023.
74814 * In tr_update_mode 0, Target Rate (TR) is updated to
74821 * 0: TR is updated when QPC. rtts_with_cnps == 0
74851 * as a reduction reference. Values between 0 and 6 represent factor of
74859 * 0 for disable, 1 for enable.
74867 * 0 for not_ect, 1 for ect_0, 2 for ect_1
74871 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT UINT32_C(0x0)
74873 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 UINT32_C(0x1)
74874 /* ECN Capable Transport-0 */
74875 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 UINT32_C(0x2)
75006 * For TLV encapsulated messages this field must be 0x8000.
75015 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
75017 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
75019 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
75026 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
75028 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
75030 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
75041 * Global TLV range: `0 - (63k-1)`
75055 * level table indices 0 to 7.
75061 * DCN queue level table indices 0 to 7.
75065 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK UINT32_C(0x3fff)
75066 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT 0
75068 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP UINT32_C(0x4000)
75070 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM UINT32_C(0x8000)
75072 #define CREQ_QUERY_ROCE_CC_GEN2_RESP_SB_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK UINT32_C(0x3fff0000)
75087 #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
75103 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC UINT32_C(0x1)
75105 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G UINT32_C(0x2)
75107 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE UINT32_C(0x4)
75109 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR UINT32_C(0x8)
75111 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR UINT32_C(0x10)
75113 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN UINT32_C(0x20)
75115 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP UINT32_C(0x40)
75117 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP UINT32_C(0x80)
75119 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP UINT32_C(0x100)
75121 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT UINT32_C(0x200)
75123 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE UINT32_C(0x400)
75125 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP UINT32_C(0x800)
75127 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE UINT32_C(0x1000)
75129 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP UINT32_C(0x2000)
75131 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE UINT32_C(0x4000)
75133 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE UINT32_C(0x8000)
75136 #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC UINT32_C(0x1)
75138 #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK UINT32_C(0xfe)
75158 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK UINT32_C(0x3)
75159 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0
75161 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK UINT32_C(0xfc)
75165 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK UINT32_C(0x7)
75166 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0
75168 #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK UINT32_C(0xf8)
75172 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
75173 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0
75175 #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK UINT32_C(0xffc0)
75182 #define CMDQ_MODIFY_ROCE_CC_RTT_MASK UINT32_C(0x3fff)
75183 #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0
75185 #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK UINT32_C(0xc000)
75189 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK UINT32_C(0x3ff)
75190 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0
75192 #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK UINT32_C(0xfc00)
75196 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE UINT32_C(0x0)
75198 * Probabilistic marking. On chips with CC Gen 0 support this
75201 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE UINT32_C(0x1)
75205 * CC support level 0 support 0 to 3 Tx queues.
75206 * CC support level 1 supports 0 to 7 Tx queues.
75233 * For TLV encapsulated messages this field must be 0x8000.
75242 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
75244 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
75246 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
75253 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
75255 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
75257 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
75268 * Global TLV range: `0 - (63k-1)`
75288 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC UINT32_C(0x8c)
75304 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC UINT32_C(0x1)
75306 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G UINT32_C(0x2)
75308 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE UINT32_C(0x4)
75310 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR UINT32_C(0x8)
75312 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR UINT32_C(0x10)
75314 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN UINT32_C(0x20)
75316 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP UINT32_C(0x40)
75318 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP UINT32_C(0x80)
75320 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP UINT32_C(0x100)
75322 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT UINT32_C(0x200)
75324 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE UINT32_C(0x400)
75326 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP UINT32_C(0x800)
75328 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE UINT32_C(0x1000)
75330 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP UINT32_C(0x2000)
75332 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE UINT32_C(0x4000)
75334 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE UINT32_C(0x8000)
75337 #define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC UINT32_C(0x1)
75339 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK UINT32_C(0xfe)
75359 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK UINT32_C(0x3)
75360 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0
75362 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK UINT32_C(0xfc)
75366 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK UINT32_C(0x7)
75367 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0
75369 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK UINT32_C(0xf8)
75373 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK UINT32_C(0x3f)
75374 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0
75376 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK UINT32_C(0xffc0)
75383 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK UINT32_C(0x3fff)
75384 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0
75386 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK UINT32_C(0xc000)
75390 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK UINT32_C(0x3ff)
75391 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0
75393 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK UINT32_C(0xfc00)
75397 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE UINT32_C(0x0)
75399 * Probabilistic marking. On chips with CC Gen 0 support this
75402 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE UINT32_C(0x1)
75406 * CC support level 0 support 0 to 3 Tx queues.
75407 * CC support level 1 supports 0 to 7 Tx queues.
75431 * For TLV encapsulated messages this field must be 0x8000.
75440 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
75442 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
75444 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
75451 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
75453 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
75455 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
75466 * Global TLV range: `0 - (63k-1)`
75484 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS UINT32_C(0x1)
75489 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP UINT32_C(0x2)
75491 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE UINT32_C(0x4)
75493 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES UINT32_C(0x8)
75495 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS UINT32_C(0x10)
75497 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE UINT32_C(0x20)
75502 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH UINT32_C(0x40)
75507 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH UINT32_C(0x80)
75509 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH UINT32_C(0x100)
75511 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT UINT32_C(0x200)
75513 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR UINT32_C(0x400)
75515 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH UINT32_C(0x800)
75517 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN UINT32_C(0x1000)
75522 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS UINT32_C(0x2000)
75524 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN UINT32_C(0x4000)
75526 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN UINT32_C(0x8000)
75528 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC UINT32_C(0x10000)
75533 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH UINT32_C(0x20000)
75535 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH UINT32_C(0x40000)
75537 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN UINT32_C(0x80000)
75539 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX UINT32_C(0x100000)
75544 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX UINT32_C(0x200000)
75546 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND UINT32_C(0x400000)
75551 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR UINT32_C(0x800000)
75556 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR UINT32_C(0x1000000)
75561 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH UINT32_C(0x2000000)
75563 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV UINT32_C(0x4000000)
75568 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH UINT32_C(0x8000000)
75573 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS UINT32_C(0x10000000)
75575 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO UINT32_C(0x20000000)
75580 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH UINT32_C(0x40000000)
75585 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 UINT32_C(0x80000000)
75590 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 UINT32_C(0x100000000)L
75592 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE UINT32_C(0x200000000)L
75597 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT UINT32_C(0x400000000)L
75602 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH UINT32_C(0x800000000)L
75607 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 UINT32_C(0x1000000000)L
75612 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 UINT32_C(0x2000000000)L
75617 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES UINT32_C(0x4000000000)L
75619 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN UINT32_C(0x8000000000)L
75624 …#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH UINT32_C(0x10000000…
75626 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN UINT32_C(0x20000000000)L
75628 …#define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN UINT32_C(0x40000000…
75630 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN UINT32_C(0x80000000000)L
75640 * is 0 - 1023.
75644 * In tr_update_mode 0, Target Rate (TR) is updated to
75651 * 0: TR is updated when QPC. rtts_with_cnps == 0
75681 * as a reduction reference. Values between 0 and 6 represent factor of
75689 * 0 for disable, 1 for enable.
75697 * 0 for not_ect, 1 for ect_0, 2 for ect_1
75701 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT UINT32_C(0x0)
75703 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 UINT32_C(0x1)
75704 /* ECN Capable Transport-0 */
75705 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 UINT32_C(0x2)
75836 * For TLV encapsulated messages this field must be 0x8000.
75845 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE UINT32_C(0x1)
75847 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_LAST UINT32_C(0x0)
75849 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_MORE_NOT_LAST UINT32_C(0x1)
75856 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED UINT32_C(0x2)
75858 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_NO (UINT32_C(0x0) << 1)
75860 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_TLV_FLAGS_REQUIRED_YES (UINT32_C(0x1) << 1)
75871 * Global TLV range: `0 - (63k-1)`
75890 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_IDX UINT32_C(0x1)
75892 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_THR UINT32_C(0x2)
75894 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_CR UINT32_C(0x4)
75896 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_INC_CNP UINT32_C(0x8)
75898 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_UPD_IMM UINT32_C(0x10)
75900 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_MODIFY_MASK_DCN_QLEVEL_TBL_TR UINT32_C(0x20)
75901 /* DCN queue level table index. Valid values are from 0 to 7. */
75916 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_MASK UINT32_C(0x3fff)
75917 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_CR_SFT 0
75919 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_INC_CNP UINT32_C(0x4000)
75921 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_UPD_IMM UINT32_C(0x8000)
75923 #define CMDQ_MODIFY_ROCE_CC_GEN2_TLV_DCN_QLEVEL_TBL_ACT_TR_MASK UINT32_C(0x3fff0000)
75938 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK UINT32_C(0x3f)
75939 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0
75941 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT UINT32_C(0x38)
75952 * will write 1. The odd passes will write 0.
75954 #define CREQ_MODIFY_ROCE_CC_RESP_V UINT32_C(0x1)
75958 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC UINT32_C(0x8c)
75974 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE UINT32_C(0x8f)
75990 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN UINT32_C(0x1)
75992 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP UINT32_C(0x2)
75994 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP UINT32_C(0x4)
75996 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE UINT32_C(0x8)
75998 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID UINT32_C(0x10)
76001 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE UINT32_C(0x1)
76003 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK UINT32_C(0xfe)
76007 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK UINT32_C(0xf)
76008 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0
76010 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK UINT32_C(0xf0)
76017 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE UINT32_C(0x1)
76019 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP UINT32_C(0x2)
76021 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR UINT32_C(0x3)
76023 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD UINT32_C(0x4)
76041 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK UINT32_C(0x3f)
76042 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0
76044 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT UINT32_C(0x38)
76055 * will write 1. The odd passes will write 0.
76057 #define CREQ_SET_LINK_AGGR_MODE_RESP_V UINT32_C(0x1)
76061 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE UINT32_C(0x8f)
76076 #define CMDQ_VF_BACKCHANNEL_REQUEST_OPCODE_VF_BACKCHANNEL_REQUEST UINT32_C(0x86)
76109 #define CMDQ_READ_VF_MEMORY_OPCODE_READ_VF_MEMORY UINT32_C(0x87)
76124 /* VF id, as provided in 0xC0 VF request notification */
76142 #define CMDQ_COMPLETE_VF_REQUEST_OPCODE_COMPLETE_VF_REQUEST UINT32_C(0x88)
76162 /* VF id, as provided in 0xC0 VF request notification */
76187 #define CMDQ_ORCHESTRATE_QID_MIGRATION_OPCODE_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93)
76202 #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_MASK UINT32_C(0xf)
76203 #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_SFT 0
76205 #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_ENABLE_NATIVE_QID_RANGE UINT32_C(0x0)
76207 …#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_ENABLE_EXTENDED_QID_RANGE UINT32_C(0x…
76209 #define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_NATIVE_QID_RANGE UINT32_C(0x2)
76211 …#define CMDQ_ORCHESTRATE_QID_MIGRATION_QID_MIGRATION_FLAGS_DISABLE_EXTENDED_QID_RANGE UINT32_C(0x…
76214 #define CMDQ_ORCHESTRATE_QID_MIGRATION_UNUSED4_MASK UINT32_C(0xf0)
76232 #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_MASK UINT32_C(0x3f)
76233 #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_SFT 0
76235 #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_TYPE_QP_EVENT UINT32_C(0x38)
76246 * will write 1. The odd passes will write 0.
76248 #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_V UINT32_C(0x1)
76252 #define CREQ_ORCHESTRATE_QID_MIGRATION_RESP_EVENT_ORCHESTRATE_QID_MIGRATION UINT32_C(0x93)
76268 #define CMDQ_CREATE_QP_BATCH_OPCODE_CREATE_QP_BATCH UINT32_C(0x94)
76310 #define CREQ_CREATE_QP_BATCH_RESP_TYPE_MASK UINT32_C(0x3f)
76311 #define CREQ_CREATE_QP_BATCH_RESP_TYPE_SFT 0
76313 #define CREQ_CREATE_QP_BATCH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
76324 * will write 1. The odd passes will write 0.
76326 #define CREQ_CREATE_QP_BATCH_RESP_V UINT32_C(0x1)
76330 #define CREQ_CREATE_QP_BATCH_RESP_EVENT_CREATE_QP_BATCH UINT32_C(0x94)
76352 #define CMDQ_DESTROY_QP_BATCH_OPCODE_DESTROY_QP_BATCH UINT32_C(0x95)
76387 #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_MASK UINT32_C(0x3f)
76388 #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_SFT 0
76390 #define CREQ_DESTROY_QP_BATCH_RESP_TYPE_QP_EVENT UINT32_C(0x38)
76401 * will write 1. The odd passes will write 0.
76403 #define CREQ_DESTROY_QP_BATCH_RESP_V UINT32_C(0x1)
76407 #define CREQ_DESTROY_QP_BATCH_RESP_EVENT_DESTROY_QP_BATCH UINT32_C(0x95)
76432 #define CMDQ_ALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96)
76453 * If update_period_ms is 0, then the stats update
76475 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK UINT32_C(0x3f)
76476 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT 0
76478 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT UINT32_C(0x38)
76490 * will write 1. The odd passes will write 0.
76492 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_V UINT32_C(0x1)
76496 #define CREQ_ALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_ALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x96)
76512 #define CMDQ_DEALLOCATE_ROCE_STATS_EXT_CTX_OPCODE_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97)
76543 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_MASK UINT32_C(0x3f)
76544 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_SFT 0
76546 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_TYPE_QP_EVENT UINT32_C(0x38)
76558 * will write 1. The odd passes will write 0.
76560 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_V UINT32_C(0x1)
76564 #define CREQ_DEALLOCATE_ROCE_STATS_EXT_CTX_RESP_EVENT_DEALLOCATE_ROCE_STATS_EXT_CTX UINT32_C(0x97)
76583 #define CMDQ_QUERY_ROCE_STATS_EXT_V2_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
76614 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_MASK UINT32_C(0x3f)
76615 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_SFT 0
76617 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_TYPE_QP_EVENT UINT32_C(0x38)
76629 * will write 1. The odd passes will write 0.
76631 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_V UINT32_C(0x1)
76635 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_EVENT_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
76647 #define CREQ_QUERY_ROCE_STATS_EXT_V2_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT_V2 UINT32_C(0x98)
76765 #define CREQ_FUNC_EVENT_TYPE_MASK UINT32_C(0x3f)
76766 #define CREQ_FUNC_EVENT_TYPE_SFT 0
76768 #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT UINT32_C(0x3a)
76775 * will write 1. The odd passes will write 0.
76777 #define CREQ_FUNC_EVENT_V UINT32_C(0x1)
76787 #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR UINT32_C(0x1)
76792 #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR UINT32_C(0x2)
76797 #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR UINT32_C(0x3)
76799 #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR UINT32_C(0x4)
76801 #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR UINT32_C(0x5)
76806 #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR UINT32_C(0x6)
76808 #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR UINT32_C(0x7)
76810 #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR UINT32_C(0x8)
76812 #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR UINT32_C(0x9)
76814 #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR UINT32_C(0xa)
76820 #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR UINT32_C(0xb)
76822 #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST UINT32_C(0x80)
76827 #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED UINT32_C(0x81)
76844 #define CREQ_QP_EVENT_TYPE_MASK UINT32_C(0x3f)
76845 #define CREQ_QP_EVENT_TYPE_SFT 0
76847 #define CREQ_QP_EVENT_TYPE_QP_EVENT UINT32_C(0x38)
76852 #define CREQ_QP_EVENT_STATUS_SUCCESS UINT32_C(0x0)
76854 #define CREQ_QP_EVENT_STATUS_FAIL UINT32_C(0x1)
76856 #define CREQ_QP_EVENT_STATUS_RESOURCES UINT32_C(0x2)
76858 #define CREQ_QP_EVENT_STATUS_INVALID_CMD UINT32_C(0x3)
76860 #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED UINT32_C(0x4)
76862 #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER UINT32_C(0x5)
76864 #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR UINT32_C(0x6)
76866 #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR UINT32_C(0x7)
76875 * will write 1. The odd passes will write 0.
76877 #define CREQ_QP_EVENT_V UINT32_C(0x1)
76881 #define CREQ_QP_EVENT_EVENT_CREATE_QP UINT32_C(0x1)
76883 #define CREQ_QP_EVENT_EVENT_DESTROY_QP UINT32_C(0x2)
76885 #define CREQ_QP_EVENT_EVENT_MODIFY_QP UINT32_C(0x3)
76887 #define CREQ_QP_EVENT_EVENT_QUERY_QP UINT32_C(0x4)
76889 #define CREQ_QP_EVENT_EVENT_CREATE_SRQ UINT32_C(0x5)
76891 #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ UINT32_C(0x6)
76893 #define CREQ_QP_EVENT_EVENT_QUERY_SRQ UINT32_C(0x8)
76895 #define CREQ_QP_EVENT_EVENT_CREATE_CQ UINT32_C(0x9)
76897 #define CREQ_QP_EVENT_EVENT_DESTROY_CQ UINT32_C(0xa)
76899 #define CREQ_QP_EVENT_EVENT_RESIZE_CQ UINT32_C(0xc)
76901 #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW UINT32_C(0xd)
76903 #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY UINT32_C(0xe)
76905 #define CREQ_QP_EVENT_EVENT_REGISTER_MR UINT32_C(0xf)
76907 #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR UINT32_C(0x10)
76909 #define CREQ_QP_EVENT_EVENT_ADD_GID UINT32_C(0x11)
76911 #define CREQ_QP_EVENT_EVENT_DELETE_GID UINT32_C(0x12)
76913 #define CREQ_QP_EVENT_EVENT_MODIFY_GID UINT32_C(0x17)
76915 #define CREQ_QP_EVENT_EVENT_QUERY_GID UINT32_C(0x18)
76917 #define CREQ_QP_EVENT_EVENT_CREATE_QP1 UINT32_C(0x13)
76919 #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 UINT32_C(0x14)
76921 #define CREQ_QP_EVENT_EVENT_CREATE_AH UINT32_C(0x15)
76923 #define CREQ_QP_EVENT_EVENT_DESTROY_AH UINT32_C(0x16)
76925 #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW UINT32_C(0x80)
76927 #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW UINT32_C(0x81)
76929 #define CREQ_QP_EVENT_EVENT_STOP_FUNC UINT32_C(0x82)
76931 #define CREQ_QP_EVENT_EVENT_QUERY_FUNC UINT32_C(0x83)
76933 #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES UINT32_C(0x84)
76938 #define CREQ_QP_EVENT_EVENT_READ_CONTEXT UINT32_C(0x85)
76940 #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS UINT32_C(0x8a)
76942 #define CREQ_QP_EVENT_EVENT_QUERY_VERSION UINT32_C(0x8b)
76944 #define CREQ_QP_EVENT_EVENT_MODIFY_CC UINT32_C(0x8c)
76946 #define CREQ_QP_EVENT_EVENT_QUERY_CC UINT32_C(0x8d)
76948 #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS UINT32_C(0x8e)
76950 #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE UINT32_C(0x8f)
76955 #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND UINT32_C(0x91)
76957 #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0)
76959 #define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION UINT32_C(0xc1)
76976 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK UINT32_C(0x3f)
76977 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0
76979 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT UINT32_C(0x38)
76988 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR UINT32_C(0x0)
76997 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR UINT32_C(0x1)
77004 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT UINT32_C(0x2)
77011 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT UINT32_C(0x3)
77016 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 UINT32_C(0x4)
77021 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 UINT32_C(0x5)
77026 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 UINT32_C(0x6)
77031 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 UINT32_C(0x7)
77037 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR UINT32_C(0x8)
77043 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR UINT32_C(0x9)
77050 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH UINT32_C(0xa)
77057 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP UINT32_C(0xb)
77075 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND UINT32_C(0xc)
77093 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG UINT32_C(0xd)
77107 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE UINT32_C(0xe)
77113 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR UINT32_C(0xf)
77119 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR UINT32_C(0x10)
77124 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR UINT32_C(0x11)
77129 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR UINT32_C(0x12)
77134 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR UINT32_C(0x13)
77140 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR UINT32_C(0x14)
77145 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR UINT32_C(0x15)
77152 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR UINT32_C(0x16)
77160 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR UINT32_C(0x17)
77167 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR UINT32_C(0x18)
77174 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR UINT32_C(0x19)
77183 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR UINT32_C(0x1a)
77193 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR UINT32_C(0x1b)
77209 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR UINT32_C(0x1c)
77215 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SQ_OVERFLOW UINT32_C(0x1d)
77223 * will write 1. The odd passes will write 0.
77225 #define CREQ_QP_ERROR_NOTIFICATION_V UINT32_C(0x1)
77229 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION UINT32_C(0xc0)
77235 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR UINT32_C(0x0)
77242 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX UINT32_C(0x1)
77250 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH UINT32_C(0x2)
77257 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE UINT32_C(0x3)
77265 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR UINT32_C(0x4)
77273 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT UINT32_C(0x5)
77282 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY UINT32_C(0x6)
77290 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR UINT32_C(0x7)
77298 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION UINT32_C(0x8)
77305 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR UINT32_C(0x9)
77314 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY UINT32_C(0xa)
77322 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR UINT32_C(0xb)
77330 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION UINT32_C(0xc)
77337 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR UINT32_C(0xd)
77344 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW UINT32_C(0xe)
77351 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE UINT32_C(0xf)
77357 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC UINT32_C(0x10)
77368 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE UINT32_C(0x11)
77374 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR UINT32_C(0x12)
77380 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR UINT32_C(0x13)
77386 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR UINT32_C(0x14)
77391 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY UINT32_C(0x15)
77396 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR UINT32_C(0x16)
77401 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR UINT32_C(0x17)
77406 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR UINT32_C(0x18)
77411 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR UINT32_C(0x19)
77418 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR UINT32_C(0x1b)
77425 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR UINT32_C(0x1c)
77431 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND UINT32_C(0x1d)
77437 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RQ_OVERFLOW UINT32_C(0x1e)
77463 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK UINT32_C(0x3f)
77464 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0
77466 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT UINT32_C(0x38)
77473 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR UINT32_C(0x1)
77475 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR UINT32_C(0x2)
77477 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR UINT32_C(0x3)
77479 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR UINT32_C(0x4)
77481 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR UINT32_C(0x5)
77483 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR UINT32_C(0x6)
77492 * will write 1. The odd passes will write 0.
77494 #define CREQ_CQ_ERROR_NOTIFICATION_V UINT32_C(0x1)
77498 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION UINT32_C(0xc1)
77509 #define SQ_BASE_WQE_TYPE_SEND UINT32_C(0x0)
77516 #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
77522 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
77528 #define SQ_BASE_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
77534 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
77540 #define SQ_BASE_WQE_TYPE_READ_WQE UINT32_C(0x6)
77546 #define SQ_BASE_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
77552 #define SQ_BASE_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
77558 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
77564 #define SQ_BASE_WQE_TYPE_FR_PMR UINT32_C(0xd)
77570 #define SQ_BASE_WQE_TYPE_BIND UINT32_C(0xe)
77576 #define SQ_BASE_WQE_TYPE_FR_PPMR UINT32_C(0xf)
77578 #define SQ_BASE_WQE_TYPE_SEND_V3 UINT32_C(0x10)
77584 #define SQ_BASE_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11)
77590 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12)
77596 #define SQ_BASE_WQE_TYPE_UDSEND_V3 UINT32_C(0x13)
77602 #define SQ_BASE_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14)
77608 #define SQ_BASE_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15)
77614 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16)
77620 #define SQ_BASE_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17)
77626 #define SQ_BASE_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18)
77632 #define SQ_BASE_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19)
77638 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a)
77644 #define SQ_BASE_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b)
77650 #define SQ_BASE_WQE_TYPE_BIND_V3 UINT32_C(0x1c)
77652 #define SQ_BASE_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d)
77654 #define SQ_BASE_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e)
77665 * the mode). In variable-sized WQE mode there can be 0-30 SGE
77701 #define SQ_PSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff)
77702 #define SQ_PSN_SEARCH_START_PSN_SFT 0
77704 #define SQ_PSN_SEARCH_OPCODE_MASK UINT32_C(0xff000000)
77708 #define SQ_PSN_SEARCH_NEXT_PSN_MASK UINT32_C(0xffffff)
77709 #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0
77711 #define SQ_PSN_SEARCH_FLAGS_MASK UINT32_C(0xff000000)
77722 #define SQ_PSN_SEARCH_EXT_START_PSN_MASK UINT32_C(0xffffff)
77723 #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0
77725 #define SQ_PSN_SEARCH_EXT_OPCODE_MASK UINT32_C(0xff000000)
77729 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK UINT32_C(0xffffff)
77730 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0
77732 #define SQ_PSN_SEARCH_EXT_FLAGS_MASK UINT32_C(0xff000000)
77752 #define SQ_MSN_SEARCH_START_PSN_MASK UINT32_C(0xffffff)
77753 #define SQ_MSN_SEARCH_START_PSN_SFT 0
77755 #define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL
77762 #define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL
77773 #define SQ_SEND_WQE_TYPE_SEND UINT32_C(0x0)
77780 #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
77786 #define SQ_SEND_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
77789 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
77790 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
77793 * 0, and the SQ is configured to support Unsignaled completion
77798 #define SQ_SEND_FLAGS_SIGNAL_COMP UINT32_C(0x1)
77805 #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
77812 #define SQ_SEND_FLAGS_UC_FENCE UINT32_C(0x4)
77819 #define SQ_SEND_FLAGS_SE UINT32_C(0x8)
77824 #define SQ_SEND_FLAGS_INLINE UINT32_C(0x10)
77827 * cleared to 0, then TWE provides the timestamp.
77829 #define SQ_SEND_FLAGS_WQE_TS_EN UINT32_C(0x20)
77834 #define SQ_SEND_FLAGS_DEBUG_TRACE UINT32_C(0x40)
77873 #define SQ_SEND_DST_QP_MASK UINT32_C(0xffffff)
77874 #define SQ_SEND_DST_QP_SFT 0
77880 #define SQ_SEND_AVID_MASK UINT32_C(0xfffff)
77881 #define SQ_SEND_AVID_SFT 0
77889 #define SQ_SEND_TIMESTAMP_MASK UINT32_C(0xffffff)
77890 #define SQ_SEND_TIMESTAMP_SFT 0
77892 * When inline=0, then this area is filled with from 1 to 6
77896 * send based on the length_or_AVID field. Bits [7:0] of word 0
77909 #define SQ_SEND_HDR_WQE_TYPE_SEND UINT32_C(0x0)
77916 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD UINT32_C(0x1)
77922 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID UINT32_C(0x2)
77925 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
77926 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
77929 * 0, and the SQ is configured to support Unsignaled completion
77934 #define SQ_SEND_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
77941 #define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
77948 #define SQ_SEND_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
77955 #define SQ_SEND_HDR_FLAGS_SE UINT32_C(0x8)
77960 #define SQ_SEND_HDR_FLAGS_INLINE UINT32_C(0x10)
77963 * cleared to 0, then TWE provides the timestamp.
77965 #define SQ_SEND_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
77970 #define SQ_SEND_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
78009 #define SQ_SEND_HDR_DST_QP_MASK UINT32_C(0xffffff)
78010 #define SQ_SEND_HDR_DST_QP_SFT 0
78016 #define SQ_SEND_HDR_AVID_MASK UINT32_C(0xfffff)
78017 #define SQ_SEND_HDR_AVID_SFT 0
78025 #define SQ_SEND_HDR_TIMESTAMP_MASK UINT32_C(0xffffff)
78026 #define SQ_SEND_HDR_TIMESTAMP_SFT 0
78036 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND UINT32_C(0x0)
78039 …ine SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
78040 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
78043 * 0, and the SQ is configured to support Unsignaled completion
78048 #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP UINT32_C(0x1)
78050 #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
78052 #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE UINT32_C(0x4)
78054 #define SQ_SEND_RAWETH_QP1_FLAGS_SE UINT32_C(0x8)
78059 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE UINT32_C(0x10)
78062 * cleared to 0, then TWE provides the timestamp.
78064 #define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN UINT32_C(0x20)
78069 #define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE UINT32_C(0x40)
78095 #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
78104 #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM UINT32_C(0x2)
78116 #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC UINT32_C(0x4)
78123 #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP UINT32_C(0x8)
78132 #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
78137 #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC UINT32_C(0x100)
78142 #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC UINT32_C(0x200)
78162 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
78163 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0
78165 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE UINT32_C(0x1000)
78167 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
78170 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
78172 /* 0x88a8 */
78173 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
78174 /* 0x8100 */
78175 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
78176 /* 0x9100 */
78177 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
78178 /* 0x9200 */
78179 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
78180 /* 0x9300 */
78181 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
78183 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
78186 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
78194 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK UINT32_C(0xf0000000)
78197 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
78199 * - meta[17:16] - TPID select value (0 = 0x8100).
78201 * - meta[11:0] - VID value.
78203 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
78213 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK UINT32_C(0xffffff)
78214 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0
78216 * When inline=0, then this area is filled with from 1 to 6
78220 * send based on the length_or_AVID field. Bits [7:0] of word 0
78233 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND UINT32_C(0x0)
78236 …SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
78237 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
78240 * 0, and the SQ is configured to support Unsignaled completion
78245 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
78247 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
78249 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
78251 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE UINT32_C(0x8)
78256 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE UINT32_C(0x10)
78259 * cleared to 0, then TWE provides the timestamp.
78261 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
78266 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
78292 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
78301 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM UINT32_C(0x2)
78313 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC UINT32_C(0x4)
78320 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP UINT32_C(0x8)
78329 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
78334 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC UINT32_C(0x100)
78339 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC UINT32_C(0x200)
78359 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
78360 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0
78362 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE UINT32_C(0x1000)
78364 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
78367 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
78369 /* 0x88a8 */
78370 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
78371 /* 0x8100 */
78372 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
78373 /* 0x9100 */
78374 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
78375 /* 0x9200 */
78376 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
78377 /* 0x9300 */
78378 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
78380 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
78383 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
78391 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK UINT32_C(0xf0000000)
78394 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
78396 * - meta[17:16] - TPID select value (0 = 0x8100).
78398 * - meta[11:0] - VID value.
78400 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
78410 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK UINT32_C(0xffffff)
78411 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0
78425 #define SQ_RDMA_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
78431 #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
78437 #define SQ_RDMA_WQE_TYPE_READ_WQE UINT32_C(0x6)
78440 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
78441 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
78444 * 0, and the SQ is configured to support Unsignaled
78449 #define SQ_RDMA_FLAGS_SIGNAL_COMP UINT32_C(0x1)
78454 #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
78459 #define SQ_RDMA_FLAGS_UC_FENCE UINT32_C(0x4)
78466 #define SQ_RDMA_FLAGS_SE UINT32_C(0x8)
78471 #define SQ_RDMA_FLAGS_INLINE UINT32_C(0x10)
78474 * cleared to 0, then TWE provides the timestamp.
78476 #define SQ_RDMA_FLAGS_WQE_TS_EN UINT32_C(0x20)
78481 #define SQ_RDMA_FLAGS_DEBUG_TRACE UINT32_C(0x40)
78515 #define SQ_RDMA_TIMESTAMP_MASK UINT32_C(0xffffff)
78516 #define SQ_RDMA_TIMESTAMP_SFT 0
78518 * When inline=0, then this area is filled with from 1 to 6
78522 * write based on the length field. Bits [7:0] of word 0
78539 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE UINT32_C(0x4)
78545 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD UINT32_C(0x5)
78551 #define SQ_RDMA_HDR_WQE_TYPE_READ_WQE UINT32_C(0x6)
78554 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
78555 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
78558 * 0, and the SQ is configured to support Unsignaled
78563 #define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
78568 #define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
78573 #define SQ_RDMA_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
78580 #define SQ_RDMA_HDR_FLAGS_SE UINT32_C(0x8)
78585 #define SQ_RDMA_HDR_FLAGS_INLINE UINT32_C(0x10)
78588 * cleared to 0, then TWE provides the timestamp.
78590 #define SQ_RDMA_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
78595 #define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
78629 #define SQ_RDMA_HDR_TIMESTAMP_MASK UINT32_C(0xffffff)
78630 #define SQ_RDMA_HDR_TIMESTAMP_SFT 0
78644 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
78650 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
78653 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
78654 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
78657 * 0, and the SQ is configured to support Unsignaled
78662 #define SQ_ATOMIC_FLAGS_SIGNAL_COMP UINT32_C(0x1)
78667 #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
78672 #define SQ_ATOMIC_FLAGS_UC_FENCE UINT32_C(0x4)
78679 #define SQ_ATOMIC_FLAGS_SE UINT32_C(0x8)
78681 #define SQ_ATOMIC_FLAGS_INLINE UINT32_C(0x10)
78686 #define SQ_ATOMIC_FLAGS_WQE_TS_EN UINT32_C(0x20)
78691 #define SQ_ATOMIC_FLAGS_DEBUG_TRACE UINT32_C(0x40)
78727 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS UINT32_C(0x8)
78733 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA UINT32_C(0xb)
78736 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
78737 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
78740 * 0, and the SQ is configured to support Unsignaled
78745 #define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
78750 #define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
78755 #define SQ_ATOMIC_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
78762 #define SQ_ATOMIC_HDR_FLAGS_SE UINT32_C(0x8)
78764 #define SQ_ATOMIC_HDR_FLAGS_INLINE UINT32_C(0x10)
78769 #define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
78774 #define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
78804 #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
78807 …ine SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
78808 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
78811 * 0, and the SQ is configured to support Unsignaled
78816 #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP UINT32_C(0x1)
78821 #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
78826 #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE UINT32_C(0x4)
78833 #define SQ_LOCALINVALIDATE_FLAGS_SE UINT32_C(0x8)
78835 #define SQ_LOCALINVALIDATE_FLAGS_INLINE UINT32_C(0x10)
78837 * This flag is not applicable and should be 0 for a local memory
78840 #define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN UINT32_C(0x20)
78845 #define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE UINT32_C(0x40)
78870 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID UINT32_C(0xc)
78873 …SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
78874 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
78877 * 0, and the SQ is configured to support Unsignaled
78882 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
78887 #define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
78892 #define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
78899 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SE UINT32_C(0x8)
78901 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE UINT32_C(0x10)
78903 * This flag is not applicable and should be 0 for a local memory
78906 #define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
78911 #define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
78934 #define SQ_FR_PMR_WQE_TYPE_FR_PMR UINT32_C(0xd)
78939 * 0, and the SQ is configured to support Unsignaled
78944 #define SQ_FR_PMR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
78949 #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
78954 #define SQ_FR_PMR_FLAGS_UC_FENCE UINT32_C(0x4)
78956 #define SQ_FR_PMR_FLAGS_SE UINT32_C(0x8)
78958 #define SQ_FR_PMR_FLAGS_INLINE UINT32_C(0x10)
78960 * This flag is not applicable and should be 0 for a local memory
78963 #define SQ_FR_PMR_FLAGS_WQE_TS_EN UINT32_C(0x20)
78968 #define SQ_FR_PMR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
78971 * the operation is allowed. '0' means operation is
78976 #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
78978 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
78980 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
78982 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
78984 #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
78986 /* Page size. 0 for 4KB page size, ... to 8TB. */
78987 #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
78988 #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0
78990 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
78992 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
78994 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
78996 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
78998 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
79000 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
79002 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
79004 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
79006 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
79008 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
79010 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
79012 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
79014 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
79016 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
79018 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
79020 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
79022 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
79024 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
79026 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
79028 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
79030 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
79032 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
79034 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
79036 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
79038 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
79040 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
79042 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
79044 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
79046 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
79048 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
79050 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
79052 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
79055 #define SQ_FR_PMR_ZERO_BASED UINT32_C(0x20)
79067 /* PBL page size. 0 for 4KB page size, ... to 8TB. */
79068 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
79069 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0
79071 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
79073 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
79075 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
79077 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
79079 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
79081 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
79083 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
79085 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
79087 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
79089 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
79091 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
79093 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
79095 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
79097 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
79099 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
79101 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
79103 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
79105 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
79107 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
79109 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
79111 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
79113 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
79115 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
79117 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
79119 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
79121 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
79123 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
79125 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
79127 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
79129 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
79131 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
79133 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
79136 #define SQ_FR_PMR_NUMLEVELS_MASK UINT32_C(0xc0)
79142 #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6)
79148 #define SQ_FR_PMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6)
79156 #define SQ_FR_PMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6)
79177 #define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR UINT32_C(0xd)
79182 * 0, and the SQ is configured to support Unsignaled
79187 #define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
79192 #define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
79197 #define SQ_FR_PMR_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
79199 #define SQ_FR_PMR_HDR_FLAGS_SE UINT32_C(0x8)
79201 #define SQ_FR_PMR_HDR_FLAGS_INLINE UINT32_C(0x10)
79203 * This flag is not applicable and should be 0 for a local memory
79206 #define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
79211 #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
79214 * the operation is allowed. '0' means operation is
79219 #define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
79221 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
79223 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
79225 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
79227 #define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
79229 /* Page size. 0 for 4KB page size, ... to 8TB. */
79230 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
79231 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0
79233 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
79235 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
79237 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
79239 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
79241 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
79243 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
79245 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
79247 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
79249 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
79251 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
79253 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
79255 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
79257 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
79259 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
79261 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
79263 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
79265 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
79267 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
79269 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
79271 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
79273 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
79275 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
79277 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
79279 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
79281 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
79283 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
79285 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
79287 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
79289 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
79291 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
79293 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
79295 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
79298 #define SQ_FR_PMR_HDR_ZERO_BASED UINT32_C(0x20)
79310 /* PBL page size. 0 for 4KB page size, ... to 8TB. */
79311 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
79312 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0
79314 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
79316 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
79318 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
79320 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
79322 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
79324 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
79326 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
79328 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
79330 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
79332 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
79334 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
79336 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
79338 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
79340 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
79342 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
79344 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
79346 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
79348 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
79350 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
79352 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
79354 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
79356 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
79358 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
79360 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
79362 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
79364 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
79366 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
79368 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
79370 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
79372 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
79374 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
79376 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
79379 #define SQ_FR_PMR_HDR_NUMLEVELS_MASK UINT32_C(0xc0)
79385 #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6)
79391 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6)
79399 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6)
79418 #define SQ_FR_PPMR_WQE_TYPE_FR_PPMR UINT32_C(0xf)
79423 * 0, and the SQ is configured to support Unsignaled
79428 #define SQ_FR_PPMR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
79433 #define SQ_FR_PPMR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
79438 #define SQ_FR_PPMR_FLAGS_UC_FENCE UINT32_C(0x4)
79440 #define SQ_FR_PPMR_FLAGS_SE UINT32_C(0x8)
79442 #define SQ_FR_PPMR_FLAGS_INLINE UINT32_C(0x10)
79444 * This flag is not applicable and should be 0 for a local memory
79447 #define SQ_FR_PPMR_FLAGS_WQE_TS_EN UINT32_C(0x20)
79452 #define SQ_FR_PPMR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
79455 * the operation is allowed. '0' means operation is
79460 #define SQ_FR_PPMR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
79462 #define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
79464 #define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
79466 #define SQ_FR_PPMR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
79468 #define SQ_FR_PPMR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
79470 /* Page size. 0 for 4KB page size, ... to 8TB. */
79471 #define SQ_FR_PPMR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
79472 #define SQ_FR_PPMR_PAGE_SIZE_LOG_SFT 0
79474 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
79476 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
79478 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
79480 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
79482 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
79484 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
79486 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
79488 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
79490 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
79492 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
79494 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
79496 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
79498 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
79500 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
79502 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
79504 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
79506 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
79508 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
79510 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
79512 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
79514 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
79516 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
79518 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
79520 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
79522 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
79524 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
79526 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
79528 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
79530 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
79532 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
79534 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
79536 #define SQ_FR_PPMR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
79539 #define SQ_FR_PPMR_ZERO_BASED UINT32_C(0x20)
79553 /* PBL page size. 0 for 4KB page size, ... to 8TB. */
79554 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
79555 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_SFT 0
79557 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
79559 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
79561 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
79563 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
79565 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
79567 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
79569 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
79571 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
79573 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
79575 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
79577 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
79579 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
79581 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
79583 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
79585 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
79587 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
79589 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
79591 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
79593 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
79595 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
79597 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
79599 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
79601 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
79603 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
79605 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
79607 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
79609 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
79611 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
79613 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
79615 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
79617 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
79619 #define SQ_FR_PPMR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
79622 #define SQ_FR_PPMR_PROXY_VF_VALID UINT32_C(0x20)
79624 #define SQ_FR_PPMR_NUMLEVELS_MASK UINT32_C(0xc0)
79630 #define SQ_FR_PPMR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6)
79636 #define SQ_FR_PPMR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6)
79644 #define SQ_FR_PPMR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6)
79665 #define SQ_FR_PPMR_HDR_WQE_TYPE_FR_PPMR UINT32_C(0xf)
79670 * 0, and the SQ is configured to support Unsignaled
79675 #define SQ_FR_PPMR_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
79680 #define SQ_FR_PPMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
79685 #define SQ_FR_PPMR_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
79687 #define SQ_FR_PPMR_HDR_FLAGS_SE UINT32_C(0x8)
79689 #define SQ_FR_PPMR_HDR_FLAGS_INLINE UINT32_C(0x10)
79691 * This flag is not applicable and should be 0 for a local memory
79694 #define SQ_FR_PPMR_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
79699 #define SQ_FR_PPMR_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
79702 * the operation is allowed. '0' means operation is
79707 #define SQ_FR_PPMR_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
79709 #define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
79711 #define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
79713 #define SQ_FR_PPMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
79715 #define SQ_FR_PPMR_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
79717 /* Page size. 0 for 4KB page size, ... to 8TB. */
79718 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
79719 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_SFT 0
79721 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
79723 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
79725 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
79727 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
79729 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
79731 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
79733 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
79735 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
79737 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
79739 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
79741 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
79743 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
79745 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
79747 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
79749 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
79751 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
79753 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
79755 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
79757 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
79759 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
79761 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
79763 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
79765 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
79767 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
79769 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
79771 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
79773 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
79775 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
79777 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
79779 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
79781 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
79783 #define SQ_FR_PPMR_HDR_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
79786 #define SQ_FR_PPMR_HDR_ZERO_BASED UINT32_C(0x20)
79800 /* PBL page size. 0 for 4KB page size, ... to 8TB. */
79801 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
79802 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0
79804 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
79806 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
79808 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
79810 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
79812 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
79814 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
79816 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
79818 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
79820 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
79822 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
79824 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
79826 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
79828 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
79830 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
79832 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
79834 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
79836 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
79838 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
79840 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
79842 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
79844 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
79846 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
79848 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
79850 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
79852 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
79854 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
79856 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
79858 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
79860 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
79862 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
79864 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
79866 #define SQ_FR_PPMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
79869 #define SQ_FR_PPMR_HDR_PROXY_VF_VALID UINT32_C(0x20)
79871 #define SQ_FR_PPMR_HDR_NUMLEVELS_MASK UINT32_C(0xc0)
79877 #define SQ_FR_PPMR_HDR_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 6)
79883 #define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 6)
79891 #define SQ_FR_PPMR_HDR_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 6)
79914 #define SQ_BIND_WQE_TYPE_BIND UINT32_C(0xe)
79917 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
79918 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
79921 * 0, and the SQ is configured to support Unsignaled
79926 #define SQ_BIND_FLAGS_SIGNAL_COMP UINT32_C(0x1)
79931 #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
79936 #define SQ_BIND_FLAGS_UC_FENCE UINT32_C(0x4)
79938 #define SQ_BIND_FLAGS_SE UINT32_C(0x8)
79940 #define SQ_BIND_FLAGS_INLINE UINT32_C(0x10)
79942 * This flag is not applicable and should be 0 for a local memory
79945 #define SQ_BIND_FLAGS_WQE_TS_EN UINT32_C(0x20)
79950 #define SQ_BIND_FLAGS_DEBUG_TRACE UINT32_C(0x40)
79953 * the operation is allowed. '0' means operation is
79957 …IND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK UINT32_C(0xff)
79958 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0
79966 #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
79968 #define SQ_BIND_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
79977 #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
79986 #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
79994 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
80003 #define SQ_BIND_ZERO_BASED UINT32_C(0x1)
80023 #define SQ_BIND_MW_TYPE UINT32_C(0x2)
80025 #define SQ_BIND_MW_TYPE_TYPE1 (UINT32_C(0x0) << 1)
80027 #define SQ_BIND_MW_TYPE_TYPE2 (UINT32_C(0x1) << 1)
80070 #define SQ_BIND_HDR_WQE_TYPE_BIND UINT32_C(0xe)
80073 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK UINT32_C(0xff)
80074 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
80077 * 0, and the SQ is configured to support Unsignaled
80082 #define SQ_BIND_HDR_FLAGS_SIGNAL_COMP UINT32_C(0x1)
80087 #define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
80092 #define SQ_BIND_HDR_FLAGS_UC_FENCE UINT32_C(0x4)
80094 #define SQ_BIND_HDR_FLAGS_SE UINT32_C(0x8)
80096 #define SQ_BIND_HDR_FLAGS_INLINE UINT32_C(0x10)
80098 * This flag is not applicable and should be 0 for a local memory
80101 #define SQ_BIND_HDR_FLAGS_WQE_TS_EN UINT32_C(0x20)
80106 #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE UINT32_C(0x40)
80109 * the operation is allowed. '0' means operation is
80113 …HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK UINT32_C(0xff)
80114 …efine SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0
80122 #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
80124 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
80133 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
80142 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
80150 #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
80159 #define SQ_BIND_HDR_ZERO_BASED UINT32_C(0x1)
80179 #define SQ_BIND_HDR_MW_TYPE UINT32_C(0x2)
80181 #define SQ_BIND_HDR_MW_TYPE_TYPE1 (UINT32_C(0x0) << 1)
80183 #define SQ_BIND_HDR_MW_TYPE_TYPE2 (UINT32_C(0x1) << 1)
80218 #define SQ_MSN_SEARCH_V3_START_PSN_MASK UINT32_C(0xffffff)
80219 #define SQ_MSN_SEARCH_V3_START_PSN_SFT 0
80221 #define SQ_MSN_SEARCH_V3_NEXT_PSN_MASK UINT32_C(0xffffff000000)L
80228 #define SQ_MSN_SEARCH_V3_START_IDX_MASK UINT32_C(0xffff000000000000)L
80239 #define SQ_MSN_SEARCH_V3_SGNLD UINT32_C(0x1)
80245 #define SQ_MSN_SEARCH_V3_PREV_SGNLD_LOCAL_MEM_WQE UINT32_C(0x2)
80256 #define SQ_SEND_V3_WQE_TYPE_SEND_V3 UINT32_C(0x10)
80262 #define SQ_SEND_V3_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11)
80268 #define SQ_SEND_V3_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12)
80273 * 0, and the SQ is configured to support Unsignaled completion
80278 #define SQ_SEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
80285 #define SQ_SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
80292 #define SQ_SEND_V3_FLAGS_UC_FENCE UINT32_C(0x4)
80298 #define SQ_SEND_V3_FLAGS_SE UINT32_C(0x8)
80303 #define SQ_SEND_V3_FLAGS_INLINE UINT32_C(0x10)
80306 * cleared to 0, then TWE provides the timestamp.
80308 #define SQ_SEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
80313 #define SQ_SEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
80326 #define SQ_SEND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
80327 #define SQ_SEND_V3_WQE_SIZE_SFT 0
80332 * Zero means all 16 bytes are valid. One means only bits 7:0 of
80338 * ((inline_length == 0 ) ? 16 : inline_length)
80346 #define SQ_SEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
80347 #define SQ_SEND_V3_INLINE_LENGTH_SFT 0
80366 #define SQ_SEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
80367 #define SQ_SEND_V3_TIMESTAMP_SFT 0
80369 * When inline=0, then this area is filled with from 1 to 30 SGEs
80374 * Bits [7:0] of word 0 hold the first byte to go out on the wire.
80386 #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_V3 UINT32_C(0x10)
80392 #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_IMMED_V3 UINT32_C(0x11)
80398 #define SQ_SEND_HDR_V3_WQE_TYPE_SEND_W_INVALID_V3 UINT32_C(0x12)
80403 * 0, and the SQ is configured to support Unsignaled completion
80408 #define SQ_SEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
80415 #define SQ_SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
80422 #define SQ_SEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
80428 #define SQ_SEND_HDR_V3_FLAGS_SE UINT32_C(0x8)
80433 #define SQ_SEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
80436 * cleared to 0, then TWE provides the timestamp.
80438 #define SQ_SEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
80443 #define SQ_SEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
80456 #define SQ_SEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
80457 #define SQ_SEND_HDR_V3_WQE_SIZE_SFT 0
80462 * Zero means all 16 bytes are valid. One means only bits 7:0 of
80468 * ((inline_length == 0 ) ? 16 : inline_length)
80476 #define SQ_SEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
80477 #define SQ_SEND_HDR_V3_INLINE_LENGTH_SFT 0
80496 #define SQ_SEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
80497 #define SQ_SEND_HDR_V3_TIMESTAMP_SFT 0
80507 #define SQ_RAWQP1SEND_V3_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d)
80512 * 0, and the SQ is configured to support Unsignaled completion
80517 #define SQ_RAWQP1SEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
80524 #define SQ_RAWQP1SEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
80531 #define SQ_RAWQP1SEND_V3_FLAGS_UC_FENCE UINT32_C(0x4)
80539 #define SQ_RAWQP1SEND_V3_FLAGS_SE UINT32_C(0x8)
80544 #define SQ_RAWQP1SEND_V3_FLAGS_INLINE UINT32_C(0x10)
80547 * cleared to 0, then TWE provides the timestamp.
80549 #define SQ_RAWQP1SEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
80554 #define SQ_RAWQP1SEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
80565 #define SQ_RAWQP1SEND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
80566 #define SQ_RAWQP1SEND_V3_WQE_SIZE_SFT 0
80571 * Zero means all 16 bytes are valid. One means only bits 7:0 of
80577 * ((inline_length == 0 ) ? 16 : inline_length)
80585 #define SQ_RAWQP1SEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
80586 #define SQ_RAWQP1SEND_V3_INLINE_LENGTH_SFT 0
80606 #define SQ_RAWQP1SEND_V3_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
80615 #define SQ_RAWQP1SEND_V3_LFLAGS_IP_CHKSUM UINT32_C(0x2)
80627 #define SQ_RAWQP1SEND_V3_LFLAGS_NOCRC UINT32_C(0x4)
80636 #define SQ_RAWQP1SEND_V3_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
80646 * - If outer UDP checksum is 0, then do not update it.
80650 #define SQ_RAWQP1SEND_V3_LFLAGS_OT_IP_CHKSUM UINT32_C(0x20)
80655 #define SQ_RAWQP1SEND_V3_LFLAGS_ROCE_CRC UINT32_C(0x100)
80660 #define SQ_RAWQP1SEND_V3_LFLAGS_FCOE_CRC UINT32_C(0x200)
80679 #define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
80680 #define SQ_RAWQP1SEND_V3_CFA_ACTION_HIGH_SFT 0
80688 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
80689 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_VID_SFT 0
80691 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_DE UINT32_C(0x1000)
80693 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
80696 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
80698 /* 0x88a8 */
80699 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
80700 /* 0x8100 */
80701 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
80702 /* 0x9100 */
80703 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
80704 /* 0x9200 */
80705 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
80706 /* 0x9300 */
80707 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
80709 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
80712 #define SQ_RAWQP1SEND_V3_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
80720 #define SQ_RAWQP1SEND_V3_CFA_META_KEY_MASK UINT32_C(0xf0000000)
80723 #define SQ_RAWQP1SEND_V3_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
80725 * - meta[17:16] - TPID select value (0 = 0x8100).
80727 * - meta[11:0] - VID value.
80729 #define SQ_RAWQP1SEND_V3_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
80737 #define SQ_RAWQP1SEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
80738 #define SQ_RAWQP1SEND_V3_TIMESTAMP_SFT 0
80741 * When inline=0, then this area is filled with from 1 to 6 SGEs
80746 * Bits [7:0] of word 0 hold the first byte to go out on the wire.
80758 #define SQ_RAWQP1SEND_HDR_V3_WQE_TYPE_RAWQP1SEND_V3 UINT32_C(0x1d)
80763 * 0, and the SQ is configured to support Unsignaled completion
80768 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
80775 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
80782 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
80790 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_SE UINT32_C(0x8)
80795 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
80798 * cleared to 0, then TWE provides the timestamp.
80800 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
80805 #define SQ_RAWQP1SEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
80816 #define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
80817 #define SQ_RAWQP1SEND_HDR_V3_WQE_SIZE_SFT 0
80822 * Zero means all 16 bytes are valid. One means only bits 7:0 of
80828 * ((inline_length == 0 ) ? 16 : inline_length)
80836 #define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
80837 #define SQ_RAWQP1SEND_HDR_V3_INLINE_LENGTH_SFT 0
80857 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)
80866 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_IP_CHKSUM UINT32_C(0x2)
80878 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_NOCRC UINT32_C(0x4)
80887 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)
80897 * - If outer UDP checksum is 0, then do not update it.
80901 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_OT_IP_CHKSUM UINT32_C(0x20)
80906 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_ROCE_CRC UINT32_C(0x100)
80911 #define SQ_RAWQP1SEND_HDR_V3_LFLAGS_FCOE_CRC UINT32_C(0x200)
80930 #define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_MASK UINT32_C(0x3ff)
80931 #define SQ_RAWQP1SEND_HDR_V3_CFA_ACTION_HIGH_SFT 0
80939 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)
80940 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_VID_SFT 0
80942 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_DE UINT32_C(0x1000)
80944 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)
80947 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)
80949 /* 0x88a8 */
80950 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID88A8 (UINT32_C(0x0) << 16)
80951 /* 0x8100 */
80952 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID8100 (UINT32_C(0x1) << 16)
80953 /* 0x9100 */
80954 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9100 (UINT32_C(0x2) << 16)
80955 /* 0x9200 */
80956 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9200 (UINT32_C(0x3) << 16)
80957 /* 0x9300 */
80958 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPID9300 (UINT32_C(0x4) << 16)
80960 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_TPID_TPIDCFG (UINT32_C(0x5) << 16)
80963 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)
80971 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_MASK UINT32_C(0xf0000000)
80974 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_NONE (UINT32_C(0x0) << 28)
80976 * - meta[17:16] - TPID select value (0 = 0x8100).
80978 * - meta[11:0] - VID value.
80980 #define SQ_RAWQP1SEND_HDR_V3_CFA_META_KEY_VLAN_TAG (UINT32_C(0x1) << 28)
80988 #define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
80989 #define SQ_RAWQP1SEND_HDR_V3_TIMESTAMP_SFT 0
81004 #define SQ_UDSEND_V3_WQE_TYPE_UDSEND_V3 UINT32_C(0x13)
81010 #define SQ_UDSEND_V3_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14)
81015 * 0, and the SQ is configured to support Unsignaled completion
81020 #define SQ_UDSEND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
81027 #define SQ_UDSEND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
81034 #define SQ_UDSEND_V3_FLAGS_UC_FENCE UINT32_C(0x4)
81040 #define SQ_UDSEND_V3_FLAGS_SE UINT32_C(0x8)
81045 #define SQ_UDSEND_V3_FLAGS_INLINE UINT32_C(0x10)
81048 * cleared to 0, then TWE provides the timestamp.
81050 #define SQ_UDSEND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
81055 #define SQ_UDSEND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
81066 #define SQ_UDSEND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
81067 #define SQ_UDSEND_V3_WQE_SIZE_SFT 0
81072 * Zero means all 16 bytes are valid. One means only bits 7:0 of
81078 * ((inline_length == 0 ) ? 16 : inline_length)
81086 #define SQ_UDSEND_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
81087 #define SQ_UDSEND_V3_INLINE_LENGTH_SFT 0
81116 #define SQ_UDSEND_V3_DST_QP_MASK UINT32_C(0xffffff)
81117 #define SQ_UDSEND_V3_DST_QP_SFT 0
81123 #define SQ_UDSEND_V3_AVID_MASK UINT32_C(0x3ff)
81124 #define SQ_UDSEND_V3_AVID_SFT 0
81132 #define SQ_UDSEND_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
81133 #define SQ_UDSEND_V3_TIMESTAMP_SFT 0
81135 * When inline=0, then this area is filled with from 1 to 30 SGEs
81140 * Bits [7:0] of word 0 hold the first byte to go out on the wire.
81156 #define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_V3 UINT32_C(0x13)
81162 #define SQ_UDSEND_HDR_V3_WQE_TYPE_UDSEND_W_IMMED_V3 UINT32_C(0x14)
81167 * 0, and the SQ is configured to support Unsignaled completion
81172 #define SQ_UDSEND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
81179 #define SQ_UDSEND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
81186 #define SQ_UDSEND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
81192 #define SQ_UDSEND_HDR_V3_FLAGS_SE UINT32_C(0x8)
81197 #define SQ_UDSEND_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
81200 * cleared to 0, then TWE provides the timestamp.
81202 #define SQ_UDSEND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
81207 #define SQ_UDSEND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
81218 #define SQ_UDSEND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
81219 #define SQ_UDSEND_HDR_V3_WQE_SIZE_SFT 0
81224 * Zero means all 16 bytes are valid. One means only bits 7:0 of
81230 * ((inline_length == 0 ) ? 16 : inline_length)
81238 #define SQ_UDSEND_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
81239 #define SQ_UDSEND_HDR_V3_INLINE_LENGTH_SFT 0
81268 #define SQ_UDSEND_HDR_V3_DST_QP_MASK UINT32_C(0xffffff)
81269 #define SQ_UDSEND_HDR_V3_DST_QP_SFT 0
81275 #define SQ_UDSEND_HDR_V3_AVID_MASK UINT32_C(0x3ff)
81276 #define SQ_UDSEND_HDR_V3_AVID_SFT 0
81284 #define SQ_UDSEND_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
81285 #define SQ_UDSEND_HDR_V3_TIMESTAMP_SFT 0
81299 #define SQ_RDMA_V3_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15)
81305 #define SQ_RDMA_V3_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16)
81311 #define SQ_RDMA_V3_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17)
81316 * 0, and the SQ is configured to support Unsignaled
81321 #define SQ_RDMA_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
81326 #define SQ_RDMA_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
81331 #define SQ_RDMA_V3_FLAGS_UC_FENCE UINT32_C(0x4)
81337 #define SQ_RDMA_V3_FLAGS_SE UINT32_C(0x8)
81342 #define SQ_RDMA_V3_FLAGS_INLINE UINT32_C(0x10)
81345 * cleared to 0, then TWE provides the timestamp.
81347 #define SQ_RDMA_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
81352 #define SQ_RDMA_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
81363 #define SQ_RDMA_V3_WQE_SIZE_MASK UINT32_C(0x3f)
81364 #define SQ_RDMA_V3_WQE_SIZE_SFT 0
81369 * Zero means all 16 bytes are valid. One means only bits 7:0 of
81375 * ((inline_length == 0 ) ? 16 : inline_length)
81383 #define SQ_RDMA_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
81384 #define SQ_RDMA_V3_INLINE_LENGTH_SFT 0
81410 #define SQ_RDMA_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
81411 #define SQ_RDMA_V3_TIMESTAMP_SFT 0
81413 * When inline=0, then this area is filled with from 1 to 30 SGEs
81417 * Length of data is described in the inline_length field. Bits [7:0]
81418 * of word 0 hold the first byte to go out on the wire.
81434 #define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_WQE_V3 UINT32_C(0x15)
81440 #define SQ_RDMA_HDR_V3_WQE_TYPE_WRITE_W_IMMED_V3 UINT32_C(0x16)
81446 #define SQ_RDMA_HDR_V3_WQE_TYPE_READ_WQE_V3 UINT32_C(0x17)
81451 * 0, and the SQ is configured to support Unsignaled
81456 #define SQ_RDMA_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
81461 #define SQ_RDMA_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
81466 #define SQ_RDMA_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
81472 #define SQ_RDMA_HDR_V3_FLAGS_SE UINT32_C(0x8)
81477 #define SQ_RDMA_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
81480 * cleared to 0, then TWE provides the timestamp.
81482 #define SQ_RDMA_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
81487 #define SQ_RDMA_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
81498 #define SQ_RDMA_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
81499 #define SQ_RDMA_HDR_V3_WQE_SIZE_SFT 0
81504 * Zero means all 16 bytes are valid. One means only bits 7:0 of
81510 * ((inline_length == 0 ) ? 16 : inline_length)
81518 #define SQ_RDMA_HDR_V3_INLINE_LENGTH_MASK UINT32_C(0xf)
81519 #define SQ_RDMA_HDR_V3_INLINE_LENGTH_SFT 0
81545 #define SQ_RDMA_HDR_V3_TIMESTAMP_MASK UINT32_C(0xffffff)
81546 #define SQ_RDMA_HDR_V3_TIMESTAMP_SFT 0
81560 #define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18)
81566 #define SQ_ATOMIC_V3_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19)
81571 * 0, and the SQ is configured to support Unsignaled
81576 #define SQ_ATOMIC_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
81581 #define SQ_ATOMIC_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
81586 #define SQ_ATOMIC_V3_FLAGS_UC_FENCE UINT32_C(0x4)
81592 #define SQ_ATOMIC_V3_FLAGS_SE UINT32_C(0x8)
81594 #define SQ_ATOMIC_V3_FLAGS_INLINE UINT32_C(0x10)
81599 #define SQ_ATOMIC_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
81604 #define SQ_ATOMIC_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
81612 #define SQ_ATOMIC_V3_WQE_SIZE_MASK UINT32_C(0x3f)
81613 #define SQ_ATOMIC_V3_WQE_SIZE_SFT 0
81680 #define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_CS_V3 UINT32_C(0x18)
81686 #define SQ_ATOMIC_HDR_V3_WQE_TYPE_ATOMIC_FA_V3 UINT32_C(0x19)
81691 * 0, and the SQ is configured to support Unsignaled
81696 #define SQ_ATOMIC_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
81701 #define SQ_ATOMIC_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
81706 #define SQ_ATOMIC_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
81712 #define SQ_ATOMIC_HDR_V3_FLAGS_SE UINT32_C(0x8)
81714 #define SQ_ATOMIC_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
81719 #define SQ_ATOMIC_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
81724 #define SQ_ATOMIC_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
81732 #define SQ_ATOMIC_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
81733 #define SQ_ATOMIC_HDR_V3_WQE_SIZE_SFT 0
81777 #define SQ_LOCALINVALIDATE_V3_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a)
81782 * 0, and the SQ is configured to support Unsignaled
81787 #define SQ_LOCALINVALIDATE_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
81792 #define SQ_LOCALINVALIDATE_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
81797 #define SQ_LOCALINVALIDATE_V3_FLAGS_UC_FENCE UINT32_C(0x4)
81799 * This flag is not applicable and should be 0 for a local memory
81802 #define SQ_LOCALINVALIDATE_V3_FLAGS_SE UINT32_C(0x8)
81804 * This flag is not applicable and should be 0 for a local memory
81807 #define SQ_LOCALINVALIDATE_V3_FLAGS_INLINE UINT32_C(0x10)
81809 * This flag is not applicable and should be 0 for a local memory
81812 #define SQ_LOCALINVALIDATE_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
81817 #define SQ_LOCALINVALIDATE_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
81826 #define SQ_LOCALINVALIDATE_V3_WQE_SIZE_MASK UINT32_C(0x3f)
81827 #define SQ_LOCALINVALIDATE_V3_WQE_SIZE_SFT 0
81854 #define SQ_LOCALINVALIDATE_HDR_V3_WQE_TYPE_LOCAL_INVALID_V3 UINT32_C(0x1a)
81859 * 0, and the SQ is configured to support Unsignaled
81864 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
81869 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
81874 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
81876 * This flag is not applicable and should be 0 for a local memory
81879 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_SE UINT32_C(0x8)
81881 * This flag is not applicable and should be 0 for a local memory
81884 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
81886 * This flag is not applicable and should be 0 for a local memory
81889 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
81894 #define SQ_LOCALINVALIDATE_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
81903 #define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
81904 #define SQ_LOCALINVALIDATE_HDR_V3_WQE_SIZE_SFT 0
81936 #define SQ_FR_PMR_V3_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b)
81941 * 0, and the SQ is configured to support Unsignaled
81946 #define SQ_FR_PMR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
81951 #define SQ_FR_PMR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
81956 #define SQ_FR_PMR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
81958 * This flag is not applicable and should be 0 for a local memory
81961 #define SQ_FR_PMR_V3_FLAGS_SE UINT32_C(0x8)
81963 * This flag is not applicable and should be 0 for a local memory
81966 #define SQ_FR_PMR_V3_FLAGS_INLINE UINT32_C(0x10)
81968 * This flag is not applicable and should be 0 for a local memory
81971 #define SQ_FR_PMR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
81976 #define SQ_FR_PMR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
81984 #define SQ_FR_PMR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
81985 #define SQ_FR_PMR_V3_WQE_SIZE_SFT 0
81990 #define SQ_FR_PMR_V3_ZERO_BASED UINT32_C(0x40)
81993 * the operation is allowed. '0' means operation is
81998 #define SQ_FR_PMR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
82000 #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
82002 #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
82004 #define SQ_FR_PMR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
82006 #define SQ_FR_PMR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
82024 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
82025 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_SFT 0
82027 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
82029 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
82031 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
82033 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
82035 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
82037 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
82039 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
82041 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
82043 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
82045 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
82047 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
82049 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
82051 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
82053 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
82055 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
82057 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
82059 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
82061 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
82063 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
82065 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
82067 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
82069 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
82071 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
82073 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
82075 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
82077 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
82079 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
82081 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
82083 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
82085 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
82087 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
82089 #define SQ_FR_PMR_V3_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
82096 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x3e0)
82099 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (UINT32_C(0x0) << 5)
82101 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (UINT32_C(0x1) << 5)
82103 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (UINT32_C(0x2) << 5)
82105 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (UINT32_C(0x3) << 5)
82107 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (UINT32_C(0x4) << 5)
82109 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (UINT32_C(0x5) << 5)
82111 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (UINT32_C(0x6) << 5)
82113 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (UINT32_C(0x7) << 5)
82115 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (UINT32_C(0x8) << 5)
82117 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (UINT32_C(0x9) << 5)
82119 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (UINT32_C(0xa) << 5)
82121 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (UINT32_C(0xb) << 5)
82123 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (UINT32_C(0xc) << 5)
82125 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (UINT32_C(0xd) << 5)
82127 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (UINT32_C(0xe) << 5)
82129 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (UINT32_C(0xf) << 5)
82131 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (UINT32_C(0x10) << 5)
82133 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (UINT32_C(0x11) << 5)
82135 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (UINT32_C(0x12) << 5)
82137 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (UINT32_C(0x13) << 5)
82139 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (UINT32_C(0x14) << 5)
82141 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (UINT32_C(0x15) << 5)
82143 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (UINT32_C(0x16) << 5)
82145 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (UINT32_C(0x17) << 5)
82147 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (UINT32_C(0x18) << 5)
82149 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (UINT32_C(0x19) << 5)
82151 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (UINT32_C(0x1a) << 5)
82153 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (UINT32_C(0x1b) << 5)
82155 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (UINT32_C(0x1c) << 5)
82157 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (UINT32_C(0x1d) << 5)
82159 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (UINT32_C(0x1e) << 5)
82161 #define SQ_FR_PMR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (UINT32_C(0x1f) << 5)
82164 #define SQ_FR_PMR_V3_NUMLEVELS_MASK UINT32_C(0xc00)
82170 #define SQ_FR_PMR_V3_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 10)
82177 #define SQ_FR_PMR_V3_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 10)
82185 #define SQ_FR_PMR_V3_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 10)
82207 #define SQ_FR_PMR_HDR_V3_WQE_TYPE_FR_PMR_V3 UINT32_C(0x1b)
82212 * 0, and the SQ is configured to support Unsignaled
82217 #define SQ_FR_PMR_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
82222 #define SQ_FR_PMR_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
82227 #define SQ_FR_PMR_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
82229 * This flag is not applicable and should be 0 for a local memory
82232 #define SQ_FR_PMR_HDR_V3_FLAGS_SE UINT32_C(0x8)
82234 * This flag is not applicable and should be 0 for a local memory
82237 #define SQ_FR_PMR_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
82239 * This flag is not applicable and should be 0 for a local memory
82242 #define SQ_FR_PMR_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
82247 #define SQ_FR_PMR_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
82255 #define SQ_FR_PMR_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82256 #define SQ_FR_PMR_HDR_V3_WQE_SIZE_SFT 0
82261 #define SQ_FR_PMR_HDR_V3_ZERO_BASED UINT32_C(0x40)
82264 * the operation is allowed. '0' means operation is
82269 #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
82271 #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
82273 #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
82275 #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
82277 #define SQ_FR_PMR_HDR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
82295 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_MASK UINT32_C(0x1f)
82296 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_SFT 0
82298 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4K UINT32_C(0x0)
82300 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8K UINT32_C(0x1)
82302 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16K UINT32_C(0x2)
82304 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32K UINT32_C(0x3)
82306 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64K UINT32_C(0x4)
82308 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128K UINT32_C(0x5)
82310 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256K UINT32_C(0x6)
82312 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512K UINT32_C(0x7)
82314 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1M UINT32_C(0x8)
82316 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2M UINT32_C(0x9)
82318 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4M UINT32_C(0xa)
82320 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8M UINT32_C(0xb)
82322 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16M UINT32_C(0xc)
82324 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32M UINT32_C(0xd)
82326 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64M UINT32_C(0xe)
82328 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128M UINT32_C(0xf)
82330 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256M UINT32_C(0x10)
82332 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512M UINT32_C(0x11)
82334 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1G UINT32_C(0x12)
82336 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2G UINT32_C(0x13)
82338 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4G UINT32_C(0x14)
82340 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8G UINT32_C(0x15)
82342 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_16G UINT32_C(0x16)
82344 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_32G UINT32_C(0x17)
82346 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_64G UINT32_C(0x18)
82348 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_128G UINT32_C(0x19)
82350 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_256G UINT32_C(0x1a)
82352 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_512G UINT32_C(0x1b)
82354 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_1T UINT32_C(0x1c)
82356 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_2T UINT32_C(0x1d)
82358 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_4T UINT32_C(0x1e)
82360 #define SQ_FR_PMR_HDR_V3_PAGE_SIZE_LOG_PGSZ_8T UINT32_C(0x1f)
82367 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_MASK UINT32_C(0x3e0)
82370 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4K (UINT32_C(0x0) << 5)
82372 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8K (UINT32_C(0x1) << 5)
82374 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16K (UINT32_C(0x2) << 5)
82376 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32K (UINT32_C(0x3) << 5)
82378 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64K (UINT32_C(0x4) << 5)
82380 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128K (UINT32_C(0x5) << 5)
82382 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256K (UINT32_C(0x6) << 5)
82384 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512K (UINT32_C(0x7) << 5)
82386 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1M (UINT32_C(0x8) << 5)
82388 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2M (UINT32_C(0x9) << 5)
82390 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4M (UINT32_C(0xa) << 5)
82392 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8M (UINT32_C(0xb) << 5)
82394 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16M (UINT32_C(0xc) << 5)
82396 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32M (UINT32_C(0xd) << 5)
82398 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64M (UINT32_C(0xe) << 5)
82400 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128M (UINT32_C(0xf) << 5)
82402 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256M (UINT32_C(0x10) << 5)
82404 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512M (UINT32_C(0x11) << 5)
82406 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1G (UINT32_C(0x12) << 5)
82408 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2G (UINT32_C(0x13) << 5)
82410 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4G (UINT32_C(0x14) << 5)
82412 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8G (UINT32_C(0x15) << 5)
82414 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_16G (UINT32_C(0x16) << 5)
82416 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_32G (UINT32_C(0x17) << 5)
82418 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_64G (UINT32_C(0x18) << 5)
82420 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_128G (UINT32_C(0x19) << 5)
82422 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_256G (UINT32_C(0x1a) << 5)
82424 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_512G (UINT32_C(0x1b) << 5)
82426 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_1T (UINT32_C(0x1c) << 5)
82428 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_2T (UINT32_C(0x1d) << 5)
82430 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_4T (UINT32_C(0x1e) << 5)
82432 #define SQ_FR_PMR_HDR_V3_PBL_PAGE_SIZE_LOG_PGSZ_8T (UINT32_C(0x1f) << 5)
82435 #define SQ_FR_PMR_HDR_V3_NUMLEVELS_MASK UINT32_C(0xc00)
82441 #define SQ_FR_PMR_HDR_V3_NUMLEVELS_PHYSICAL (UINT32_C(0x0) << 10)
82448 #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER1 (UINT32_C(0x1) << 10)
82456 #define SQ_FR_PMR_HDR_V3_NUMLEVELS_LAYER2 (UINT32_C(0x2) << 10)
82482 #define SQ_BIND_V3_WQE_TYPE_BIND_V3 UINT32_C(0x1c)
82487 * 0, and the SQ is configured to support Unsignaled
82492 #define SQ_BIND_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
82497 #define SQ_BIND_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
82502 #define SQ_BIND_V3_FLAGS_UC_FENCE UINT32_C(0x4)
82504 * This flag is not applicable and should be 0 for a local memory
82507 #define SQ_BIND_V3_FLAGS_SE UINT32_C(0x8)
82509 * This flag is not applicable and should be 0 for a local memory
82512 #define SQ_BIND_V3_FLAGS_INLINE UINT32_C(0x10)
82514 * This flag is not applicable and should be 0 for a local memory
82517 #define SQ_BIND_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
82522 #define SQ_BIND_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
82529 #define SQ_BIND_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82530 #define SQ_BIND_V3_WQE_SIZE_SFT 0
82536 #define SQ_BIND_V3_ZERO_BASED UINT32_C(0x40)
82556 #define SQ_BIND_V3_MW_TYPE UINT32_C(0x80)
82558 #define SQ_BIND_V3__TYPE1 (UINT32_C(0x0) << 7)
82560 #define SQ_BIND_V3__TYPE2 (UINT32_C(0x1) << 7)
82564 * the operation is allowed. '0' means operation is
82575 #define SQ_BIND_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
82577 #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
82585 #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
82593 #define SQ_BIND_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
82601 #define SQ_BIND_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
82643 #define SQ_BIND_HDR_V3_WQE_TYPE_BIND_V3 UINT32_C(0x1c)
82648 * 0, and the SQ is configured to support Unsignaled
82653 #define SQ_BIND_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
82658 #define SQ_BIND_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
82663 #define SQ_BIND_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
82665 * This flag is not applicable and should be 0 for a local memory
82668 #define SQ_BIND_HDR_V3_FLAGS_SE UINT32_C(0x8)
82670 * This flag is not applicable and should be 0 for a local memory
82673 #define SQ_BIND_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
82675 * This flag is not applicable and should be 0 for a local memory
82678 #define SQ_BIND_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
82683 #define SQ_BIND_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
82690 #define SQ_BIND_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82691 #define SQ_BIND_HDR_V3_WQE_SIZE_SFT 0
82697 #define SQ_BIND_HDR_V3_ZERO_BASED UINT32_C(0x40)
82717 #define SQ_BIND_HDR_V3_MW_TYPE UINT32_C(0x80)
82719 #define SQ_BIND_HDR_V3__TYPE1 (UINT32_C(0x0) << 7)
82721 #define SQ_BIND_HDR_V3__TYPE2 (UINT32_C(0x1) << 7)
82725 * the operation is allowed. '0' means operation is
82736 #define SQ_BIND_HDR_V3_ACCESS_CNTL_LOCAL_WRITE UINT32_C(0x1)
82738 #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_READ UINT32_C(0x2)
82746 #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_WRITE UINT32_C(0x4)
82754 #define SQ_BIND_HDR_V3_ACCESS_CNTL_REMOTE_ATOMIC UINT32_C(0x8)
82762 #define SQ_BIND_HDR_V3_ACCESS_CNTL_WINDOW_BIND UINT32_C(0x10)
82802 #define SQ_CHANGE_UDPSRCPORT_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e)
82807 * 0, and the SQ is configured to support Unsignaled
82812 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
82817 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
82825 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_UC_FENCE UINT32_C(0x4)
82827 * This flag is not applicable and should be 0 for a local memory
82830 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_SE UINT32_C(0x8)
82832 * This flag is not applicable and should be 0 for a local memory
82835 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_INLINE UINT32_C(0x10)
82837 * This flag is not applicable and should be 0 for a local memory
82840 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
82845 #define SQ_CHANGE_UDPSRCPORT_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
82853 #define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82854 #define SQ_CHANGE_UDPSRCPORT_V3_WQE_SIZE_SFT 0
82874 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_TYPE_CHANGE_UDPSRCPORT_V3 UINT32_C(0x1e)
82879 * 0, and the SQ is configured to support Unsignaled
82884 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SIGNAL_COMP UINT32_C(0x1)
82889 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_RD_OR_ATOMIC_FENCE UINT32_C(0x2)
82897 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_UC_FENCE UINT32_C(0x4)
82899 * This flag is not applicable and should be 0 for a local memory
82902 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_SE UINT32_C(0x8)
82904 * This flag is not applicable and should be 0 for a local memory
82907 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_INLINE UINT32_C(0x10)
82909 * This flag is not applicable and should be 0 for a local memory
82912 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_WQE_TS_EN UINT32_C(0x20)
82917 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_FLAGS_DEBUG_TRACE UINT32_C(0x40)
82925 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_MASK UINT32_C(0x3f)
82926 #define SQ_CHANGE_UDPSRCPORT_HDR_V3_WQE_SIZE_SFT 0
82949 #define RQ_WQE_WQE_TYPE_RCV UINT32_C(0x80)
82970 #define RQ_WQE_WR_ID_MASK UINT32_C(0xfffff)
82971 #define RQ_WQE_WR_ID_SFT 0
82990 #define RQ_WQE_HDR_WQE_TYPE_RCV UINT32_C(0x80)
83011 #define RQ_WQE_HDR_WR_ID_MASK UINT32_C(0xfffff)
83012 #define RQ_WQE_HDR_WR_ID_SFT 0
83026 #define RQ_WQE_V3_WQE_TYPE_RCV_V3 UINT32_C(0x90)
83058 #define RQ_WQE_HDR_V3_WQE_TYPE_RCV_V3 UINT32_C(0x90)
83087 #define CQ_BASE_TOGGLE UINT32_C(0x1)
83089 #define CQ_BASE_CQE_TYPE_MASK UINT32_C(0x1e)
83095 #define CQ_BASE_CQE_TYPE_REQ (UINT32_C(0x0) << 1)
83100 #define CQ_BASE_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1)
83105 #define CQ_BASE_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1)
83110 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1)
83116 #define CQ_BASE_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1)
83121 #define CQ_BASE_CQE_TYPE_REQ_V3 (UINT32_C(0x8) << 1)
83126 #define CQ_BASE_CQE_TYPE_RES_RC_V3 (UINT32_C(0x9) << 1)
83132 #define CQ_BASE_CQE_TYPE_RES_UD_V3 (UINT32_C(0xa) << 1)
83138 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (UINT32_C(0xb) << 1)
83145 #define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (UINT32_C(0xc) << 1)
83150 #define CQ_BASE_CQE_TYPE_NO_OP (UINT32_C(0xd) << 1)
83155 #define CQ_BASE_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1)
83161 #define CQ_BASE_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1)
83166 #define CQ_BASE_STATUS_OK UINT32_C(0x0)
83173 #define CQ_BASE_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1)
83187 #define CQ_BASE_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
83194 #define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3)
83204 #define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
83214 #define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
83223 #define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x6)
83230 #define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x7)
83241 #define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8)
83251 #define CQ_BASE_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x9)
83261 #define CQ_BASE_STATUS_REMOTE_OPERATION_ERR UINT32_C(0xa)
83268 #define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0xb)
83275 #define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xc)
83280 #define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
83286 #define CQ_BASE_STATUS_HW_FLUSH_ERR UINT32_C(0xe)
83292 #define CQ_BASE_STATUS_OVERFLOW_ERR UINT32_C(0xf)
83314 * QPC.sq_size (i.e. the valid range of the SQ Consumer Index is 0
83327 #define CQ_REQ_TOGGLE UINT32_C(0x1)
83329 #define CQ_REQ_CQE_TYPE_MASK UINT32_C(0x1e)
83335 #define CQ_REQ_CQE_TYPE_REQ (UINT32_C(0x0) << 1)
83340 * the driver. When this bit is '0', it indicates that the packet
83347 #define CQ_REQ_PUSH UINT32_C(0x20)
83350 /* OK is 0 */
83351 #define CQ_REQ_STATUS_OK UINT32_C(0x0)
83353 #define CQ_REQ_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1)
83355 #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
83357 #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x3)
83359 #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x4)
83361 #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
83363 #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6)
83365 #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x7)
83367 #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR UINT32_C(0x8)
83369 #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0x9)
83371 #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xa)
83373 #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xb)
83412 #define CQ_RES_RC_TOGGLE UINT32_C(0x1)
83414 #define CQ_RES_RC_CQE_TYPE_MASK UINT32_C(0x1e)
83420 #define CQ_RES_RC_CQE_TYPE_RES_RC (UINT32_C(0x1) << 1)
83424 /* OK is 0 */
83425 #define CQ_RES_RC_STATUS_OK UINT32_C(0x0)
83427 #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
83429 #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
83431 #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
83433 #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
83435 #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
83437 #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x6)
83439 #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
83441 #define CQ_RES_RC_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
83448 #define CQ_RES_RC_FLAGS_SRQ UINT32_C(0x1)
83450 #define CQ_RES_RC_FLAGS_SRQ_RQ UINT32_C(0x0)
83452 #define CQ_RES_RC_FLAGS_SRQ_SRQ UINT32_C(0x1)
83455 #define CQ_RES_RC_FLAGS_IMM UINT32_C(0x2)
83457 #define CQ_RES_RC_FLAGS_INV UINT32_C(0x4)
83458 #define CQ_RES_RC_FLAGS_RDMA UINT32_C(0x8)
83460 #define CQ_RES_RC_FLAGS_RDMA_SEND (UINT32_C(0x0) << 3)
83462 #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (UINT32_C(0x1) << 3)
83470 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
83471 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0
83483 #define CQ_RES_UD_LENGTH_MASK UINT32_C(0x3fff)
83484 #define CQ_RES_UD_LENGTH_SFT 0
83491 #define CQ_RES_UD_CFA_METADATA_VID_MASK UINT32_C(0xfff)
83492 #define CQ_RES_UD_CFA_METADATA_VID_SFT 0
83494 #define CQ_RES_UD_CFA_METADATA_DE UINT32_C(0x1000)
83496 #define CQ_RES_UD_CFA_METADATA_PRI_MASK UINT32_C(0xe000)
83518 #define CQ_RES_UD_TOGGLE UINT32_C(0x1)
83520 #define CQ_RES_UD_CQE_TYPE_MASK UINT32_C(0x1e)
83526 #define CQ_RES_UD_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1)
83534 #define CQ_RES_UD_STATUS_OK UINT32_C(0x0)
83542 #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
83549 #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
83551 #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
83553 #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
83555 #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
83557 #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
83559 #define CQ_RES_UD_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
83566 #define CQ_RES_UD_FLAGS_SRQ UINT32_C(0x1)
83568 #define CQ_RES_UD_FLAGS_SRQ_RQ UINT32_C(0x0)
83570 #define CQ_RES_UD_FLAGS_SRQ_SRQ UINT32_C(0x1)
83573 #define CQ_RES_UD_FLAGS_IMM UINT32_C(0x2)
83574 #define CQ_RES_UD_FLAGS_UNUSED_MASK UINT32_C(0xc)
83576 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
83579 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
83581 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
83583 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
83589 #define CQ_RES_UD_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0)
83592 #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6)
83595 * - metadata[11:0] contains the vlan VID value.
83599 #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (UINT32_C(0x1) << 6)
83604 * - VXLAN = VNI[23:0] -> VXLAN Network ID
83605 * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier.
83606 * - NVGRE = TNI[23:0] -> Tenant Network ID
83607 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
83608 * - IPV4 = 0 (not populated)
83609 * - IPV6 = Flow Label[19:0]
83610 * - PPPoE = sessionID[15:0]
83611 * - MPLs = Outer label[19:0]
83612 * - UPAR = Selected[31:0] with bit mask
83614 #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6)
83619 #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6)
83623 * - metadata[8:0] contains the outer_l3_offset.
83624 * - metadata[15:9] contains the inner_l2_offset[6:0]
83626 #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6)
83632 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK UINT32_C(0xc00)
83640 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
83641 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0
83643 #define CQ_RES_UD_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
83656 #define CQ_RES_UD_V2_LENGTH_MASK UINT32_C(0x3fff)
83657 #define CQ_RES_UD_V2_LENGTH_SFT 0
83661 #define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
83662 #define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0
83664 #define CQ_RES_UD_V2_CFA_METADATA0_DE UINT32_C(0x1000)
83666 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
83688 #define CQ_RES_UD_V2_TOGGLE UINT32_C(0x1)
83690 #define CQ_RES_UD_V2_CQE_TYPE_MASK UINT32_C(0x1e)
83696 #define CQ_RES_UD_V2_CQE_TYPE_RES_UD (UINT32_C(0x2) << 1)
83704 #define CQ_RES_UD_V2_STATUS_OK UINT32_C(0x0)
83712 #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
83719 #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
83721 #define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
83723 #define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
83725 #define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
83727 #define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
83729 #define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
83736 #define CQ_RES_UD_V2_FLAGS_SRQ UINT32_C(0x1)
83738 #define CQ_RES_UD_V2_FLAGS_SRQ_RQ UINT32_C(0x0)
83740 #define CQ_RES_UD_V2_FLAGS_SRQ_SRQ UINT32_C(0x1)
83743 #define CQ_RES_UD_V2_FLAGS_IMM UINT32_C(0x2)
83744 #define CQ_RES_UD_V2_FLAGS_UNUSED_MASK UINT32_C(0xc)
83746 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
83749 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
83751 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
83753 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
83756 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0)
83759 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6)
83762 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
83763 * de, vid[11:0]} The metadata2 field contains the table scope
83764 * and action record pointer. - metadata2[25:0] contains the
83768 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6)
83772 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
83775 * - VXLAN = VNI[23:0] -> VXLAN Network ID
83776 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
83777 * - NVGRE = TNI[23:0] -> Tenant Network ID
83778 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
83779 * - IPv4 = 0 (not populated)
83780 * - IPv6 = Flow Label[19:0]
83781 * - PPPoE = sessionID[15:0]
83782 * - MPLs = Outer label[19:0]
83783 * - UPAR = Selected[31:0] with bit mask
83785 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6)
83789 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
83793 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6)
83797 * - metadata[8:0] contains the outer_l3_offset.
83798 * - metadata[15:9] contains the inner_l2_offset[6:0]
83800 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6)
83808 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
83809 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0
83810 #define CQ_RES_UD_V2_CFA_METADATA1_MASK UINT32_C(0xf00000)
83812 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
83813 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000)
83815 /* 0x88a8 */
83816 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20)
83817 /* 0x8100 */
83818 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20)
83819 /* 0x9100 */
83820 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20)
83821 /* 0x9200 */
83822 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20)
83823 /* 0x9300 */
83824 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20)
83826 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20)
83828 /* When meta_format != 0, this value is the VLAN valid. */
83829 #define CQ_RES_UD_V2_CFA_METADATA1_VALID UINT32_C(0x800000)
83831 #define CQ_RES_UD_V2_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
83844 #define CQ_RES_UD_CFA_LENGTH_MASK UINT32_C(0x3fff)
83845 #define CQ_RES_UD_CFA_LENGTH_SFT 0
83859 #define CQ_RES_UD_CFA_QID_MASK UINT32_C(0xfffff)
83860 #define CQ_RES_UD_CFA_QID_SFT 0
83867 #define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK UINT32_C(0xfff)
83868 #define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0
83870 #define CQ_RES_UD_CFA_CFA_METADATA_DE UINT32_C(0x1000)
83872 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK UINT32_C(0xe000)
83875 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK UINT32_C(0xffff0000)
83890 #define CQ_RES_UD_CFA_TOGGLE UINT32_C(0x1)
83892 #define CQ_RES_UD_CFA_CQE_TYPE_MASK UINT32_C(0x1e)
83900 #define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1)
83908 #define CQ_RES_UD_CFA_STATUS_OK UINT32_C(0x0)
83916 #define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
83923 #define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
83925 #define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
83927 #define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
83929 #define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
83931 #define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
83933 #define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
83940 #define CQ_RES_UD_CFA_FLAGS_SRQ UINT32_C(0x1)
83942 #define CQ_RES_UD_CFA_FLAGS_SRQ_RQ UINT32_C(0x0)
83944 #define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ UINT32_C(0x1)
83947 #define CQ_RES_UD_CFA_FLAGS_IMM UINT32_C(0x2)
83948 #define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK UINT32_C(0xc)
83950 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
83953 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
83955 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
83957 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
83963 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0)
83966 * If ext_meta_format is equal to 0, there is no metadata
83969 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6)
83971 * If ext_meta_format is equal to 0, the metadata field contains
83973 * - metadata[11:0] contains the vlan VID value.
83978 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (UINT32_C(0x1) << 6)
83982 * - VXLAN = VNI[23:0] -> VXLAN Network ID
83983 * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier
83984 * - NVGRE = TNI[23:0] -> Tenant Network ID
83985 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
83986 * - IPV4 = 0 (not populated)
83987 * - IPV6 = Flow Label[19:0]
83988 * - PPPoE = sessionID[15:0]
83989 * - MPLs = Outer label[19:0]
83990 * - UPAR = Selected[31:0] with bit mask
83992 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6)
83997 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6)
84002 * - metadata[8:0] contains the outer_l3_offset.
84007 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6)
84013 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK UINT32_C(0xc00)
84021 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
84022 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0
84024 #define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
84037 #define CQ_RES_UD_CFA_V2_LENGTH_MASK UINT32_C(0x3fff)
84038 #define CQ_RES_UD_CFA_V2_LENGTH_SFT 0
84042 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
84043 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0
84045 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE UINT32_C(0x1000)
84047 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
84057 #define CQ_RES_UD_CFA_V2_QID_MASK UINT32_C(0xfffff)
84058 #define CQ_RES_UD_CFA_V2_QID_SFT 0
84062 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
84063 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
84064 * act_rec_ptr[25:0]}
84065 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
84066 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
84067 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
84085 #define CQ_RES_UD_CFA_V2_TOGGLE UINT32_C(0x1)
84087 #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK UINT32_C(0x1e)
84095 #define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (UINT32_C(0x4) << 1)
84103 #define CQ_RES_UD_CFA_V2_STATUS_OK UINT32_C(0x0)
84111 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
84118 #define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
84120 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
84122 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
84124 #define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
84126 #define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
84128 #define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
84135 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ UINT32_C(0x1)
84137 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ UINT32_C(0x0)
84139 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ UINT32_C(0x1)
84142 #define CQ_RES_UD_CFA_V2_FLAGS_IMM UINT32_C(0x2)
84143 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK UINT32_C(0xc)
84145 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
84148 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
84150 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
84152 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
84155 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0)
84158 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6)
84161 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
84162 * de, vid[11:0]} The metadata2 field contains the table scope
84163 * and action record pointer. - metadata2[25:0] contains the
84167 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6)
84171 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
84174 * - VXLAN = VNI[23:0] -> VXLAN Network ID
84175 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
84176 * - NVGRE = TNI[23:0] -> Tenant Network ID
84177 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
84178 * - IPv4 = 0 (not populated)
84179 * - IPv6 = Flow Label[19:0]
84180 * - PPPoE = sessionID[15:0]
84181 * - MPLs = Outer label[19:0]
84182 * - UPAR = Selected[31:0] with bit mask
84184 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6)
84188 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
84192 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6)
84196 * - metadata[8:0] contains the outer_l3_offset.
84197 * - metadata[15:9] contains the inner_l2_offset[6:0]
84199 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6)
84207 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
84208 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0
84209 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK UINT32_C(0xf00000)
84211 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
84212 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000)
84214 /* 0x88a8 */
84215 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20)
84216 /* 0x8100 */
84217 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20)
84218 /* 0x9100 */
84219 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20)
84220 /* 0x9200 */
84221 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20)
84222 /* 0x9300 */
84223 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20)
84225 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20)
84227 /* When meta_format != 0, this value is the VLAN valid. */
84228 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID UINT32_C(0x800000)
84230 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
84243 #define CQ_RES_RAWETH_QP1_LENGTH_MASK UINT32_C(0x3fff)
84244 #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0
84246 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK UINT32_C(0x3ff)
84247 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0
84253 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1)
84258 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK UINT32_C(0x3c0)
84264 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6)
84270 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (UINT32_C(0x1) << 6)
84277 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6)
84284 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6)
84291 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6)
84298 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6)
84305 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6)
84311 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6)
84317 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6)
84324 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10)
84329 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20)
84334 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
84339 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
84344 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100)
84350 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
84356 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
84362 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
84368 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
84374 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9)
84380 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9)
84386 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9)
84389 * have failed (e.g. TTL = 0) in the tunnel header. Valid
84392 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9)
84399 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
84405 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
84412 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
84417 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
84420 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
84422 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
84428 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
84434 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
84439 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
84441 …#define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) << …
84447 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
84465 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC UINT32_C(0x1)
84471 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2)
84477 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
84483 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
84488 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
84491 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
84495 * - raweth_qp1_metadata[11:0] contains the vlan VID value.
84500 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
84505 * - VXLAN = VNI[23:0] -> VXLAN Network ID
84506 * - Geneve (NGE) = VNI[23:0] -> Virtual Network Identifier.
84507 * - NVGRE = TNI[23:0] -> Tenant Network ID
84508 * - GRE = KEY[31:0] -> key field with bit mask. zero if K = 0
84509 * - IPV4 = 0 (not populated)
84510 * - IPV6 = Flow Label[19:0]
84511 * - PPPoE = sessionID[15:0]
84512 * - MPLs = Outer label[19:0]
84513 * - UPAR = Selected[31:0] with bit mask
84515 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
84520 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
84524 * - metadata[8:0] contains the outer_l3_offset.
84525 * - metadata[15:9] contains the inner_l2_offset[6:0]
84527 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
84531 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
84535 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100)
84540 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
84545 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
84553 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
84560 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK UINT32_C(0xffff)
84561 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0
84563 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK UINT32_C(0xfff)
84564 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0
84566 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE UINT32_C(0x1000)
84568 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK UINT32_C(0xe000)
84571 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK UINT32_C(0xffff0000)
84579 #define CQ_RES_RAWETH_QP1_TOGGLE UINT32_C(0x1)
84581 #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK UINT32_C(0x1e)
84587 #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1)
84595 #define CQ_RES_RAWETH_QP1_STATUS_OK UINT32_C(0x0)
84603 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
84610 #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
84612 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
84614 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
84616 #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
84618 #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
84620 #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
84627 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ UINT32_C(0x1)
84629 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ UINT32_C(0x0)
84631 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ UINT32_C(0x1)
84639 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
84640 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0
84647 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000)
84660 #define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK UINT32_C(0x3fff)
84661 #define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0
84663 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK UINT32_C(0x3ff)
84664 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0
84670 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR UINT32_C(0x1)
84675 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK UINT32_C(0x3c0)
84681 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6)
84687 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (UINT32_C(0x1) << 6)
84694 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (UINT32_C(0x2) << 6)
84701 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (UINT32_C(0x3) << 6)
84708 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (UINT32_C(0x4) << 6)
84715 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (UINT32_C(0x5) << 6)
84722 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (UINT32_C(0x7) << 6)
84728 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6)
84734 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6)
84741 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10)
84746 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20)
84751 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
84756 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
84761 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100)
84767 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
84773 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
84779 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
84785 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
84791 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (UINT32_C(0x3) << 9)
84797 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x4) << 9)
84803 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x5) << 9)
84806 * have failed (e.g. TTL = 0) in the tunnel header. Valid
84809 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x6) << 9)
84816 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
84822 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
84829 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
84834 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
84837 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
84839 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
84845 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
84851 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
84856 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
84858 …#define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) …
84864 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
84869 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
84870 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0
84872 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE UINT32_C(0x1000)
84874 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
84883 * When this bit is '0', the cs_ok field has the following
84884 * definition:- ip_cs_ok[2:0] = The number of header groups with a
84891 * field has the following definition: - hdr_cnt[2:0] = The number of
84898 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE UINT32_C(0x8)
84900 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
84903 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
84906 * information: - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],
84907 * de, vid[11:0]} The metadata2 field contains the table scope
84908 * and action record pointer. - metadata2[25:0] contains the
84912 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
84916 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
84919 * - VXLAN = VNI[23:0] -> VXLAN Network ID
84920 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
84921 * - NVGRE = TNI[23:0] -> Tenant Network ID
84922 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
84923 * - IPv4 = 0 (not populated)
84924 * - IPv6 = Flow Label[19:0]
84925 * - PPPoE = sessionID[15:0]
84926 * - MPLs = Outer label[19:0]
84927 * - UPAR = Selected[31:0] with bit mask
84929 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
84933 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
84937 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
84941 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
84944 * - metadata2[8:0] contains the outer_l3_offset.
84949 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
84953 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
84957 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100)
84962 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
84968 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK UINT32_C(0xfc00)
84976 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
84981 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
84982 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
84983 * act_rec_ptr[25:0]}
84984 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
84985 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
84986 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
84997 #define CQ_RES_RAWETH_QP1_V2_TOGGLE UINT32_C(0x1)
84999 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK UINT32_C(0x1e)
85005 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (UINT32_C(0x3) << 1)
85013 #define CQ_RES_RAWETH_QP1_V2_STATUS_OK UINT32_C(0x0)
85021 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x1)
85028 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x2)
85030 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x3)
85032 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
85034 #define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x5)
85036 #define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0x7)
85038 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR UINT32_C(0x8)
85045 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ UINT32_C(0x1)
85047 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ UINT32_C(0x0)
85049 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ UINT32_C(0x1)
85057 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK UINT32_C(0xfffff)
85058 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0
85059 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK UINT32_C(0xf00000)
85061 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
85062 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000)
85064 /* 0x88a8 */
85065 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (UINT32_C(0x0) << 20)
85066 /* 0x8100 */
85067 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (UINT32_C(0x1) << 20)
85068 /* 0x9100 */
85069 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (UINT32_C(0x2) << 20)
85070 /* 0x9200 */
85071 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (UINT32_C(0x3) << 20)
85072 /* 0x9300 */
85073 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (UINT32_C(0x4) << 20)
85075 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (UINT32_C(0x5) << 20)
85077 /* When meta_format != 0, this value is the VLAN valid. */
85078 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID UINT32_C(0x800000)
85086 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK UINT32_C(0xff000000)
85120 #define CQ_TERMINAL_TOGGLE UINT32_C(0x1)
85122 #define CQ_TERMINAL_CQE_TYPE_MASK UINT32_C(0x1e)
85128 #define CQ_TERMINAL_CQE_TYPE_TERMINAL (UINT32_C(0xe) << 1)
85133 #define CQ_TERMINAL_STATUS_OK UINT32_C(0x0)
85152 #define CQ_CUTOFF_TOGGLE UINT32_C(0x1)
85154 #define CQ_CUTOFF_CQE_TYPE_MASK UINT32_C(0x1e)
85157 #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (UINT32_C(0xf) << 1)
85173 #define CQ_CUTOFF_RESIZE_TOGGLE_MASK UINT32_C(0x60)
85178 #define CQ_CUTOFF_STATUS_OK UINT32_C(0x0)
85197 #define CQ_NO_OP_TOGGLE UINT32_C(0x1)
85199 #define CQ_NO_OP_CQE_TYPE_MASK UINT32_C(0x1e)
85205 #define CQ_NO_OP_CQE_TYPE_NO_OP (UINT32_C(0xd) << 1)
85210 #define CQ_NO_OP_STATUS_OK UINT32_C(0x0)
85234 * (i.e. the valid range of the SQ Consumer Index is 0 to
85253 #define CQ_REQ_V3_TOGGLE UINT32_C(0x1)
85255 #define CQ_REQ_V3_CQE_TYPE_MASK UINT32_C(0x1e)
85261 #define CQ_REQ_V3_CQE_TYPE_REQ_V3 (UINT32_C(0x8) << 1)
85266 * the driver. When this bit is '0', it indicates that the packet
85274 #define CQ_REQ_V3_PUSH UINT32_C(0x20)
85278 #define CQ_REQ_V3_STATUS_OK UINT32_C(0x0)
85285 #define CQ_REQ_V3_STATUS_BAD_RESPONSE_ERR UINT32_C(0x1)
85299 #define CQ_REQ_V3_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
85309 #define CQ_REQ_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
85319 #define CQ_REQ_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
85326 #define CQ_REQ_V3_STATUS_MEMORY_MGT_OPERATION_ERR UINT32_C(0x7)
85337 #define CQ_REQ_V3_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8)
85347 #define CQ_REQ_V3_STATUS_REMOTE_ACCESS_ERR UINT32_C(0x9)
85357 #define CQ_REQ_V3_STATUS_REMOTE_OPERATION_ERR UINT32_C(0xa)
85364 #define CQ_REQ_V3_STATUS_RNR_NAK_RETRY_CNT_ERR UINT32_C(0xb)
85371 #define CQ_REQ_V3_STATUS_TRANSPORT_RETRY_CNT_ERR UINT32_C(0xc)
85376 #define CQ_REQ_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
85382 #define CQ_REQ_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf)
85397 * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The
85438 #define CQ_RES_RC_V3_TOGGLE UINT32_C(0x1)
85440 #define CQ_RES_RC_V3_CQE_TYPE_MASK UINT32_C(0x1e)
85446 #define CQ_RES_RC_V3_CQE_TYPE_RES_RC_V3 (UINT32_C(0x9) << 1)
85451 #define CQ_RES_RC_V3_STATUS_OK UINT32_C(0x0)
85465 #define CQ_RES_RC_V3_STATUS_LOCAL_LENGTH_ERR UINT32_C(0x2)
85475 #define CQ_RES_RC_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
85485 #define CQ_RES_RC_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
85494 #define CQ_RES_RC_V3_STATUS_LOCAL_ACCESS_ERROR UINT32_C(0x6)
85505 #define CQ_RES_RC_V3_STATUS_REMOTE_INVALID_REQUEST_ERR UINT32_C(0x8)
85510 #define CQ_RES_RC_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
85516 #define CQ_RES_RC_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe)
85522 #define CQ_RES_RC_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf)
85529 #define CQ_RES_RC_V3_FLAGS_SRQ UINT32_C(0x1)
85531 #define CQ_RES_RC_V3_FLAGS_SRQ_RQ UINT32_C(0x0)
85533 #define CQ_RES_RC_V3_FLAGS_SRQ_SRQ UINT32_C(0x1)
85536 #define CQ_RES_RC_V3_FLAGS_IMM UINT32_C(0x2)
85538 #define CQ_RES_RC_V3_FLAGS_INV UINT32_C(0x4)
85539 #define CQ_RES_RC_V3_FLAGS_RDMA UINT32_C(0x8)
85541 #define CQ_RES_RC_V3_FLAGS_RDMA_SEND (UINT32_C(0x0) << 3)
85543 #define CQ_RES_RC_V3_FLAGS_RDMA_RDMA_WRITE (UINT32_C(0x1) << 3)
85557 * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The
85574 #define CQ_RES_UD_V3_LENGTH_MASK UINT32_C(0x3fff)
85575 #define CQ_RES_UD_V3_LENGTH_SFT 0
85599 #define CQ_RES_UD_V3_TOGGLE UINT32_C(0x1)
85601 #define CQ_RES_UD_V3_CQE_TYPE_MASK UINT32_C(0x1e)
85608 #define CQ_RES_UD_V3_CQE_TYPE_RES_UD_V3 (UINT32_C(0xa) << 1)
85613 #define CQ_RES_UD_V3_STATUS_OK UINT32_C(0x0)
85620 #define CQ_RES_UD_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3)
85630 #define CQ_RES_UD_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
85640 #define CQ_RES_UD_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
85645 #define CQ_RES_UD_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
85651 #define CQ_RES_UD_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe)
85657 #define CQ_RES_UD_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf)
85664 #define CQ_RES_UD_V3_FLAGS_SRQ UINT32_C(0x1)
85666 #define CQ_RES_UD_V3_FLAGS_SRQ_RQ UINT32_C(0x0)
85668 #define CQ_RES_UD_V3_FLAGS_SRQ_SRQ UINT32_C(0x1)
85671 #define CQ_RES_UD_V3_FLAGS_IMM UINT32_C(0x2)
85672 #define CQ_RES_UD_V3_FLAGS_UNUSED_MASK UINT32_C(0xc)
85674 #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
85677 #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
85679 #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
85681 #define CQ_RES_UD_V3_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
85695 * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The
85712 #define CQ_RES_RAWETH_QP1_V3_LENGTH_MASK UINT32_C(0x3fff)
85713 #define CQ_RES_RAWETH_QP1_V3_LENGTH_SFT 0
85720 #define CQ_RES_RAWETH_QP1_V3_ERROR UINT32_C(0x1)
85725 #define CQ_RES_RAWETH_QP1_V3_ITYPE_MASK UINT32_C(0x3c0)
85731 #define CQ_RES_RAWETH_QP1_V3_ITYPE_NOT_KNOWN (UINT32_C(0x0) << 6)
85737 #define CQ_RES_RAWETH_QP1_V3_ITYPE_IP (UINT32_C(0x1) << 6)
85744 #define CQ_RES_RAWETH_QP1_V3_ITYPE_TCP (UINT32_C(0x2) << 6)
85751 #define CQ_RES_RAWETH_QP1_V3_ITYPE_UDP (UINT32_C(0x3) << 6)
85758 #define CQ_RES_RAWETH_QP1_V3_ITYPE_FCOE (UINT32_C(0x4) << 6)
85765 #define CQ_RES_RAWETH_QP1_V3_ITYPE_ROCE (UINT32_C(0x5) << 6)
85772 #define CQ_RES_RAWETH_QP1_V3_ITYPE_ICMP (UINT32_C(0x7) << 6)
85778 #define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_WO_TIMESTAMP (UINT32_C(0x8) << 6)
85784 #define CQ_RES_RAWETH_QP1_V3_ITYPE_PTP_W_TIMESTAMP (UINT32_C(0x9) << 6)
85786 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_MASK UINT32_C(0xf000)
85788 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
85789 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x7000)
85791 /* When meta_format != 0, this value is the VLAN valid. */
85792 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA1_VALID UINT32_C(0x8000)
85798 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_IP_CS_ERROR UINT32_C(0x10)
85803 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_L4_CS_ERROR UINT32_C(0x20)
85808 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_IP_CS_ERROR UINT32_C(0x40)
85813 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_L4_CS_ERROR UINT32_C(0x80)
85818 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_CRC_ERROR UINT32_C(0x100)
85824 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK UINT32_C(0xe00)
85830 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 9)
85836 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (UINT32_C(0x1) << 9)
85842 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (UINT32_C(0x2) << 9)
85848 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (UINT32_C(0x3) << 9)
85854 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (UINT32_C(0x4) << 9)
85857 * have failed (e.g. TTL = 0) in the tunnel header. Valid
85860 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (UINT32_C(0x5) << 9)
85866 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_TOTAL_ERROR (UINT32_C(0x6) << 9)
85873 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_MASK UINT32_C(0xf000)
85879 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (UINT32_C(0x0) << 12)
85886 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (UINT32_C(0x1) << 12)
85891 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (UINT32_C(0x2) << 12)
85894 * have failed (e.g. TTL = 0). Valid for IPv4, and IPv6
85896 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (UINT32_C(0x3) << 12)
85902 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (UINT32_C(0x4) << 12)
85908 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (UINT32_C(0x5) << 12)
85913 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (UINT32_C(0x6) << 12)
85915 …#define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (UINT32_C(0x7) …
85921 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (UINT32_C(0x8) << 12)
85926 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
85927 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_VID_SFT 0
85929 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_DE UINT32_C(0x1000)
85931 #define CQ_RES_RAWETH_QP1_V3_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
85944 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_CS_CALC UINT32_C(0x1)
85950 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_L4_CS_CALC UINT32_C(0x2)
85956 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
85962 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
85964 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
85967 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
85972 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
85977 * - metadata2[25:0] contains the action record pointer.
85980 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 4)
85985 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
85990 * - VXLAN = VNI[23:0] -> VXLAN Network ID
85991 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
85992 * - NVGRE = TNI[23:0] -> Tenant Network ID
85993 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
85994 * - IPv4 = 0 (not populated)
85995 * - IPv6 = Flow Label[19:0]
85996 * - PPPoE = sessionID[15:0]
85997 * - MPLs = Outer label[19:0]
85998 * - UPAR = Selected[31:0] with bit mask
86000 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 4)
86005 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
86010 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 4)
86015 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
86020 * - metadata2[8:0] contains the outer_l3_offset.
86025 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 4)
86029 * A value of '0' indicates IPv4. A value of '1' indicates IPv6.
86033 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_IP_TYPE UINT32_C(0x100)
86038 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
86039 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE UINT32_C(0x400)
86041 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV4 (UINT32_C(0x0) << 10)
86043 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_T_IP_TYPE_IPV6 (UINT32_C(0x1) << 10)
86051 #define CQ_RES_RAWETH_QP1_V3_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK UINT32_C(0xffff0000)
86057 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
86058 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
86059 * act_rec_ptr[25:0]}
86060 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
86061 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
86062 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
86071 #define CQ_RES_RAWETH_QP1_V3_TOGGLE UINT32_C(0x1)
86073 #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_MASK UINT32_C(0x1e)
86080 #define CQ_RES_RAWETH_QP1_V3_CQE_TYPE_RES_RAWETH_QP1_V3 (UINT32_C(0xb) << 1)
86085 #define CQ_RES_RAWETH_QP1_V3_STATUS_OK UINT32_C(0x0)
86092 #define CQ_RES_RAWETH_QP1_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3)
86102 #define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
86112 #define CQ_RES_RAWETH_QP1_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
86117 #define CQ_RES_RAWETH_QP1_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
86123 #define CQ_RES_RAWETH_QP1_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe)
86129 #define CQ_RES_RAWETH_QP1_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf)
86136 #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ UINT32_C(0x1)
86138 #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_RQ UINT32_C(0x0)
86140 #define CQ_RES_RAWETH_QP1_V3_FLAGS_SRQ_SRQ UINT32_C(0x1)
86165 * range for rq_prod/cons_idx is from 0 to QPC.rq_size-1. The
86182 #define CQ_RES_UD_CFA_V3_LENGTH_MASK UINT32_C(0x3fff)
86183 #define CQ_RES_UD_CFA_V3_LENGTH_SFT 0
86187 #define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_MASK UINT32_C(0xfff)
86188 #define CQ_RES_UD_CFA_V3_CFA_METADATA0_VID_SFT 0
86190 #define CQ_RES_UD_CFA_V3_CFA_METADATA0_DE UINT32_C(0x1000)
86192 #define CQ_RES_UD_CFA_V3_CFA_METADATA0_PRI_MASK UINT32_C(0xe000)
86203 #define CQ_RES_UD_CFA_V3_QID_MASK UINT32_C(0x7ff)
86204 #define CQ_RES_UD_CFA_V3_QID_SFT 0
86205 #define CQ_RES_UD_CFA_V3_UNUSED_MASK UINT32_C(0xff800)
86207 #define CQ_RES_UD_CFA_V3_CFA_METADATA1_MASK UINT32_C(0xf00000)
86209 /* When meta_format != 0, this value is the VLAN TPID_SEL. */
86210 #define CQ_RES_UD_CFA_V3_CFA_METADATA1_TPID_SEL_MASK UINT32_C(0x700000)
86212 /* When meta_format != 0, this value is the VLAN valid. */
86213 #define CQ_RES_UD_CFA_V3_CFA_METADATA1_VALID UINT32_C(0x800000)
86215 #define CQ_RES_UD_CFA_V3_SRC_QP_HIGH_MASK UINT32_C(0xff000000)
86221 * - meta_format 0 - none - metadata2 = 0 - not valid/not stripped
86222 * - meta_format 1 - act_rec_ptr - metadata2 = {table_scope[5:0],
86223 * act_rec_ptr[25:0]}
86224 * - meta_format 2 - tunnel_id - metadata2 = tunnel_id[31:0]
86225 * - meta_format 3 - chdr_data - metadata2 = updated_chdr_data[31:0]
86226 * - meta_format 4 - hdr_offsets - metadata2 = hdr_offsets[31:0]
86242 #define CQ_RES_UD_CFA_V3_TOGGLE UINT32_C(0x1)
86244 #define CQ_RES_UD_CFA_V3_CQE_TYPE_MASK UINT32_C(0x1e)
86252 #define CQ_RES_UD_CFA_V3_CQE_TYPE_RES_UD_CFA_V3 (UINT32_C(0xc) << 1)
86257 #define CQ_RES_UD_CFA_V3_STATUS_OK UINT32_C(0x0)
86264 #define CQ_RES_UD_CFA_V3_STATUS_HW_LOCAL_LENGTH_ERR UINT32_C(0x3)
86274 #define CQ_RES_UD_CFA_V3_STATUS_LOCAL_QP_OPERATION_ERR UINT32_C(0x4)
86284 #define CQ_RES_UD_CFA_V3_STATUS_LOCAL_PROTECTION_ERR UINT32_C(0x5)
86289 #define CQ_RES_UD_CFA_V3_STATUS_WORK_REQUEST_FLUSHED_ERR UINT32_C(0xd)
86295 #define CQ_RES_UD_CFA_V3_STATUS_HW_FLUSH_ERR UINT32_C(0xe)
86301 #define CQ_RES_UD_CFA_V3_STATUS_OVERFLOW_ERR UINT32_C(0xf)
86308 #define CQ_RES_UD_CFA_V3_FLAGS_SRQ UINT32_C(0x1)
86310 #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_RQ UINT32_C(0x0)
86312 #define CQ_RES_UD_CFA_V3_FLAGS_SRQ_SRQ UINT32_C(0x1)
86315 #define CQ_RES_UD_CFA_V3_FLAGS_IMM UINT32_C(0x2)
86316 #define CQ_RES_UD_CFA_V3_FLAGS_UNUSED_MASK UINT32_C(0xc)
86318 #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_MASK UINT32_C(0x30)
86321 #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V1 (UINT32_C(0x0) << 4)
86323 #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV4 (UINT32_C(0x2) << 4)
86325 #define CQ_RES_UD_CFA_V3_FLAGS_ROCE_IP_VER_V2IPV6 (UINT32_C(0x3) << 4)
86328 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_MASK UINT32_C(0x3c0)
86331 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_NONE (UINT32_C(0x0) << 6)
86336 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
86341 * - metadata2[25:0] contains the action record pointer.
86344 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_ACT_REC_PTR (UINT32_C(0x1) << 6)
86349 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
86354 * - VXLAN = VNI[23:0] -> VXLAN Network ID
86355 * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier
86356 * - NVGRE = TNI[23:0] -> Tenant Network ID
86357 * - GRE = KEY[31:0] -> key field with bit mask. zero if K=0
86358 * - IPv4 = 0 (not populated)
86359 * - IPv6 = Flow Label[19:0]
86360 * - PPPoE = sessionID[15:0]
86361 * - MPLs = Outer label[19:0]
86362 * - UPAR = Selected[31:0] with bit mask
86364 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_TUNNEL_ID (UINT32_C(0x2) << 6)
86369 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0],de, vid[11:0]}
86374 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_CHDR_DATA (UINT32_C(0x3) << 6)
86379 * - vtag[19:0] = {valid, tpid_sel[2:0], pri[2:0], de, vid[11:0]}
86384 * - metadata2[8:0] contains the outer_l3_offset.
86389 #define CQ_RES_UD_CFA_V3_FLAGS_META_FORMAT_HDR_OFFSET (UINT32_C(0x4) << 6)
86409 #define NQ_BASE_TYPE_MASK UINT32_C(0x3f)
86410 #define NQ_BASE_TYPE_SFT 0
86412 #define NQ_BASE_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
86414 #define NQ_BASE_TYPE_SRQ_EVENT UINT32_C(0x32)
86416 #define NQ_BASE_TYPE_DBQ_EVENT UINT32_C(0x34)
86418 #define NQ_BASE_TYPE_QP_EVENT UINT32_C(0x38)
86420 #define NQ_BASE_TYPE_FUNC_EVENT UINT32_C(0x3a)
86422 #define NQ_BASE_TYPE_NQ_REASSIGN UINT32_C(0x3c)
86425 #define NQ_BASE_INFO10_MASK UINT32_C(0xffc0)
86436 * will write 1. The odd passes will write 0.
86438 #define NQ_BASE_V UINT32_C(0x1)
86440 #define NQ_BASE_INFO63_MASK UINT32_C(0xfffffffe)
86456 #define NQ_CN_TYPE_MASK UINT32_C(0x3f)
86457 #define NQ_CN_TYPE_SFT 0
86459 #define NQ_CN_TYPE_CQ_NOTIFICATION UINT32_C(0x30)
86472 #define NQ_CN_TOGGLE_MASK UINT32_C(0xc0)
86484 * will write 1. The odd passes will write 0.
86486 #define NQ_CN_V UINT32_C(0x1)
86505 #define NQ_SRQ_EVENT_TYPE_MASK UINT32_C(0x3f)
86506 #define NQ_SRQ_EVENT_TYPE_SFT 0
86508 #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT UINT32_C(0x32)
86515 #define NQ_SRQ_EVENT_TOGGLE_MASK UINT32_C(0xc0)
86523 #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT UINT32_C(0x1)
86536 * will write 1. The odd passes will write 0.
86538 #define NQ_SRQ_EVENT_V UINT32_C(0x1)
86559 #define NQ_DBQ_EVENT_TYPE_MASK UINT32_C(0x3f)
86560 #define NQ_DBQ_EVENT_TYPE_SFT 0
86562 #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT UINT32_C(0x34)
86571 #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT UINT32_C(0x1)
86578 #define NQ_DBQ_EVENT_DB_PFID_MASK UINT32_C(0xf)
86579 #define NQ_DBQ_EVENT_DB_PFID_SFT 0
86585 #define NQ_DBQ_EVENT_DB_DPI_MASK UINT32_C(0xfffff)
86586 #define NQ_DBQ_EVENT_DB_DPI_SFT 0
86591 * will write 1. The odd passes will write 0.
86593 #define NQ_DBQ_EVENT_V UINT32_C(0x1)
86600 #define NQ_DBQ_EVENT_DB_XID_MASK UINT32_C(0xfffff)
86601 #define NQ_DBQ_EVENT_DB_XID_SFT 0
86606 #define NQ_DBQ_EVENT_DB_TYPE_MASK UINT32_C(0xf0000000)
86625 #define NQ_REASSIGN_TYPE_MASK UINT32_C(0x3f)
86626 #define NQ_REASSIGN_TYPE_SFT 0
86628 #define NQ_REASSIGN_TYPE_NQ_REASSIGN UINT32_C(0x3c)
86640 * will write 1. The odd passes will write 0.
86642 #define NQ_REASSIGN_V UINT32_C(0x1)
86656 #define XRRQ_IRRQ_TYPE UINT32_C(0x1)
86658 #define XRRQ_IRRQ_TYPE_READ_REQ UINT32_C(0x0)
86660 #define XRRQ_IRRQ_TYPE_ATOMIC_REQ UINT32_C(0x1)
86667 #define XRRQ_IRRQ_CREDITS_MASK UINT32_C(0xf800)
86673 #define XRRQ_IRRQ_PSN_MASK UINT32_C(0xffffff)
86674 #define XRRQ_IRRQ_PSN_SFT 0
86682 #define XRRQ_IRRQ_MSN_MASK UINT32_C(0xffffff)
86683 #define XRRQ_IRRQ_MSN_SFT 0
86709 #define XRRQ_ORRQ_TYPE UINT32_C(0x1)
86711 #define XRRQ_ORRQ_TYPE_READ_REQ UINT32_C(0x0)
86713 #define XRRQ_ORRQ_TYPE_ATOMIC_REQ UINT32_C(0x1)
86736 #define XRRQ_ORRQ_NUM_SGES_MASK UINT32_C(0xf800)
86746 #define XRRQ_ORRQ_PSN_MASK UINT32_C(0xffffff)
86747 #define XRRQ_ORRQ_PSN_SFT 0
86755 #define XRRQ_ORRQ_END_PSN_MASK UINT32_C(0xffffff)
86756 #define XRRQ_ORRQ_END_PSN_SFT 0
86763 * aligned 0b0000 lsb added to get 64 bit address.
86778 * This field indicates if the PTE is valid. A value of '0'
86783 #define PTU_PTE_VALID UINT32_C(0x1)
86792 #define PTU_PTE_LAST UINT32_C(0x2)
86799 #define PTU_PTE_NEXT_TO_LAST UINT32_C(0x4)
86801 #define PTU_PTE_UNUSED_MASK UINT32_C(0xff8)
86808 #define PTU_PTE_PAGE_MASK UINT32_C(0xfffffffffffff000)L
86818 * This field indicates if the PTE is valid. A value of '0'
86823 #define PTU_PDE_VALID UINT32_C(0x1)
86825 #define PTU_PDE_UNUSED_MASK UINT32_C(0xffe)
86832 #define PTU_PDE_PAGE_MASK UINT32_C(0xfffffffffffff000)L
86838 * format directly to byte offset 0 of the appropriate doorbell page.
86863 #define DBC_DBC_INDEX_MASK UINT32_C(0xffffff)
86864 #define DBC_DBC_INDEX_SFT 0
86873 #define DBC_DBC_EPOCH UINT32_C(0x1000000)
86884 #define DBC_DBC_TOGGLE_MASK UINT32_C(0x6000000)
86896 #define DBC_DBC_XID_MASK UINT32_C(0xfffff)
86897 #define DBC_DBC_XID_SFT 0
86902 #define DBC_DBC_PATH_MASK UINT32_C(0x3000000)
86905 #define DBC_DBC_PATH_ROCE (UINT32_C(0x0) << 24)
86907 #define DBC_DBC_PATH_L2 (UINT32_C(0x1) << 24)
86909 #define DBC_DBC_PATH_ENGINE (UINT32_C(0x2) << 24)
86918 #define DBC_DBC_VALID UINT32_C(0x4000000)
86924 #define DBC_DBC_DEBUG_TRACE UINT32_C(0x8000000)
86926 #define DBC_DBC_TYPE_MASK UINT32_C(0xf0000000)
86934 #define DBC_DBC_TYPE_SQ (UINT32_C(0x0) << 28)
86940 #define DBC_DBC_TYPE_RQ (UINT32_C(0x1) << 28)
86946 #define DBC_DBC_TYPE_SRQ (UINT32_C(0x2) << 28)
86954 #define DBC_DBC_TYPE_SRQ_ARM (UINT32_C(0x3) << 28)
86960 #define DBC_DBC_TYPE_CQ (UINT32_C(0x4) << 28)
86965 #define DBC_DBC_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28)
86971 #define DBC_DBC_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28)
86980 #define DBC_DBC_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28)
86991 #define DBC_DBC_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28)
86999 #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28)
87005 #define DBC_DBC_TYPE_NQ (UINT32_C(0xa) << 28)
87010 #define DBC_DBC_TYPE_NQ_ARM (UINT32_C(0xb) << 28)
87016 #define DBC_DBC_TYPE_NQ_MASK (UINT32_C(0xe) << 28)
87027 #define DBC_DBC_TYPE_NULL (UINT32_C(0xf) << 28)
87048 #define DBC_DBC32_XID_MASK UINT32_C(0xfffff)
87049 #define DBC_DBC32_XID_SFT 0
87054 #define DBC_DBC32_PATH_MASK UINT32_C(0xc00000)
87057 #define DBC_DBC32_PATH_ROCE (UINT32_C(0x0) << 22)
87059 #define DBC_DBC32_PATH_L2 (UINT32_C(0x1) << 22)
87062 * When abs=0, this value is the value to add to the appropriate
87070 #define DBC_DBC32_INCR_MASK UINT32_C(0xf000000)
87073 #define DBC_DBC32_ABS UINT32_C(0x10000000)
87075 #define DBC_DBC32_TYPE_MASK UINT32_C(0xe0000000)
87082 #define DBC_DBC32_TYPE_SQ (UINT32_C(0x0) << 29)
87089 * combine buffer) within doorbell page. WCB#0 = offset 16, WCB#1 =
87120 #define DB_PUSH_START_DB_INDEX_MASK UINT32_C(0xffffff)
87121 #define DB_PUSH_START_DB_INDEX_SFT 0
87127 #define DB_PUSH_START_DB_PI_LO_MASK UINT32_C(0xff000000)
87135 #define DB_PUSH_START_DB_XID_MASK UINT32_C(0xfffff00000000)L
87142 #define DB_PUSH_START_DB_PI_HI_MASK UINT32_C(0xf0000000000000)L
87145 #define DB_PUSH_START_DB_TYPE_MASK UINT32_C(0xf000000000000000)L
87152 #define DB_PUSH_START_DB_TYPE_PUSH_START (UINT32_C(0xc)L << 60)
87158 #define DB_PUSH_START_DB_TYPE_PUSH_END (UINT32_C(0xd)L << 60)
87165 * buffer) within doorbell page. WCB#0 = offset 16, WCB#1 = offset 24,
87199 #define DB_PUSH_END_DB_INDEX_MASK UINT32_C(0xffffff)
87200 #define DB_PUSH_END_DB_INDEX_SFT 0
87206 #define DB_PUSH_END_DB_PI_LO_MASK UINT32_C(0xff000000)
87214 #define DB_PUSH_END_DB_XID_MASK UINT32_C(0xfffff00000000)L
87221 #define DB_PUSH_END_DB_PI_HI_MASK UINT32_C(0xf0000000000000)L
87227 #define DB_PUSH_END_DB_PATH_MASK UINT32_C(0x300000000000000)L
87230 #define DB_PUSH_END_DB_PATH_ROCE (UINT32_C(0x0)L << 56)
87232 #define DB_PUSH_END_DB_PATH_L2 (UINT32_C(0x1)L << 56)
87234 #define DB_PUSH_END_DB_PATH_ENGINE (UINT32_C(0x2)L << 56)
87241 #define DB_PUSH_END_DB_DEBUG_TRACE UINT32_C(0x800000000000000)L
87243 #define DB_PUSH_END_DB_TYPE_MASK UINT32_C(0xf000000000000000)L
87250 #define DB_PUSH_END_DB_TYPE_PUSH_START (UINT32_C(0xc)L << 60)
87256 #define DB_PUSH_END_DB_TYPE_PUSH_END (UINT32_C(0xd)L << 60)
87272 * push_index should be written to 0. The push_index should point
87281 #define DB_PUSH_INFO_PUSH_INDEX_MASK UINT32_C(0xffffff)
87282 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0
87285 * 0 means 256B size of push. The push write is done in 8B units
87291 #define DB_PUSH_INFO_PUSH_SIZE_MASK UINT32_C(0x1f000000)
87298 * message format directly to byte offset 0xC of the appropriate
87342 #define DBC_ABSOLUTE_DB_32_INDEX_MASK UINT32_C(0xffff)
87343 #define DBC_ABSOLUTE_DB_32_INDEX_SFT 0
87352 #define DBC_ABSOLUTE_DB_32_EPOCH UINT32_C(0x10000)
87363 #define DBC_ABSOLUTE_DB_32_TOGGLE_MASK UINT32_C(0x60000)
87373 #define DBC_ABSOLUTE_DB_32_MXID_MASK UINT32_C(0x1f80000)
87379 #define DBC_ABSOLUTE_DB_32_PATH_MASK UINT32_C(0x6000000)
87382 #define DBC_ABSOLUTE_DB_32_PATH_ROCE (UINT32_C(0x0) << 25)
87384 #define DBC_ABSOLUTE_DB_32_PATH_L2 (UINT32_C(0x1) << 25)
87393 #define DBC_ABSOLUTE_DB_32_VALID UINT32_C(0x8000000)
87395 #define DBC_ABSOLUTE_DB_32_TYPE_MASK UINT32_C(0xf0000000)
87403 #define DBC_ABSOLUTE_DB_32_TYPE_SQ (UINT32_C(0x0) << 28)
87409 #define DBC_ABSOLUTE_DB_32_TYPE_RQ (UINT32_C(0x1) << 28)
87415 #define DBC_ABSOLUTE_DB_32_TYPE_SRQ (UINT32_C(0x2) << 28)
87423 #define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARM (UINT32_C(0x3) << 28)
87429 #define DBC_ABSOLUTE_DB_32_TYPE_CQ (UINT32_C(0x4) << 28)
87434 #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28)
87440 #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28)
87450 #define DBC_ABSOLUTE_DB_32_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28)
87461 #define DBC_ABSOLUTE_DB_32_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28)
87467 #define DBC_ABSOLUTE_DB_32_TYPE_NQ (UINT32_C(0xa) << 28)
87472 #define DBC_ABSOLUTE_DB_32_TYPE_NQ_ARM (UINT32_C(0xb) << 28)
87478 #define DBC_ABSOLUTE_DB_32_TYPE_NQ_MASK (UINT32_C(0xe) << 28)
87489 #define DBC_ABSOLUTE_DB_32_TYPE_NULL (UINT32_C(0xf) << 28)
87513 #define DBC_RELATIVE_DB_32_XID_MASK UINT32_C(0xfffff)
87514 #define DBC_RELATIVE_DB_32_XID_SFT 0
87519 #define DBC_RELATIVE_DB_32_PATH_MASK UINT32_C(0xc00000)
87522 #define DBC_RELATIVE_DB_32_PATH_ROCE (UINT32_C(0x0) << 22)
87524 #define DBC_RELATIVE_DB_32_PATH_L2 (UINT32_C(0x1) << 22)
87533 #define DBC_RELATIVE_DB_32_INCR_MASK UINT32_C(0x1f000000)
87536 #define DBC_RELATIVE_DB_32_TYPE_MASK UINT32_C(0xe0000000)
87544 #define DBC_RELATIVE_DB_32_TYPE_SQ (UINT32_C(0x0) << 29)
87550 #define DBC_RELATIVE_DB_32_TYPE_SRQ (UINT32_C(0x1) << 29)
87556 #define DBC_RELATIVE_DB_32_TYPE_CQ (UINT32_C(0x2) << 29)
87562 #define DBC_RELATIVE_DB_32_TYPE_CQ_ARMALL (UINT32_C(0x3) << 29)
87568 #define DBC_RELATIVE_DB_32_TYPE_NQ (UINT32_C(0x4) << 29)
87573 #define DBC_RELATIVE_DB_32_TYPE_NQ_ARM (UINT32_C(0x5) << 29)
87579 #define DBC_RELATIVE_DB_32_TYPE_NQ_MASK (UINT32_C(0x6) << 29)
87598 #define DBC_DRK_VALID UINT32_C(0x1)
87600 #define DBC_DRK_LAST UINT32_C(0x2)
87602 #define DBC_DRK_LINKED UINT32_C(0x4)
87607 #define DBC_DRK_DB_FORMAT UINT32_C(0x8)
87609 #define DBC_DRK_DB_FORMAT_B64 (UINT32_C(0x0) << 3)
87615 #define DBC_DRK_DB_FORMAT_B32A (UINT32_C(0x1) << 3)
87622 #define DBC_DRK_STRIDE_MASK UINT32_C(0x300)
87629 #define DBC_DRK_STRIDE_OFF (UINT32_C(0x0) << 8)
87636 #define DBC_DRK_STRIDE_SZ64 (UINT32_C(0x1) << 8)
87643 #define DBC_DRK_STRIDE_SZ128 (UINT32_C(0x2) << 8)
87649 #define DBC_DRK_SIZE_MASK UINT32_C(0xc00)
87652 #define DBC_DRK_SIZE_FOUR (UINT32_C(0x0) << 10)
87654 #define DBC_DRK_SIZE_ONE (UINT32_C(0x1) << 10)
87656 #define DBC_DRK_SIZE_TWO (UINT32_C(0x2) << 10)
87658 #define DBC_DRK_SIZE_THREE (UINT32_C(0x3) << 10)
87670 #define DBC_DRK_PI_MASK UINT32_C(0xffff)
87671 #define DBC_DRK_PI_SFT 0
87673 * It is the application memory page(4KB) pointer when linked = 0.
87684 * format directly to byte offset 0 of the appropriate doorbell page.
87715 #define DBC_DBC_V3_INDEX_MASK UINT32_C(0xffffff)
87716 #define DBC_DBC_V3_INDEX_SFT 0
87725 #define DBC_DBC_V3_EPOCH UINT32_C(0x1000000)
87736 #define DBC_DBC_V3_TOGGLE_MASK UINT32_C(0x6000000)
87749 #define DBC_DBC_V3_XID_MASK UINT32_C(0xfff)
87750 #define DBC_DBC_V3_XID_SFT 0
87755 #define DBC_DBC_V3_PATH_MASK UINT32_C(0x3000000)
87758 #define DBC_DBC_V3_PATH_ROCE (UINT32_C(0x0) << 24)
87760 #define DBC_DBC_V3_PATH_L2 (UINT32_C(0x1) << 24)
87769 #define DBC_DBC_V3_VALID UINT32_C(0x4000000)
87775 #define DBC_DBC_V3_DEBUG_TRACE UINT32_C(0x8000000)
87777 #define DBC_DBC_V3_TYPE_MASK UINT32_C(0xf0000000)
87784 #define DBC_DBC_V3_TYPE_SQ (UINT32_C(0x0) << 28)
87790 #define DBC_DBC_V3_TYPE_RQ (UINT32_C(0x1) << 28)
87796 #define DBC_DBC_V3_TYPE_SRQ (UINT32_C(0x2) << 28)
87805 #define DBC_DBC_V3_TYPE_SRQ_ARM (UINT32_C(0x3) << 28)
87816 #define DBC_DBC_V3_TYPE_CQ (UINT32_C(0x4) << 28)
87827 #define DBC_DBC_V3_TYPE_CQ_ARMSE (UINT32_C(0x5) << 28)
87838 #define DBC_DBC_V3_TYPE_CQ_ARMALL (UINT32_C(0x6) << 28)
87849 #define DBC_DBC_V3_TYPE_CQ_ARMENA (UINT32_C(0x7) << 28)
87860 #define DBC_DBC_V3_TYPE_SRQ_ARMENA (UINT32_C(0x8) << 28)
87871 #define DBC_DBC_V3_TYPE_CQ_CUTOFF_ACK (UINT32_C(0x9) << 28)
87890 #define DBC_DBC_V3_TYPE_NQ (UINT32_C(0xa) << 28)
87897 #define DBC_DBC_V3_TYPE_NQ_ARM (UINT32_C(0xb) << 28)
87916 #define DBC_DBC_V3_TYPE_CQ_REASSIGN (UINT32_C(0xc) << 28)
87923 #define DBC_DBC_V3_TYPE_NQ_MASK (UINT32_C(0xe) << 28)
87931 #define DBC_DBC_V3_TYPE_NULL (UINT32_C(0xf) << 28)
87937 * message format directly to offset 0x40 of the appropriate doorbell
87960 #define DBC_XP_XID_MASK UINT32_C(0xfff)
87961 #define DBC_XP_XID_SFT 0
87967 #define DBC_XP_DEBUG_TRACE UINT32_C(0x1000000)
87969 #define DBC_XP_TYPE_MASK UINT32_C(0xf0000000)
87977 #define DBC_XP_TYPE_SQ (UINT32_C(0x0) << 28)
87983 #define DBC_XP_TYPE_RQ (UINT32_C(0x1) << 28)
87989 #define DBC_XP_TYPE_SRQ (UINT32_C(0x2) << 28)
88012 * A value below 0x8000 is an indication that the firmware is still
88016 * > 0x0000 to 0x00FF : SBL state information
88017 * > 0x0200 to 0x02FF : SBI state information
88018 * > 0x0400 to 0x04FF : SRT state information
88019 * > 0x0600 to 0x06FF : CRT/CHIMP state information
88020 * > 0x0800 to 0x08FF : External Firmware state information
88021 * > 0x0A00 to 0x0FFF : Reserved for future fw functionality
88023 * A value of 0x8000 indicates firmware is ready and healthy. The
88026 * A value over 0x8000 is an indication that the firmware has
88032 * > 0x81XX - 0xBFXX : 63 ASIC blocks
88033 * > 0xC0XX to 0xFDXX : 62 Firmware modules
88034 * > 0xFE00 to 0xFEFF : External firmware module
88035 * > 0xFFXX : Reserved for future
88037 #define FW_STATUS_REG_CODE_MASK UINT32_C(0xffff)
88038 #define FW_STATUS_REG_CODE_SFT 0
88040 #define FW_STATUS_REG_CODE_READY UINT32_C(0x8000)
88051 #define FW_STATUS_REG_IMAGE_DEGRADED UINT32_C(0x10000)
88060 * is greater than 0x8000 (32768 decimal).
88062 #define FW_STATUS_REG_RECOVERABLE UINT32_C(0x20000)
88071 * greater than 0x8000 (32768 decimal).
88073 #define FW_STATUS_REG_CRASHDUMP_ONGOING UINT32_C(0x40000)
88080 * code field is greater than 0x8000 (32768 decimal).
88082 #define FW_STATUS_REG_CRASHDUMP_COMPLETE UINT32_C(0x80000)
88091 * 0x8000 (32768 decimal).
88093 #define FW_STATUS_REG_SHUTDOWN UINT32_C(0x100000)
88100 * than 0x8000 (32768 decimal).
88102 #define FW_STATUS_REG_CRASHED_NO_MASTER UINT32_C(0x200000)
88107 * This bit is valid only when the code field is greater than 0x8000
88110 #define FW_STATUS_REG_RECOVERING UINT32_C(0x400000)
88115 #define FW_STATUS_REG_MANU_DEBUG_STATUS UINT32_C(0x800000)
88120 * offset: 0x31001F0). Host software is expected to read from this
88133 #define HCOMM_STATUS_VER_MASK UINT32_C(0xff)
88134 #define HCOMM_STATUS_VER_SFT 0
88135 #define HCOMM_STATUS_VER_LATEST UINT32_C(0x1)
88141 #define HCOMM_STATUS_SIGNATURE_MASK UINT32_C(0xffffff00)
88143 #define HCOMM_STATUS_SIGNATURE_VAL (UINT32_C(0x484353) << 8)
88146 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK UINT32_C(0x3)
88147 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0
88149 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG UINT32_C(0x0)
88151 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC UINT32_C(0x1)
88153 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 UINT32_C(0x2)
88155 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 UINT32_C(0x3)
88161 #define HCOMM_STATUS_TRUE_OFFSET_MASK UINT32_C(0xfffffffc)
88166 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL
88191 * * 0x0-0xFFF8 - The function ID
88192 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
88193 * * 0xFFFD - Reserved for user-space HWRM interface
88194 * * 0xFFFF - HWRM
88225 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_NVM_TEST UINT32_C(0x1)
88227 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_LINK_TEST UINT32_C(0x2)
88229 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_REGISTER_TEST UINT32_C(0x4)
88231 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_MEMORY_TEST UINT32_C(0x8)
88233 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
88235 #define HWRM_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
88238 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_NVM_TEST UINT32_C(0x1)
88240 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_LINK_TEST UINT32_C(0x2)
88242 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_REGISTER_TEST UINT32_C(0x4)
88244 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_MEMORY_TEST UINT32_C(0x8)
88246 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
88248 #define HWRM_SELFTEST_QLIST_OUTPUT_OFFLINE_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
88268 #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED UINT32_C(0x0)
88270 #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED UINT32_C(0x1)
88272 #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED UINT32_C(0x2)
88274 #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED UINT32_C(0x3)
88276 #define HWRM_SELFTEST_QLIST_OUTPUT_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED UINT32_C(0x4)
88312 * * 0x0-0xFFF8 - The function ID
88313 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
88314 * * 0xFFFD - Reserved for user-space HWRM interface
88315 * * 0xFFFF - HWRM
88328 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_NVM_TEST UINT32_C(0x1)
88330 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_LINK_TEST UINT32_C(0x2)
88332 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_REGISTER_TEST UINT32_C(0x4)
88334 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_MEMORY_TEST UINT32_C(0x8)
88336 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10)
88338 #define HWRM_SELFTEST_EXEC_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20)
88356 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_NVM_TEST UINT32_C(0x1)
88358 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_LINK_TEST UINT32_C(0x2)
88360 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_REGISTER_TEST UINT32_C(0x4)
88362 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_MEMORY_TEST UINT32_C(0x8)
88364 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PCIE_SERDES_TEST UINT32_C(0x10)
88366 #define HWRM_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_ETHERNET_SERDES_TEST UINT32_C(0x20)
88370 * failed(0).
88377 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_NVM_TEST UINT32_C(0x1)
88382 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_LINK_TEST UINT32_C(0x2)
88387 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_REGISTER_TEST UINT32_C(0x4)
88392 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_MEMORY_TEST UINT32_C(0x8)
88397 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PCIE_SERDES_TEST UINT32_C(0x10)
88402 #define HWRM_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_ETHERNET_SERDES_TEST UINT32_C(0x20)
88437 * * 0x0-0xFFF8 - The function ID
88438 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
88439 * * 0xFFFD - Reserved for user-space HWRM interface
88440 * * 0xFFFF - HWRM
88497 * * 0x0-0xFFF8 - The function ID
88498 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
88499 * * 0xFFFD - Reserved for user-space HWRM interface
88500 * * 0xFFFF - HWRM
88514 * copying the data to the host from. This should be set to 0 on the
88530 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_MASK UINT32_C(0x7)
88531 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_UNUSED_TEST_SFT 0
88533 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_EYE_PROJECTION UINT32_C(0x8)
88535 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_PCIE_SERDES_TEST UINT32_C(0x10)
88537 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_FLAGS_ETHERNET_SERDES_TEST UINT32_C(0x20)
88543 * Valid values from 0 to 16.
88545 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PCIE_LANE_NO_MASK UINT32_C(0xf)
88546 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PCIE_LANE_NO_SFT 0
88548 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION UINT32_C(0x10)
88549 /* Value 0 indicates Horizontal plot request. */
88550 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_HORIZONTAL (UINT32_C(0x0) << 4)
88552 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_DIRECTION_VERTICAL (UINT32_C(0x1) << 4)
88555 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE UINT32_C(0x20)
88557 * Value 0 indicates left/top projection in horizontal/vertical
88560 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_LEFT_TOP (UINT32_C(0x0) << 5)
88566 …#define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_PROJ_TYPE_RIGHT_BOTTOM (UINT32_C(0x1) <<…
88569 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_OPTIONS_RSVD_MASK UINT32_C(0xc0)
88577 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E8 UINT32_C(0x0)
88579 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E9 UINT32_C(0x1)
88581 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E10 UINT32_C(0x2)
88583 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E11 UINT32_C(0x3)
88585 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_TARGETBER_BER_1E12 UINT32_C(0x4)
88593 * Value 0 indicates that collection of the eyescope should be
88597 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_SYNCHRONOUS UINT32_C(0x0)
88602 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_START UINT32_C(0x1)
88607 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_PROGRESS UINT32_C(0x2)
88613 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_INPUT_ACTION_STOP UINT32_C(0x3)
88641 * current eyescope operation in tenths of a percentage. 0 (0.0) to
88652 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE UINT32_C(0x1)
88654 * Value 0 indicates that bit_count value is a raw total
88657 …efine HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_TOTAL UINT32_C(0x0)
88663 …efine HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_BIT_COUNT_TYPE_BIT_COUNT_POW2 UINT32_C(0x1)
88666 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA_OUTPUT_FLAGS_RSVD_MASK UINT32_C(0xfe)
88709 * * 0x0-0xFFF8 - The function ID
88710 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
88711 * * 0xFFFD - Reserved for user-space HWRM interface
88712 * * 0xFFFF - HWRM
88723 * This field indicates the lock/unlock operation. 0 means Unlock and
88775 * * 0x0-0xFFF8 - The function ID
88776 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
88777 * * 0xFFFD - Reserved for user-space HWRM interface
88778 * * 0xFFFF - HWRM
88804 * The value can wrap around. On error, a value of 0 on all ticks
88810 * The value can wrap around. On error, a value of 0 on all ticks
88816 * The value can wrap around. On error, a value of 0 on all ticks
88854 * * 0x0-0xFFF8 - The function ID
88855 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
88856 * * 0xFFFD - Reserved for user-space HWRM interface
88857 * * 0xFFFF - HWRM
88872 #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_CRID UINT32_C(0x1)
88877 #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_SRT_REV_ID UINT32_C(0x2)
88882 #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_CRT_REV_ID UINT32_C(0x4)
88887 #define HWRM_MFG_OTP_CFG_INPUT_ENABLES_SBI_REV_ID UINT32_C(0x8)
88944 * * 0x0-0xFFF8 - The function ID
88945 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
88946 * * 0xFFFD - Reserved for user-space HWRM interface
88947 * * 0xFFFF - HWRM
88962 #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_CRID UINT32_C(0x1)
88967 #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_SRT_REV_ID UINT32_C(0x2)
88972 #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_CRT_REV_ID UINT32_C(0x4)
88977 #define HWRM_MFG_OTP_QCFG_INPUT_ENABLES_SBI_REV_ID UINT32_C(0x8)
89039 * * 0x0-0xFFF8 - The function ID
89040 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89041 * * 0xFFFD - Reserved for user-space HWRM interface
89042 * * 0xFFFF - HWRM
89068 #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_INCREMENTAL UINT32_C(0x1)
89070 #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_FIXED UINT32_C(0x2)
89072 #define HWRM_MFG_HDMA_TEST_INPUT_SUBTYPE_RANDOM UINT32_C(0x3)
89123 * * 0x0-0xFFF8 - The function ID
89124 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89125 * * 0xFFFD - Reserved for user-space HWRM interface
89126 * * 0xFFFF - HWRM
89142 /* i2c slave address. If set to 0xffff, fw will decide what to use. */
89199 * * 0x0-0xFFF8 - The function ID
89200 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89201 * * 0xFFFD - Reserved for user-space HWRM interface
89202 * * 0xFFFF - HWRM
89218 /* i2c slave address. If set to 0xffff, fw will decide what to use. */
89279 * * 0x0-0xFFF8 - The function ID
89280 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89281 * * 0xFFFD - Reserved for user-space HWRM interface
89282 * * 0xFFFF - HWRM
89331 * field is optional. When set to 0, the SoC will determine the
89340 #define HWRM_MFG_SOC_IMAGE_INPUT_FLAGS_START UINT32_C(0x1)
89345 #define HWRM_MFG_SOC_IMAGE_INPUT_FLAGS_END UINT32_C(0x2)
89351 * shall increment this number by 1. The value 0 is used when
89405 * * 0x0-0xFFF8 - The function ID
89406 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89407 * * 0xFFFD - Reserved for user-space HWRM interface
89408 * * 0xFFFF - HWRM
89501 * * 0x0-0xFFF8 - The function ID
89502 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89503 * * 0xFFFD - Reserved for user-space HWRM interface
89504 * * 0xFFFF - HWRM
89519 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_INPUT_FLAGS_FORCE UINT32_C(0x1)
89539 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_ALREADY_LOCKED UINT32_C(0x1)
89541 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_NOT_EMPTY UINT32_C(0x2)
89543 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_MISSING_FACT_CFG UINT32_C(0x4)
89545 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE_OUTPUT_ERROR_STATUS_MISSING_VPD UINT32_C(0x8)
89580 * * 0x0-0xFFF8 - The function ID
89581 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89582 * * 0xFFFD - Reserved for user-space HWRM interface
89583 * * 0xFFFF - HWRM
89657 * * 0x0-0xFFF8 - The function ID
89658 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89659 * * 0xFFFD - Reserved for user-space HWRM interface
89660 * * 0xFFFF - HWRM
89686 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_IS_EMPTY UINT32_C(0x1)
89688 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_CHECKSUM_FAIL UINT32_C(0x2)
89690 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_MALFORMED_DATA UINT32_C(0x4)
89692 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH_OUTPUT_HEALTH_STATUS_NOT_LOCKED UINT32_C(0x8)
89728 * * 0x0-0xFFF8 - The function ID
89729 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89730 * * 0xFFFD - Reserved for user-space HWRM interface
89731 * * 0xFFFF - HWRM
89746 /* Provisioning slot number. 0-indexed. */
89758 #define HWRM_MFG_PRVSN_EXPORT_CSR_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1)
89773 /* Provisioning slot number. 0-indexed. */
89799 #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
89801 #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1)
89803 #define HWRM_MFG_PRVSN_EXPORT_CSR_CMD_ERR_CODE_BUFFER_LENGTH UINT32_C(0x2)
89831 * * 0x0-0xFFF8 - The function ID
89832 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89833 * * 0xFFFD - Reserved for user-space HWRM interface
89834 * * 0xFFFF - HWRM
89849 /* Provisioning slot number. 0-indexed. */
89861 #define HWRM_MFG_PRVSN_IMPORT_CERT_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1)
89876 /* Provisioning slot number. 0-indexed. */
89881 #define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_NOT_PROVISIONED UINT32_C(0x0)
89883 #define HWRM_MFG_PRVSN_IMPORT_CERT_OUTPUT_STATE_PROVISIONED UINT32_C(0x1)
89906 #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
89908 #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1)
89910 #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_SLOT_LOCKED UINT32_C(0x2)
89912 #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_STORAGE UINT32_C(0x3)
89914 #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_CERT_VERIFY_FAIL UINT32_C(0x4)
89916 #define HWRM_MFG_PRVSN_IMPORT_CERT_CMD_ERR_CODE_NO_SIGNED_DEVICE_CERT UINT32_C(0x5)
89944 * * 0x0-0xFFF8 - The function ID
89945 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
89946 * * 0xFFFD - Reserved for user-space HWRM interface
89947 * * 0xFFFF - HWRM
89978 #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_INVALID UINT32_C(0x0)
89980 #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_SPDM UINT32_C(0x1)
89982 #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_CERBERUS UINT32_C(0x2)
89984 #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_GET_STATE_VALID_NONE UINT32_C(0xff)
89990 * The slot_status field is undetermined if get_state_valid = 0.
89994 #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_MASK UINT32_C(0xff)
89995 #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_SFT 0
89997 #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_NOT_PROVISIONED UINT32_C(0x0)
90002 #define HWRM_MFG_PRVSN_GET_STATE_OUTPUT_SLOT_STATUS_SLOT_N_PROVISIONED UINT32_C(0x1)
90039 * * 0x0-0xFFF8 - The function ID
90040 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90041 * * 0xFFFD - Reserved for user-space HWRM interface
90042 * * 0xFFFF - HWRM
90057 /* Provisioning slot number. 0-indexed. */
90069 #define HWRM_MFG_PRVSN_EXPORT_CERT_INPUT_FLAGS_SECURE_SOC_SUPPORT UINT32_C(0x1)
90084 /* Provisioning slot number. 0-indexed. */
90090 * return a successful response with cert_len equal to 0.
90114 #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
90116 #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_SLOT_INVALID UINT32_C(0x1)
90121 #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_CERT_INVALID UINT32_C(0x2)
90123 #define HWRM_MFG_PRVSN_EXPORT_CERT_CMD_ERR_CODE_BUFFER_LENGTH UINT32_C(0x3)
90151 * * 0x0-0xFFF8 - The function ID
90152 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90153 * * 0xFFFD - Reserved for user-space HWRM interface
90154 * * 0xFFFF - HWRM
90184 #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_INVALID UINT32_C(0x0)
90186 #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_HASH_STATE_VALID UINT32_C(0x1)
90194 #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_BOOTUP UINT32_C(0x0)
90196 #define HWRM_MFG_GET_NVM_MEASUREMENT_OUTPUT_CALC_TIME_LIVE UINT32_C(0x1)
90236 * * 0x0-0xFFF8 - The function ID
90237 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90238 * * 0xFFFD - Reserved for user-space HWRM interface
90239 * * 0xFFFF - HWRM
90266 /* PBL version info. Start at 0, roll if change in structure */
90327 * * 0x0-0xFFF8 - The function ID
90328 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90329 * * 0xFFFD - Reserved for user-space HWRM interface
90330 * * 0xFFFF - HWRM
90364 #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_AVAILABLE_TESTS_PERIPHERAL_TEST UINT32_C(0x1)
90376 #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_CO_CPU_MEMORY UINT32_C(0x1)
90378 #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_DPLL_EEPROM UINT32_C(0x2)
90380 #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_DPLL_MMCX UINT32_C(0x4)
90382 #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_GNSS UINT32_C(0x8)
90384 #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_CO_CPU_PCIE UINT32_C(0x10)
90386 #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_INTERNAL_FABRIC UINT32_C(0x20)
90388 #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_OCXO UINT32_C(0x40)
90390 #define HWRM_MFG_SELFTEST_QLIST_OUTPUT_PERIPHERAL_TESTS_TELECOM_PLL UINT32_C(0x80)
90425 * * 0x0-0xFFF8 - The function ID
90426 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90427 * * 0xFFFD - Reserved for user-space HWRM interface
90428 * * 0xFFFF - HWRM
90444 #define HWRM_MFG_SELFTEST_EXEC_INPUT_FLAGS_PERIPHERAL_TEST UINT32_C(0x1)
90452 #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_CO_CPU_MEMORY UINT32_C(0x1)
90454 #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_DPLL_EEPROM UINT32_C(0x2)
90456 #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_DPLL_MMCX UINT32_C(0x4)
90458 #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_GNSS UINT32_C(0x8)
90460 #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_CO_CPU_PCIE UINT32_C(0x10)
90462 #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_INTERNAL_FABRIC UINT32_C(0x20)
90464 #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_OCXO UINT32_C(0x40)
90466 #define HWRM_MFG_SELFTEST_EXEC_INPUT_PERIPHERAL_TESTS_TELECOM_PLL UINT32_C(0x80)
90483 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_REQUESTED_TESTS_PERIPHERAL_TEST UINT32_C(0x1)
90487 * failed(0).
90494 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_TEST_SUCCESS_PERIPHERAL_TEST UINT32_C(0x1)
90503 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_CO_CPU_MEMORY UINT32_C(0x1)
90505 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_DPLL_EEPROM UINT32_C(0x2)
90507 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_DPLL_MMCX UINT32_C(0x4)
90509 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_GNSS UINT32_C(0x8)
90511 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_CO_CPU_PCIE UINT32_C(0x10)
90513 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_INTERNAL_FABRIC UINT32_C(0x20)
90515 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_OCXO UINT32_C(0x40)
90517 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_REQUESTED_TESTS_TELECOM_PLL UINT32_C(0x80)
90525 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_CO_CPU_MEMORY UINT32_C(0x1)
90527 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_DPLL_EEPROM UINT32_C(0x2)
90529 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_DPLL_MMCX UINT32_C(0x4)
90531 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_GNSS UINT32_C(0x8)
90533 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_CO_CPU_PCIE UINT32_C(0x10)
90535 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_INTERNAL_FABRIC UINT32_C(0x20)
90540 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_OCXO UINT32_C(0x40)
90542 #define HWRM_MFG_SELFTEST_EXEC_OUTPUT_PERIPHERAL_TESTS_SUCCESS_TELECOM_PLL UINT32_C(0x80)
90577 * * 0x0-0xFFF8 - The function ID
90578 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90579 * * 0xFFFD - Reserved for user-space HWRM interface
90580 * * 0xFFFF - HWRM
90592 * to 0x14e4 when used for Broadcom internal use when
90599 #define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_INVALID UINT32_C(0x0)
90601 #define HWRM_OEM_CMD_INPUT_NAMING_AUTHORITY_PCI_SIG UINT32_C(0x1)
90606 #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_INVALID UINT32_C(0x0)
90608 #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_TRUFLOW UINT32_C(0x1)
90610 #define HWRM_OEM_CMD_INPUT_MESSAGE_FAMILY_ROCE UINT32_C(0x2)
90671 * * 0x0-0xFFF8 - The function ID
90672 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90673 * * 0xFFFD - Reserved for user-space HWRM interface
90674 * * 0xFFFF - HWRM
90724 * * 0x0-0xFFF8 - The function ID
90725 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90726 * * 0xFFFD - Reserved for user-space HWRM interface
90727 * * 0xFFFF - HWRM
90766 #define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_DESTINATION UINT32_C(0x0)
90768 #define HWRM_UDCC_QCAPS_OUTPUT_SESSION_TYPE_PER_QP UINT32_C(0x1)
90818 * * 0x0-0xFFF8 - The function ID
90819 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90820 * * 0xFFFD - Reserved for user-space HWRM interface
90821 * * 0xFFFF - HWRM
90836 #define HWRM_UDCC_CFG_INPUT_ENABLES_UDCC_MODE UINT32_C(0x1)
90840 #define HWRM_UDCC_CFG_INPUT_UDCC_MODE_DISABLED UINT32_C(0x0)
90842 #define HWRM_UDCC_CFG_INPUT_UDCC_MODE_ENABLED UINT32_C(0x1)
90892 * * 0x0-0xFFF8 - The function ID
90893 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90894 * * 0xFFFD - Reserved for user-space HWRM interface
90895 * * 0xFFFF - HWRM
90954 * * 0x0-0xFFF8 - The function ID
90955 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
90956 * * 0xFFFD - Reserved for user-space HWRM interface
90957 * * 0xFFFF - HWRM
90969 #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_SESSION_STATE UINT32_C(0x1)
90971 #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_DEST_MAC UINT32_C(0x2)
90973 #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_SRC_MAC UINT32_C(0x4)
90975 #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_TX_STATS_RECORD UINT32_C(0x8)
90977 #define HWRM_UDCC_SESSION_CFG_INPUT_ENABLES_RX_STATS_RECORD UINT32_C(0x10)
90985 #define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_ENABLED UINT32_C(0x1)
90987 #define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_FLOW_NOT_CREATED UINT32_C(0x2)
90989 #define HWRM_UDCC_SESSION_CFG_INPUT_SESSION_STATE_FLOW_HAS_BEEN_DELETED UINT32_C(0x4)
91056 * * 0x0-0xFFF8 - The function ID
91057 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91058 * * 0xFFFD - Reserved for user-space HWRM interface
91059 * * 0xFFFF - HWRM
91092 #define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_ENABLED UINT32_C(0x1)
91094 #define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_FLOW_NOT_CREATED UINT32_C(0x2)
91096 #define HWRM_UDCC_SESSION_QCFG_OUTPUT_SESSION_STATE_FLOW_HAS_BEEN_DELETED UINT32_C(0x4)
91157 * * 0x0-0xFFF8 - The function ID
91158 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91159 * * 0xFFFD - Reserved for user-space HWRM interface
91160 * * 0xFFFF - HWRM
91265 * * 0x0-0xFFF8 - The function ID
91266 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91267 * * 0xFFFD - Reserved for user-space HWRM interface
91268 * * 0xFFFF - HWRM
91352 * * 0x0-0xFFF8 - The function ID
91353 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91354 * * 0xFFFD - Reserved for user-space HWRM interface
91355 * * 0xFFFF - HWRM
91445 * * 0x0-0xFFF8 - The function ID
91446 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
91447 * * 0xFFFD - Reserved for user-space HWRM interface
91448 * * 0xFFFF - HWRM