Lines Matching +full:0 +full:x1f8
47 #define SIBA_ENUM_SIZE 0x00100000 /**< size of the enumeration space */
64 * [0x0000-0x0dff] core registers
65 * [0x0e00-0x0eff] SIBA_R1 registers (sonics >= 2.3)
66 * [0x0f00-0x0fff] SIBA_R0 registers
69 #define SIBA_CFG0_OFFSET 0xf00 /**< first configuration block */
70 #define SIBA_CFG1_OFFSET 0xe00 /**< second configuration block (sonics >= 2.3) */
71 #define SIBA_CFG_SIZE 0x100 /**< cfg register block size */
83 #define SIBA_CFG0_IPSFLAG 0x08 /**< initiator port ocp slave flag */
84 #define SIBA_CFG0_TPSFLAG 0x18 /**< target port ocp slave flag */
85 #define SIBA_CFG0_TMERRLOGA 0x48 /**< sonics >= 2.3 */
86 #define SIBA_CFG0_TMERRLOG 0x50 /**< sonics >= 2.3 */
87 #define SIBA_CFG0_ADMATCH3 0x60 /**< address match3 */
88 #define SIBA_CFG0_ADMATCH2 0x68 /**< address match2 */
89 #define SIBA_CFG0_ADMATCH1 0x70 /**< address match1 */
90 #define SIBA_CFG0_IMSTATE 0x90 /**< initiator agent state */
91 #define SIBA_CFG0_INTVEC 0x94 /**< interrupt mask */
92 #define SIBA_CFG0_TMSTATELOW 0x98 /**< target state */
93 #define SIBA_CFG0_TMSTATEHIGH 0x9c /**< target state */
94 #define SIBA_CFG0_BWA0 0xa0 /**< bandwidth allocation table0 */
95 #define SIBA_CFG0_IMCONFIGLOW 0xa8 /**< initiator configuration */
96 #define SIBA_CFG0_IMCONFIGHIGH 0xac /**< initiator configuration */
97 #define SIBA_CFG0_ADMATCH0 0xb0 /**< address match0 */
98 #define SIBA_CFG0_TMCONFIGLOW 0xb8 /**< target configuration */
99 #define SIBA_CFG0_TMCONFIGHIGH 0xbc /**< target configuration */
100 #define SIBA_CFG0_BCONFIG 0xc0 /**< broadcast configuration */
101 #define SIBA_CFG0_BSTATE 0xc8 /**< broadcast state */
102 #define SIBA_CFG0_ACTCNFG 0xd8 /**< activate configuration */
103 #define SIBA_CFG0_FLAGST 0xe8 /**< current sbflags */
104 #define SIBA_CFG0_IDLOW 0xf8 /**< identification */
105 #define SIBA_CFG0_IDHIGH 0xfc /**< identification */
108 #define SIBA_CFG1_IMERRLOGA 0xa8 /**< (sonics >= 2.3) */
109 #define SIBA_CFG1_IMERRLOG 0xb0 /**< sbtmerrlog (sonics >= 2.3) */
110 #define SIBA_CFG1_TMPORTCONNID0 0xd8 /**< sonics >= 2.3 */
111 #define SIBA_CFG1_TMPORTLOCK0 0xf8 /**< sonics >= 2.3 */
114 #define SIBA_IPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
115 #define SIBA_IPS_INT1_SHIFT 0
116 #define SIBA_IPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
118 #define SIBA_IPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
120 #define SIBA_IPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
127 #define SIBA_TPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
128 #define SIBA_TPS_NUM0_SHIFT 0
129 #define SIBA_TPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
132 #define SIBA_TMEL_CM 0x00000007 /* command */
133 #define SIBA_TMEL_CI 0x0000ff00 /* connection id */
134 #define SIBA_TMEL_EC 0x0f000000 /* error code */
135 #define SIBA_TMEL_ME 0x80000000 /* multiple error */
138 #define SIBA_IM_PC 0xf /* pipecount */
139 #define SIBA_IM_AP_MASK 0x30 /* arbitration policy */
140 #define SIBA_IM_AP_BOTH 0x00 /* use both timeslaces and token */
141 #define SIBA_IM_AP_TS 0x10 /* use timesliaces only */
142 #define SIBA_IM_AP_TK 0x20 /* use token only */
143 #define SIBA_IM_AP_RSV 0x30 /* reserved */
144 #define SIBA_IM_IBE 0x20000 /* inbanderror */
145 #define SIBA_IM_TO 0x40000 /* timeout */
146 #define SIBA_IM_BY 0x01800000 /* busy (sonics >= 2.3) */
147 #define SIBA_IM_RJ 0x02000000 /* reject (sonics >= 2.3) */
150 #define SIBA_TML_RESET 0x0001 /* reset */
151 #define SIBA_TML_REJ_MASK 0x0006 /* reject field */
152 #define SIBA_TML_REJ 0x0002 /* reject */
153 #define SIBA_TML_TMPREJ 0x0004 /* temporary reject, for error recovery */
154 #define SIBA_TML_SICF_MASK 0xFFFF0000 /* core IOCTL flags */
158 #define SIBA_TMH_SERR 0x0001 /* serror */
159 #define SIBA_TMH_INT 0x0002 /* interrupt */
160 #define SIBA_TMH_BUSY 0x0004 /* busy */
161 #define SIBA_TMH_TO 0x0020 /* timeout (sonics >= 2.3) */
162 #define SIBA_TMH_SISF_MASK 0xFFFF0000 /* core IOST flags */
166 #define SIBA_BWA_TAB0_MASK 0xffff /* lookup table 0 */
167 #define SIBA_BWA_TAB1_MASK 0xffff /* lookup table 1 */
171 #define SIBA_IMCL_STO_MASK 0x7 /* service timeout */
172 #define SIBA_IMCL_RTO_MASK 0x70 /* request timeout */
174 #define SIBA_IMCL_CID_MASK 0xff0000 /* connection id */
178 #define SIBA_IMCH_IEM_MASK 0xc /* inband error mode */
179 #define SIBA_IMCH_TEM_MASK 0x30 /* timeout error mode */
181 #define SIBA_IMCH_BEM_MASK 0xc0 /* bus error mode */
185 #define SIBA_AM_TYPE_MASK 0x3 /* address type */
186 #define SIBA_AM_TYPE_SHIFT 0x0
187 #define SIBA_AM_AD64 0x4 /* reserved */
188 #define SIBA_AM_ADINT0_MASK 0xf8 /* type0 size */
190 #define SIBA_AM_ADINT1_MASK 0x1f8 /* type1 size */
192 #define SIBA_AM_ADINT2_MASK 0x1f8 /* type2 size */
194 #define SIBA_AM_ADEN 0x400 /* enable */
195 #define SIBA_AM_ADNEG 0x800 /* negative decode */
196 #define SIBA_AM_BASE0_MASK 0xffffff00 /* type0 base address */
198 #define SIBA_AM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
200 #define SIBA_AM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
204 #define SIBA_TMCL_CD_MASK 0xff /* clock divide */
205 #define SIBA_TMCL_CO_MASK 0xf800 /* clock offset */
207 #define SIBA_TMCL_IF_MASK 0xfc0000 /* interrupt flags */
209 #define SIBA_TMCL_IM_MASK 0x3000000 /* interrupt mode */
213 #define SIBA_TMCH_BM_MASK 0x3 /* busy mode */
214 #define SIBA_TMCH_RM_MASK 0x3 /* retry mode */
216 #define SIBA_TMCH_SM_MASK 0x30 /* stop mode */
218 #define SIBA_TMCH_EM_MASK 0x300 /* sb error mode */
220 #define SIBA_TMCH_IM_MASK 0xc00 /* int mode */
224 #define SIBA_BC_LAT_MASK 0x3 /* sb latency */
225 #define SIBA_BC_MAX0_MASK 0xf0000 /* maxccntr0 */
227 #define SIBA_BC_MAX1_MASK 0xf00000 /* maxccntr1 */
231 #define SIBA_BS_SRD 0x1 /* st reg disable */
232 #define SIBA_BS_HRD 0x2 /* hold reg disable */
235 #define SIBA_IDL_CS_MASK 0x3 /* config space */
236 #define SIBA_IDL_CS_SHIFT 0
237 #define SIBA_IDL_NRADDR_MASK 0x38 /* # address ranges supported */
239 #define SIBA_IDL_SYNCH 0x40 /* sync */
240 #define SIBA_IDL_INIT 0x80 /* initiator */
241 #define SIBA_IDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
243 #define SIBA_IDL_MAXLAT_MASK 0xf000 /* maximum backplane latency */
245 #define SIBA_IDL_FIRST_MASK 0x10000 /* this initiator is first */
247 #define SIBA_IDL_CW_MASK 0xc0000 /* cycle counter width */
249 #define SIBA_IDL_TP_MASK 0xf00000 /* target ports */
251 #define SIBA_IDL_IP_MASK 0xf000000 /* initiator ports */
253 #define SIBA_IDL_SBREV_MASK 0xf0000000 /* sonics backplane revision code */
255 #define SIBA_IDL_SBREV_2_2 0x0 /* version 2.2 or earlier */
256 #define SIBA_IDL_SBREV_2_3 0x1 /* version 2.3 */
259 #define SIBA_IDH_RC_MASK 0x000f /* revision code */
260 #define SIBA_IDH_RCE_MASK 0x7000 /* revision code extension field */
262 #define SIBA_IDH_DEVICE_MASK 0x8ff0 /* core code */
264 #define SIBA_IDH_VENDOR_MASK 0xffff0000 /* vendor code */
270 #define SIBA_COMMIT 0xfd8 /* update buffered registers value */