Lines Matching +full:software +full:- +full:configurable

1 /*-
9  * Permission to use, copy, modify, and/or distribute this software for any
13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
19  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
36  * -  PCI (cid=0x804, revision <= 12)
47  * -  PCI (cid=0x804, revision >= 13)
48  * -  PCIE (cid=0x820) with ChipCommon (revision <= 31)
59  * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
70  * - PCIE Gen 2 (cid=0x83c)
82  *	[0x0000+0x????]	fixed	ARM tightly-coupled memory (TCM).
89  * - Mapped GPIO CSRs into the PCI config space. Refer to
93  * - Mapped the clock CSR into the PCI config space. Refer to
106 /* PCI (non-PCIe) GPIO/Clock Config Registers */
132 #define	BHNDB_PCI_V0_BAR0_WIN0_OFFSET	0x0	/* bar0 + 0x0 accesses configurable 4K region of backplan…
147 #define	BHNDB_PCI_V1_BAR0_WIN0_OFFSET	0x0	/* bar0 + 0x0 accesses configurable 4K region of backplan…
162 #define	BHNDB_PCI_V2_BAR0_WIN0_OFFSET	0x0	/* bar0 + 0x0 accesses configurable 4K region of backplan…
171 /* PCI_V3 (PCIe-G2) */
176 #define	BHNDB_PCI_V3_BAR0_WIN0_OFFSET	0x0	/* bar0 + 0x0 accesses configurable 4K region of backplan…
207 /* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN  */
210 #define	BHNDB_PCI_GPIO_XTAL_ON		0x40	/* PCI config space GPIO 14 for Xtal power-up */
211 #define	BHNDB_PCI_GPIO_PLL_OFF		0x80	/* PCI config space GPIO 15 for PLL power-down */