Lines Matching +full:shadow +full:- +full:interrupts
1 /*-
36 * - PCI (cid=0x804, revision <= 12)
41 * [0x1000+0x0800] fixed SPROM shadow
47 * - PCI (cid=0x804, revision >= 13)
48 * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
53 * [0x1000+0x1000] fixed SPROM shadow
59 * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
70 * - PCIE Gen 2 (cid=0x83c)
82 * [0x0000+0x????] fixed ARM tightly-coupled memory (TCM).
89 * - Mapped GPIO CSRs into the PCI config space. Refer to
93 * - Mapped the clock CSR into the PCI config space. Refer to
100 #define BHNDB_PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
101 #define BHNDB_PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
102 #define BHNDB_PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
106 /* PCI (non-PCIe) GPIO/Clock Config Registers */
134 #define BHNDB_PCI_V0_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */
149 #define BHNDB_PCI_V1_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */
171 /* PCI_V3 (PCIe-G2) */
207 /* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN */
210 #define BHNDB_PCI_GPIO_XTAL_ON 0x40 /* PCI config space GPIO 14 for Xtal power-up */
211 #define BHNDB_PCI_GPIO_PLL_OFF 0x80 /* PCI config space GPIO 15 for PLL power-down */