Lines Matching full:pci

27  * Common PCI/PCIE Bridge Configuration Registers.
32 * in BHND PCI/PCIE bridge cores:
36 * - PCI (cid=0x804, revision <= 12)
42 * [0x1800+0x0E00] fixed pci core device registers
43 * [0x1E00+0x0200] fixed pci core siba config registers
47 * - PCI (cid=0x804, revision >= 13)
54 * [0x2000+0x1000] fixed pci/pcie core registers
65 * [0x2000+0x1000] fixed pci/pcie core registers
76 * [0x2000+0x1000] fixed pci/pcie core registers
88 * == PCI Cores Revision >= 3 ==
89 * - Mapped GPIO CSRs into the PCI config space. Refer to
92 * == PCI/PCIE Cores Revision >= 14 ==
93 * - Mapped the clock CSR into the PCI config space. Refer to
97 /* Common PCI/PCIE Config Registers */
100 #define BHNDB_PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
101 #define BHNDB_PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
106 /* PCI (non-PCIe) GPIO/Clock Config Registers */
107 #define BHNDB_PCI_CLK_CTL 0xa8 /* clock control/status (pci >=rev14) */
108 #define BHNDB_PCI_GPIO_IN 0xb0 /* gpio input (pci >=rev3) */
109 #define BHNDB_PCI_GPIO_OUT 0xb4 /* gpio output (pci >=rev3) */
110 #define BHNDB_PCI_GPIO_OUTEN 0xb8 /* gpio output enable (pci >=rev3) */
112 /* Hardware revisions used to determine PCI revision */
119 * Number of times to retry writing to a PCI window address register.
121 * On siba(4) devices, it's possible that writing a PCI window register may
134 #define BHNDB_PCI_V0_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */
136 #define BHNDB_PCI_V0_BAR0_PCIREG_OFFSET 0x1800 /* bar0 + 6K accesses pci core registers (not includ…
138 #define BHNDB_PCI_V0_BAR0_PCISB_OFFSET 0x1E00 /* bar0 + 7.5K accesses pci core's SSB CFG register b…
149 #define BHNDB_PCI_V1_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */
151 #define BHNDB_PCI_V1_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */
166 #define BHNDB_PCI_V2_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */
180 #define BHNDB_PCI_V3_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */
207 /* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN */
208 #define BHNDB_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
209 #define BHNDB_PCI_GPIO_HWRAD_OFF 0x20 /* PCI config space GPIO 13 for hw radio disable */
210 #define BHNDB_PCI_GPIO_XTAL_ON 0x40 /* PCI config space GPIO 14 for Xtal power-up */
211 #define BHNDB_PCI_GPIO_PLL_OFF 0x80 /* PCI config space GPIO 15 for PLL power-down */