Lines Matching +full:gpio +full:- +full:config

1 /*-
36  * -  PCI (cid=0x804, revision <= 12)
43  *	[0x1E00+0x0200]	fixed	pci core siba config registers
47  * -  PCI (cid=0x804, revision >= 13)
48  * -  PCIE (cid=0x820) with ChipCommon (revision <= 31)
59  * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
70  * - PCIE Gen 2 (cid=0x83c)
82  *	[0x0000+0x????]	fixed	ARM tightly-coupled memory (TCM).
89  * - Mapped GPIO CSRs into the PCI config space. Refer to
93  * - Mapped the clock CSR into the PCI config space. Refer to
97 /* Common PCI/PCIE Config Registers */
106 /* PCI (non-PCIe) GPIO/Clock Config Registers */
108 #define	BHNDB_PCI_GPIO_IN		0xb0	/* gpio input (pci >=rev3) */
109 #define	BHNDB_PCI_GPIO_OUT		0xb4	/* gpio output (pci >=rev3) */
110 #define	BHNDB_PCI_GPIO_OUTEN		0xb8	/* gpio output enable (pci >=rev3) */
171 /* PCI_V3 (PCIe-G2) */
207 /* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN  */
208 #define	BHNDB_PCI_GPIO_SCS		0x10	/* PCI config space bit 4 for 4306c0 slow clock source */
209 #define	BHNDB_PCI_GPIO_HWRAD_OFF		0x20	/* PCI config space GPIO 13 for hw radio disable */
210 #define	BHNDB_PCI_GPIO_XTAL_ON		0x40	/* PCI config space GPIO 14 for Xtal power-up */
211 #define	BHNDB_PCI_GPIO_PLL_OFF		0x80	/* PCI config space GPIO 15 for PLL power-down */