Lines Matching +full:config +full:- +full:space
1 /*-
36 * - PCI (cid=0x804, revision <= 12)
40 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
43 * [0x1E00+0x0200] fixed pci core siba config registers
47 * - PCI (cid=0x804, revision >= 13)
48 * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
52 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
59 * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
63 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
64 * [0x1000+0x1000] dynamic mapped backplane address space (window 1).
70 * - PCIE Gen 2 (cid=0x83c)
74 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
75 * [0x1000+0x1000] dynamic mapped backplane address space (window 1).
82 * [0x0000+0x????] fixed ARM tightly-coupled memory (TCM).
89 * - Mapped GPIO CSRs into the PCI config space. Refer to
93 * - Mapped the clock CSR into the PCI config space. Refer to
97 /* Common PCI/PCIE Config Registers */
106 /* PCI (non-PCIe) GPIO/Clock Config Registers */
128 #define BHNDB_PCI_V0_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */
129 #define BHNDB_PCI_V0_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */
132 …V0_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */
143 #define BHNDB_PCI_V1_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */
144 #define BHNDB_PCI_V1_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */
147 …V1_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */
157 #define BHNDB_PCI_V2_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */
158 #define BHNDB_PCI_V2_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */
159 #define BHNDB_PCI_V2_BAR0_WIN1_CONTROL 0xAC /* backplane address space accessed by BAR0/WIN1 */
162 …V2_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */
171 /* PCI_V3 (PCIe-G2) */
172 #define BHNDB_PCI_V3_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */
173 #define BHNDB_PCI_V3_BAR0_WIN1_CONTROL 0x70 /* backplane address space accessed by BAR0/WIN1 */
176 …V3_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */
207 /* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN */
208 #define BHNDB_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
209 #define BHNDB_PCI_GPIO_HWRAD_OFF 0x20 /* PCI config space GPIO 13 for hw radio disable */
210 #define BHNDB_PCI_GPIO_XTAL_ON 0x40 /* PCI config space GPIO 14 for Xtal power-up */
211 #define BHNDB_PCI_GPIO_PLL_OFF 0x80 /* PCI config space GPIO 15 for PLL power-down */