Lines Matching +full:4 +full:kb
37 * BAR0 size: 8KB
49 * BAR0 size: 16KB
60 * BAR0 size: 16KB
71 * BAR0 size: 32KB
84 * 4KB mapping, newer devices will vary.
121 * On siba(4) devices, it's possible that writing a PCI window register may
131 #define BHNDB_PCI_V0_BAR0_SIZE 0x2000 /* 8KB BAR0 */
132 #define BHNDB_PCI_V0_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplan…
134 #define BHNDB_PCI_V0_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */
146 #define BHNDB_PCI_V1_BAR0_SIZE 0x4000 /* 16KB BAR0 */
147 #define BHNDB_PCI_V1_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplan…
149 #define BHNDB_PCI_V1_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */
161 #define BHNDB_PCI_V2_BAR0_SIZE 0x4000 /* 16KB BAR0 */
162 #define BHNDB_PCI_V2_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplan…
164 #define BHNDB_PCI_V2_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */
175 #define BHNDB_PCI_V3_BAR0_SIZE 0x8000 /* 32KB BAR0 */
176 #define BHNDB_PCI_V3_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplan…
178 #define BHNDB_PCI_V3_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */
196 #define BHNDB_PCI_SPROM_SZ_1KB 0x00 /**< 1KB sprom size */
197 #define BHNDB_PCI_SPROM_SZ_4KB 0x01 /**< 4KB sprom size */
198 #define BHNDB_PCI_SPROM_SZ_16KB 0x02 /**< 16KB sprom size */
208 #define BHNDB_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */