Lines Matching +full:dma +full:- +full:window

1 /*-
33  * configured as PCI-BHND bridges.
74  * Generic PCI-SIBA bridge configuration usable with all known siba(4)-based
79  * - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices.
80  * - Compatible with siba(4) bus enumeration.
81  * - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped
87 		{ -1,			0,		0 }
91 		/* bar0+0x0000: configurable backplane window */
104 	/* DMA unsupported under generic configuration */
109  * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based
114  * - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices.
115  * - Compatible with both siba(4) and bcma(4) bus enumeration.
120 		{ -1,			0,		0 }
124 		/* bar0+0x0000: configurable backplane window */
153 	/* DMA unsupported under generic configuration */
258 	BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3,
281  * - PCI (cid=0x804, revision <= 12)
286 		{ -1,			0,		0 }
290 		/* bar0+0x0000: configurable backplane window */
313 		 * the 4K core register block; these are mapped non-contigiously
360  * PCI_V1 (PCI-only) hardware configuration (PCI version)
363  * - PCI (cid=0x804, revision >= 13)
368 		{ -1,			0,		0 }
372 		/* bar0+0x0000: configurable backplane window */
438  * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
443 		{ -1,			0,		0 }
447 		/* bar0+0x0000: configurable backplane window */
518  * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
523 		{ -1,			0,		0 }
527 		/* bar0+0x0000: configurable backplane window */
538 		/* bar0+0x1000: configurable backplane window */
601  * - PCIE2 (cid=0x83c)
606 		{ -1,			0,		0 }
610 		/* bar0+0x0000: configurable backplane window */
621 		/* bar0+0x1000: configurable backplane window */