Lines Matching +full:rx +full:- +full:mode
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #define BFE_PME 0x00001000 /* PHY Mode Enable */
42 #define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
46 #define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */
58 #define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */
111 #define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */
116 #define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */
117 #define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */
118 #define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */
120 #define BFE_RXCONF 0x00000400 /* EMAC RX Config */
130 #define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */
182 #define BFE_TX_FMODE 0x00000002 /* Flow Mode */
216 #define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */
217 #define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */
218 #define BFE_RX_O 0x00000588 /* MIB RX Octets */
219 #define BFE_RX_P 0x0000058C /* MIB RX Packets */
220 #define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */
221 #define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */
222 #define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */
223 #define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */
224 #define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */
225 #define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */
226 #define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */
227 #define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */
228 #define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */
229 #define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */
230 #define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */
231 #define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */
232 #define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */
233 #define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */
234 #define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */
235 #define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */
236 #define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */
237 #define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */
238 #define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */
271 #define BFE_SERR 0x00000001 /* S-error */
292 #define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */
293 #define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */
294 #define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */
302 #define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */
308 #define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */
309 #define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */
310 #define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */
311 #define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */
312 #define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */
410 #define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */
413 #define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */
444 #define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg)
446 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->bfe_res, reg, val)
454 #define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED)
455 #define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx)
456 #define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx)
458 #define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1
530 #define BFE_MIB_CNT (MIB_RX_NPAUSE - MIB_TX_GOOD_O + 1)