Lines Matching +full:0 +full:x801
32 #define BFE_PCI_MEMLO 0x10
33 #define BFE_PCI_MEMHIGH 0x14
34 #define BFE_PCI_INTLINE 0x3C
37 #define BFE_DEVCTRL 0x00000000 /* Device Control */
38 #define BFE_PFE 0x00000080 /* Pattern Filtering Enable */
39 #define BFE_IPP 0x00000400 /* Internal EPHY Present */
40 #define BFE_EPR 0x00008000 /* EPHY Reset */
41 #define BFE_PME 0x00001000 /* PHY Mode Enable */
42 #define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
43 #define BFE_PADDR 0x0007c000 /* PHY Address */
46 #define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */
47 #define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */
49 #define BFE_ISTAT 0x00000020 /* Interrupt Status */
50 #define BFE_ISTAT_PME 0x00000040 /* Power Management Event */
51 #define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */
52 #define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */
53 #define BFE_ISTAT_DATAE 0x00000800 /* Data Error */
54 #define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */
55 #define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */
56 #define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
57 #define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
58 #define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */
59 #define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */
60 #define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */
61 #define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */
62 #define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */
66 #define BFE_IMASK 0x00000024 /* Interrupt Mask */
70 #define BFE_MAC_CTRL 0x000000A8 /* MAC Control */
71 #define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
72 #define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */
73 #define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */
74 #define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */
77 #define BFE_MAC_FLOW 0x000000AC /* MAC Flow Control */
78 #define BFE_FLOW_RX_HIWAT 0x000000ff /* Onchip FIFO HI Water Mark */
79 #define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
81 #define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */
82 #define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */
83 #define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */
86 #define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */
87 #define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */
88 #define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */
89 #define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */
90 #define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */
91 #define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */
93 #define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */
94 #define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */
95 #define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */
96 #define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
97 #define BFE_STAT_SMASK 0x0000f000 /* State Mask */
98 #define BFE_STAT_DISABLE 0x00000000 /* State Disabled */
99 #define BFE_STAT_SACTIVE 0x00001000 /* State Active */
100 #define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */
101 #define BFE_STAT_STOPPED 0x00003000 /* State Stopped */
102 #define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */
103 #define BFE_STAT_EMASK 0x000f0000 /* Error Mask */
104 #define BFE_STAT_ENONE 0x00000000 /* Error None */
105 #define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */
106 #define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
107 #define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */
108 #define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */
109 #define BFE_STAT_FLUSHED 0x00100000 /* Flushed */
111 #define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */
112 #define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */
113 #define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */
116 #define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */
117 #define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */
118 #define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */
120 #define BFE_RXCONF 0x00000400 /* EMAC RX Config */
121 #define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */
122 #define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */
123 #define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */
124 #define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */
125 #define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */
126 #define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */
127 #define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
128 #define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */
130 #define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */
131 #define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */
133 #define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */
134 #define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */
135 #define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */
137 #define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */
138 #define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */
139 #define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */
143 #define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */
144 #define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */
145 #define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */
146 #define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */
147 #define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */
155 #define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */
156 #define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */
157 #define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */
158 #define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
159 #define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */
161 #define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */
162 #define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */
163 #define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */
165 #define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */
166 #define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */
167 #define BFE_CAM_MSEL 0x00000002 /* Mask Select */
168 #define BFE_CAM_READ 0x00000004 /* Read */
169 #define BFE_CAM_WRITE 0x00000008 /* Read */
170 #define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */
171 #define BFE_CAM_BUSY 0x80000000 /* CAM Busy */
174 #define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */
175 #define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */
176 #define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */
177 #define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */
178 #define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */
180 #define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */
181 #define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */
182 #define BFE_TX_FMODE 0x00000002 /* Flow Mode */
183 #define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */
184 #define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */
186 #define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */
188 #define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */
189 #define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */
192 #define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */
193 #define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */
194 #define BFE_TX_O 0x00000508 /* MIB TX Octets */
195 #define BFE_TX_P 0x0000050C /* MIB TX Packets */
196 #define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */
197 #define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */
198 #define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */
199 #define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */
200 #define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */
201 #define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */
202 #define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */
203 #define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */
204 #define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */
205 #define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */
206 #define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */
207 #define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */
208 #define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */
209 #define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */
210 #define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */
211 #define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */
212 #define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */
213 #define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */
214 #define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */
215 #define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */
216 #define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */
217 #define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */
218 #define BFE_RX_O 0x00000588 /* MIB RX Octets */
219 #define BFE_RX_P 0x0000058C /* MIB RX Packets */
220 #define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */
221 #define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */
222 #define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */
223 #define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */
224 #define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */
225 #define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */
226 #define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */
227 #define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */
228 #define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */
229 #define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */
230 #define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */
231 #define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */
232 #define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */
233 #define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */
234 #define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */
235 #define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */
236 #define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */
237 #define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */
238 #define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */
240 #define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */
241 #define BFE_PC 0x0000000f /* Pipe Count */
242 #define BFE_AP_MASK 0x00000030 /* Arbitration Priority */
243 #define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */
244 #define BFE_AP_TS 0x00000010 /* Use timeslices only */
245 #define BFE_AP_TK 0x00000020 /* Use token only */
246 #define BFE_AP_RSV 0x00000030 /* Reserved */
247 #define BFE_IBE 0x00020000 /* In Band Error */
248 #define BFE_TO 0x00040000 /* Timeout */
253 #define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */
254 #define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
255 #define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
256 #define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
257 #define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
258 #define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */
259 #define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
260 #define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
262 #define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */
263 #define BFE_RESET 0x00000001 /* Reset */
264 #define BFE_REJECT 0x00000002 /* Reject */
265 #define BFE_CLOCK 0x00010000 /* Clock Enable */
266 #define BFE_FGC 0x00020000 /* Force Gated Clocks On */
267 #define BFE_PE 0x40000000 /* Power Management Enable */
268 #define BFE_BE 0x80000000 /* BIST Enable */
270 #define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */
271 #define BFE_SERR 0x00000001 /* S-error */
272 #define BFE_INT 0x00000002 /* Interrupt */
273 #define BFE_BUSY 0x00000004 /* Busy */
274 #define BFE_GCR 0x20000000 /* Gated Clock Request */
275 #define BFE_BISTF 0x40000000 /* BIST Failed */
276 #define BFE_BISTD 0x80000000 /* BIST Done */
278 #define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */
279 #define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */
280 #define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */
281 #define BFE_TAB0_SHIFT 0
284 #define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */
285 #define BFE_STO_MASK 0x00000003 /* Service Timeout */
286 #define BFE_RTO_MASK 0x00000030 /* Request Timeout */
287 #define BFE_CID_MASK 0x00ff0000 /* Connection ID */
291 #define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */
292 #define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */
293 #define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */
294 #define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */
298 #define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */
299 #define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */
300 #define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */
301 #define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */
302 #define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */
307 #define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */
308 #define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */
309 #define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */
310 #define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */
311 #define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */
312 #define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */
318 #define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */
319 #define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */
320 #define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */
321 #define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */
325 #define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */
326 #define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */
327 #define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */
329 #define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */
330 #define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */
332 #define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */
333 #define BFE_CS_MASK 0x00000003 /* Config Space Mask */
334 #define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */
335 #define BFE_SYNCH 0x00000040 /* Sync */
336 #define BFE_INIT 0x00000080 /* Initiator */
337 #define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */
338 #define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */
339 #define BFE_FIRST 0x00010000 /* This Initiator is First */
340 #define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */
341 #define BFE_TP_MASK 0x00f00000 /* Target Ports */
342 #define BFE_IP_MASK 0x0f000000 /* Initiator Ports */
350 #define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */
351 #define BFE_RC_MASK 0x0000000f /* Revision Code */
352 #define BFE_CC_MASK 0x0000fff0 /* Core Code */
353 #define BFE_VC_MASK 0xffff0000 /* Vendor Code */
357 #define BFE_CORE_ILINE20 0x801
358 #define BFE_CORE_SDRAM 0x803
359 #define BFE_CORE_PCI 0x804
360 #define BFE_CORE_MIPS 0x805
361 #define BFE_CORE_ENET 0x806
362 #define BFE_CORE_CODEC 0x807
363 #define BFE_CORE_USB 0x808
364 #define BFE_CORE_ILINE100 0x80a
365 #define BFE_CORE_EXTIF 0x811
368 #define BFE_BAR0_WIN 0x80
369 #define BFE_BAR1_WIN 0x84
370 #define BFE_SPROM_CONTROL 0x88
371 #define BFE_BAR1_CONTROL 0x8c
374 #define BFE_SSB_CONTROL 0x00000000
375 #define BFE_SSB_ARBCONTROL 0x00000010
376 #define BFE_SSB_ISTAT 0x00000020
377 #define BFE_SSB_IMASK 0x00000024
378 #define BFE_SSB_MBOX 0x00000028
379 #define BFE_SSB_BCAST_ADDR 0x00000050
380 #define BFE_SSB_BCAST_DATA 0x00000054
381 #define BFE_SSB_PCI_TRANS_0 0x00000100
382 #define BFE_SSB_PCI_TRANS_1 0x00000104
383 #define BFE_SSB_PCI_TRANS_2 0x00000108
384 #define BFE_SSB_SPROM 0x00000800
386 #define BFE_SSB_PCI_MEM 0x00000000
387 #define BFE_SSB_PCI_IO 0x00000001
388 #define BFE_SSB_PCI_CFG0 0x00000002
389 #define BFE_SSB_PCI_CFG1 0x00000003
390 #define BFE_SSB_PCI_PREF 0x00000004
391 #define BFE_SSB_PCI_BURST 0x00000008
392 #define BFE_SSB_PCI_MASK0 0xfc000000
393 #define BFE_SSB_PCI_MASK1 0xfc000000
394 #define BFE_SSB_PCI_MASK2 0xc0000000
396 #define BFE_DESC_LEN 0x00001fff
397 #define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */
398 #define BFE_DESC_EOT 0x10000000 /* End of Table */
399 #define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */
400 #define BFE_DESC_EOF 0x40000000 /* End of Frame */
401 #define BFE_DESC_SOF 0x80000000 /* Start of Frame */
406 #define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */
407 #define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */
408 #define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */
409 #define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */
410 #define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */
411 #define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */
412 #define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */
413 #define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */
414 #define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */
419 #define BFE_PCI_DMA 0x40000000
420 #define BFE_REG_PCI 0x18002000
422 #define BCOM_VENDORID 0x14E4
423 #define BCOM_DEVICEID_BCM4401 0x4401
424 #define BCOM_DEVICEID_BCM4401B0 0x170c
441 #define BFE_DMA_MAXADDR 0x3FFFFFFF /* 1GB DMA address limit. */
442 #define BFE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
458 #define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1
482 #define MIB_TX_GOOD_O 0
604 #define BFE_FLAG_DETACH 0x4000
605 #define BFE_FLAG_LINK 0x8000