Lines Matching full:l
1138 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
1139 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
1140 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
1141 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
1142 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
1143 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
1144 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
1145 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
1146 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
1147 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
1148 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
1149 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
1150 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
1151 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
1152 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
1153 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
1154 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
1155 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
1156 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
1157 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
1158 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
1159 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
1160 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
1161 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
1162 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
1163 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
1164 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
1165 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
1166 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
1487 #define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
1488 #define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
1489 #define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
1490 #define BCE_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
1491 #define BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
1492 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
1493 #define BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
1500 #define BCE_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
1501 #define BCE_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
1502 #define BCE_PCICFG_MISC_STATUS_M66EN (1L<<2)
1503 #define BCE_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
1505 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
1506 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
1507 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
1508 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
1512 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1513 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1514 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1515 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1516 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1517 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1518 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1519 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1521 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1522 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1524 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1525 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1526 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1527 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
1528 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
1530 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1531 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1532 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1533 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1534 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1535 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1536 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
1537 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
1538 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
1545 #define BCE_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
1546 #define BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
1547 #define BCE_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
1563 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
1564 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
1565 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
1566 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
1567 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
1568 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
1569 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
1570 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
1572 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
1573 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
1574 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
1575 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
1576 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
1577 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
1578 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
1579 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
1583 #define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
1584 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
1585 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
1586 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
1587 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
1588 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
1589 #define BCE_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
1590 #define BCE_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
1591 #define BCE_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
1592 #define BCE_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
1593 #define BCE_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
1594 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
1595 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
1596 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
1597 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
1598 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
1599 #define BCE_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
1600 #define BCE_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
1601 #define BCE_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
1602 #define BCE_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
1604 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
1605 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
1606 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
1607 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
1608 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
1609 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
1610 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
1611 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
1612 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
1613 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
1614 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
1615 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
1616 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
1617 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
1618 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
1619 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
1622 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
1623 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
1624 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
1625 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
1626 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
1627 #define BCE_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
1628 #define BCE_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
1632 #define BCE_PCI_CONFIG_3_FORCE_PME (1L<<24)
1633 #define BCE_PCI_CONFIG_3_PME_STATUS (1L<<25)
1634 #define BCE_PCI_CONFIG_3_PME_ENABLE (1L<<26)
1636 #define BCE_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
1637 #define BCE_PCI_CONFIG_3_PCI_POWER (1L<<31)
1655 #define BCE_PCI_EXP_ROM_ADDR_REQ (1L<<31)
1659 #define BCE_PCI_VPD_INTF_INTF_REQ (1L<<0)
1680 #define BCE_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
1681 #define BCE_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
1682 #define BCE_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
1683 #define BCE_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
1684 #define BCE_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
1685 #define BCE_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
1686 #define BCE_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
1687 #define BCE_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
1688 #define BCE_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
1689 #define BCE_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
1690 #define BCE_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
1691 #define BCE_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
1692 #define BCE_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
1693 #define BCE_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
1694 #define BCE_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
1695 #define BCE_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
1697 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
1698 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
1699 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
1700 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
1703 #define BCE_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
1704 #define BCE_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
1705 #define BCE_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
1711 #define BCE_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
1712 #define BCE_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
1713 #define BCE_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
1714 #define BCE_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
1715 #define BCE_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
1716 #define BCE_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
1719 #define BCE_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
1720 #define BCE_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
1740 #define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0)
1741 #define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1)
1742 #define BCE_MISC_COMMAND_SW_RESET (1L<<4)
1743 #define BCE_MISC_COMMAND_POR_RESET (1L<<5)
1744 #define BCE_MISC_COMMAND_HD_RESET (1L<<6)
1745 #define BCE_MISC_COMMAND_CMN_SW_RESET (1L<<7)
1746 #define BCE_MISC_COMMAND_PAR_ERROR (1L<<8)
1747 #define BCE_MISC_COMMAND_CS16_ERR (1L<<9)
1750 #define BCE_MISC_COMMAND_POWERDOWN_EVENT (1L<<23)
1751 #define BCE_MISC_COMMAND_SW_SHUTDOWN (1L<<24)
1752 #define BCE_MISC_COMMAND_SHUTDOWN_EN (1L<<25)
1753 #define BCE_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26)
1754 #define BCE_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27)
1755 #define BCE_MISC_COMMAND_PCIE_DIS (1L<<28)
1758 #define BCE_MISC_CFG_GRC_TMOUT (1L<<0)
1760 #define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
1761 #define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
1762 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
1763 #define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
1764 #define BCE_MISC_CFG_BIST_EN (1L<<3)
1765 #define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
1766 #define BCE_MISC_CFG_RESERVED5_TE (1L<<5)
1767 #define BCE_MISC_CFG_RESERVED6_TE (1L<<6)
1768 #define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
1770 #define BCE_MISC_CFG_LEDMODE_MAC (0L<<8)
1771 #define BCE_MISC_CFG_LEDMODE_PHY1_TE (1L<<8)
1772 #define BCE_MISC_CFG_LEDMODE_PHY2_TE (2L<<8)
1773 #define BCE_MISC_CFG_LEDMODE_PHY3_TE (3L<<8)
1774 #define BCE_MISC_CFG_LEDMODE_PHY4_TE (4L<<8)
1775 #define BCE_MISC_CFG_LEDMODE_PHY5_TE (5L<<8)
1776 #define BCE_MISC_CFG_LEDMODE_PHY6_TE (6L<<8)
1777 #define BCE_MISC_CFG_LEDMODE_PHY7_TE (7L<<8)
1778 #define BCE_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11)
1779 #define BCE_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12)
1781 #define BCE_MISC_CFG_LEDMODE_MAC_XI (0L<<8)
1782 #define BCE_MISC_CFG_LEDMODE_PHY1_XI (1L<<8)
1783 #define BCE_MISC_CFG_LEDMODE_PHY2_XI (2L<<8)
1784 #define BCE_MISC_CFG_LEDMODE_PHY3_XI (3L<<8)
1785 #define BCE_MISC_CFG_LEDMODE_MAC2_XI (4L<<8)
1786 #define BCE_MISC_CFG_LEDMODE_PHY4_XI (5L<<8)
1787 #define BCE_MISC_CFG_LEDMODE_PHY5_XI (6L<<8)
1788 #define BCE_MISC_CFG_LEDMODE_PHY6_XI (7L<<8)
1789 #define BCE_MISC_CFG_LEDMODE_MAC3_XI (8L<<8)
1790 #define BCE_MISC_CFG_LEDMODE_PHY7_XI (9L<<8)
1791 #define BCE_MISC_CFG_LEDMODE_PHY8_XI (10L<<8)
1792 #define BCE_MISC_CFG_LEDMODE_PHY9_XI (11L<<8)
1793 #define BCE_MISC_CFG_LEDMODE_MAC4_XI (12L<<8)
1794 #define BCE_MISC_CFG_LEDMODE_PHY10_XI (13L<<8)
1795 #define BCE_MISC_CFG_LEDMODE_PHY11_XI (14L<<8)
1796 #define BCE_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8)
1797 #define BCE_MISC_CFG_PORT_SELECT_XI (1L<<13)
1798 #define BCE_MISC_CFG_PARITY_MODE_XI (1L<<14)
1802 #define BCE_MISC_ID_BOND_ID_X (0L<<0)
1803 #define BCE_MISC_ID_BOND_ID_C (3L<<0)
1804 #define BCE_MISC_ID_BOND_ID_S (12L<<0)
1810 #define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1811 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
1812 #define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1813 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1814 #define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
1815 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
1816 #define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1817 #define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1818 #define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1819 #define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
1820 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1821 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1822 #define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
1823 #define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
1824 #define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1825 #define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
1826 #define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1827 #define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
1828 #define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
1829 #define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
1830 #define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1831 #define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
1832 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1833 #define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1834 #define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1835 #define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
1836 #define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
1837 #define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
1838 #define BCE_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1842 #define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1843 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
1844 #define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1845 #define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1846 #define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
1847 #define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
1848 #define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1849 #define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1850 #define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1851 #define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
1852 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1853 #define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1854 #define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
1855 #define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
1856 #define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1857 #define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
1858 #define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1859 #define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
1860 #define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
1861 #define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
1862 #define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1863 #define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
1864 #define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1865 #define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1866 #define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1867 #define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
1868 #define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
1869 #define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
1870 #define BCE_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1877 #define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1878 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
1879 #define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1880 #define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1881 #define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
1882 #define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
1883 #define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1884 #define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1885 #define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1886 #define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
1887 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1888 #define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1889 #define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
1890 #define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
1891 #define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1892 #define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
1893 #define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1894 #define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
1895 #define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
1896 #define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
1897 #define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1898 #define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
1899 #define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1900 #define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1901 #define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1902 #define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
1903 #define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
1904 #define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
1905 #define BCE_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1912 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1913 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1914 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1915 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1916 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1917 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1918 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1919 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1921 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1922 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1924 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1925 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1926 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1927 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
1929 #define BCE_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
1931 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1932 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1933 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1934 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1935 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1937 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1938 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17)
1939 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18)
1940 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19)
1942 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17)
1945 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27)
1968 #define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1969 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
1970 #define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1971 #define BCE_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1972 #define BCE_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
1973 #define BCE_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
1974 #define BCE_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1975 #define BCE_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1976 #define BCE_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1977 #define BCE_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
1978 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1979 #define BCE_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1980 #define BCE_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
1981 #define BCE_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
1982 #define BCE_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1983 #define BCE_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
1984 #define BCE_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1985 #define BCE_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
1986 #define BCE_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
1987 #define BCE_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
1988 #define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1989 #define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
1990 #define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1991 #define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1992 #define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1993 #define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
1994 #define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
1995 #define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
1996 #define BCE_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
2058 #define BCE_MISC_RESERVED2_PCIE_DIS (1L<<0)
2059 #define BCE_MISC_RESERVED2_LINK_IN_L23 (1L<<1)
2062 #define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
2063 #define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
2064 #define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
2065 #define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
2066 #define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
2067 #define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
2068 #define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
2069 #define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
2070 #define BCE_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8)
2071 #define BCE_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9)
2073 #define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
2074 #define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
2075 #define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
2076 #define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
2079 #define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
2080 #define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
2084 #define BCE_MISC_SMB_IN_RDY (1L<<8)
2085 #define BCE_MISC_SMB_IN_DONE (1L<<9)
2086 #define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10)
2096 #define BCE_MISC_SMB_OUT_RDY (1L<<8)
2097 #define BCE_MISC_SMB_OUT_START (1L<<9)
2098 #define BCE_MISC_SMB_OUT_LAST (1L<<10)
2099 #define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11)
2100 #define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12)
2101 #define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
2104 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
2105 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
2106 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
2107 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
2108 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
2109 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
2110 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20)
2111 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
2113 #define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
2114 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
2115 #define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
2116 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
2117 #define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
2138 #define BCE_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
2139 #define BCE_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
2140 #define BCE_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
2141 #define BCE_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
2142 #define BCE_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
2143 #define BCE_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
2144 #define BCE_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
2145 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
2146 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
2147 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
2148 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
2149 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
2150 #define BCE_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
2151 #define BCE_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
2152 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
2153 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
2154 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
2155 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
2156 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
2157 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
2158 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
2159 #define BCE_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
2160 #define BCE_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
2161 #define BCE_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
2162 #define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
2163 #define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
2164 #define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
2165 #define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
2166 #define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
2167 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
2168 #define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
2169 #define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
2170 #define BCE_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0)
2171 #define BCE_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1)
2172 #define BCE_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2)
2173 #define BCE_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3)
2174 #define BCE_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4)
2175 #define BCE_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5)
2176 #define BCE_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6)
2177 #define BCE_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7)
2178 #define BCE_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8)
2179 #define BCE_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9)
2180 #define BCE_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10)
2181 #define BCE_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11)
2182 #define BCE_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12)
2183 #define BCE_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13)
2184 #define BCE_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14)
2185 #define BCE_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15)
2186 #define BCE_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16)
2187 #define BCE_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17)
2188 #define BCE_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18)
2189 #define BCE_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19)
2190 #define BCE_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20)
2191 #define BCE_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21)
2192 #define BCE_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22)
2193 #define BCE_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23)
2194 #define BCE_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24)
2195 #define BCE_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25)
2196 #define BCE_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26)
2197 #define BCE_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27)
2198 #define BCE_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28)
2199 #define BCE_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29)
2200 #define BCE_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30)
2201 #define BCE_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31)
2204 #define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
2205 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
2206 #define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
2207 #define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
2208 #define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
2209 #define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
2210 #define BCE_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
2211 #define BCE_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
2212 #define BCE_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
2213 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
2214 #define BCE_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
2215 #define BCE_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
2216 #define BCE_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
2217 #define BCE_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
2218 #define BCE_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
2219 #define BCE_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
2220 #define BCE_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
2221 #define BCE_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
2222 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
2223 #define BCE_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
2224 #define BCE_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
2225 #define BCE_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
2226 #define BCE_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
2227 #define BCE_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
2228 #define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
2229 #define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
2230 #define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
2231 #define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
2232 #define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
2233 #define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
2234 #define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
2235 #define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
2236 #define BCE_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0)
2237 #define BCE_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2)
2238 #define BCE_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3)
2239 #define BCE_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4)
2240 #define BCE_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5)
2241 #define BCE_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6)
2242 #define BCE_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7)
2243 #define BCE_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8)
2244 #define BCE_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9)
2245 #define BCE_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10)
2246 #define BCE_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11)
2247 #define BCE_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12)
2248 #define BCE_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13)
2249 #define BCE_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14)
2250 #define BCE_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15)
2251 #define BCE_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16)
2252 #define BCE_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17)
2253 #define BCE_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18)
2254 #define BCE_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19)
2255 #define BCE_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20)
2256 #define BCE_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21)
2257 #define BCE_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22)
2258 #define BCE_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23)
2259 #define BCE_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24)
2260 #define BCE_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25)
2261 #define BCE_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26)
2262 #define BCE_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27)
2263 #define BCE_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28)
2264 #define BCE_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29)
2267 #define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
2268 #define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
2269 #define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
2270 #define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
2271 #define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
2272 #define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
2273 #define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
2274 #define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
2275 #define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
2276 #define BCE_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0)
2277 #define BCE_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1)
2278 #define BCE_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2)
2279 #define BCE_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3)
2280 #define BCE_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4)
2281 #define BCE_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5)
2282 #define BCE_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6)
2292 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0)
2293 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0)
2294 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0)
2295 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0)
2296 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0)
2297 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0)
2298 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0)
2299 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0)
2300 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0)
2301 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0)
2302 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0)
2303 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0)
2304 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0)
2305 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0)
2306 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0)
2307 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0)
2309 #define BCE_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4)
2310 #define BCE_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4)
2311 #define BCE_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4)
2312 #define BCE_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4)
2313 #define BCE_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4)
2314 #define BCE_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4)
2315 #define BCE_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4)
2316 #define BCE_MISC_VREG_CONTROL_2_5_NOM (7L<<4)
2317 #define BCE_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4)
2318 #define BCE_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4)
2319 #define BCE_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4)
2320 #define BCE_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4)
2321 #define BCE_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4)
2322 #define BCE_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4)
2323 #define BCE_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4)
2324 #define BCE_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4)
2326 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8)
2327 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8)
2328 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8)
2329 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8)
2330 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8)
2331 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8)
2332 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8)
2333 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8)
2334 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8)
2335 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8)
2336 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8)
2337 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8)
2338 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8)
2339 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8)
2340 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8)
2341 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8)
2347 #define BCE_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0)
2348 #define BCE_MISC_GP_HW_CTL0_RMII_MODE (1L<<1)
2349 #define BCE_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2)
2350 #define BCE_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3)
2351 #define BCE_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4)
2352 #define BCE_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5)
2353 #define BCE_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6)
2355 #define BCE_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7)
2356 #define BCE_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8)
2357 #define BCE_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9)
2358 #define BCE_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10)
2360 #define BCE_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11)
2361 #define BCE_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12)
2362 #define BCE_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13)
2363 #define BCE_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14)
2364 #define BCE_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15)
2366 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16)
2367 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16)
2368 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16)
2369 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16)
2370 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16)
2371 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16)
2372 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20)
2373 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21)
2375 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22)
2376 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22)
2377 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22)
2378 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22)
2380 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24)
2381 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24)
2382 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24)
2383 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24)
2385 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26)
2386 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26)
2387 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26)
2388 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26)
2390 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28)
2391 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28)
2392 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28)
2393 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28)
2395 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30)
2396 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30)
2397 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30)
2398 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30)
2401 #define BCE_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0)
2402 #define BCE_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1)
2403 #define BCE_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2)
2404 #define BCE_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3)
2409 #define BCE_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0)
2410 #define BCE_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1)
2411 #define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2)
2412 #define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3)
2417 #define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
2418 #define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
2419 #define BCE_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16)
2424 #define BCE_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0)
2452 #define BCE_MISC_CS16_ERR_ENA_PCI (1L<<0)
2453 #define BCE_MISC_CS16_ERR_ENA_RDMA (1L<<1)
2454 #define BCE_MISC_CS16_ERR_ENA_TDMA (1L<<2)
2455 #define BCE_MISC_CS16_ERR_ENA_EMAC (1L<<3)
2456 #define BCE_MISC_CS16_ERR_ENA_CTX (1L<<4)
2457 #define BCE_MISC_CS16_ERR_ENA_TBDR (1L<<5)
2458 #define BCE_MISC_CS16_ERR_ENA_RBDC (1L<<6)
2459 #define BCE_MISC_CS16_ERR_ENA_COM (1L<<7)
2460 #define BCE_MISC_CS16_ERR_ENA_CP (1L<<8)
2461 #define BCE_MISC_CS16_ERR_STA_PCI (1L<<16)
2462 #define BCE_MISC_CS16_ERR_STA_RDMA (1L<<17)
2463 #define BCE_MISC_CS16_ERR_STA_TDMA (1L<<18)
2464 #define BCE_MISC_CS16_ERR_STA_EMAC (1L<<19)
2465 #define BCE_MISC_CS16_ERR_STA_CTX (1L<<20)
2466 #define BCE_MISC_CS16_ERR_STA_TBDR (1L<<21)
2467 #define BCE_MISC_CS16_ERR_STA_RBDC (1L<<22)
2468 #define BCE_MISC_CS16_ERR_STA_COM (1L<<23)
2469 #define BCE_MISC_CS16_ERR_STA_CP (1L<<24)
2479 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0)
2480 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0)
2481 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0)
2483 #define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11)
2484 #define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12)
2485 #define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13)
2486 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14)
2487 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15)
2488 #define BCE_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16)
2489 #define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17)
2490 #define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18)
2491 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19)
2492 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20)
2494 #define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24)
2495 #define BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25)
2497 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26)
2498 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26)
2499 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26)
2500 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26)
2504 #define BCE_MISC_OTP_CMD1_FMODE_IDLE (0L<<0)
2505 #define BCE_MISC_OTP_CMD1_FMODE_WRITE (1L<<0)
2506 #define BCE_MISC_OTP_CMD1_FMODE_INIT (2L<<0)
2507 #define BCE_MISC_OTP_CMD1_FMODE_SET (3L<<0)
2508 #define BCE_MISC_OTP_CMD1_FMODE_RST (4L<<0)
2509 #define BCE_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0)
2510 #define BCE_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0)
2511 #define BCE_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0)
2512 #define BCE_MISC_OTP_CMD1_USEPINS (1L<<8)
2513 #define BCE_MISC_OTP_CMD1_PROGSEL (1L<<9)
2514 #define BCE_MISC_OTP_CMD1_PROGSTART (1L<<10)
2516 #define BCE_MISC_OTP_CMD1_PBYP (1L<<19)
2519 #define BCE_MISC_OTP_CMD1_SADBYP (1L<<30)
2520 #define BCE_MISC_OTP_CMD1_DEBUG (1L<<31)
2525 #define BCE_MISC_OTP_CMD2_DOSEL_0 (0L<<16)
2526 #define BCE_MISC_OTP_CMD2_DOSEL_1 (1L<<16)
2527 #define BCE_MISC_OTP_CMD2_DOSEL_127 (127L<<16)
2531 #define BCE_MISC_OTP_STATUS_VALID (1L<<8)
2532 #define BCE_MISC_OTP_STATUS_BUSY (1L<<9)
2533 #define BCE_MISC_OTP_STATUS_BUSYSM (1L<<10)
2534 #define BCE_MISC_OTP_STATUS_DONE (1L<<11)
2537 #define BCE_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0)
2538 #define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1)
2539 #define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2)
2540 #define BCE_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3)
2545 #define BCE_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0)
2546 #define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1)
2547 #define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2)
2548 #define BCE_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3)
2553 #define BCE_MISC_BIST_CS0_MBIST_EN (1L<<0)
2555 #define BCE_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3)
2556 #define BCE_MISC_BIST_CS0_MBIST_DONE (1L<<8)
2557 #define BCE_MISC_BIST_CS0_MBIST_GO (1L<<9)
2558 #define BCE_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31)
2562 #define BCE_MISC_BIST_CS1_MBIST_EN (1L<<0)
2564 #define BCE_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3)
2565 #define BCE_MISC_BIST_CS1_MBIST_DONE (1L<<8)
2566 #define BCE_MISC_BIST_CS1_MBIST_GO (1L<<9)
2570 #define BCE_MISC_BIST_CS2_MBIST_EN (1L<<0)
2572 #define BCE_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3)
2573 #define BCE_MISC_BIST_CS2_MBIST_DONE (1L<<8)
2574 #define BCE_MISC_BIST_CS2_MBIST_GO (1L<<9)
2578 #define BCE_MISC_BIST_CS3_MBIST_EN (1L<<0)
2580 #define BCE_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3)
2581 #define BCE_MISC_BIST_CS3_MBIST_DONE (1L<<8)
2582 #define BCE_MISC_BIST_CS3_MBIST_GO (1L<<9)
2586 #define BCE_MISC_BIST_CS4_MBIST_EN (1L<<0)
2588 #define BCE_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3)
2589 #define BCE_MISC_BIST_CS4_MBIST_DONE (1L<<8)
2590 #define BCE_MISC_BIST_CS4_MBIST_GO (1L<<9)
2594 #define BCE_MISC_BIST_CS5_MBIST_EN (1L<<0)
2596 #define BCE_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3)
2597 #define BCE_MISC_BIST_CS5_MBIST_DONE (1L<<8)
2598 #define BCE_MISC_BIST_CS5_MBIST_GO (1L<<9)
2608 #define BCE_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0)
2609 #define BCE_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1)
2612 #define BCE_MISC_USPLL_CTRL_VC_EN (1L<<10)
2616 #define BCE_MISC_USPLL_CTRL_TESTD_EN (1L<<19)
2618 #define BCE_MISC_USPLL_CTRL_TESTA_EN (1L<<23)
2620 #define BCE_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26)
2621 #define BCE_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27)
2622 #define BCE_MISC_USPLL_CTRL_ANALOG_RST (1L<<28)
2623 #define BCE_MISC_USPLL_CTRL_LOCK (1L<<29)
2626 #define BCE_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0)
2627 #define BCE_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1)
2628 #define BCE_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2)
2629 #define BCE_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3)
2630 #define BCE_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4)
2631 #define BCE_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5)
2632 #define BCE_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6)
2633 #define BCE_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7)
2634 #define BCE_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8)
2635 #define BCE_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9)
2636 #define BCE_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10)
2637 #define BCE_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11)
2638 #define BCE_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12)
2639 #define BCE_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13)
2640 #define BCE_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14)
2641 #define BCE_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15)
2642 #define BCE_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16)
2643 #define BCE_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17)
2644 #define BCE_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18)
2645 #define BCE_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19)
2646 #define BCE_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20)
2647 #define BCE_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21)
2648 #define BCE_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22)
2649 #define BCE_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23)
2650 #define BCE_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24)
2651 #define BCE_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25)
2652 #define BCE_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26)
2653 #define BCE_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27)
2654 #define BCE_MISC_PERR_STATUS0_THBUF_PERR (1L<<28)
2655 #define BCE_MISC_PERR_STATUS0_TDMA_PERR (1L<<29)
2656 #define BCE_MISC_PERR_STATUS0_TBDC_PERR (1L<<30)
2657 #define BCE_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31)
2660 #define BCE_MISC_PERR_STATUS1_RBDC_PERR (1L<<0)
2661 #define BCE_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2)
2662 #define BCE_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3)
2663 #define BCE_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4)
2664 #define BCE_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5)
2665 #define BCE_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6)
2666 #define BCE_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7)
2667 #define BCE_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8)
2668 #define BCE_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9)
2669 #define BCE_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10)
2670 #define BCE_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11)
2671 #define BCE_MISC_PERR_STATUS1_COMQ_PERR (1L<<12)
2672 #define BCE_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13)
2673 #define BCE_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14)
2674 #define BCE_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15)
2675 #define BCE_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16)
2676 #define BCE_MISC_PERR_STATUS1_TASQ_PERR (1L<<17)
2677 #define BCE_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18)
2678 #define BCE_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19)
2679 #define BCE_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20)
2680 #define BCE_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21)
2681 #define BCE_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22)
2682 #define BCE_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23)
2683 #define BCE_MISC_PERR_STATUS1_CPQ_PERR (1L<<24)
2684 #define BCE_MISC_PERR_STATUS1_CSQ_PERR (1L<<25)
2685 #define BCE_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26)
2686 #define BCE_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27)
2687 #define BCE_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28)
2688 #define BCE_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29)
2691 #define BCE_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0)
2692 #define BCE_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1)
2693 #define BCE_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2)
2694 #define BCE_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3)
2695 #define BCE_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4)
2696 #define BCE_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5)
2697 #define BCE_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6)
2701 #define BCE_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0)
2702 #define BCE_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0)
2703 #define BCE_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0)
2704 #define BCE_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0)
2706 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3)
2707 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3)
2708 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3)
2709 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3)
2713 #define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11)
2714 #define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11)
2715 #define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11)
2716 #define BCE_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13)
2717 #define BCE_MISC_LCPLL_CTRL0_RESERVED (1L<<14)
2718 #define BCE_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15)
2719 #define BCE_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16)
2720 #define BCE_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17)
2721 #define BCE_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18)
2722 #define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19)
2723 #define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20)
2724 #define BCE_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21)
2725 #define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22)
2726 #define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23)
2727 #define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24)
2728 #define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25)
2729 #define BCE_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26)
2730 #define BCE_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27)
2734 #define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5)
2735 #define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6)
2736 #define BCE_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7)
2739 #define BCE_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0)
2740 #define BCE_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1)
2741 #define BCE_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2)
2742 #define BCE_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3)
2746 #define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15)
2747 #define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15)
2748 #define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15)
2751 #define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5)
2752 #define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5)
2753 #define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5)
2755 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6)
2756 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6)
2757 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6)
2758 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6)
2760 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8)
2761 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8)
2762 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8)
2763 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8)
2765 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10)
2766 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10)
2767 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10)
2768 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10)
2775 #define BCE_DMA_COMMAND_ENABLE (1L<<0)
2778 #define BCE_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
2779 #define BCE_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
2780 #define BCE_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
2781 #define BCE_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
2782 #define BCE_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
2783 #define BCE_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
2784 #define BCE_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
2785 #define BCE_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
2786 #define BCE_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
2787 #define BCE_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
2788 #define BCE_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
2791 #define BCE_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
2792 #define BCE_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
2793 #define BCE_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
2794 #define BCE_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
2795 #define BCE_DMA_CONFIG_ONE_DMA (1L<<6)
2796 #define BCE_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
2797 #define BCE_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
2798 #define BCE_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
2799 #define BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
2803 #define BCE_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
2818 #define BCE_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3)
2820 #define BCE_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7)
2822 #define BCE_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11)
2824 #define BCE_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15)
2826 #define BCE_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19)
2828 #define BCE_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23)
2830 #define BCE_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27)
2832 #define BCE_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31)
2836 #define BCE_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3)
2838 #define BCE_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7)
2840 #define BCE_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11)
2842 #define BCE_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15)
2844 #define BCE_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19)
2846 #define BCE_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23)
2848 #define BCE_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27)
2850 #define BCE_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31)
2880 #define BCE_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16)
2881 #define BCE_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17)
2882 #define BCE_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18)
2913 #define BCE_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
2914 #define BCE_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
2915 #define BCE_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
2954 #define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
2955 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
2956 #define BCE_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
2957 #define BCE_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
2962 #define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
2963 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
2964 #define BCE_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
2965 #define BCE_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
2970 #define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
2971 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
2972 #define BCE_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
2973 #define BCE_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
2983 #define BCE_CTX_COMMAND_ENABLED (1L<<0)
2984 #define BCE_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1)
2985 #define BCE_CTX_COMMAND_DISABLE_PLRU (1L<<2)
2986 #define BCE_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3)
2988 #define BCE_CTX_COMMAND_MEM_INIT (1L<<13)
2990 #define BCE_CTX_COMMAND_PAGE_SIZE_256 (0L<<16)
2991 #define BCE_CTX_COMMAND_PAGE_SIZE_512 (1L<<16)
2992 #define BCE_CTX_COMMAND_PAGE_SIZE_1K (2L<<16)
2993 #define BCE_CTX_COMMAND_PAGE_SIZE_2K (3L<<16)
2994 #define BCE_CTX_COMMAND_PAGE_SIZE_4K (4L<<16)
2995 #define BCE_CTX_COMMAND_PAGE_SIZE_8K (5L<<16)
2996 #define BCE_CTX_COMMAND_PAGE_SIZE_16K (6L<<16)
2997 #define BCE_CTX_COMMAND_PAGE_SIZE_32K (7L<<16)
2998 #define BCE_CTX_COMMAND_PAGE_SIZE_64K (8L<<16)
2999 #define BCE_CTX_COMMAND_PAGE_SIZE_128K (9L<<16)
3000 #define BCE_CTX_COMMAND_PAGE_SIZE_256K (10L<<16)
3001 #define BCE_CTX_COMMAND_PAGE_SIZE_512K (11L<<16)
3002 #define BCE_CTX_COMMAND_PAGE_SIZE_1M (12L<<16)
3005 #define BCE_CTX_STATUS_LOCK_WAIT (1L<<0)
3006 #define BCE_CTX_STATUS_READ_STAT (1L<<16)
3007 #define BCE_CTX_STATUS_WRITE_STAT (1L<<17)
3008 #define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18)
3009 #define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
3010 #define BCE_CTX_STATUS_EXT_READ_STAT (1L<<20)
3011 #define BCE_CTX_STATUS_EXT_WRITE_STAT (1L<<21)
3012 #define BCE_CTX_STATUS_MISS_STAT (1L<<22)
3013 #define BCE_CTX_STATUS_HIT_STAT (1L<<23)
3014 #define BCE_CTX_STATUS_DEAD_LOCK (1L<<24)
3015 #define BCE_CTX_STATUS_USAGE_CNT_ERR (1L<<25)
3016 #define BCE_CTX_STATUS_INVALID_PAGE (1L<<26)
3035 #define BCE_CTX_LOCK_TYPE_VOID_XI (0L<<0)
3036 #define BCE_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0)
3037 #define BCE_CTX_LOCK_TYPE_TX_XI (2L<<0)
3038 #define BCE_CTX_LOCK_TYPE_TIMER_XI (4L<<0)
3039 #define BCE_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0)
3041 #define BCE_CTX_LOCK_GRANTED (1L<<26)
3046 #define BCE_CTX_LOCK_STATUS (1L<<30)
3047 #define BCE_CTX_LOCK_REQ (1L<<31)
3052 #define BCE_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23)
3054 #define BCE_CTX_CTX_CTRL_ATTR (1L<<26)
3055 #define BCE_CTX_CTX_CTRL_WRITE_REQ (1L<<30)
3056 #define BCE_CTX_CTX_CTRL_READ_REQ (1L<<31)
3074 #define BCE_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0)
3075 #define BCE_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1)
3076 #define BCE_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6)
3079 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19)
3080 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20)
3081 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21)
3082 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22)
3083 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23)
3084 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24)
3085 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25)
3086 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26)
3087 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27)
3088 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28)
3089 #define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29)
3118 #define BCE_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16)
3119 #define BCE_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17)
3120 #define BCE_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18)
3129 #define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
3130 #define BCE_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14)
3146 #define BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30)
3147 #define BCE_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31)
3150 #define BCE_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0)
3156 #define BCE_CTX_CAM_CTRL_RESET (1L<<27)
3157 #define BCE_CTX_CAM_CTRL_INVALIDATE (1L<<28)
3158 #define BCE_CTX_CAM_CTRL_SEARCH (1L<<29)
3159 #define BCE_CTX_CAM_CTRL_WRITE_REQ (1L<<30)
3160 #define BCE_CTX_CAM_CTRL_READ_REQ (1L<<31)
3167 #define BCE_EMAC_MODE_RESET (1L<<0)
3168 #define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1)
3170 #define BCE_EMAC_MODE_PORT_NONE (0L<<2)
3171 #define BCE_EMAC_MODE_PORT_MII (1L<<2)
3172 #define BCE_EMAC_MODE_PORT_GMII (2L<<2)
3173 #define BCE_EMAC_MODE_PORT_MII_10 (3L<<2)
3174 #define BCE_EMAC_MODE_MAC_LOOP (1L<<4)
3175 #define BCE_EMAC_MODE_25G (1L<<5)
3176 #define BCE_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
3177 #define BCE_EMAC_MODE_TX_BURST (1L<<8)
3178 #define BCE_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
3179 #define BCE_EMAC_MODE_EXT_LINK_POL (1L<<10)
3180 #define BCE_EMAC_MODE_FORCE_LINK (1L<<11)
3181 #define BCE_EMAC_MODE_MPKT (1L<<18)
3182 #define BCE_EMAC_MODE_MPKT_RCVD (1L<<19)
3183 #define BCE_EMAC_MODE_ACPI_RCVD (1L<<20)
3186 #define BCE_EMAC_STATUS_LINK (1L<<11)
3187 #define BCE_EMAC_STATUS_LINK_CHANGE (1L<<12)
3188 #define BCE_EMAC_STATUS_MI_COMPLETE (1L<<22)
3189 #define BCE_EMAC_STATUS_MI_INT (1L<<23)
3190 #define BCE_EMAC_STATUS_AP_ERROR (1L<<24)
3191 #define BCE_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
3194 #define BCE_EMAC_ATTENTION_ENA_LINK (1L<<11)
3195 #define BCE_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
3196 #define BCE_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
3197 #define BCE_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
3200 #define BCE_EMAC_LED_OVERRIDE (1L<<0)
3201 #define BCE_EMAC_LED_1000MB_OVERRIDE (1L<<1)
3202 #define BCE_EMAC_LED_100MB_OVERRIDE (1L<<2)
3203 #define BCE_EMAC_LED_10MB_OVERRIDE (1L<<3)
3204 #define BCE_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
3205 #define BCE_EMAC_LED_BLNK_TRAFFIC (1L<<5)
3206 #define BCE_EMAC_LED_TRAFFIC (1L<<6)
3207 #define BCE_EMAC_LED_1000MB (1L<<7)
3208 #define BCE_EMAC_LED_100MB (1L<<8)
3209 #define BCE_EMAC_LED_10MB (1L<<9)
3210 #define BCE_EMAC_LED_TRAFFIC_STAT (1L<<10)
3212 #define BCE_EMAC_LED_BLNK_RATE_ENA (1L<<31)
3251 #define BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
3256 #define BCE_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
3258 #define BCE_EMAC_SERDES_CNTL_BGMAX (1L<<10)
3259 #define BCE_EMAC_SERDES_CNTL_BGMIN (1L<<11)
3260 #define BCE_EMAC_SERDES_CNTL_TXMODE (1L<<12)
3261 #define BCE_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
3262 #define BCE_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
3263 #define BCE_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
3264 #define BCE_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
3265 #define BCE_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
3266 #define BCE_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
3267 #define BCE_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
3273 #define BCE_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
3280 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
3281 #define BCE_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
3282 #define BCE_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
3283 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
3284 #define BCE_EMAC_MDIO_COMM_FAIL (1L<<28)
3285 #define BCE_EMAC_MDIO_COMM_START_BUSY (1L<<29)
3286 #define BCE_EMAC_MDIO_COMM_DISEXT (1L<<30)
3289 #define BCE_EMAC_MDIO_STATUS_LINK (1L<<0)
3290 #define BCE_EMAC_MDIO_STATUS_10MB (1L<<1)
3293 #define BCE_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
3294 #define BCE_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
3295 #define BCE_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
3296 #define BCE_EMAC_MDIO_MODE_MDIO (1L<<9)
3297 #define BCE_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
3298 #define BCE_EMAC_MDIO_MODE_MDC (1L<<11)
3299 #define BCE_EMAC_MDIO_MODE_MDINT (1L<<12)
3303 #define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
3306 #define BCE_EMAC_TX_MODE_RESET (1L<<0)
3307 #define BCE_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
3308 #define BCE_EMAC_TX_MODE_FLOW_EN (1L<<4)
3309 #define BCE_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
3310 #define BCE_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
3311 #define BCE_EMAC_TX_MODE_LINK_AWARE (1L<<7)
3314 #define BCE_EMAC_TX_STATUS_XOFFED (1L<<0)
3315 #define BCE_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
3316 #define BCE_EMAC_TX_STATUS_XON_SENT (1L<<2)
3317 #define BCE_EMAC_TX_STATUS_LINK_UP (1L<<3)
3318 #define BCE_EMAC_TX_STATUS_UNDERRUN (1L<<4)
3326 #define BCE_EMAC_RX_MODE_RESET (1L<<0)
3327 #define BCE_EMAC_RX_MODE_FLOW_EN (1L<<2)
3328 #define BCE_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
3329 #define BCE_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
3330 #define BCE_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
3331 #define BCE_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
3332 #define BCE_EMAC_RX_MODE_LLC_CHK (1L<<7)
3333 #define BCE_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
3334 #define BCE_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
3335 #define BCE_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
3336 #define BCE_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
3337 #define BCE_EMAC_RX_MODE_SORT_MODE (1L<<12)
3340 #define BCE_EMAC_RX_STATUS_FFED (1L<<0)
3341 #define BCE_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
3342 #define BCE_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
3377 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
3378 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
3379 #define BCE_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
3380 #define BCE_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
3381 #define BCE_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
3382 #define BCE_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
3383 #define BCE_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
3408 #define BCE_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
3409 #define BCE_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
3410 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
3411 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
3412 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
3463 #define BCE_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
3464 #define BCE_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
3465 #define BCE_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
3466 #define BCE_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
3467 #define BCE_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26)
3468 #define BCE_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
3469 #define BCE_EMAC_RXMAC_DEBUG4_START (1L<<28)
3473 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
3474 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
3475 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
3476 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
3477 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
3478 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
3479 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
3488 #define BCE_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
3490 #define BCE_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
3491 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
3492 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
3493 #define BCE_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
3494 #define BCE_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
3496 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
3556 #define BCE_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
3557 #define BCE_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
3559 #define BCE_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
3560 #define BCE_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
3561 #define BCE_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
3562 #define BCE_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
3563 #define BCE_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
3571 #define BCE_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
3598 #define BCE_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
3599 #define BCE_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
3619 #define BCE_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
3620 #define BCE_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
3621 #define BCE_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
3622 #define BCE_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
3623 #define BCE_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
3624 #define BCE_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
3625 #define BCE_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
3626 #define BCE_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
3627 #define BCE_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
3628 #define BCE_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
3629 #define BCE_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
3630 #define BCE_EMAC_TXMAC_DEBUG4_GO (1L<<31)
3661 #define BCE_RPM_COMMAND_ENABLED (1L<<0)
3662 #define BCE_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
3665 #define BCE_RPM_STATUS_MBUF_WAIT (1L<<0)
3666 #define BCE_RPM_STATUS_FREE_WAIT (1L<<1)
3669 #define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
3670 #define BCE_RPM_CONFIG_ACPI_ENA (1L<<1)
3671 #define BCE_RPM_CONFIG_ACPI_KEEP (1L<<2)
3672 #define BCE_RPM_CONFIG_MP_KEEP (1L<<3)
3674 #define BCE_RPM_CONFIG_IGNORE_VLAN (1L<<31)
3677 #define BCE_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN (1L<<30)
3678 #define BCE_RPM_MGMT_PKT_CTRL_MGMT_EN (1L<<31)
3694 #define BCE_RPM_SORT_USER0_BC_EN (1L<<16)
3695 #define BCE_RPM_SORT_USER0_MC_EN (1L<<17)
3696 #define BCE_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
3697 #define BCE_RPM_SORT_USER0_PROM_EN (1L<<19)
3699 #define BCE_RPM_SORT_USER0_PROM_VLAN (1L<<24)
3700 #define BCE_RPM_SORT_USER0_ENA (1L<<31)
3704 #define BCE_RPM_SORT_USER1_BC_EN (1L<<16)
3705 #define BCE_RPM_SORT_USER1_MC_EN (1L<<17)
3706 #define BCE_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
3707 #define BCE_RPM_SORT_USER1_PROM_EN (1L<<19)
3709 #define BCE_RPM_SORT_USER1_PROM_VLAN (1L<<24)
3710 #define BCE_RPM_SORT_USER1_ENA (1L<<31)
3714 #define BCE_RPM_SORT_USER2_BC_EN (1L<<16)
3715 #define BCE_RPM_SORT_USER2_MC_EN (1L<<17)
3716 #define BCE_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
3717 #define BCE_RPM_SORT_USER2_PROM_EN (1L<<19)
3719 #define BCE_RPM_SORT_USER2_PROM_VLAN (1L<<24)
3720 #define BCE_RPM_SORT_USER2_ENA (1L<<31)
3724 #define BCE_RPM_SORT_USER3_BC_EN (1L<<16)
3725 #define BCE_RPM_SORT_USER3_MC_EN (1L<<17)
3726 #define BCE_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
3727 #define BCE_RPM_SORT_USER3_PROM_EN (1L<<19)
3729 #define BCE_RPM_SORT_USER3_PROM_VLAN (1L<<24)
3730 #define BCE_RPM_SORT_USER3_ENA (1L<<31)
3745 #define BCE_RPM_RC_CNTL_0_PRIORITY (1L<<11)
3746 #define BCE_RPM_RC_CNTL_0_P4 (1L<<12)
3748 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
3749 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
3750 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
3751 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
3752 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
3754 #define BCE_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
3755 #define BCE_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
3756 #define BCE_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
3757 #define BCE_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
3758 #define BCE_RPM_RC_CNTL_0_SBIT (1L<<19)
3760 #define BCE_RPM_RC_CNTL_0_MAP (1L<<24)
3761 #define BCE_RPM_RC_CNTL_0_DISCARD (1L<<25)
3762 #define BCE_RPM_RC_CNTL_0_MASK (1L<<26)
3763 #define BCE_RPM_RC_CNTL_0_P1 (1L<<27)
3764 #define BCE_RPM_RC_CNTL_0_P2 (1L<<28)
3765 #define BCE_RPM_RC_CNTL_0_P3 (1L<<29)
3766 #define BCE_RPM_RC_CNTL_0_NBIT (1L<<30)
3853 #define BCE_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
3854 #define BCE_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
3855 #define BCE_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
3856 #define BCE_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
3857 #define BCE_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
3858 #define BCE_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
3859 #define BCE_RPM_DEBUG0_LLC_SNAP (1L<<22)
3860 #define BCE_RPM_DEBUG0_FM_STARTED (1L<<23)
3861 #define BCE_RPM_DEBUG0_DONE (1L<<24)
3862 #define BCE_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
3863 #define BCE_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
3864 #define BCE_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
3865 #define BCE_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
3866 #define BCE_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
3870 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
3871 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
3872 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
3873 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
3874 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
3875 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
3876 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
3877 #define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
3878 #define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
3879 #define BCE_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
3880 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
3881 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
3882 #define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
3887 #define BCE_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
3888 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
3889 #define BCE_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
3890 #define BCE_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
3895 #define BCE_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
3896 #define BCE_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
3897 #define BCE_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
3898 #define BCE_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
3899 #define BCE_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
3900 #define BCE_RPM_DEBUG2_FM_DISCARD (1L<<29)
3901 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
3902 #define BCE_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
3906 #define BCE_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
3907 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
3908 #define BCE_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
3909 #define BCE_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
3910 #define BCE_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
3911 #define BCE_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
3912 #define BCE_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
3914 #define BCE_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
3915 #define BCE_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
3916 #define BCE_RPM_DEBUG3_DROP_NXT (1L<<23)
3930 #define BCE_RPM_DEBUG3_MBFREE_FSM (1L<<29)
3931 #define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
3932 #define BCE_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
3933 #define BCE_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
3936 #define BCE_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
3942 #define BCE_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
3949 #define BCE_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
3950 #define BCE_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
3951 #define BCE_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
3952 #define BCE_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
3953 #define BCE_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
3954 #define BCE_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
3955 #define BCE_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
3956 #define BCE_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
3957 #define BCE_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
3958 #define BCE_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
3959 #define BCE_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
3960 #define BCE_RPM_DEBUG5_HOLDREG_RD (1L<<31)
3971 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
3972 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
3973 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
3974 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
3975 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
3976 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
3977 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
3978 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
3979 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
3980 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
3981 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
3982 #define BCE_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
3983 #define BCE_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
3984 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
3985 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
3986 #define BCE_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
3987 #define BCE_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
3988 #define BCE_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
3989 #define BCE_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
3990 #define BCE_RPM_DEBUG8_EOF_DET (1L<<12)
3991 #define BCE_RPM_DEBUG8_SOF_DET (1L<<13)
3992 #define BCE_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
3993 #define BCE_RPM_DEBUG8_ALL_DONE (1L<<15)
3999 #define BCE_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
4001 #define BCE_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
4002 #define BCE_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
4003 #define BCE_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
4004 #define BCE_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
4056 #define BCE_TIMER_COMMAND_ENABLED (1L<<0)
4059 #define BCE_TIMER_STATUS_CMP_FTQ_WAIT (1L<<0)
4060 #define BCE_TIMER_STATUS_POLL_PASS_CNT (1L<<8)
4061 #define BCE_TIMER_STATUS_TMR1_CNT (1L<<9)
4062 #define BCE_TIMER_STATUS_TMR2_CNT (1L<<10)
4063 #define BCE_TIMER_STATUS_TMR3_CNT (1L<<11)
4064 #define BCE_TIMER_STATUS_TMR4_CNT (1L<<12)
4065 #define BCE_TIMER_STATUS_TMR5_CNT (1L<<13)
4084 #define BCE_RBUF_COMMAND_ENABLED (1L<<0)
4085 #define BCE_RBUF_COMMAND_FREE_INIT (1L<<1)
4086 #define BCE_RBUF_COMMAND_RAM_INIT (1L<<2)
4087 #define BCE_RBUF_COMMAND_OVER_FREE (1L<<4)
4088 #define BCE_RBUF_COMMAND_ALLOC_REQ (1L<<5)
4131 #define BCE_RV2P_COMMAND_ENABLED (1L<<0)
4132 #define BCE_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
4133 #define BCE_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
4134 #define BCE_RV2P_COMMAND_ABORT0 (1L<<4)
4135 #define BCE_RV2P_COMMAND_ABORT1 (1L<<5)
4136 #define BCE_RV2P_COMMAND_ABORT2 (1L<<6)
4137 #define BCE_RV2P_COMMAND_ABORT3 (1L<<7)
4138 #define BCE_RV2P_COMMAND_ABORT4 (1L<<8)
4139 #define BCE_RV2P_COMMAND_ABORT5 (1L<<9)
4140 #define BCE_RV2P_COMMAND_PROC1_RESET (1L<<16)
4141 #define BCE_RV2P_COMMAND_PROC2_RESET (1L<<17)
4142 #define BCE_RV2P_COMMAND_CTXIF_RESET (1L<<18)
4145 #define BCE_RV2P_STATUS_ALWAYS_0 (1L<<0)
4146 #define BCE_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
4147 #define BCE_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
4148 #define BCE_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
4149 #define BCE_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
4150 #define BCE_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
4151 #define BCE_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
4154 #define BCE_RV2P_CONFIG_STALL_PROC1 (1L<<0)
4155 #define BCE_RV2P_CONFIG_STALL_PROC2 (1L<<1)
4156 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
4157 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
4158 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
4159 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
4160 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
4161 #define BCE_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
4162 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
4163 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
4164 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
4165 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
4166 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
4167 #define BCE_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
4169 #define BCE_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
4170 #define BCE_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
4171 #define BCE_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
4172 #define BCE_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
4173 #define BCE_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
4174 #define BCE_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
4175 #define BCE_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
4176 #define BCE_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
4177 #define BCE_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
4178 #define BCE_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
4179 #define BCE_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
4180 #define BCE_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
4181 #define BCE_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
4201 #define BCE_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
4205 #define BCE_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
4212 #define BCE_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4215 #define BCE_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4221 #define BCE_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
4222 #define BCE_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
4223 #define BCE_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
4224 #define BCE_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
4225 #define BCE_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
4226 #define BCE_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
4227 #define BCE_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
4228 #define BCE_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
4229 #define BCE_RV2P_PFTQ_CMD_POP (1L<<30)
4230 #define BCE_RV2P_PFTQ_CMD_BUSY (1L<<31)
4233 #define BCE_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
4234 #define BCE_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
4235 #define BCE_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
4242 #define BCE_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
4243 #define BCE_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
4244 #define BCE_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
4245 #define BCE_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
4246 #define BCE_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
4247 #define BCE_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
4248 #define BCE_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
4249 #define BCE_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
4250 #define BCE_RV2P_TFTQ_CMD_POP (1L<<30)
4251 #define BCE_RV2P_TFTQ_CMD_BUSY (1L<<31)
4254 #define BCE_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
4255 #define BCE_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
4256 #define BCE_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
4263 #define BCE_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
4264 #define BCE_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
4265 #define BCE_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
4266 #define BCE_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
4267 #define BCE_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
4268 #define BCE_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
4269 #define BCE_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
4270 #define BCE_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
4271 #define BCE_RV2P_MFTQ_CMD_POP (1L<<30)
4272 #define BCE_RV2P_MFTQ_CMD_BUSY (1L<<31)
4275 #define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
4276 #define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
4277 #define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
4286 #define BCE_MQ_COMMAND_ENABLED (1L<<0)
4287 #define BCE_MQ_COMMAND_INIT (1L<<1)
4288 #define BCE_MQ_COMMAND_OVERFLOW (1L<<4)
4289 #define BCE_MQ_COMMAND_WR_ERROR (1L<<5)
4290 #define BCE_MQ_COMMAND_RD_ERROR (1L<<6)
4291 #define BCE_MQ_COMMAND_IDB_CFG_ERROR (1L<<7)
4292 #define BCE_MQ_COMMAND_IDB_OVERFLOW (1L<<10)
4293 #define BCE_MQ_COMMAND_NO_BIN_ERROR (1L<<11)
4294 #define BCE_MQ_COMMAND_NO_MAP_ERROR (1L<<12)
4297 #define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
4298 #define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
4299 #define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18)
4300 #define BCE_MQ_STATUS_IDB_OFLOW_STAT (1L<<19)
4303 #define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
4304 #define BCE_MQ_CONFIG_HALT_DIS (1L<<1)
4305 #define BCE_MQ_CONFIG_BIN_MQ_MODE (1L<<2)
4306 #define BCE_MQ_CONFIG_DIS_IDB_DROP (1L<<3)
4308 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
4309 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
4310 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
4311 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
4312 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
4320 #define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28)
4414 #define BCE_TBDR_COMMAND_ENABLE (1L<<0)
4415 #define BCE_TBDR_COMMAND_SOFT_RST (1L<<1)
4416 #define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4)
4419 #define BCE_TBDR_STATUS_DMA_WAIT (1L<<0)
4420 #define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1)
4421 #define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
4422 #define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
4423 #define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
4424 #define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
4425 #define BCE_TBDR_STATUS_BURST_CNT (1L<<6)
4429 #define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8)
4430 #define BCE_TBDR_CONFIG_PRIORITY (1L<<9)
4431 #define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
4433 #define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
4434 #define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
4435 #define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
4436 #define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
4437 #define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
4438 #define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
4439 #define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
4440 #define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
4441 #define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
4442 #define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
4443 #define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
4444 #define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
4445 #define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
4449 #define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4452 #define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4458 #define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10)
4459 #define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
4460 #define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
4461 #define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
4462 #define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26)
4463 #define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
4464 #define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
4465 #define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
4466 #define BCE_TBDR_FTQ_CMD_POP (1L<<30)
4467 #define BCE_TBDR_FTQ_CMD_BUSY (1L<<31)
4470 #define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0)
4471 #define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
4472 #define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4481 #define BCE_TDMA_COMMAND_ENABLED (1L<<0)
4482 #define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4)
4483 #define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
4486 #define BCE_TDMA_STATUS_DMA_WAIT (1L<<0)
4487 #define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
4488 #define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
4489 #define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3)
4490 #define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
4491 #define BCE_TDMA_STATUS_BURST_CNT (1L<<17)
4494 #define BCE_TDMA_CONFIG_ONE_DMA (1L<<0)
4495 #define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1)
4497 #define BCE_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
4502 #define BCE_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
4503 #define BCE_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
4504 #define BCE_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
4505 #define BCE_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
4506 #define BCE_TDMA_CONFIG_ALIGN_ENA (1L<<15)
4507 #define BCE_TDMA_CONFIG_CHK_L2_BD (1L<<16)
4516 #define BCE_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
4519 #define BCE_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
4520 #define BCE_TDMA_DMAD_FSM_DR_INTF (1L<<16)
4547 #define BCE_TDMA_FTQ_CMD_WR_TOP (1L<<10)
4548 #define BCE_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
4549 #define BCE_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
4550 #define BCE_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
4551 #define BCE_TDMA_FTQ_CMD_RD_DATA (1L<<26)
4552 #define BCE_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
4553 #define BCE_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
4554 #define BCE_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
4555 #define BCE_TDMA_FTQ_CMD_POP (1L<<30)
4556 #define BCE_TDMA_FTQ_CMD_BUSY (1L<<31)
4559 #define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0)
4560 #define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
4561 #define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4570 #define BCE_NVM_COMMAND_RST (1L<<0)
4571 #define BCE_NVM_COMMAND_DONE (1L<<3)
4572 #define BCE_NVM_COMMAND_DOIT (1L<<4)
4573 #define BCE_NVM_COMMAND_WR (1L<<5)
4574 #define BCE_NVM_COMMAND_ERASE (1L<<6)
4575 #define BCE_NVM_COMMAND_FIRST (1L<<7)
4576 #define BCE_NVM_COMMAND_LAST (1L<<8)
4577 #define BCE_NVM_COMMAND_WREN (1L<<16)
4578 #define BCE_NVM_COMMAND_WRDI (1L<<17)
4579 #define BCE_NVM_COMMAND_EWSR (1L<<18)
4580 #define BCE_NVM_COMMAND_WRSR (1L<<19)
4589 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
4590 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
4591 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
4592 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
4593 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
4594 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
4595 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
4599 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
4600 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
4601 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
4602 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
4603 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
4604 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
4605 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
4609 #define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
4610 #define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
4611 #define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
4612 #define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
4613 #define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
4614 #define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
4615 #define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
4618 #define BCE_NVM_CFG1_FLASH_MODE (1L<<0)
4619 #define BCE_NVM_CFG1_BUFFER_MODE (1L<<1)
4620 #define BCE_NVM_CFG1_PASS_MODE (1L<<2)
4621 #define BCE_NVM_CFG1_BITBANG_MODE (1L<<3)
4623 #define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
4624 #define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
4627 #define BCE_NVM_CFG1_PROTECT_MODE (1L<<24)
4628 #define BCE_NVM_CFG1_FLASH_SIZE (1L<<25)
4629 #define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
4643 #define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
4644 #define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
4645 #define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
4646 #define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
4647 #define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
4648 #define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
4649 #define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
4650 #define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
4651 #define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8)
4652 #define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9)
4653 #define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10)
4654 #define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11)
4655 #define BCE_NVM_SW_ARB_REQ0 (1L<<12)
4656 #define BCE_NVM_SW_ARB_REQ1 (1L<<13)
4657 #define BCE_NVM_SW_ARB_REQ2 (1L<<14)
4658 #define BCE_NVM_SW_ARB_REQ3 (1L<<15)
4661 #define BCE_NVM_ACCESS_ENABLE_EN (1L<<0)
4662 #define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
4674 #define BCE_HC_COMMAND_ENABLE (1L<<0)
4675 #define BCE_HC_COMMAND_SKIP_ABORT (1L<<4)
4676 #define BCE_HC_COMMAND_COAL_NOW (1L<<16)
4677 #define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
4678 #define BCE_HC_COMMAND_STATS_NOW (1L<<18)
4680 #define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19)
4681 #define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
4682 #define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19)
4683 #define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19)
4684 #define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21)
4685 #define BCE_HC_COMMAND_MAIN_PWR_INT (1L<<22)
4686 #define BCE_HC_COMMAND_COAL_ON_NEXT_EVENT (1L<<27)
4689 #define BCE_HC_STATUS_MASTER_ABORT (1L<<0)
4690 #define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
4691 #define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
4692 #define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
4693 #define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
4694 #define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
4695 #define BCE_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
4696 #define BCE_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
4697 #define BCE_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
4698 #define BCE_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
4701 #define BCE_HC_CONFIG_COLLECT_STATS (1L<<0)
4702 #define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1)
4703 #define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2)
4704 #define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3)
4705 #define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4)
4706 #define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
4707 #define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6)
4709 #define BCE_HC_CONFIG_PER_MODE (1L<<16)
4710 #define BCE_HC_CONFIG_ONE_SHOT (1L<<17)
4711 #define BCE_HC_CONFIG_USE_INT_PARAM (1L<<18)
4712 #define BCE_HC_CONFIG_SET_MASK_AT_RD (1L<<19)
4715 #define BCE_HC_CONFIG_SB_ADDR_INC_64B (0L<<24)
4716 #define BCE_HC_CONFIG_SB_ADDR_INC_128B (1L<<24)
4717 #define BCE_HC_CONFIG_SB_ADDR_INC_256B (2L<<24)
4718 #define BCE_HC_CONFIG_SB_ADDR_INC_512B (3L<<24)
4719 #define BCE_HC_CONFIG_SB_ADDR_INC_1024B (4L<<24)
4720 #define BCE_HC_CONFIG_SB_ADDR_INC_2048B (5L<<24)
4721 #define BCE_HC_CONFIG_SB_ADDR_INC_4096B (6L<<24)
4722 #define BCE_HC_CONFIG_SB_ADDR_INC_8192B (7L<<24)
4723 #define BCE_HC_CONFIG_GEN_STAT_AVG_INTR (1L<<29)
4724 #define BCE_HC_CONFIG_UNMASK_ALL (1L<<30)
4725 #define BCE_HC_CONFIG_TX_SEL (1L<<31)
4777 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
4778 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
4779 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
4780 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
4781 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
4782 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
4783 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
4784 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
4785 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
4786 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
4787 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
4788 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
4789 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
4790 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
4791 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
4792 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
4793 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
4794 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
4795 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
4796 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
4797 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
4798 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
4799 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
4800 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
4801 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
4802 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
4803 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
4804 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
4805 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
4806 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
4807 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
4808 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
4809 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
4810 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
4811 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
4812 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
4813 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
4814 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
4815 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
4816 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
4817 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
4818 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
4819 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
4820 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
4821 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
4822 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
4823 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
4824 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
4825 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
4826 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
4827 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
4828 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
4829 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
4830 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
4831 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
4832 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
4833 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
4834 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
4835 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
4836 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
4837 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
4838 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
4839 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
4840 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
4841 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
4842 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
4843 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
4844 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
4845 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
4846 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
4847 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
4848 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
4849 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
4850 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
4851 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
4852 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
4853 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
4854 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
4855 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
4856 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
4857 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
4858 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
4859 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
4860 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
4861 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
4862 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
4863 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
4864 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
4865 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
4866 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
4867 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
4868 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
4869 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
4870 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
4871 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
4872 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
4873 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
4874 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
4875 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
4876 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
4877 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
4878 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
4879 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
4880 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
4881 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
4882 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
4883 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
4884 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
4885 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
4886 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
4887 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
4888 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
4889 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
4890 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
4891 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
4892 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
4893 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
4894 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
4895 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
4896 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
4897 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
4898 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
4903 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52L<<0)
4904 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57L<<0)
4905 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58L<<0)
4906 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85L<<0)
4907 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86L<<0)
4908 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87L<<0)
4909 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88L<<0)
4910 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89L<<0)
4911 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90L<<0)
4912 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91L<<0)
4913 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92L<<0)
4914 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93L<<0)
4915 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94L<<0)
4916 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123L<<0)
4917 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124L<<0)
4918 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125L<<0)
4919 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126L<<0)
4920 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128L<<0)
4921 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129L<<0)
4922 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130L<<0)
4923 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131L<<0)
4924 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132L<<0)
4925 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133L<<0)
4926 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134L<<0)
4927 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135L<<0)
4928 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136L<<0)
4929 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137L<<0)
4930 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138L<<0)
4931 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139L<<0)
4932 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140L<<0)
4933 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141L<<0)
4934 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142L<<0)
4935 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143L<<0)
4936 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144L<<0)
4937 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145L<<0)
4938 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146L<<0)
4939 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147L<<0)
4940 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148L<<0)
4941 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149L<<0)
4942 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150L<<0)
4943 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151L<<0)
4944 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152L<<0)
4945 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153L<<0)
4946 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154L<<0)
4947 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155L<<0)
4948 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156L<<0)
4949 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157L<<0)
4950 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158L<<0)
4951 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159L<<0)
4952 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160L<<0)
4953 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161L<<0)
4954 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162L<<0)
4955 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163L<<0)
4956 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164L<<0)
4957 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165L<<0)
4958 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166L<<0)
4959 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167L<<0)
4960 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168L<<0)
4961 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169L<<0)
4962 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170L<<0)
4963 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171L<<0)
4964 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172L<<0)
4965 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173L<<0)
4966 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174L<<0)
4967 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175L<<0)
4968 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176L<<0)
4969 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177L<<0)
4970 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178L<<0)
5040 #define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
5041 #define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
5042 #define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
5043 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
5044 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
5045 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
5046 #define BCE_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
5047 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
5048 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
5049 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
5050 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
5052 #define BCE_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
5053 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
5054 #define BCE_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
5055 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
5056 #define BCE_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
5057 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
5058 #define BCE_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
5059 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
5060 #define BCE_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
5061 #define BCE_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
5062 #define BCE_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
5065 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
5066 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
5067 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
5070 #define BCE_HC_VIS_1_HW_INTACK_STATE (1L<<4)
5071 #define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
5072 #define BCE_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
5073 #define BCE_HC_VIS_1_SW_INTACK_STATE (1L<<5)
5074 #define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
5075 #define BCE_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
5076 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
5077 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
5078 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
5079 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
5080 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
5081 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
5083 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
5084 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
5085 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
5086 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
5087 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
5088 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
5089 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
5090 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
5092 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
5093 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
5094 #define BCE_HC_VIS_1_INT_GEN_STATE (1L<<23)
5095 #define BCE_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
5096 #define BCE_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
5098 #define BCE_HC_VIS_1_INT_B (1L<<27)
5102 #define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
5105 #define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
5117 #define BCE_HC_SB_CONFIG_1_RX_TMR_MODE (1L<<1)
5118 #define BCE_HC_SB_CONFIG_1_TX_TMR_MODE (1L<<2)
5119 #define BCE_HC_SB_CONFIG_1_COM_TMR_MODE (1L<<3)
5120 #define BCE_HC_SB_CONFIG_1_CMD_TMR_MODE (1L<<4)
5121 #define BCE_HC_SB_CONFIG_1_PER_MODE (1L<<16)
5122 #define BCE_HC_SB_CONFIG_1_ONE_SHOT (1L<<17)
5123 #define BCE_HC_SB_CONFIG_1_USE_INT_PARAM (1L<<18)
5159 #define BCE_HC_SB_CONFIG_2_RX_TMR_MODE (1L<<1)
5160 #define BCE_HC_SB_CONFIG_2_TX_TMR_MODE (1L<<2)
5161 #define BCE_HC_SB_CONFIG_2_COM_TMR_MODE (1L<<3)
5162 #define BCE_HC_SB_CONFIG_2_CMD_TMR_MODE (1L<<4)
5163 #define BCE_HC_SB_CONFIG_2_PER_MODE (1L<<16)
5164 #define BCE_HC_SB_CONFIG_2_ONE_SHOT (1L<<17)
5165 #define BCE_HC_SB_CONFIG_2_USE_INT_PARAM (1L<<18)
5201 #define BCE_HC_SB_CONFIG_3_RX_TMR_MODE (1L<<1)
5202 #define BCE_HC_SB_CONFIG_3_TX_TMR_MODE (1L<<2)
5203 #define BCE_HC_SB_CONFIG_3_COM_TMR_MODE (1L<<3)
5204 #define BCE_HC_SB_CONFIG_3_CMD_TMR_MODE (1L<<4)
5205 #define BCE_HC_SB_CONFIG_3_PER_MODE (1L<<16)
5206 #define BCE_HC_SB_CONFIG_3_ONE_SHOT (1L<<17)
5207 #define BCE_HC_SB_CONFIG_3_USE_INT_PARAM (1L<<18)
5243 #define BCE_HC_SB_CONFIG_4_RX_TMR_MODE (1L<<1)
5244 #define BCE_HC_SB_CONFIG_4_TX_TMR_MODE (1L<<2)
5245 #define BCE_HC_SB_CONFIG_4_COM_TMR_MODE (1L<<3)
5246 #define BCE_HC_SB_CONFIG_4_CMD_TMR_MODE (1L<<4)
5247 #define BCE_HC_SB_CONFIG_4_PER_MODE (1L<<16)
5248 #define BCE_HC_SB_CONFIG_4_ONE_SHOT (1L<<17)
5249 #define BCE_HC_SB_CONFIG_4_USE_INT_PARAM (1L<<18)
5285 #define BCE_HC_SB_CONFIG_5_RX_TMR_MODE (1L<<1)
5286 #define BCE_HC_SB_CONFIG_5_TX_TMR_MODE (1L<<2)
5287 #define BCE_HC_SB_CONFIG_5_COM_TMR_MODE (1L<<3)
5288 #define BCE_HC_SB_CONFIG_5_CMD_TMR_MODE (1L<<4)
5289 #define BCE_HC_SB_CONFIG_5_PER_MODE (1L<<16)
5290 #define BCE_HC_SB_CONFIG_5_ONE_SHOT (1L<<17)
5291 #define BCE_HC_SB_CONFIG_5_USE_INT_PARAM (1L<<18)
5327 #define BCE_HC_SB_CONFIG_6_RX_TMR_MODE (1L<<1)
5328 #define BCE_HC_SB_CONFIG_6_TX_TMR_MODE (1L<<2)
5329 #define BCE_HC_SB_CONFIG_6_COM_TMR_MODE (1L<<3)
5330 #define BCE_HC_SB_CONFIG_6_CMD_TMR_MODE (1L<<4)
5331 #define BCE_HC_SB_CONFIG_6_PER_MODE (1L<<16)
5332 #define BCE_HC_SB_CONFIG_6_ONE_SHOT (1L<<17)
5333 #define BCE_HC_SB_CONFIG_6_USE_INT_PARAM (1L<<18)
5369 #define BCE_HC_SB_CONFIG_7_RX_TMR_MODE (1L<<1)
5370 #define BCE_HC_SB_CONFIG_7_TX_TMR_MODE (1L<<2)
5371 #define BCE_HC_SB_CONFIG_7_COM_TMR_MODE (1L<<3)
5372 #define BCE_HC_SB_CONFIG_7_CMD_TMR_MODE (1L<<4)
5373 #define BCE_HC_SB_CONFIG_7_PER_MODE (1L<<16)
5374 #define BCE_HC_SB_CONFIG_7_ONE_SHOT (1L<<17)
5375 #define BCE_HC_SB_CONFIG_7_USE_INT_PARAM (1L<<18)
5411 #define BCE_HC_SB_CONFIG_8_RX_TMR_MODE (1L<<1)
5412 #define BCE_HC_SB_CONFIG_8_TX_TMR_MODE (1L<<2)
5413 #define BCE_HC_SB_CONFIG_8_COM_TMR_MODE (1L<<3)
5414 #define BCE_HC_SB_CONFIG_8_CMD_TMR_MODE (1L<<4)
5415 #define BCE_HC_SB_CONFIG_8_PER_MODE (1L<<16)
5416 #define BCE_HC_SB_CONFIG_8_ONE_SHOT (1L<<17)
5417 #define BCE_HC_SB_CONFIG_8_USE_INT_PARAM (1L<<18)
5457 #define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0)
5458 #define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1)
5459 #define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
5460 #define BCE_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
5461 #define BCE_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
5462 #define BCE_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
5463 #define BCE_TXP_CPU_MODE_SOFT_HALT (1L<<10)
5464 #define BCE_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
5465 #define BCE_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
5466 #define BCE_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
5467 #define BCE_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
5470 #define BCE_TXP_CPU_STATE_BREAKPOINT (1L<<0)
5471 #define BCE_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
5472 #define BCE_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
5473 #define BCE_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
5474 #define BCE_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
5475 #define BCE_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
5476 #define BCE_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
5477 #define BCE_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
5478 #define BCE_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
5479 #define BCE_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
5480 #define BCE_TXP_CPU_STATE_INTERRRUPT (1L<<12)
5481 #define BCE_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
5482 #define BCE_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
5483 #define BCE_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
5486 #define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5487 #define BCE_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
5488 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
5489 #define BCE_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
5490 #define BCE_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
5491 #define BCE_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
5492 #define BCE_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
5493 #define BCE_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
5494 #define BCE_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
5495 #define BCE_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
5496 #define BCE_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
5505 #define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5512 #define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10)
5513 #define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
5514 #define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
5515 #define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25)
5516 #define BCE_TXP_FTQ_CMD_RD_DATA (1L<<26)
5517 #define BCE_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
5518 #define BCE_TXP_FTQ_CMD_ADD_DATA (1L<<28)
5519 #define BCE_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
5520 #define BCE_TXP_FTQ_CMD_POP (1L<<30)
5521 #define BCE_TXP_FTQ_CMD_BUSY (1L<<31)
5524 #define BCE_TXP_FTQ_CTL_INTERVENE (1L<<0)
5525 #define BCE_TXP_FTQ_CTL_OVERFLOW (1L<<1)
5526 #define BCE_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
5537 #define BCE_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
5538 #define BCE_TPAT_CPU_MODE_STEP_ENA (1L<<1)
5539 #define BCE_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
5540 #define BCE_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
5541 #define BCE_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
5542 #define BCE_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
5543 #define BCE_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
5544 #define BCE_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
5545 #define BCE_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
5546 #define BCE_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
5547 #define BCE_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
5550 #define BCE_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
5551 #define BCE_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
5552 #define BCE_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
5553 #define BCE_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
5554 #define BCE_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
5555 #define BCE_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6)
5556 #define BCE_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
5557 #define BCE_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
5558 #define BCE_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
5559 #define BCE_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
5560 #define BCE_TPAT_CPU_STATE_INTERRRUPT (1L<<12)
5561 #define BCE_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
5562 #define BCE_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
5563 #define BCE_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
5566 #define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5567 #define BCE_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
5568 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
5569 #define BCE_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
5570 #define BCE_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
5571 #define BCE_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
5572 #define BCE_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
5573 #define BCE_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
5574 #define BCE_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
5575 #define BCE_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
5576 #define BCE_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
5585 #define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5591 #define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10)
5592 #define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
5593 #define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
5594 #define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
5595 #define BCE_TPAT_FTQ_CMD_RD_DATA (1L<<26)
5596 #define BCE_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
5597 #define BCE_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
5598 #define BCE_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
5599 #define BCE_TPAT_FTQ_CMD_POP (1L<<30)
5600 #define BCE_TPAT_FTQ_CMD_BUSY (1L<<31)
5603 #define BCE_TPAT_FTQ_CTL_INTERVENE (1L<<0)
5604 #define BCE_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
5605 #define BCE_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
5616 #define BCE_RXP_CPU_MODE_LOCAL_RST (1L<<0)
5617 #define BCE_RXP_CPU_MODE_STEP_ENA (1L<<1)
5618 #define BCE_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
5619 #define BCE_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
5620 #define BCE_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
5621 #define BCE_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
5622 #define BCE_RXP_CPU_MODE_SOFT_HALT (1L<<10)
5623 #define BCE_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
5624 #define BCE_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
5625 #define BCE_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
5626 #define BCE_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
5629 #define BCE_RXP_CPU_STATE_BREAKPOINT (1L<<0)
5630 #define BCE_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
5631 #define BCE_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
5632 #define BCE_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
5633 #define BCE_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
5634 #define BCE_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6)
5635 #define BCE_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
5636 #define BCE_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
5637 #define BCE_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
5638 #define BCE_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
5639 #define BCE_RXP_CPU_STATE_INTERRRUPT (1L<<12)
5640 #define BCE_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
5641 #define BCE_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
5642 #define BCE_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
5645 #define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5646 #define BCE_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
5647 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
5648 #define BCE_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
5649 #define BCE_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
5650 #define BCE_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
5651 #define BCE_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
5652 #define BCE_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
5653 #define BCE_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
5654 #define BCE_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
5655 #define BCE_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
5664 #define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5671 #define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10)
5672 #define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
5673 #define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
5674 #define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
5675 #define BCE_RXP_CFTQ_CMD_RD_DATA (1L<<26)
5676 #define BCE_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
5677 #define BCE_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
5678 #define BCE_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
5679 #define BCE_RXP_CFTQ_CMD_POP (1L<<30)
5680 #define BCE_RXP_CFTQ_CMD_BUSY (1L<<31)
5683 #define BCE_RXP_CFTQ_CTL_INTERVENE (1L<<0)
5684 #define BCE_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
5685 #define BCE_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
5692 #define BCE_RXP_FTQ_CMD_WR_TOP (1L<<10)
5693 #define BCE_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
5694 #define BCE_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
5695 #define BCE_RXP_FTQ_CMD_SFT_RESET (1L<<25)
5696 #define BCE_RXP_FTQ_CMD_RD_DATA (1L<<26)
5697 #define BCE_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
5698 #define BCE_RXP_FTQ_CMD_ADD_DATA (1L<<28)
5699 #define BCE_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
5700 #define BCE_RXP_FTQ_CMD_POP (1L<<30)
5701 #define BCE_RXP_FTQ_CMD_BUSY (1L<<31)
5704 #define BCE_RXP_FTQ_CTL_INTERVENE (1L<<0)
5705 #define BCE_RXP_FTQ_CTL_OVERFLOW (1L<<1)
5706 #define BCE_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
5717 #define BCE_COM_CPU_MODE_LOCAL_RST (1L<<0)
5718 #define BCE_COM_CPU_MODE_STEP_ENA (1L<<1)
5719 #define BCE_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
5720 #define BCE_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
5721 #define BCE_COM_CPU_MODE_MSG_BIT1 (1L<<6)
5722 #define BCE_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
5723 #define BCE_COM_CPU_MODE_SOFT_HALT (1L<<10)
5724 #define BCE_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
5725 #define BCE_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
5726 #define BCE_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
5727 #define BCE_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
5730 #define BCE_COM_CPU_STATE_BREAKPOINT (1L<<0)
5731 #define BCE_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
5732 #define BCE_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
5733 #define BCE_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
5734 #define BCE_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
5735 #define BCE_COM_CPU_STATE_BAD_pc_HALTED (1L<<6)
5736 #define BCE_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
5737 #define BCE_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
5738 #define BCE_COM_CPU_STATE_SOFT_HALTED (1L<<10)
5739 #define BCE_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
5740 #define BCE_COM_CPU_STATE_INTERRRUPT (1L<<12)
5741 #define BCE_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
5742 #define BCE_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
5743 #define BCE_COM_CPU_STATE_BLOCKED_READ (1L<<31)
5746 #define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5747 #define BCE_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
5748 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
5749 #define BCE_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
5750 #define BCE_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
5751 #define BCE_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
5752 #define BCE_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
5753 #define BCE_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
5754 #define BCE_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
5755 #define BCE_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
5756 #define BCE_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
5765 #define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5772 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
5773 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
5774 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
5775 #define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
5776 #define BCE_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
5777 #define BCE_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
5778 #define BCE_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
5779 #define BCE_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
5780 #define BCE_COM_COMXQ_FTQ_CMD_POP (1L<<30)
5781 #define BCE_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
5784 #define BCE_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
5785 #define BCE_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
5786 #define BCE_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
5793 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
5794 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
5795 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
5796 #define BCE_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
5797 #define BCE_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
5798 #define BCE_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
5799 #define BCE_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
5800 #define BCE_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
5801 #define BCE_COM_COMTQ_FTQ_CMD_POP (1L<<30)
5802 #define BCE_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
5805 #define BCE_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
5806 #define BCE_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
5807 #define BCE_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
5814 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
5815 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
5816 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
5817 #define BCE_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
5818 #define BCE_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
5819 #define BCE_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
5820 #define BCE_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
5821 #define BCE_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
5822 #define BCE_COM_COMQ_FTQ_CMD_POP (1L<<30)
5823 #define BCE_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
5826 #define BCE_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
5827 #define BCE_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
5828 #define BCE_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
5839 #define BCE_CP_CPU_MODE_LOCAL_RST (1L<<0)
5840 #define BCE_CP_CPU_MODE_STEP_ENA (1L<<1)
5841 #define BCE_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
5842 #define BCE_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
5843 #define BCE_CP_CPU_MODE_MSG_BIT1 (1L<<6)
5844 #define BCE_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
5845 #define BCE_CP_CPU_MODE_SOFT_HALT (1L<<10)
5846 #define BCE_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
5847 #define BCE_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
5848 #define BCE_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
5849 #define BCE_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
5852 #define BCE_CP_CPU_STATE_BREAKPOINT (1L<<0)
5853 #define BCE_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
5854 #define BCE_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
5855 #define BCE_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
5856 #define BCE_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
5857 #define BCE_CP_CPU_STATE_BAD_pc_HALTED (1L<<6)
5858 #define BCE_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
5859 #define BCE_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
5860 #define BCE_CP_CPU_STATE_SOFT_HALTED (1L<<10)
5861 #define BCE_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
5862 #define BCE_CP_CPU_STATE_INTERRRUPT (1L<<12)
5863 #define BCE_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
5864 #define BCE_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
5865 #define BCE_CP_CPU_STATE_BLOCKED_READ (1L<<31)
5868 #define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5869 #define BCE_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
5870 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
5871 #define BCE_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
5872 #define BCE_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
5873 #define BCE_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
5874 #define BCE_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
5875 #define BCE_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
5876 #define BCE_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
5877 #define BCE_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
5878 #define BCE_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
5887 #define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5894 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
5895 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
5896 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
5897 #define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
5898 #define BCE_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
5899 #define BCE_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
5900 #define BCE_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
5901 #define BCE_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
5902 #define BCE_CP_CPQ_FTQ_CMD_POP (1L<<30)
5903 #define BCE_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
5906 #define BCE_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
5907 #define BCE_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
5908 #define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
5928 #define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0)
5929 #define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1)
5930 #define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
5931 #define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
5932 #define BCE_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
5933 #define BCE_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
5934 #define BCE_MCP_CPU_MODE_SOFT_HALT (1L<<10)
5935 #define BCE_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
5936 #define BCE_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
5937 #define BCE_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
5938 #define BCE_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
5941 #define BCE_MCP_CPU_STATE_BREAKPOINT (1L<<0)
5942 #define BCE_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
5943 #define BCE_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
5944 #define BCE_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
5945 #define BCE_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
5946 #define BCE_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6)
5947 #define BCE_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
5948 #define BCE_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
5949 #define BCE_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
5950 #define BCE_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
5951 #define BCE_MCP_CPU_STATE_INTERRRUPT (1L<<12)
5952 #define BCE_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
5953 #define BCE_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
5954 #define BCE_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
5957 #define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
5958 #define BCE_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
5959 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
5960 #define BCE_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
5961 #define BCE_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
5962 #define BCE_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
5963 #define BCE_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
5964 #define BCE_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
5965 #define BCE_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
5966 #define BCE_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
5967 #define BCE_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
5976 #define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5983 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
5984 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
5985 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
5986 #define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
5987 #define BCE_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
5988 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
5989 #define BCE_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
5990 #define BCE_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
5991 #define BCE_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
5992 #define BCE_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
5995 #define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
5996 #define BCE_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
5997 #define BCE_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)