Lines Matching +full:0 +full:x00001414

82 /* MII Control Register 0x0 */
102 /* MII Status Register 0x1 */
122 /* MII Autoneg Advertisement Register 0x4 */
142 /* MII Autoneg Link Partner Ability Register 0x5 */
162 /* 1000Base-T Control Register 0x09 */
182 /* MII 1000Base-T Status Register 0x0a */
194 /* MII Extended Status Register 0x0f */
214 /* MII Autoneg Link Partner Ability Register 0x19 */
245 #define BCE_CP_LOAD 		0x00000001
246 #define BCE_CP_SEND		0x00000002
247 #define BCE_CP_RECV		0x00000004
248 #define BCE_CP_INTR		0x00000008
249 #define BCE_CP_UNLOAD		0x00000010
250 #define BCE_CP_RESET		0x00000020
251 #define BCE_CP_PHY			0x00000040
252 #define BCE_CP_NVRAM		0x00000080
253 #define BCE_CP_FIRMWARE	0x00000100
254 #define BCE_CP_CTX			0x00000200
255 #define BCE_CP_REG			0x00000400
256 #define BCE_CP_MISC		0x00400000
257 #define BCE_CP_SPECIAL		0x00800000
258 #define BCE_CP_ALL			0x00FFFFFF
260 #define BCE_CP_MASK		0x00FFFFFF
262 #define BCE_LEVEL_FATAL	0x00000000
263 #define BCE_LEVEL_WARN		0x01000000
264 #define BCE_LEVEL_INFO		0x02000000
265 #define BCE_LEVEL_VERBOSE	0x03000000
266 #define BCE_LEVEL_EXTREME	0x04000000
267 #define BCE_LEVEL_INSANE	0x05000000
269 #define BCE_LEVEL_MASK		0xFF000000
373 	} while (0)
431 case 0x00: DBPRINT(sc, BCE_INSANE_PHY,					\
432 	"%s(): phy = %d, reg = 0x%04X (BMCR   ), val = 0x%b\n",		\
433 	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
435 case 0x01: DBPRINT(sc, BCE_INSANE_PHY,					\
436 	"%s(): phy = %d, reg = 0x%04X (BMSR   ), val = 0x%b\n",		\
437 	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
439 case 0x04: DBPRINT(sc, BCE_INSANE_PHY,					\
440 	"%s(): phy = %d, reg = 0x%04X (ANAR   ), val = 0x%b\n",		\
441 	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
443 case 0x05: DBPRINT(sc, BCE_INSANE_PHY,					\
444 	"%s(): phy = %d, reg = 0x%04X (ANLPAR ), val = 0x%b\n",		\
445 	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
447 case 0x09: DBPRINT(sc, BCE_INSANE_PHY,					\
448 	"%s(): phy = %d, reg = 0x%04X (1000CTL), val = 0x%b\n",		\
449 	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
451 case 0x0a: DBPRINT(sc, BCE_INSANE_PHY,					\
452 	"%s(): phy = %d, reg = 0x%04X (1000STS), val = 0x%b\n",		\
453 	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
455 case 0x0f: DBPRINT(sc, BCE_INSANE_PHY,					\
456 	"%s(): phy = %d, reg = 0x%04X (EXTSTS ), val = 0x%b\n",		\
457 	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
459 case 0x19: DBPRINT(sc, BCE_INSANE_PHY,					\
460 	"%s(): phy = %d, reg = 0x%04X (AUXSTS ), val = 0x%b\n",		\
461 	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff,	\
464 	"%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",			\
465 	__FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff);	\
493 #define BRCM_VENDORID				0x14E4
494 #define BRCM_DEVICEID_BCM5706			0x164A
495 #define BRCM_DEVICEID_BCM5706S			0x16AA
496 #define BRCM_DEVICEID_BCM5708			0x164C
497 #define BRCM_DEVICEID_BCM5708S			0x16AC
498 #define BRCM_DEVICEID_BCM5709			0x1639
499 #define BRCM_DEVICEID_BCM5709S			0x163A
500 #define BRCM_DEVICEID_BCM5716			0x163B
502 #define HP_VENDORID				0x103C
504 #define PCI_ANY_ID				(u_int16_t) (~0U)
506 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
508 #define BCE_CHIP_NUM(sc)		(((sc)->bce_chipid) & 0xffff0000)
509 #define BCE_CHIP_NUM_5706		0x57060000
510 #define BCE_CHIP_NUM_5708		0x57080000
511 #define BCE_CHIP_NUM_5709		0x57090000
513 #define BCE_CHIP_REV(sc)		(((sc)->bce_chipid) & 0x0000f000)
514 #define BCE_CHIP_REV_Ax			0x00000000
515 #define BCE_CHIP_REV_Bx			0x00001000
516 #define BCE_CHIP_REV_Cx			0x00002000
518 #define BCE_CHIP_METAL(sc)		(((sc)->bce_chipid) & 0x00000ff0)
519 #define BCE_CHIP_BOND(bp)		(((sc)->bce_chipid) & 0x0000000f)
521 #define BCE_CHIP_ID(sc)			(((sc)->bce_chipid) & 0xfffffff0)
522 #define BCE_CHIP_ID_5706_A0		0x57060000
523 #define BCE_CHIP_ID_5706_A1		0x57060010
524 #define BCE_CHIP_ID_5706_A2		0x57060020
525 #define BCE_CHIP_ID_5706_A3		0x57060030
526 #define BCE_CHIP_ID_5708_A0		0x57080000
527 #define BCE_CHIP_ID_5708_B0		0x57081000
528 #define BCE_CHIP_ID_5708_B1		0x57081010
529 #define BCE_CHIP_ID_5708_B2		0x57081020
530 #define BCE_CHIP_ID_5709_A0		0x57090000
531 #define BCE_CHIP_ID_5709_A1		0x57090010
532 #define BCE_CHIP_ID_5709_B0		0x57091000
533 #define BCE_CHIP_ID_5709_B1		0x57091010
534 #define BCE_CHIP_ID_5709_B2		0x57091020
535 #define BCE_CHIP_ID_5709_C0		0x57092000
537 #define BCE_CHIP_BOND_ID(sc)		(((sc)->bce_chipid) & 0xf)
540 #define BCE_CHIP_BOND_ID_SERDES_BIT	0x01
544 #define BCE_ASICREV_BCM5700		0x06
548 #define BCE_CHIPREV_5700_AX		0x70
549 #define BCE_CHIPREV_5700_BX		0x71
550 #define BCE_CHIPREV_5700_CX		0x72
551 #define BCE_CHIPREV_5701_AX		0x00
593 #define BUFFERED_FLASH_TOTAL_SIZE	0x21000
619 #define FLASH_BACKUP_STRAP_MASK		(0xf << 26)
627 #define BCE_NV_BUFFERED		0x00000001
628 #define BCE_NV_TRANSLATE	0x00000002
629 #define BCE_NV_WREN		0x00000004
660 #define BCE_DRV_RESET_SIGNATURE			0x00000000
661 #define BCE_DRV_RESET_SIGNATURE_MAGIC		0x4841564b /* HAVK */
663 #define BCE_DRV_MB				0x00000004
664 #define BCE_DRV_MSG_CODE	 		0xff000000
665 #define BCE_DRV_MSG_CODE_RESET		 	0x01000000
666 #define BCE_DRV_MSG_CODE_UNLOAD			0x02000000
667 #define BCE_DRV_MSG_CODE_SHUTDOWN	 	0x03000000
668 #define BCE_DRV_MSG_CODE_SUSPEND_WOL		0x04000000
669 #define BCE_DRV_MSG_CODE_FW_TIMEOUT	 	0x05000000
670 #define BCE_DRV_MSG_CODE_PULSE		 	0x06000000
671 #define BCE_DRV_MSG_CODE_DIAG		 	0x07000000
672 #define BCE_DRV_MSG_CODE_SUSPEND_NO_WOL	 	0x09000000
673 #define BCE_DRV_MSG_CODE_UNLOAD_LNK_DN		0x0b000000
674 #define BCE_DRV_MSG_CODE_CMD_SET_LINK		0x10000000
676 #define BCE_DRV_MSG_DATA			0x00ff0000
677 #define BCE_DRV_MSG_DATA_WAIT0		 	0x00010000
678 #define BCE_DRV_MSG_DATA_WAIT1			0x00020000
679 #define BCE_DRV_MSG_DATA_WAIT2			0x00030000
680 #define BCE_DRV_MSG_DATA_WAIT3			0x00040000
682 #define BCE_DRV_MSG_SEQ				0x0000ffff
684 #define BCE_FW_MB				0x00000008
685 #define BCE_FW_MSG_ACK				 0x0000ffff
686 #define BCE_FW_MSG_STATUS_MASK			 0x00ff0000
687 #define BCE_FW_MSG_STATUS_OK			 0x00000000
688 #define BCE_FW_MSG_STATUS_INVALID_ARGS		 0x00010000
689 #define BCE_FW_MSG_STATUS_DRV_PRSNT		 0x00020000
690 #define BCE_FW_MSG_STATUS_FAILURE		 0x00ff0000
692 #define BCE_LINK_STATUS				0x0000000c
693 #define BCE_LINK_STATUS_INIT_VALUE		 0xffffffff
694 #define BCE_LINK_STATUS_LINK_UP		 	 0x1
695 #define BCE_LINK_STATUS_LINK_DOWN		 0x0
696 #define BCE_LINK_STATUS_SPEED_MASK		 0x1e
697 #define BCE_LINK_STATUS_AN_INCOMPLETE		 (0<<1)
726 #define BCE_DRV_PULSE_MB			0x00000010
727 #define BCE_DRV_PULSE_SEQ_MASK			 0x00007fff
729 #define BCE_MB_ARGS_0				0x00000014
730 #define	BCE_NETLINK_SPEED_10HALF		 (1<<0)
747 #define BCE_MB_ARGS_1				0x00000018
752 #define BCE_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE	 0x00080000
754 #define BCE_DEV_INFO_SIGNATURE			0x00000020
755 #define BCE_DEV_INFO_SIGNATURE_MAGIC		 0x44564900
756 #define BCE_DEV_INFO_SIGNATURE_MAGIC_MASK	 0xffffff00
757 #define BCE_DEV_INFO_FEATURE_CFG_VALID		 0x01
758 #define BCE_DEV_INFO_SECONDARY_PORT		 0x80
759 #define BCE_DEV_INFO_DRV_ALWAYS_ALIVE		 0x40
761 #define BCE_SHARED_HW_CFG_PART_NUM		0x00000024
763 #define BCE_SHARED_HW_CFG_POWER_DISSIPATED	0x00000034
764 #define BCE_SHARED_HW_CFG_POWER_STATE_D3_MASK	 0xff000000
765 #define BCE_SHARED_HW_CFG_POWER_STATE_D2_MASK	 0xff0000
766 #define BCE_SHARED_HW_CFG_POWER_STATE_D1_MASK	 0xff00
767 #define BCE_SHARED_HW_CFG_POWER_STATE_D0_MASK	 0xff
769 #define BCE_SHARED_HW_CFG_POWER_CONSUMED	0x00000038
770 #define BCE_SHARED_HW_CFG_CONFIG		0x0000003c
771 #define BCE_SHARED_HW_CFG_DESIGN_NIC		 0
772 #define BCE_SHARED_HW_CFG_DESIGN_LOM		 0x1
773 #define BCE_SHARED_HW_CFG_PHY_COPPER		 0
774 #define BCE_SHARED_HW_CFG_PHY_FIBER		 0x2
775 #define BCE_SHARED_HW_CFG_PHY_2_5G		 0x20
776 #define BCE_SHARED_HW_CFG_PHY_BACKPLANE		 0x40
778 #define BCE_SHARED_HW_CFG_LED_MODE_MASK		 0x300
779 #define BCE_SHARED_HW_CFG_LED_MODE_MAC		 0
780 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY1	 0x100
781 #define BCE_SHARED_HW_CFG_LED_MODE_GPHY2	 0x200
783 #define BCE_SHARED_HW_CFG_CONFIG2		0x00000040
784 #define BCE_SHARED_HW_CFG2_NVM_SIZE_MASK	 0x00fff000
786 #define BCE_DEV_INFO_BC_REV			0x0000004c
788 #define BCE_PORT_HW_CFG_MAC_UPPER		0x00000050
789 #define BCE_PORT_HW_CFG_UPPERMAC_MASK		 0xffff
791 #define BCE_PORT_HW_CFG_MAC_LOWER		0x00000054
792 #define BCE_PORT_HW_CFG_CONFIG			0x00000058
793 #define BCE_PORT_HW_CFG_CFG_TXCTL3_MASK		 0x0000ffff
794 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_MASK	 0x001f0000
795 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_AN	 0x00000000
796 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_1G	 0x00030000
797 #define BCE_PORT_HW_CFG_CFG_DFLT_LINK_2_5G	 0x00040000
799 #define BCE_PORT_HW_CFG_IMD_MAC_A_UPPER		0x00000068
800 #define BCE_PORT_HW_CFG_IMD_MAC_A_LOWER		0x0000006c
801 #define BCE_PORT_HW_CFG_IMD_MAC_B_UPPER		0x00000070
802 #define BCE_PORT_HW_CFG_IMD_MAC_B_LOWER		0x00000074
803 #define BCE_PORT_HW_CFG_ISCSI_MAC_UPPER		0x00000078
804 #define BCE_PORT_HW_CFG_ISCSI_MAC_LOWER		0x0000007c
806 #define BCE_DEV_INFO_PER_PORT_HW_CONFIG2	0x000000b4
808 #define BCE_DEV_INFO_FORMAT_REV			0x000000c4
809 #define BCE_DEV_INFO_FORMAT_REV_MASK		 0xff000000
812 #define BCE_SHARED_FEATURE			0x000000c8
813 #define BCE_SHARED_FEATURE_MASK			 0xffffffff
815 #define BCE_PORT_FEATURE			0x000000d8
816 #define BCE_PORT2_FEATURE			0x00000014c
817 #define BCE_PORT_FEATURE_WOL_ENABLED		 0x01000000
818 #define BCE_PORT_FEATURE_MBA_ENABLED		 0x02000000
819 #define BCE_PORT_FEATURE_ASF_ENABLED		 0x04000000
820 #define BCE_PORT_FEATURE_IMD_ENABLED		 0x08000000
821 #define BCE_PORT_FEATURE_BAR1_SIZE_MASK		 0xf
822 #define BCE_PORT_FEATURE_BAR1_SIZE_DISABLED	 0x0
823 #define BCE_PORT_FEATURE_BAR1_SIZE_64K		 0x1
824 #define BCE_PORT_FEATURE_BAR1_SIZE_128K		 0x2
825 #define BCE_PORT_FEATURE_BAR1_SIZE_256K		 0x3
826 #define BCE_PORT_FEATURE_BAR1_SIZE_512K		 0x4
827 #define BCE_PORT_FEATURE_BAR1_SIZE_1M		 0x5
828 #define BCE_PORT_FEATURE_BAR1_SIZE_2M		 0x6
829 #define BCE_PORT_FEATURE_BAR1_SIZE_4M		 0x7
830 #define BCE_PORT_FEATURE_BAR1_SIZE_8M		 0x8
831 #define BCE_PORT_FEATURE_BAR1_SIZE_16M		 0x9
832 #define BCE_PORT_FEATURE_BAR1_SIZE_32M		 0xa
833 #define BCE_PORT_FEATURE_BAR1_SIZE_64M		 0xb
834 #define BCE_PORT_FEATURE_BAR1_SIZE_128M		 0xc
835 #define BCE_PORT_FEATURE_BAR1_SIZE_256M		 0xd
836 #define BCE_PORT_FEATURE_BAR1_SIZE_512M		 0xe
837 #define BCE_PORT_FEATURE_BAR1_SIZE_1G		 0xf
839 #define BCE_PORT_FEATURE_WOL			0xdc
840 #define BCE_PORT2_FEATURE_WOL			0x150
842 #define BCE_PORT_FEATURE_WOL_DEFAULT_MASK	 0x30
843 #define BCE_PORT_FEATURE_WOL_DEFAULT_DISABLE	 0
844 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC	 0x10
845 #define BCE_PORT_FEATURE_WOL_DEFAULT_ACPI	 0x20
846 #define BCE_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI	 0x30
847 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_MASK	 0xf
848 #define BCE_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG	 0
855 #define BCE_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000	 0x40
856 #define BCE_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP	 0x400
857 #define BCE_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP	 0x800
859 #define BCE_PORT_FEATURE_MBA			0xe0
860 #define BCE_PORT2_FEATURE_MBA			0x154
861 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS	 0
862 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK	 0x3
863 #define BCE_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE	 0
867 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_MASK	 0x3c
868 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG	 0
869 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10HALF	 0x4
870 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_10FULL	 0x8
871 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100HALF	 0xc
872 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_100FULL	 0x10
873 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
874 #define BCE_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
875 #define BCE_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
876 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_S	 0
877 #define BCE_PORT_FEATURE_MBA_HOTKEY_CTRL_B	 0x80
879 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK	 0xff00
880 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED	 0
881 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K	 0x100
882 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K	 0x200
883 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K	 0x300
884 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K	 0x400
885 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K	 0x500
886 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K	 0x600
887 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K	 0x700
888 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K	 0x800
889 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K	 0x900
890 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K	 0xa00
891 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M	 0xb00
892 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M	 0xc00
893 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M	 0xd00
894 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M	 0xe00
895 #define BCE_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M	 0xf00
897 #define BCE_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK	 0xf0000
899 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK	 0x300000
900 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO	 0
901 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS	 0x100000
902 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H	 0x200000
903 #define BCE_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H	 0x300000
905 #define BCE_PORT_FEATURE_IMD			0xe4
906 #define BCE_PORT2_FEATURE_IMD			0x158
907 #define BCE_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT	 0
910 #define BCE_PORT_FEATURE_VLAN			0xe8
911 #define BCE_PORT2_FEATURE_VLAN			0x15c
912 #define BCE_PORT_FEATURE_MBA_VLAN_TAG_MASK	 0xffff
913 #define BCE_PORT_FEATURE_MBA_VLAN_ENABLE	 0x10000
915 #define BCE_MFW_VER_PTR				0x00000014c
917 #define BCE_BC_STATE_RESET_TYPE			0x000001c0
918 #define BCE_BC_STATE_RESET_TYPE_SIG		 0x00005254
919 #define BCE_BC_STATE_RESET_TYPE_SIG_MASK	 0x0000ffff
922     (BCE_BC_STATE_RESET_TYPE_SIG | 0x00010000)
924     (BCE_BC_STATE_RESET_TYPE_SIG | 0x00020000)
926     (BCE_BC_STATE_RESET_TYPE_SIG | 0x00030000)
941 #define BCE_BC_RESET_TYPE			0x000001c0
943 #define BCE_BC_STATE				0x000001c4
944 #define BCE_BC_STATE_ERR_MASK			0x0000ff00
945 #define BCE_BC_STATE_SIGN			0x42530000
946 #define BCE_BC_STATE_SIGN_MASK			0xffff0000
947 #define BCE_BC_STATE_BC1_START			(BCE_BC_STATE_SIGN | 0x1)
948 #define BCE_BC_STATE_GET_NVM_CFG1		(BCE_BC_STATE_SIGN | 0x2)
949 #define BCE_BC_STATE_PROG_BAR			(BCE_BC_STATE_SIGN | 0x3)
950 #define BCE_BC_STATE_INIT_VID			(BCE_BC_STATE_SIGN | 0x4)
951 #define BCE_BC_STATE_GET_NVM_CFG2		(BCE_BC_STATE_SIGN | 0x5)
952 #define BCE_BC_STATE_APPLY_WKARND		(BCE_BC_STATE_SIGN | 0x6)
953 #define BCE_BC_STATE_LOAD_BC2			(BCE_BC_STATE_SIGN | 0x7)
954 #define BCE_BC_STATE_GOING_BC2			(BCE_BC_STATE_SIGN | 0x8)
955 #define BCE_BC_STATE_GOING_DIAG			(BCE_BC_STATE_SIGN | 0x9)
956 #define BCE_BC_STATE_RT_FINAL_INIT		(BCE_BC_STATE_SIGN | 0x81)
957 #define BCE_BC_STATE_RT_WKARND			(BCE_BC_STATE_SIGN | 0x82)
958 #define BCE_BC_STATE_RT_DRV_PULSE		(BCE_BC_STATE_SIGN | 0x83)
959 #define BCE_BC_STATE_RT_FIOEVTS			(BCE_BC_STATE_SIGN | 0x84)
960 #define BCE_BC_STATE_RT_DRV_CMD			(BCE_BC_STATE_SIGN | 0x85)
961 #define BCE_BC_STATE_RT_LOW_POWER		(BCE_BC_STATE_SIGN | 0x86)
962 #define BCE_BC_STATE_RT_SET_WOL			(BCE_BC_STATE_SIGN | 0x87)
963 #define BCE_BC_STATE_RT_OTHER_FW		(BCE_BC_STATE_SIGN | 0x88)
964 #define BCE_BC_STATE_RT_GOING_D3		(BCE_BC_STATE_SIGN | 0x89)
965 #define BCE_BC_STATE_ERR_BAD_VERSION		(BCE_BC_STATE_SIGN | 0x0100)
966 #define BCE_BC_STATE_ERR_BAD_BC2_CRC		(BCE_BC_STATE_SIGN | 0x0200)
967 #define BCE_BC_STATE_ERR_BC1_LOOP		(BCE_BC_STATE_SIGN | 0x0300)
968 #define BCE_BC_STATE_ERR_UNKNOWN_CMD		(BCE_BC_STATE_SIGN | 0x0400)
969 #define BCE_BC_STATE_ERR_DRV_DEAD		(BCE_BC_STATE_SIGN | 0x0500)
970 #define BCE_BC_STATE_ERR_NO_RXP			(BCE_BC_STATE_SIGN | 0x0600)
971 #define BCE_BC_STATE_ERR_TOO_MANY_RBUF		(BCE_BC_STATE_SIGN | 0x0700)
973 #define BCE_BC_STATE_CONDITION			0x000001c8
974 #define BCE_CONDITION_INIT_POR			0x00000001
975 #define BCE_CONDITION_INIT_VAUX_AVAIL		0x00000002
976 #define BCE_CONDITION_INIT_PCI_AVAIL		0x00000004
977 #define BCE_CONDITION_INIT_PCI_RESET		0x00000008
978 #define BCE_CONDITION_INIT_HD_RESET		0x00000010 /* 5709/16 only */
979 #define BCE_CONDITION_DRV_PRESENT		0x00000100
980 #define BCE_CONDITION_LOW_POWER_LINK		0x00000200
981 #define BCE_CONDITION_CORE_RST_OCCURRED		0x00000400 /* 5709/16 only */
982 #define BCE_CONDITION_UNUSED			0x00000800
983 #define BCE_CONDITION_BUSY_EXPROM		0x00001000 /* 5706/08 only */
985 #define BCE_CONDITION_MFW_RUN_UNKNOWN		0x00000000
986 #define BCE_CONDITION_MFW_RUN_IPMI		0x00002000
987 #define BCE_CONDITION_MFW_RUN_UMP		0x00004000
988 #define BCE_CONDITION_MFW_RUN_NCSI		0x00006000
989 #define BCE_CONDITION_MFW_RUN_NONE		0x0000e000
990 #define BCE_CONDITION_MFW_RUN_MASK		0x0000e000
993 #define BCE_CONDITION_PM_STATE_MASK		0x00030000
994 #define BCE_CONDITION_PM_STATE_FULL		0x00030000
995 #define BCE_CONDITION_PM_STATE_PREP		0x00020000
996 #define BCE_CONDITION_PM_STATE_UNPREP		0x00010000
997 #define BCE_CONDITION_PM_RESERVED		0x00000000
1000 #define BCE_CONDITION_RXMODE_KEEP_VLAN		0x00040000
1001 #define BCE_CONDITION_DRV_WOL_ENABLED		0x00080000
1002 #define BCE_CONDITION_PORT_DISABLED		0x00100000
1003 #define BCE_CONDITION_DRV_MAYBE_OUT		0x00200000
1004 #define BCE_CONDITION_DPFW_DEAD			0x00400000
1006 #define BCE_BC_STATE_DEBUG_CMD			0x000001dc
1007 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE	0x42440000
1008 #define BCE_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK	0xffff0000
1009 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK	0xffff
1010 #define BCE_BC_STATE_BC_DBG_CMD_LOOP_INFINITE	0xffff
1012 #define	BCE_FW_EVT_CODE_MB			0x00000354
1013 #define	BCE_FW_EVT_CODE_SW_TIMER_EXPIRE_EVENT	0x00000000
1014 #define	BCE_FW_EVT_CODE_LINK_EVENT		0x00000001
1016 #define	BCE_DRV_ACK_CAP_MB			0x00000364
1017 #define	BCE_DRV_ACK_CAP_SIGNATURE_MAGIC		0x35450000
1019 #define	BCE_FW_CAP_MB				0x00000368
1020 #define	BCE_FW_CAP_SIGNATURE_MAGIC		0xaa550000
1021 #define	BCE_FW_ACK_SIGNATURE_MAGIC		0x52500000
1022 #define	BCE_FW_CAP_SIGNATURE_MAGIC_MASK		0xffff0000
1023 #define	BCE_FW_CAP_REMOTE_PHY_CAP		0x00000001
1024 #define	BCE_FW_CAP_REMOTE_PHY_PRESENT		0x00000002
1025 #define	BCE_FW_CAP_MFW_KEEP_VLAN		0x00000008
1026 #define	BCE_FW_CAP_BC_KEEP_VLAN			0x00000010
1028 #define	BCE_RPHY_SERDES_LINK			0x00000374
1030 #define	BCE_RPHY_COPPER_LINK			0x00000378
1032 #define HOST_VIEW_SHMEM_BASE			0x167c00
1037 #define BCE_PCI_PCIX_CMD		0x42
1081 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
1082 #define	BCE_ADDR_LO(y)			((u64) (y) & 0xFFFFFFFF)
1086 #define	BCE_ADDR_HI(y)			(0)
1104 #define TX_BD_FLAGS_CONN_FAULT		(1<<0)
1112 #define TX_BD_FLAGS_SW_OPTION_WORD	(0x1f<<8)
1127 #define RX_BD_FLAGS_NOPUSH		(1<<0)
1138 		#define STATUS_ATTN_BITS_LINK_STATE		(1L<<0)
1313 		#define L2_FHDR_STATUS_RULE_CLASS	(0x7<<0)
1386 #define BCE_L2CTX_TX_TYPE			0x00000000
1387 #define BCE_L2CTX_TX_TYPE_SIZE_L2		((0xc0/0x20)<<16)
1388 #define BCE_L2CTX_TX_TYPE_TYPE			(0xf<<28)
1389 #define BCE_L2CTX_TX_TYPE_TYPE_EMPTY		(0<<28)
1392 #define BCE_L2CTX_TX_HOST_BIDX			0x00000088
1393 #define BCE_L2CTX_TX_EST_NBD			0x00000088
1394 #define BCE_L2CTX_TX_CMD_TYPE			0x00000088
1395 #define BCE_L2CTX_TX_CMD_TYPE_TYPE		(0xf<<24)
1396 #define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2		(0<<24)
1399 #define BCE_L2CTX_TX_HOST_BSEQ			0x00000090
1400 #define BCE_L2CTX_TX_TSCH_BSEQ			0x00000094
1401 #define BCE_L2CTX_TX_TBDR_BSEQ			0x00000098
1402 #define BCE_L2CTX_TX_TBDR_BOFF			0x0000009c
1403 #define BCE_L2CTX_TX_TBDR_BIDX			0x0000009c
1404 #define BCE_L2CTX_TX_TBDR_BHADDR_HI		0x000000a0
1405 #define BCE_L2CTX_TX_TBDR_BHADDR_LO		0x000000a4
1406 #define BCE_L2CTX_TX_TXP_BOFF			0x000000a8
1407 #define BCE_L2CTX_TX_TXP_BIDX			0x000000a8
1408 #define BCE_L2CTX_TX_TXP_BSEQ			0x000000ac
1413 #define BCE_L2CTX_TX_TYPE_XI			0x00000080
1414 #define BCE_L2CTX_TX_TYPE_SIZE_L2_XI		((0xc0/0x20)<<16)
1415 #define BCE_L2CTX_TX_TYPE_TYPE_XI		(0xf<<28)
1416 #define BCE_L2CTX_TX_TYPE_TYPE_EMPTY_XI		(0<<28)
1419 #define BCE_L2CTX_TX_CMD_TYPE_XI		0x00000240
1420 #define BCE_L2CTX_TX_CMD_TYPE_TYPE_XI		(0xf<<24)
1421 #define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI	(0<<24)
1424 #define BCE_L2CTX_TX_HOST_BIDX_XI		0x00000240
1425 #define BCE_L2CTX_TX_HOST_BSEQ_XI		0x00000248
1426 #define BCE_L2CTX_TX_TBDR_BHADDR_HI_XI		0x00000258
1427 #define BCE_L2CTX_TX_TBDR_BHADDR_LO_XI		0x0000025c
1432 #define BCE_L2CTX_RX_WATER_MARK			0x00000000
1433 #define BCE_L2CTX_RX_LO_WATER_MARK_SHIFT	0
1436 #define BCE_L2CTX_RX_LO_WATER_MARK_DIS		0
1439 #define BCE_L2CTX_RX_WATER_MARKS_MSK		0x000000ff
1441 #define BCE_L2CTX_RX_BD_PRE_READ		0x00000000
1444 #define BCE_L2CTX_RX_CTX_SIZE			0x00000000
1447     ((0x20/20)<<BCE_L2CTX_RX_CTX_SIZE_SHIFT)
1449 #define BCE_L2CTX_RX_CTX_TYPE			0x00000000
1452 #define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE	(0xf<<28)
1453 #define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED	(0<<28)
1456 #define BCE_L2CTX_RX_HOST_BDIDX			0x00000004
1457 #define BCE_L2CTX_RX_HOST_BSEQ			0x00000008
1458 #define BCE_L2CTX_RX_NX_BSEQ			0x0000000c
1459 #define BCE_L2CTX_RX_NX_BDHADDR_HI		0x00000010
1460 #define BCE_L2CTX_RX_NX_BDHADDR_LO		0x00000014
1461 #define BCE_L2CTX_RX_NX_BDIDX			0x00000018
1463 #define BCE_L2CTX_RX_HOST_PG_BDIDX		0x00000044
1464 #define BCE_L2CTX_RX_PG_BUF_SIZE		0x00000048
1465 #define BCE_L2CTX_RX_RBDC_KEY			0x0000004c
1466 #define BCE_L2CTX_RX_RBDC_JUMBO_KEY		0x3ffe
1467 #define BCE_L2CTX_RX_NX_PG_BDHADDR_HI		0x00000050
1468 #define BCE_L2CTX_RX_NX_PG_BDHADDR_LO		0x00000054
1469 #define BCE_L2CTX_RX_NX_PG_BDIDX		0x00000058
1475 #define BCE_L2MQ_RX_HOST_BDIDX			0x00000004
1476 #define BCE_L2MQ_RX_HOST_BSEQ			0x00000008
1477 #define BCE_L2MQ_RX_HOST_PG_BDIDX		0x00000044
1479 #define BCE_L2MQ_TX_HOST_BIDX			0x00000088
1480 #define BCE_L2MQ_TX_HOST_BSEQ			0x00000090
1486 #define BCE_PCICFG_MISC_CONFIG				0x00000068
1494 #define BCE_PCICFG_MISC_CONFIG_ASIC_METAL_REV		 (0xffL<<16)
1495 #define BCE_PCICFG_MISC_CONFIG_ASIC_BASE_REV		 (0xfL<<24)
1496 #define BCE_PCICFG_MISC_CONFIG_ASIC_ID			 (0xfL<<28)
1497 #define BCE_PCICFG_MISC_CONFIG_ASIC_REV			 (0xffffL<<16)
1499 #define BCE_PCICFG_MISC_STATUS				0x0000006c
1500 #define BCE_PCICFG_MISC_STATUS_INTA_VALUE		 (1L<<0)
1504 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED		 (0x3L<<4)
1505 #define BCE_PCICFG_MISC_STATUS_PCIX_SPEED_66		 (0L<<4)
1510 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS		0x00000070
1511 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET	 (0xfL<<0)
1512 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
1513 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
1514 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
1515 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
1516 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
1517 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
1518 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
1519 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)
1520 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW	 (0xfL<<0)
1523 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC	 (0x7L<<8)
1524 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)
1529 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED	 (0xfL<<12)
1530 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)
1539 #define BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED	 (0xfffL<<20)
1541 #define BCE_PCICFG_REG_WINDOW_ADDRESS			0x00000078
1542 #define BCE_PCICFG_REG_WINDOW				0x00000080
1543 #define BCE_PCICFG_INT_ACK_CMD				0x00000084
1544 #define BCE_PCICFG_INT_ACK_CMD_INDEX			 (0xffffL<<0)
1549 #define BCE_PCICFG_STATUS_BIT_SET_CMD			0x00000088
1550 #define BCE_PCICFG_STATUS_BIT_CLEAR_CMD		0x0000008c
1551 #define BCE_PCICFG_MAILBOX_QUEUE_ADDR			0x00000090
1552 #define BCE_PCICFG_MAILBOX_QUEUE_DATA			0x00000094
1556  *  offset: 0x400
1558 #define BCE_PCI_GRC_WINDOW_ADDR			0x00000400
1559 #define BCE_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE	 (0x3ffffL<<8)
1561 #define BCE_PCI_CONFIG_1				0x00000404
1562 #define BCE_PCI_CONFIG_1_READ_BOUNDARY			 (0x7L<<8)
1563 #define BCE_PCI_CONFIG_1_READ_BOUNDARY_OFF		 (0L<<8)
1571 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY		 (0x7L<<11)
1572 #define BCE_PCI_CONFIG_1_WRITE_BOUNDARY_OFF		 (0L<<11)
1581 #define BCE_PCI_CONFIG_2				0x00000408
1582 #define BCE_PCI_CONFIG_2_BAR1_SIZE			 (0xfL<<0)
1583 #define BCE_PCI_CONFIG_2_BAR1_SIZE_DISABLED		 (0L<<0)
1584 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64K			 (1L<<0)
1585 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128K		 (2L<<0)
1586 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256K		 (3L<<0)
1587 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512K		 (4L<<0)
1588 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1M			 (5L<<0)
1589 #define BCE_PCI_CONFIG_2_BAR1_SIZE_2M			 (6L<<0)
1590 #define BCE_PCI_CONFIG_2_BAR1_SIZE_4M			 (7L<<0)
1591 #define BCE_PCI_CONFIG_2_BAR1_SIZE_8M			 (8L<<0)
1592 #define BCE_PCI_CONFIG_2_BAR1_SIZE_16M			 (9L<<0)
1593 #define BCE_PCI_CONFIG_2_BAR1_SIZE_32M			 (10L<<0)
1594 #define BCE_PCI_CONFIG_2_BAR1_SIZE_64M			 (11L<<0)
1595 #define BCE_PCI_CONFIG_2_BAR1_SIZE_128M		 (12L<<0)
1596 #define BCE_PCI_CONFIG_2_BAR1_SIZE_256M		 (13L<<0)
1597 #define BCE_PCI_CONFIG_2_BAR1_SIZE_512M		 (14L<<0)
1598 #define BCE_PCI_CONFIG_2_BAR1_SIZE_1G			 (15L<<0)
1603 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE			 (0xffL<<8)
1604 #define BCE_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED		 (0L<<8)
1620 #define BCE_PCI_CONFIG_2_MAX_SPLIT_LIMIT		 (0x1fL<<16)
1621 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT		 (0x3L<<21)
1622 #define BCE_PCI_CONFIG_2_MAX_READ_LIMIT_512		 (0L<<21)
1630 #define BCE_PCI_CONFIG_3				0x0000040c
1631 #define BCE_PCI_CONFIG_3_STICKY_BYTE			 (0xffL<<0)
1635 #define BCE_PCI_CONFIG_3_PM_STATE			 (0x3L<<27)
1639 #define BCE_PCI_PM_DATA_A				0x00000410
1640 #define BCE_PCI_PM_DATA_A_PM_DATA_0_PRG		 (0xffL<<0)
1641 #define BCE_PCI_PM_DATA_A_PM_DATA_1_PRG		 (0xffL<<8)
1642 #define BCE_PCI_PM_DATA_A_PM_DATA_2_PRG		 (0xffL<<16)
1643 #define BCE_PCI_PM_DATA_A_PM_DATA_3_PRG		 (0xffL<<24)
1645 #define BCE_PCI_PM_DATA_B				0x00000414
1646 #define BCE_PCI_PM_DATA_B_PM_DATA_4_PRG		 (0xffL<<0)
1647 #define BCE_PCI_PM_DATA_B_PM_DATA_5_PRG		 (0xffL<<8)
1648 #define BCE_PCI_PM_DATA_B_PM_DATA_6_PRG		 (0xffL<<16)
1649 #define BCE_PCI_PM_DATA_B_PM_DATA_7_PRG		 (0xffL<<24)
1651 #define BCE_PCI_SWAP_DIAG0				0x00000418
1652 #define BCE_PCI_SWAP_DIAG1				0x0000041c
1653 #define BCE_PCI_EXP_ROM_ADDR				0x00000420
1654 #define BCE_PCI_EXP_ROM_ADDR_ADDRESS			 (0x3fffffL<<2)
1657 #define BCE_PCI_EXP_ROM_DATA				0x00000424
1658 #define BCE_PCI_VPD_INTF				0x00000428
1659 #define BCE_PCI_VPD_INTF_INTF_REQ			 (1L<<0)
1661 #define BCE_PCI_VPD_ADDR_FLAG				0x0000042c
1662 #define BCE_PCI_VPD_ADDR_FLAG_ADDRESS			 (0x1fff<<2)
1665 #define BCE_PCI_VPD_DATA				0x00000430
1666 #define BCE_PCI_ID_VAL1				0x00000434
1667 #define BCE_PCI_ID_VAL1_DEVICE_ID			 (0xffffL<<0)
1668 #define BCE_PCI_ID_VAL1_VENDOR_ID			 (0xffffL<<16)
1670 #define BCE_PCI_ID_VAL2				0x00000438
1671 #define BCE_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID		 (0xffffL<<0)
1672 #define BCE_PCI_ID_VAL2_SUBSYSTEM_ID			 (0xffffL<<16)
1674 #define BCE_PCI_ID_VAL3				0x0000043c
1675 #define BCE_PCI_ID_VAL3_CLASS_CODE			 (0xffffffL<<0)
1676 #define BCE_PCI_ID_VAL3_REVISION_ID			 (0xffL<<24)
1678 #define BCE_PCI_ID_VAL4				0x00000440
1679 #define BCE_PCI_ID_VAL4_CAP_ENA			 (0xfL<<0)
1680 #define BCE_PCI_ID_VAL4_CAP_ENA_0			 (0L<<0)
1681 #define BCE_PCI_ID_VAL4_CAP_ENA_1			 (1L<<0)
1682 #define BCE_PCI_ID_VAL4_CAP_ENA_2			 (2L<<0)
1683 #define BCE_PCI_ID_VAL4_CAP_ENA_3			 (3L<<0)
1684 #define BCE_PCI_ID_VAL4_CAP_ENA_4			 (4L<<0)
1685 #define BCE_PCI_ID_VAL4_CAP_ENA_5			 (5L<<0)
1686 #define BCE_PCI_ID_VAL4_CAP_ENA_6			 (6L<<0)
1687 #define BCE_PCI_ID_VAL4_CAP_ENA_7			 (7L<<0)
1688 #define BCE_PCI_ID_VAL4_CAP_ENA_8			 (8L<<0)
1689 #define BCE_PCI_ID_VAL4_CAP_ENA_9			 (9L<<0)
1690 #define BCE_PCI_ID_VAL4_CAP_ENA_10			 (10L<<0)
1691 #define BCE_PCI_ID_VAL4_CAP_ENA_11			 (11L<<0)
1692 #define BCE_PCI_ID_VAL4_CAP_ENA_12			 (12L<<0)
1693 #define BCE_PCI_ID_VAL4_CAP_ENA_13			 (13L<<0)
1694 #define BCE_PCI_ID_VAL4_CAP_ENA_14			 (14L<<0)
1695 #define BCE_PCI_ID_VAL4_CAP_ENA_15			 (15L<<0)
1696 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG			 (0x3L<<6)
1697 #define BCE_PCI_ID_VAL4_PM_SCALE_PRG_0			 (0L<<6)
1701 #define BCE_PCI_ID_VAL4_MSI_LIMIT			 (0x7L<<9)
1702 #define BCE_PCI_ID_VAL4_MSI_ADVERTIZE			 (0x7L<<12)
1706 #define BCE_PCI_ID_VAL4_MAX_MEM_READ_SIZE		 (0x3L<<21)
1707 #define BCE_PCI_ID_VAL4_MAX_SPLIT_SIZE			 (0x7L<<23)
1708 #define BCE_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE		 (0x7L<<26)
1710 #define BCE_PCI_ID_VAL5				0x00000444
1711 #define BCE_PCI_ID_VAL5_D1_SUPPORT			 (1L<<0)
1718 #define BCE_PCI_PCIX_EXTENDED_STATUS			0x00000448
1721 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS	 (0xfL<<16)
1722 #define BCE_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX	 (0xffL<<24)
1724 #define BCE_PCI_ID_VAL6				0x0000044c
1725 #define BCE_PCI_ID_VAL6_MAX_LAT			 (0xffL<<0)
1726 #define BCE_PCI_ID_VAL6_MIN_GNT			 (0xffL<<8)
1727 #define BCE_PCI_ID_VAL6_BIST				 (0xffL<<16)
1729 #define BCE_PCI_MSI_DATA				0x00000450
1730 #define BCE_PCI_MSI_DATA_PCI_MSI_DATA			 (0xffffL<<0)
1732 #define BCE_PCI_MSI_ADDR_H				0x00000454
1733 #define BCE_PCI_MSI_ADDR_L				0x00000458
1737  *  offset: 0x800
1739 #define BCE_MISC_COMMAND						0x00000800
1740 #define BCE_MISC_COMMAND_ENABLE_ALL				(1L<<0)
1748 #define BCE_MISC_COMMAND_CS16_ERR_LOC			(0xfL<<12)
1749 #define BCE_MISC_COMMAND_PAR_ERR_RAM			(0x7fL<<16)
1757 #define BCE_MISC_CFG							0x00000804
1758 #define BCE_MISC_CFG_GRC_TMOUT					(1L<<0)
1759 #define BCE_MISC_CFG_NVM_WR_EN					(0x3L<<1)
1760 #define BCE_MISC_CFG_NVM_WR_EN_PROTECT			(0L<<1)
1769 #define BCE_MISC_CFG_LEDMODE					(0x7L<<8)
1770 #define BCE_MISC_CFG_LEDMODE_MAC				(0L<<8)
1780 #define BCE_MISC_CFG_LEDMODE_XI					(0xfL<<8)
1781 #define BCE_MISC_CFG_LEDMODE_MAC_XI				(0L<<8)
1800 #define BCE_MISC_ID								0x00000808
1801 #define BCE_MISC_ID_BOND_ID						(0xfL<<0)
1802 #define BCE_MISC_ID_BOND_ID_X					(0L<<0)
1803 #define BCE_MISC_ID_BOND_ID_C					(3L<<0)
1804 #define BCE_MISC_ID_BOND_ID_S					(12L<<0)
1805 #define BCE_MISC_ID_CHIP_METAL					(0xffL<<4)
1806 #define BCE_MISC_ID_CHIP_REV					(0xfL<<12)
1807 #define BCE_MISC_ID_CHIP_NUM					(0xffffL<<16)
1809 #define BCE_MISC_ENABLE_STATUS_BITS				0x0000080c
1810 #define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1839 #define BCE_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE	(0x7L<<29)
1841 #define BCE_MISC_ENABLE_SET_BITS						0x00000810
1842 #define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE	(1L<<0)
1871 #define BCE_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE		(0x7L<<29)
1873 #define BCE_MISC_ENABLE_DEFAULT							0x05ffffff
1874 #define BCE_MISC_ENABLE_DEFAULT_XI			  			0x17ffffff
1876 #define BCE_MISC_ENABLE_CLR_BITS						0x00000814
1877 #define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE	(1L<<0)
1906 #define BCE_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE		(0x7L<<29)
1908 #define BCE_MISC_ENABLE_CLR_DEFAULT						0x17ffffff
1910 #define BCE_MISC_CLOCK_CONTROL_BITS			0x00000818
1911 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET	 (0xfL<<0)
1912 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ	 (0L<<0)
1913 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ	 (1L<<0)
1914 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ	 (2L<<0)
1915 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ	 (3L<<0)
1916 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ	 (4L<<0)
1917 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ	 (5L<<0)
1918 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ	 (6L<<0)
1919 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ	 (7L<<0)
1920 #define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW	 (0xfL<<0)
1923 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC	 (0x7L<<8)
1924 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF	 (0L<<8)
1928 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI	 (0x7L<<8)
1930 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED	 (0xfL<<12)
1931 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100	 (0L<<12)
1936 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI	 (0xfL<<12)
1941 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_TE	 (0xfffL<<20)
1943 #define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI	 (0x3fL<<18)
1944 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI	 (0x7L<<24)
1946 #define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI	 (0xfL<<28)
1948 #define BCE_MISC_SPIO					0x0000081c
1949 #define BCE_MISC_SPIO_VALUE				 (0xffL<<0)
1950 #define BCE_MISC_SPIO_SET				 (0xffL<<8)
1951 #define BCE_MISC_SPIO_CLR				 (0xffL<<16)
1952 #define BCE_MISC_SPIO_FLOAT				 (0xffL<<24)
1954 #define BCE_MISC_SPIO_INT				0x00000820
1955 #define BCE_MISC_SPIO_INT_INT_STATE_TE			 (0xfL<<0)
1956 #define BCE_MISC_SPIO_INT_OLD_VALUE_TE			 (0xfL<<8)
1957 #define BCE_MISC_SPIO_INT_OLD_SET_TE			 (0xfL<<16)
1958 #define BCE_MISC_SPIO_INT_OLD_CLR_TE			 (0xfL<<24)
1959 #define BCE_MISC_SPIO_INT_INT_STATE_XI			 (0xffL<<0)
1960 #define BCE_MISC_SPIO_INT_OLD_VALUE_XI			 (0xffL<<8)
1961 #define BCE_MISC_SPIO_INT_OLD_SET_XI			 (0xffL<<16)
1962 #define BCE_MISC_SPIO_INT_OLD_CLR_XI			 (0xffL<<24)
1964 #define BCE_MISC_CONFIG_LFSR				0x00000824
1965 #define BCE_MISC_CONFIG_LFSR_DIV			 (0xffffL<<0)
1967 #define BCE_MISC_LFSR_MASK_BITS			0x00000828
1968 #define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE	 (1L<<0)
1997 #define BCE_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE	 (0x7L<<29)
1999 #define BCE_MISC_ARB_REQ0				0x0000082c
2000 #define BCE_MISC_ARB_REQ1				0x00000830
2001 #define BCE_MISC_ARB_REQ2				0x00000834
2002 #define BCE_MISC_ARB_REQ3				0x00000838
2003 #define BCE_MISC_ARB_REQ4				0x0000083c
2004 #define BCE_MISC_ARB_FREE0				0x00000840
2005 #define BCE_MISC_ARB_FREE1				0x00000844
2006 #define BCE_MISC_ARB_FREE2				0x00000848
2007 #define BCE_MISC_ARB_FREE3				0x0000084c
2008 #define BCE_MISC_ARB_FREE4				0x00000850
2009 #define BCE_MISC_ARB_REQ_STATUS0			0x00000854
2010 #define BCE_MISC_ARB_REQ_STATUS1			0x00000858
2011 #define BCE_MISC_ARB_REQ_STATUS2			0x0000085c
2012 #define BCE_MISC_ARB_REQ_STATUS3			0x00000860
2013 #define BCE_MISC_ARB_REQ_STATUS4			0x00000864
2014 #define BCE_MISC_ARB_GNT0				0x00000868
2015 #define BCE_MISC_ARB_GNT0_0				 (0x7L<<0)
2016 #define BCE_MISC_ARB_GNT0_1				 (0x7L<<4)
2017 #define BCE_MISC_ARB_GNT0_2				 (0x7L<<8)
2018 #define BCE_MISC_ARB_GNT0_3				 (0x7L<<12)
2019 #define BCE_MISC_ARB_GNT0_4				 (0x7L<<16)
2020 #define BCE_MISC_ARB_GNT0_5				 (0x7L<<20)
2021 #define BCE_MISC_ARB_GNT0_6				 (0x7L<<24)
2022 #define BCE_MISC_ARB_GNT0_7				 (0x7L<<28)
2024 #define BCE_MISC_ARB_GNT1				0x0000086c
2025 #define BCE_MISC_ARB_GNT1_8				 (0x7L<<0)
2026 #define BCE_MISC_ARB_GNT1_9				 (0x7L<<4)
2027 #define BCE_MISC_ARB_GNT1_10				 (0x7L<<8)
2028 #define BCE_MISC_ARB_GNT1_11				 (0x7L<<12)
2029 #define BCE_MISC_ARB_GNT1_12				 (0x7L<<16)
2030 #define BCE_MISC_ARB_GNT1_13				 (0x7L<<20)
2031 #define BCE_MISC_ARB_GNT1_14				 (0x7L<<24)
2032 #define BCE_MISC_ARB_GNT1_15				 (0x7L<<28)
2034 #define BCE_MISC_ARB_GNT2				0x00000870
2035 #define BCE_MISC_ARB_GNT2_16				 (0x7L<<0)
2036 #define BCE_MISC_ARB_GNT2_17				 (0x7L<<4)
2037 #define BCE_MISC_ARB_GNT2_18				 (0x7L<<8)
2038 #define BCE_MISC_ARB_GNT2_19				 (0x7L<<12)
2039 #define BCE_MISC_ARB_GNT2_20				 (0x7L<<16)
2040 #define BCE_MISC_ARB_GNT2_21				 (0x7L<<20)
2041 #define BCE_MISC_ARB_GNT2_22				 (0x7L<<24)
2042 #define BCE_MISC_ARB_GNT2_23				 (0x7L<<28)
2044 #define BCE_MISC_ARB_GNT3				0x00000874
2045 #define BCE_MISC_ARB_GNT3_24				 (0x7L<<0)
2046 #define BCE_MISC_ARB_GNT3_25				 (0x7L<<4)
2047 #define BCE_MISC_ARB_GNT3_26				 (0x7L<<8)
2048 #define BCE_MISC_ARB_GNT3_27				 (0x7L<<12)
2049 #define BCE_MISC_ARB_GNT3_28				 (0x7L<<16)
2050 #define BCE_MISC_ARB_GNT3_29				 (0x7L<<20)
2051 #define BCE_MISC_ARB_GNT3_30				 (0x7L<<24)
2052 #define BCE_MISC_ARB_GNT3_31				 (0x7L<<28)
2054 #define BCE_MISC_RESERVED1				0x00000878
2055 #define BCE_MISC_RESERVED1_MISC_RESERVED1_VALUE	 (0x3fL<<0)
2057 #define BCE_MISC_RESERVED2				0x0000087c
2058 #define BCE_MISC_RESERVED2_PCIE_DIS			 (1L<<0)
2061 #define BCE_MISC_SM_ASF_CONTROL			0x00000880
2062 #define BCE_MISC_SM_ASF_CONTROL_ASF_RST		 (1L<<0)
2072 #define BCE_MISC_SM_ASF_CONTROL_RES			 (0x3L<<10)
2077 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1		 (0x7fL<<16)
2078 #define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2		 (0x7fL<<23)
2082 #define BCE_MISC_SMB_IN				0x00000884
2083 #define BCE_MISC_SMB_IN_DAT_IN				 (0xffL<<0)
2087 #define BCE_MISC_SMB_IN_STATUS				 (0x7L<<11)
2088 #define BCE_MISC_SMB_IN_STATUS_OK			 (0x0L<<11)
2089 #define BCE_MISC_SMB_IN_STATUS_PEC			 (0x1L<<11)
2090 #define BCE_MISC_SMB_IN_STATUS_OFLOW			 (0x2L<<11)
2091 #define BCE_MISC_SMB_IN_STATUS_STOP			 (0x3L<<11)
2092 #define BCE_MISC_SMB_IN_STATUS_TIMEOUT			 (0x4L<<11)
2094 #define BCE_MISC_SMB_OUT				0x00000888
2095 #define BCE_MISC_SMB_OUT_DAT_OUT			 (0xffL<<0)
2102 #define BCE_MISC_SMB_OUT_SMB_READ_LEN			 (0x3fL<<14)
2103 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS		 (0xfL<<20)
2104 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK		 (0L<<20)
2112 #define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST	 (0xdL<<20)
2119 #define BCE_MISC_SMB_WATCHDOG				0x0000088c
2120 #define BCE_MISC_SMB_WATCHDOG_WATCHDOG			 (0xffffL<<0)
2122 #define BCE_MISC_SMB_HEARTBEAT				0x00000890
2123 #define BCE_MISC_SMB_HEARTBEAT_HEARTBEAT		 (0xffffL<<0)
2125 #define BCE_MISC_SMB_POLL_ASF				0x00000894
2126 #define BCE_MISC_SMB_POLL_ASF_POLL_ASF			 (0xffffL<<0)
2128 #define BCE_MISC_SMB_POLL_LEGACY			0x00000898
2129 #define BCE_MISC_SMB_POLL_LEGACY_POLL_LEGACY		 (0xffffL<<0)
2131 #define BCE_MISC_SMB_RETRAN				0x0000089c
2132 #define BCE_MISC_SMB_RETRAN_RETRAN			 (0xffL<<0)
2134 #define BCE_MISC_SMB_TIMESTAMP				0x000008a0
2135 #define BCE_MISC_SMB_TIMESTAMP_TIMESTAMP		 (0xffffffffL<<0)
2137 #define BCE_MISC_PERR_ENA0				0x000008a4
2138 #define BCE_MISC_PERR_ENA0_COM_MISC_CTXC		 (1L<<0)
2170 #define BCE_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI		 (1L<<0)
2203 #define BCE_MISC_PERR_ENA1				0x000008a8
2204 #define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS		 (1L<<0)
2236 #define BCE_MISC_PERR_ENA1_RBDC_PERR_EN_XI		 (1L<<0)
2266 #define BCE_MISC_PERR_ENA2				0x000008ac
2267 #define BCE_MISC_PERR_ENA2_COMQ_MISC			 (1L<<0)
2276 #define BCE_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI		 (1L<<0)
2284 #define BCE_MISC_DEBUG_VECTOR_SEL			0x000008b0
2285 #define BCE_MISC_DEBUG_VECTOR_SEL_0			 (0xfffL<<0)
2286 #define BCE_MISC_DEBUG_VECTOR_SEL_1			 (0xfffL<<12)
2287 #define BCE_MISC_DEBUG_VECTOR_SEL_1_XI			 (0xfffL<<15)
2289 #define BCE_MISC_VREG_CONTROL				0x000008b4
2290 #define BCE_MISC_VREG_CONTROL_1_2			 (0xfL<<0)
2291 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_XI		 (0xfL<<0)
2292 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI	 (0L<<0)
2293 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI	 (1L<<0)
2294 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI	 (2L<<0)
2295 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI	 (3L<<0)
2296 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI	 (4L<<0)
2297 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI	 (5L<<0)
2298 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI	 (6L<<0)
2299 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI		 (7L<<0)
2300 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI	 (8L<<0)
2301 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI	 (9L<<0)
2302 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI	 (10L<<0)
2303 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI	 (11L<<0)
2304 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI	 (12L<<0)
2305 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI	 (13L<<0)
2306 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI	 (14L<<0)
2307 #define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI	 (15L<<0)
2308 #define BCE_MISC_VREG_CONTROL_2_5			 (0xfL<<4)
2309 #define BCE_MISC_VREG_CONTROL_2_5_PLUS14		 (0L<<4)
2325 #define BCE_MISC_VREG_CONTROL_1_0_MGMT			 (0xfL<<8)
2326 #define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS14		 (0L<<8)
2343 #define BCE_MISC_FINAL_CLK_CTL_VAL			0x000008b8
2344 #define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL	 (0x3ffffffL<<6)
2346 #define BCE_MISC_GP_HW_CTL0				0x000008bc
2347 #define BCE_MISC_GP_HW_CTL0_TX_DRIVE			 (1L<<0)
2354 #define BCE_MISC_GP_HW_CTL0_RESERVED1_XI		 (0x7L<<4)
2359 #define BCE_MISC_GP_HW_CTL0_RESERVED2_XI		 (0x7L<<8)
2365 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI		 (0xfL<<16)
2366 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA		 (0L<<16)
2374 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT		 (0x3L<<22)
2375 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P		 (0L<<22)
2379 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT		 (0x3L<<24)
2380 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P		 (0L<<24)
2384 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ		 (0x3L<<26)
2385 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA	 (0L<<26)
2389 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ		 (0x3L<<28)
2390 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA	 (0L<<28)
2394 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ		 (0x3L<<30)
2395 #define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57	 (0L<<30)
2400 #define BCE_MISC_GP_HW_CTL1				0x000008c0
2401 #define BCE_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE	 (1L<<0)
2405 #define BCE_MISC_GP_HW_CTL1_RESERVED_SOFT_XI		 (0xffffL<<0)
2406 #define BCE_MISC_GP_HW_CTL1_RESERVED_HARD_XI		 (0xffffL<<16)
2408 #define BCE_MISC_NEW_HW_CTL				0x000008c4
2409 #define BCE_MISC_NEW_HW_CTL_MAIN_POR_BYPASS		 (1L<<0)
2413 #define BCE_MISC_NEW_HW_CTL_RESERVED_SHARED		 (0xfffL<<4)
2414 #define BCE_MISC_NEW_HW_CTL_RESERVED_SPLIT		 (0xffffL<<16)
2416 #define BCE_MISC_NEW_CORE_CTL				0x000008c8
2417 #define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS	 (1L<<0)
2420 #define BCE_MISC_NEW_CORE_CTL_RESERVED_CMN		 (0x3fffL<<2)
2421 #define BCE_MISC_NEW_CORE_CTL_RESERVED_TC		 (0xffffL<<16)
2423 #define BCE_MISC_ECO_HW_CTL				0x000008cc
2424 #define BCE_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN		 (1L<<0)
2425 #define BCE_MISC_ECO_HW_CTL_RESERVED_SOFT		 (0x7fffL<<1)
2426 #define BCE_MISC_ECO_HW_CTL_RESERVED_HARD		 (0xffffL<<16)
2428 #define BCE_MISC_ECO_CORE_CTL				0x000008d0
2429 #define BCE_MISC_ECO_CORE_CTL_RESERVED_SOFT		 (0xffffL<<0)
2430 #define BCE_MISC_ECO_CORE_CTL_RESERVED_HARD		 (0xffffL<<16)
2432 #define BCE_MISC_PPIO					0x000008d4
2433 #define BCE_MISC_PPIO_VALUE				 (0xfL<<0)
2434 #define BCE_MISC_PPIO_SET				 (0xfL<<8)
2435 #define BCE_MISC_PPIO_CLR				 (0xfL<<16)
2436 #define BCE_MISC_PPIO_FLOAT				 (0xfL<<24)
2438 #define BCE_MISC_PPIO_INT				0x000008d8
2439 #define BCE_MISC_PPIO_INT_INT_STATE			 (0xfL<<0)
2440 #define BCE_MISC_PPIO_INT_OLD_VALUE			 (0xfL<<8)
2441 #define BCE_MISC_PPIO_INT_OLD_SET			 (0xfL<<16)
2442 #define BCE_MISC_PPIO_INT_OLD_CLR			 (0xfL<<24)
2444 #define BCE_MISC_RESET_NUMS				0x000008dc
2445 #define BCE_MISC_RESET_NUMS_NUM_HARD_RESETS		 (0x7L<<0)
2446 #define BCE_MISC_RESET_NUMS_NUM_PCIE_RESETS		 (0x7L<<4)
2447 #define BCE_MISC_RESET_NUMS_NUM_PERSTB_RESETS		 (0x7L<<8)
2448 #define BCE_MISC_RESET_NUMS_NUM_CMN_RESETS		 (0x7L<<12)
2449 #define BCE_MISC_RESET_NUMS_NUM_PORT_RESETS		 (0x7L<<16)
2451 #define BCE_MISC_CS16_ERR				0x000008e0
2452 #define BCE_MISC_CS16_ERR_ENA_PCI			 (1L<<0)
2471 #define BCE_MISC_SPIO_EVENT				0x000008e4
2472 #define BCE_MISC_SPIO_EVENT_ENABLE			 (0xffL<<0)
2474 #define BCE_MISC_PPIO_EVENT				0x000008e8
2475 #define BCE_MISC_PPIO_EVENT_ENABLE			 (0xfL<<0)
2477 #define BCE_MISC_DUAL_MEDIA_CTRL			0x000008ec
2478 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID		 (0xffL<<0)
2479 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_X		 (0L<<0)
2480 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C		 (3L<<0)
2481 #define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S		 (12L<<0)
2482 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP	 (0x7L<<8)
2493 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL		 (0x7L<<21)
2496 #define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ	 (0xfL<<26)
2502 #define BCE_MISC_OTP_CMD1				0x000008f0
2503 #define BCE_MISC_OTP_CMD1_FMODE			 (0x7L<<0)
2504 #define BCE_MISC_OTP_CMD1_FMODE_IDLE			 (0L<<0)
2505 #define BCE_MISC_OTP_CMD1_FMODE_WRITE			 (1L<<0)
2506 #define BCE_MISC_OTP_CMD1_FMODE_INIT			 (2L<<0)
2507 #define BCE_MISC_OTP_CMD1_FMODE_SET			 (3L<<0)
2508 #define BCE_MISC_OTP_CMD1_FMODE_RST			 (4L<<0)
2509 #define BCE_MISC_OTP_CMD1_FMODE_VERIFY			 (5L<<0)
2510 #define BCE_MISC_OTP_CMD1_FMODE_RESERVED0		 (6L<<0)
2511 #define BCE_MISC_OTP_CMD1_FMODE_RESERVED1		 (7L<<0)
2515 #define BCE_MISC_OTP_CMD1_PCOUNT			 (0x7L<<16)
2517 #define BCE_MISC_OTP_CMD1_VSEL				 (0xfL<<20)
2518 #define BCE_MISC_OTP_CMD1_TM				 (0x7L<<27)
2522 #define BCE_MISC_OTP_CMD2				0x000008f4
2523 #define BCE_MISC_OTP_CMD2_OTP_ROM_ADDR			 (0x3ffL<<0)
2524 #define BCE_MISC_OTP_CMD2_DOSEL			 (0x7fL<<16)
2525 #define BCE_MISC_OTP_CMD2_DOSEL_0			 (0L<<16)
2529 #define BCE_MISC_OTP_STATUS				0x000008f8
2530 #define BCE_MISC_OTP_STATUS_DATA			 (0xffL<<0)
2536 #define BCE_MISC_OTP_SHIFT1_CMD			0x000008fc
2537 #define BCE_MISC_OTP_SHIFT1_CMD_RESET_MODE_N		 (1L<<0)
2541 #define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT		 (0x1fL<<8)
2543 #define BCE_MISC_OTP_SHIFT1_DATA			0x00000900
2544 #define BCE_MISC_OTP_SHIFT2_CMD			0x00000904
2545 #define BCE_MISC_OTP_SHIFT2_CMD_RESET_MODE_N		 (1L<<0)
2549 #define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT		 (0x1fL<<8)
2551 #define BCE_MISC_OTP_SHIFT2_DATA			0x00000908
2552 #define BCE_MISC_BIST_CS0				0x0000090c
2553 #define BCE_MISC_BIST_CS0_MBIST_EN			 (1L<<0)
2554 #define BCE_MISC_BIST_CS0_BIST_SETUP			 (0x3L<<1)
2560 #define BCE_MISC_BIST_MEMSTATUS0			0x00000910
2561 #define BCE_MISC_BIST_CS1				0x00000914
2562 #define BCE_MISC_BIST_CS1_MBIST_EN			 (1L<<0)
2563 #define BCE_MISC_BIST_CS1_BIST_SETUP			 (0x3L<<1)
2568 #define BCE_MISC_BIST_MEMSTATUS1			0x00000918
2569 #define BCE_MISC_BIST_CS2				0x0000091c
2570 #define BCE_MISC_BIST_CS2_MBIST_EN			 (1L<<0)
2571 #define BCE_MISC_BIST_CS2_BIST_SETUP			 (0x3L<<1)
2576 #define BCE_MISC_BIST_MEMSTATUS2			0x00000920
2577 #define BCE_MISC_BIST_CS3				0x00000924
2578 #define BCE_MISC_BIST_CS3_MBIST_EN			 (1L<<0)
2579 #define BCE_MISC_BIST_CS3_BIST_SETUP			 (0x3L<<1)
2584 #define BCE_MISC_BIST_MEMSTATUS3			0x00000928
2585 #define BCE_MISC_BIST_CS4				0x0000092c
2586 #define BCE_MISC_BIST_CS4_MBIST_EN			 (1L<<0)
2587 #define BCE_MISC_BIST_CS4_BIST_SETUP			 (0x3L<<1)
2592 #define BCE_MISC_BIST_MEMSTATUS4			0x00000930
2593 #define BCE_MISC_BIST_CS5				0x00000934
2594 #define BCE_MISC_BIST_CS5_MBIST_EN			 (1L<<0)
2595 #define BCE_MISC_BIST_CS5_BIST_SETUP			 (0x3L<<1)
2600 #define BCE_MISC_BIST_MEMSTATUS5			0x00000938
2601 #define BCE_MISC_MEM_TM0				0x0000093c
2602 #define BCE_MISC_MEM_TM0_PCIE_REPLAY_TM		 (0xfL<<0)
2603 #define BCE_MISC_MEM_TM0_MCP_SCPAD			 (0xfL<<8)
2604 #define BCE_MISC_MEM_TM0_UMP_TM			 (0xffL<<16)
2605 #define BCE_MISC_MEM_TM0_HB_MEM_TM			 (0xfL<<24)
2607 #define BCE_MISC_USPLL_CTRL				0x00000940
2608 #define BCE_MISC_USPLL_CTRL_PH_DET_DIS			 (1L<<0)
2610 #define BCE_MISC_USPLL_CTRL_LCPX			 (0x3fL<<2)
2611 #define BCE_MISC_USPLL_CTRL_RX				 (0x3L<<8)
2613 #define BCE_MISC_USPLL_CTRL_VCO_MG			 (0x3L<<11)
2614 #define BCE_MISC_USPLL_CTRL_KVCO_XF			 (0x7L<<13)
2615 #define BCE_MISC_USPLL_CTRL_KVCO_XS			 (0x7L<<16)
2617 #define BCE_MISC_USPLL_CTRL_TESTD_SEL			 (0x7L<<20)
2619 #define BCE_MISC_USPLL_CTRL_TESTA_SEL			 (0x3L<<24)
2625 #define BCE_MISC_PERR_STATUS0				0x00000944
2626 #define BCE_MISC_PERR_STATUS0_COM_DMAE_PERR		 (1L<<0)
2659 #define BCE_MISC_PERR_STATUS1				0x00000948
2660 #define BCE_MISC_PERR_STATUS1_RBDC_PERR		 (1L<<0)
2690 #define BCE_MISC_PERR_STATUS2				0x0000094c
2691 #define BCE_MISC_PERR_STATUS2_TGT_FIFO_PERR		 (1L<<0)
2699 #define BCE_MISC_LCPLL_CTRL0				0x00000950
2700 #define BCE_MISC_LCPLL_CTRL0_OAC			 (0x7L<<0)
2701 #define BCE_MISC_LCPLL_CTRL0_OAC_NEGTWENTY		 (0L<<0)
2702 #define BCE_MISC_LCPLL_CTRL0_OAC_ZERO			 (1L<<0)
2703 #define BCE_MISC_LCPLL_CTRL0_OAC_TWENTY		 (3L<<0)
2704 #define BCE_MISC_LCPLL_CTRL0_OAC_FORTY			 (7L<<0)
2705 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL			 (0x7L<<3)
2706 #define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_360		 (0L<<3)
2710 #define BCE_MISC_LCPLL_CTRL0_BIAS_CTRL			 (0x3L<<6)
2711 #define BCE_MISC_LCPLL_CTRL0_PLL_OBSERVE		 (0x7L<<8)
2712 #define BCE_MISC_LCPLL_CTRL0_VTH_CTRL			 (0x3L<<11)
2713 #define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_0		 (0L<<11)
2732 #define BCE_MISC_LCPLL_CTRL1				0x00000954
2733 #define BCE_MISC_LCPLL_CTRL1_CAPSELECTM		 (0x1fL<<0)
2738 #define BCE_MISC_LCPLL_STATUS				0x00000958
2739 #define BCE_MISC_LCPLL_STATUS_FREQDONE_SM		 (1L<<0)
2743 #define BCE_MISC_LCPLL_STATUS_PLLSTATE			 (0x7L<<4)
2744 #define BCE_MISC_LCPLL_STATUS_CAPSTATE			 (0x7L<<7)
2745 #define BCE_MISC_LCPLL_STATUS_CAPSELECT		 (0x1fL<<10)
2747 #define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0	 (0L<<15)
2750 #define BCE_MISC_OSCFUNDS_CTRL				0x0000095c
2752 #define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF		 (0L<<5)
2754 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM		 (0x3L<<6)
2755 #define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0		 (0L<<6)
2759 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ		 (0x3L<<8)
2760 #define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0		 (0L<<8)
2764 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ		 (0x3L<<10)
2765 #define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0		 (0L<<10)
2772  *  offset: 0xc00
2774 #define BCE_DMA_COMMAND				0x00000c00
2775 #define BCE_DMA_COMMAND_ENABLE				 (1L<<0)
2777 #define BCE_DMA_STATUS					0x00000c04
2778 #define BCE_DMA_STATUS_PAR_ERROR_STATE			 (1L<<0)
2790 #define BCE_DMA_CONFIG					0x00000c08
2791 #define BCE_DMA_CONFIG_DATA_BYTE_SWAP			 (1L<<0)
2800 #define BCE_DMA_CONFIG_NO_RCHANS_IN_USE		 (0xfL<<12)
2801 #define BCE_DMA_CONFIG_NO_WCHANS_IN_USE		 (0xfL<<16)
2802 #define BCE_DMA_CONFIG_PCI_CLK_CMP_BITS		 (0x7L<<20)
2804 #define BCE_DMA_CONFIG_BIG_SIZE			 (0xfL<<24)
2805 #define BCE_DMA_CONFIG_BIG_SIZE_NONE			 (0x0L<<24)
2806 #define BCE_DMA_CONFIG_BIG_SIZE_64			 (0x1L<<24)
2807 #define BCE_DMA_CONFIG_BIG_SIZE_128			 (0x2L<<24)
2808 #define BCE_DMA_CONFIG_BIG_SIZE_256			 (0x4L<<24)
2809 #define BCE_DMA_CONFIG_BIG_SIZE_512			 (0x8L<<24)
2811 #define BCE_DMA_BLACKOUT				0x00000c0c
2812 #define BCE_DMA_BLACKOUT_RD_RETRY_BLACKOUT		 (0xffL<<0)
2813 #define BCE_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT		 (0xffL<<8)
2814 #define BCE_DMA_BLACKOUT_WR_RETRY_BLACKOUT		 (0xffL<<16)
2816 #define BCE_DMA_RCHAN_STAT				0x00000c30
2817 #define BCE_DMA_RCHAN_STAT_COMP_CODE_0			 (0x7L<<0)
2819 #define BCE_DMA_RCHAN_STAT_COMP_CODE_1			 (0x7L<<4)
2821 #define BCE_DMA_RCHAN_STAT_COMP_CODE_2			 (0x7L<<8)
2823 #define BCE_DMA_RCHAN_STAT_COMP_CODE_3			 (0x7L<<12)
2825 #define BCE_DMA_RCHAN_STAT_COMP_CODE_4			 (0x7L<<16)
2827 #define BCE_DMA_RCHAN_STAT_COMP_CODE_5			 (0x7L<<20)
2829 #define BCE_DMA_RCHAN_STAT_COMP_CODE_6			 (0x7L<<24)
2831 #define BCE_DMA_RCHAN_STAT_COMP_CODE_7			 (0x7L<<28)
2834 #define BCE_DMA_WCHAN_STAT				0x00000c34
2835 #define BCE_DMA_WCHAN_STAT_COMP_CODE_0			 (0x7L<<0)
2837 #define BCE_DMA_WCHAN_STAT_COMP_CODE_1			 (0x7L<<4)
2839 #define BCE_DMA_WCHAN_STAT_COMP_CODE_2			 (0x7L<<8)
2841 #define BCE_DMA_WCHAN_STAT_COMP_CODE_3			 (0x7L<<12)
2843 #define BCE_DMA_WCHAN_STAT_COMP_CODE_4			 (0x7L<<16)
2845 #define BCE_DMA_WCHAN_STAT_COMP_CODE_5			 (0x7L<<20)
2847 #define BCE_DMA_WCHAN_STAT_COMP_CODE_6			 (0x7L<<24)
2849 #define BCE_DMA_WCHAN_STAT_COMP_CODE_7			 (0x7L<<28)
2852 #define BCE_DMA_RCHAN_ASSIGNMENT			0x00000c38
2853 #define BCE_DMA_RCHAN_ASSIGNMENT_0			 (0xfL<<0)
2854 #define BCE_DMA_RCHAN_ASSIGNMENT_1			 (0xfL<<4)
2855 #define BCE_DMA_RCHAN_ASSIGNMENT_2			 (0xfL<<8)
2856 #define BCE_DMA_RCHAN_ASSIGNMENT_3			 (0xfL<<12)
2857 #define BCE_DMA_RCHAN_ASSIGNMENT_4			 (0xfL<<16)
2858 #define BCE_DMA_RCHAN_ASSIGNMENT_5			 (0xfL<<20)
2859 #define BCE_DMA_RCHAN_ASSIGNMENT_6			 (0xfL<<24)
2860 #define BCE_DMA_RCHAN_ASSIGNMENT_7			 (0xfL<<28)
2862 #define BCE_DMA_WCHAN_ASSIGNMENT			0x00000c3c
2863 #define BCE_DMA_WCHAN_ASSIGNMENT_0			 (0xfL<<0)
2864 #define BCE_DMA_WCHAN_ASSIGNMENT_1			 (0xfL<<4)
2865 #define BCE_DMA_WCHAN_ASSIGNMENT_2			 (0xfL<<8)
2866 #define BCE_DMA_WCHAN_ASSIGNMENT_3			 (0xfL<<12)
2867 #define BCE_DMA_WCHAN_ASSIGNMENT_4			 (0xfL<<16)
2868 #define BCE_DMA_WCHAN_ASSIGNMENT_5			 (0xfL<<20)
2869 #define BCE_DMA_WCHAN_ASSIGNMENT_6			 (0xfL<<24)
2870 #define BCE_DMA_WCHAN_ASSIGNMENT_7			 (0xfL<<28)
2872 #define BCE_DMA_RCHAN_STAT_00				0x00000c40
2873 #define BCE_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW	 (0xffffffffL<<0)
2875 #define BCE_DMA_RCHAN_STAT_01				0x00000c44
2876 #define BCE_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH	 (0xffffffffL<<0)
2878 #define BCE_DMA_RCHAN_STAT_02				0x00000c48
2879 #define BCE_DMA_RCHAN_STAT_02_LENGTH			 (0xffffL<<0)
2884 #define BCE_DMA_RCHAN_STAT_10				0x00000c4c
2885 #define BCE_DMA_RCHAN_STAT_11				0x00000c50
2886 #define BCE_DMA_RCHAN_STAT_12				0x00000c54
2887 #define BCE_DMA_RCHAN_STAT_20				0x00000c58
2888 #define BCE_DMA_RCHAN_STAT_21				0x00000c5c
2889 #define BCE_DMA_RCHAN_STAT_22				0x00000c60
2890 #define BCE_DMA_RCHAN_STAT_30				0x00000c64
2891 #define BCE_DMA_RCHAN_STAT_31				0x00000c68
2892 #define BCE_DMA_RCHAN_STAT_32				0x00000c6c
2893 #define BCE_DMA_RCHAN_STAT_40				0x00000c70
2894 #define BCE_DMA_RCHAN_STAT_41				0x00000c74
2895 #define BCE_DMA_RCHAN_STAT_42				0x00000c78
2896 #define BCE_DMA_RCHAN_STAT_50				0x00000c7c
2897 #define BCE_DMA_RCHAN_STAT_51				0x00000c80
2898 #define BCE_DMA_RCHAN_STAT_52				0x00000c84
2899 #define BCE_DMA_RCHAN_STAT_60				0x00000c88
2900 #define BCE_DMA_RCHAN_STAT_61				0x00000c8c
2901 #define BCE_DMA_RCHAN_STAT_62				0x00000c90
2902 #define BCE_DMA_RCHAN_STAT_70				0x00000c94
2903 #define BCE_DMA_RCHAN_STAT_71				0x00000c98
2904 #define BCE_DMA_RCHAN_STAT_72				0x00000c9c
2905 #define BCE_DMA_WCHAN_STAT_00				0x00000ca0
2906 #define BCE_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW	 (0xffffffffL<<0)
2908 #define BCE_DMA_WCHAN_STAT_01				0x00000ca4
2909 #define BCE_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH	 (0xffffffffL<<0)
2911 #define BCE_DMA_WCHAN_STAT_02				0x00000ca8
2912 #define BCE_DMA_WCHAN_STAT_02_LENGTH			 (0xffffL<<0)
2917 #define BCE_DMA_WCHAN_STAT_10				0x00000cac
2918 #define BCE_DMA_WCHAN_STAT_11				0x00000cb0
2919 #define BCE_DMA_WCHAN_STAT_12				0x00000cb4
2920 #define BCE_DMA_WCHAN_STAT_20				0x00000cb8
2921 #define BCE_DMA_WCHAN_STAT_21				0x00000cbc
2922 #define BCE_DMA_WCHAN_STAT_22				0x00000cc0
2923 #define BCE_DMA_WCHAN_STAT_30				0x00000cc4
2924 #define BCE_DMA_WCHAN_STAT_31				0x00000cc8
2925 #define BCE_DMA_WCHAN_STAT_32				0x00000ccc
2926 #define BCE_DMA_WCHAN_STAT_40				0x00000cd0
2927 #define BCE_DMA_WCHAN_STAT_41				0x00000cd4
2928 #define BCE_DMA_WCHAN_STAT_42				0x00000cd8
2929 #define BCE_DMA_WCHAN_STAT_50				0x00000cdc
2930 #define BCE_DMA_WCHAN_STAT_51				0x00000ce0
2931 #define BCE_DMA_WCHAN_STAT_52				0x00000ce4
2932 #define BCE_DMA_WCHAN_STAT_60				0x00000ce8
2933 #define BCE_DMA_WCHAN_STAT_61				0x00000cec
2934 #define BCE_DMA_WCHAN_STAT_62				0x00000cf0
2935 #define BCE_DMA_WCHAN_STAT_70				0x00000cf4
2936 #define BCE_DMA_WCHAN_STAT_71				0x00000cf8
2937 #define BCE_DMA_WCHAN_STAT_72				0x00000cfc
2938 #define BCE_DMA_ARB_STAT_00				0x00000d00
2939 #define BCE_DMA_ARB_STAT_00_MASTER			 (0xffffL<<0)
2940 #define BCE_DMA_ARB_STAT_00_MASTER_ENC			 (0xffL<<16)
2941 #define BCE_DMA_ARB_STAT_00_CUR_BINMSTR		 (0xffL<<24)
2943 #define BCE_DMA_ARB_STAT_01				0x00000d04
2944 #define BCE_DMA_ARB_STAT_01_LPR_RPTR			 (0xfL<<0)
2945 #define BCE_DMA_ARB_STAT_01_LPR_WPTR			 (0xfL<<4)
2946 #define BCE_DMA_ARB_STAT_01_LPB_RPTR			 (0xfL<<8)
2947 #define BCE_DMA_ARB_STAT_01_LPB_WPTR			 (0xfL<<12)
2948 #define BCE_DMA_ARB_STAT_01_HPR_RPTR			 (0xfL<<16)
2949 #define BCE_DMA_ARB_STAT_01_HPR_WPTR			 (0xfL<<20)
2950 #define BCE_DMA_ARB_STAT_01_HPB_RPTR			 (0xfL<<24)
2951 #define BCE_DMA_ARB_STAT_01_HPB_WPTR			 (0xfL<<28)
2953 #define BCE_DMA_FUSE_CTRL0_CMD				0x00000f00
2954 #define BCE_DMA_FUSE_CTRL0_CMD_PWRUP_DONE		 (1L<<0)
2958 #define BCE_DMA_FUSE_CTRL0_CMD_SEL			 (0xfL<<8)
2960 #define BCE_DMA_FUSE_CTRL0_DATA			0x00000f04
2961 #define BCE_DMA_FUSE_CTRL1_CMD				0x00000f08
2962 #define BCE_DMA_FUSE_CTRL1_CMD_PWRUP_DONE		 (1L<<0)
2966 #define BCE_DMA_FUSE_CTRL1_CMD_SEL			 (0xfL<<8)
2968 #define BCE_DMA_FUSE_CTRL1_DATA			0x00000f0c
2969 #define BCE_DMA_FUSE_CTRL2_CMD				0x00000f10
2970 #define BCE_DMA_FUSE_CTRL2_CMD_PWRUP_DONE		 (1L<<0)
2974 #define BCE_DMA_FUSE_CTRL2_CMD_SEL			 (0xfL<<8)
2976 #define BCE_DMA_FUSE_CTRL2_DATA			0x00000f14
2980  *  offset: 0x1000
2982 #define BCE_CTX_COMMAND									0x00001000
2983 #define BCE_CTX_COMMAND_ENABLED							(1L<<0)
2987 #define BCE_CTX_COMMAND_FLUSH_AHEAD						(0x1fL<<8)
2989 #define BCE_CTX_COMMAND_PAGE_SIZE						(0xfL<<16)
2990 #define BCE_CTX_COMMAND_PAGE_SIZE_256					(0L<<16)
3004 #define BCE_CTX_STATUS									0x00001004
3005 #define BCE_CTX_STATUS_LOCK_WAIT						(1L<<0)
3018 #define BCE_CTX_VIRT_ADDR								0x00001008
3019 #define BCE_CTX_VIRT_ADDR_VIRT_ADDR						(0x7fffL<<6)
3021 #define BCE_CTX_PAGE_TBL								0x0000100c
3022 #define BCE_CTX_PAGE_TBL_PAGE_TBL						(0x3fffL<<6)
3024 #define BCE_CTX_DATA_ADR								0x00001010
3025 #define BCE_CTX_DATA_ADR_DATA_ADR						(0x7ffffL<<2)
3027 #define BCE_CTX_DATA									0x00001014
3028 #define BCE_CTX_LOCK									0x00001018
3029 #define BCE_CTX_LOCK_TYPE								(0x7L<<0)
3030 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID				(0x0L<<0)
3031 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL			(0x1L<<0)
3032 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX					(0x2L<<0)
3033 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER				(0x4L<<0)
3034 #define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE			(0x7L<<0)
3035 #define BCE_CTX_LOCK_TYPE_VOID_XI						(0L<<0)
3036 #define BCE_CTX_LOCK_TYPE_PROTOCOL_XI					(1L<<0)
3037 #define BCE_CTX_LOCK_TYPE_TX_XI							(2L<<0)
3038 #define BCE_CTX_LOCK_TYPE_TIMER_XI						(4L<<0)
3039 #define BCE_CTX_LOCK_TYPE_COMPLETE_XI					(7L<<0)
3040 #define BCE_CTX_LOCK_CID_VALUE							(0x3fffL<<7)
3042 #define BCE_CTX_LOCK_MODE								(0x7L<<27)
3043 #define BCE_CTX_LOCK_MODE_UNLOCK						(0x0L<<27)
3044 #define BCE_CTX_LOCK_MODE_IMMEDIATE						(0x1L<<27)
3045 #define BCE_CTX_LOCK_MODE_SURE							(0x2L<<27)
3049 #define BCE_CTX_CTX_CTRL								0x0000101c
3050 #define BCE_CTX_CTX_CTRL_CTX_ADDR						(0x7ffffL<<2)
3051 #define BCE_CTX_CTX_CTRL_MOD_USAGE_CNT					(0x3L<<21)
3053 #define BCE_CTX_CTX_CTRL_PREFETCH_SIZE					(0x3L<<24)
3058 #define BCE_CTX_CTX_DATA								0x00001020
3059 #define BCE_CTX_ACCESS_STATUS							0x00001040
3060 #define BCE_CTX_ACCESS_STATUS_MASTERENCODED				(0xfL<<0)
3061 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM			(0x3L<<10)
3062 #define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM			(0x3L<<12)
3063 #define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM		(0x3L<<14)
3064 #define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST			(0x7ffL<<17)
3065 #define BCE_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI		(0x1fL<<0)
3066 #define BCE_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI		(0x1fL<<5)
3067 #define BCE_CTX_ACCESS_STATUS_REQUEST_XI				(0x3fffffL<<10)
3069 #define BCE_CTX_DBG_LOCK_STATUS							0x00001044
3070 #define BCE_CTX_DBG_LOCK_STATUS_SM						(0x3ffL<<0)
3071 #define BCE_CTX_DBG_LOCK_STATUS_MATCH					(0x3ffL<<22)
3073 #define BCE_CTX_CACHE_CTRL_STATUS						0x00001048
3074 #define BCE_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW		(1L<<0)
3077 #define BCE_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT		(0x3fL<<7)
3078 #define BCE_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED	(0x3fL<<13)
3091 #define BCE_CTX_CACHE_CTRL_SM_STATUS					0x0000104c
3092 #define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_DWC				(0x7L<<0)
3093 #define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC			(0x7L<<3)
3094 #define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC			(0x7L<<6)
3095 #define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC			(0x7L<<9)
3096 #define BCE_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR	(0x7fffL<<16)
3098 #define BCE_CTX_CACHE_STATUS							0x00001050
3099 #define BCE_CTX_CACHE_STATUS_HELD_ENTRIES				(0x3ffL<<0)
3100 #define BCE_CTX_CACHE_STATUS_MAX_HELD_ENTRIES			(0x3ffL<<16)
3102 #define BCE_CTX_DMA_STATUS								0x00001054
3103 #define BCE_CTX_DMA_STATUS_RD_CHAN0_STATUS				(0x3L<<0)
3104 #define BCE_CTX_DMA_STATUS_RD_CHAN1_STATUS				(0x3L<<2)
3105 #define BCE_CTX_DMA_STATUS_RD_CHAN2_STATUS				(0x3L<<4)
3106 #define BCE_CTX_DMA_STATUS_RD_CHAN3_STATUS				(0x3L<<6)
3107 #define BCE_CTX_DMA_STATUS_RD_CHAN4_STATUS				(0x3L<<8)
3108 #define BCE_CTX_DMA_STATUS_RD_CHAN5_STATUS				(0x3L<<10)
3109 #define BCE_CTX_DMA_STATUS_RD_CHAN6_STATUS				(0x3L<<12)
3110 #define BCE_CTX_DMA_STATUS_RD_CHAN7_STATUS				(0x3L<<14)
3111 #define BCE_CTX_DMA_STATUS_RD_CHAN8_STATUS				(0x3L<<16)
3112 #define BCE_CTX_DMA_STATUS_RD_CHAN9_STATUS				(0x3L<<18)
3113 #define BCE_CTX_DMA_STATUS_RD_CHAN10_STATUS				(0x3L<<20)
3115 #define BCE_CTX_REP_STATUS								0x00001058
3116 #define BCE_CTX_REP_STATUS_ERROR_ENTRY					(0x3ffL<<0)
3117 #define BCE_CTX_REP_STATUS_ERROR_CLIENT_ID				(0x1fL<<10)
3122 #define BCE_CTX_CKSUM_ERROR_STATUS						0x0000105c
3123 #define BCE_CTX_CKSUM_ERROR_STATUS_CALCULATED			(0xffffL<<0)
3124 #define BCE_CTX_CKSUM_ERROR_STATUS_EXPECTED				(0xffffL<<16)
3126 #define BCE_CTX_CHNL_LOCK_STATUS_0						0x00001080
3127 #define BCE_CTX_CHNL_LOCK_STATUS_0_CID					(0x3fffL<<0)
3128 #define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE					(0x3L<<14)
3131 #define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE_XI				(0x7L<<15)
3133 #define BCE_CTX_CHNL_LOCK_STATUS_1						0x00001084
3134 #define BCE_CTX_CHNL_LOCK_STATUS_2						0x00001088
3135 #define BCE_CTX_CHNL_LOCK_STATUS_3						0x0000108c
3136 #define BCE_CTX_CHNL_LOCK_STATUS_4						0x00001090
3137 #define BCE_CTX_CHNL_LOCK_STATUS_5						0x00001094
3138 #define BCE_CTX_CHNL_LOCK_STATUS_6						0x00001098
3139 #define BCE_CTX_CHNL_LOCK_STATUS_7						0x0000109c
3140 #define BCE_CTX_CHNL_LOCK_STATUS_8						0x000010a0
3141 #define BCE_CTX_CHNL_LOCK_STATUS_9						0x000010a4
3143 #define BCE_CTX_CACHE_DATA								0x000010c4
3144 #define BCE_CTX_HOST_PAGE_TBL_CTRL						0x000010c8
3145 #define BCE_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR		(0x1ffL<<0)
3149 #define BCE_CTX_HOST_PAGE_TBL_DATA0						0x000010cc
3150 #define BCE_CTX_HOST_PAGE_TBL_DATA0_VALID				(1L<<0)
3151 #define BCE_CTX_HOST_PAGE_TBL_DATA0_VALUE				(0xffffffL<<8)
3153 #define BCE_CTX_HOST_PAGE_TBL_DATA1						0x000010d0
3154 #define BCE_CTX_CAM_CTRL								0x000010d4
3155 #define BCE_CTX_CAM_CTRL_CAM_ADDR						(0x3ffL<<0)
3164  *  offset: 0x1400
3166 #define BCE_EMAC_MODE					0x00001400
3167 #define BCE_EMAC_MODE_RESET				 (1L<<0)
3169 #define BCE_EMAC_MODE_PORT				 (0x3L<<2)
3170 #define BCE_EMAC_MODE_PORT_NONE			 (0L<<2)
3185 #define BCE_EMAC_STATUS				0x00001404
3193 #define BCE_EMAC_ATTENTION_ENA				0x00001408
3199 #define BCE_EMAC_LED					0x0000140c
3200 #define BCE_EMAC_LED_OVERRIDE				 (1L<<0)
3211 #define BCE_EMAC_LED_BLNK_RATE				 (0xfffL<<19)
3214 #define BCE_EMAC_MAC_MATCH0				0x00001410
3215 #define BCE_EMAC_MAC_MATCH1				0x00001414
3216 #define BCE_EMAC_MAC_MATCH2				0x00001418
3217 #define BCE_EMAC_MAC_MATCH3				0x0000141c
3218 #define BCE_EMAC_MAC_MATCH4				0x00001420
3219 #define BCE_EMAC_MAC_MATCH5				0x00001424
3220 #define BCE_EMAC_MAC_MATCH6				0x00001428
3221 #define BCE_EMAC_MAC_MATCH7				0x0000142c
3222 #define BCE_EMAC_MAC_MATCH8				0x00001430
3223 #define BCE_EMAC_MAC_MATCH9				0x00001434
3224 #define BCE_EMAC_MAC_MATCH10				0x00001438
3225 #define BCE_EMAC_MAC_MATCH11				0x0000143c
3226 #define BCE_EMAC_MAC_MATCH12				0x00001440
3227 #define BCE_EMAC_MAC_MATCH13				0x00001444
3228 #define BCE_EMAC_MAC_MATCH14				0x00001448
3229 #define BCE_EMAC_MAC_MATCH15				0x0000144c
3230 #define BCE_EMAC_MAC_MATCH16				0x00001450
3231 #define BCE_EMAC_MAC_MATCH17				0x00001454
3232 #define BCE_EMAC_MAC_MATCH18				0x00001458
3233 #define BCE_EMAC_MAC_MATCH19				0x0000145c
3234 #define BCE_EMAC_MAC_MATCH20				0x00001460
3235 #define BCE_EMAC_MAC_MATCH21				0x00001464
3236 #define BCE_EMAC_MAC_MATCH22				0x00001468
3237 #define BCE_EMAC_MAC_MATCH23				0x0000146c
3238 #define BCE_EMAC_MAC_MATCH24				0x00001470
3239 #define BCE_EMAC_MAC_MATCH25				0x00001474
3240 #define BCE_EMAC_MAC_MATCH26				0x00001478
3241 #define BCE_EMAC_MAC_MATCH27				0x0000147c
3242 #define BCE_EMAC_MAC_MATCH28				0x00001480
3243 #define BCE_EMAC_MAC_MATCH29				0x00001484
3244 #define BCE_EMAC_MAC_MATCH30				0x00001488
3245 #define BCE_EMAC_MAC_MATCH31				0x0000148c
3246 #define BCE_EMAC_BACKOFF_SEED				0x00001498
3247 #define BCE_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED	 (0x3ffL<<0)
3249 #define BCE_EMAC_RX_MTU_SIZE				0x0000149c
3250 #define BCE_EMAC_RX_MTU_SIZE_MTU_SIZE			 (0xffffL<<0)
3253 #define BCE_EMAC_SERDES_CNTL				0x000014a4
3254 #define BCE_EMAC_SERDES_CNTL_RXR			 (0x7L<<0)
3255 #define BCE_EMAC_SERDES_CNTL_RXG			 (0x3L<<3)
3257 #define BCE_EMAC_SERDES_CNTL_TXBIAS			 (0x7L<<7)
3268 #define BCE_EMAC_SERDES_CNTL_REGCTL12			 (0x3L<<20)
3269 #define BCE_EMAC_SERDES_CNTL_REGCTL25			 (0x3L<<22)
3271 #define BCE_EMAC_SERDES_STATUS				0x000014a8
3272 #define BCE_EMAC_SERDES_STATUS_RX_STAT			 (0xffL<<0)
3275 #define BCE_EMAC_MDIO_COMM				0x000014ac
3276 #define BCE_EMAC_MDIO_COMM_DATA			 (0xffffL<<0)
3277 #define BCE_EMAC_MDIO_COMM_REG_ADDR			 (0x1fL<<16)
3278 #define BCE_EMAC_MDIO_COMM_PHY_ADDR			 (0x1fL<<21)
3279 #define BCE_EMAC_MDIO_COMM_COMMAND			 (0x3L<<26)
3280 #define BCE_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0		 (0L<<26)
3288 #define BCE_EMAC_MDIO_STATUS				0x000014b0
3289 #define BCE_EMAC_MDIO_STATUS_LINK			 (1L<<0)
3292 #define BCE_EMAC_MDIO_MODE				0x000014b4
3300 #define BCE_EMAC_MDIO_MODE_CLOCK_CNT			 (0x1fL<<16)
3302 #define BCE_EMAC_MDIO_AUTO_STATUS			0x000014b8
3303 #define BCE_EMAC_MDIO_AUTO_STATUS_AUTO_ERR		 (1L<<0)
3305 #define BCE_EMAC_TX_MODE				0x000014bc
3306 #define BCE_EMAC_TX_MODE_RESET				 (1L<<0)
3313 #define BCE_EMAC_TX_STATUS				0x000014c0
3314 #define BCE_EMAC_TX_STATUS_XOFFED			 (1L<<0)
3320 #define BCE_EMAC_TX_LENGTHS				0x000014c4
3321 #define BCE_EMAC_TX_LENGTHS_SLOT			 (0xffL<<0)
3322 #define BCE_EMAC_TX_LENGTHS_IPG			 (0xfL<<8)
3323 #define BCE_EMAC_TX_LENGTHS_IPG_CRS			 (0x3L<<12)
3325 #define BCE_EMAC_RX_MODE				0x000014c8
3326 #define BCE_EMAC_RX_MODE_RESET				 (1L<<0)
3339 #define BCE_EMAC_RX_STATUS				0x000014cc
3340 #define BCE_EMAC_RX_STATUS_FFED			 (1L<<0)
3344 #define BCE_EMAC_MULTICAST_HASH0			0x000014d0
3345 #define BCE_EMAC_MULTICAST_HASH1			0x000014d4
3346 #define BCE_EMAC_MULTICAST_HASH2			0x000014d8
3347 #define BCE_EMAC_MULTICAST_HASH3			0x000014dc
3348 #define BCE_EMAC_MULTICAST_HASH4			0x000014e0
3349 #define BCE_EMAC_MULTICAST_HASH5			0x000014e4
3350 #define BCE_EMAC_MULTICAST_HASH6			0x000014e8
3351 #define BCE_EMAC_MULTICAST_HASH7			0x000014ec
3352 #define BCE_EMAC_RX_STAT_IFHCINOCTETS			0x00001500
3353 #define BCE_EMAC_RX_STAT_IFHCINBADOCTETS		0x00001504
3354 #define BCE_EMAC_RX_STAT_ETHERSTATSFRAGMENTS		0x00001508
3355 #define BCE_EMAC_RX_STAT_IFHCINUCASTPKTS		0x0000150c
3356 #define BCE_EMAC_RX_STAT_IFHCINMULTICASTPKTS		0x00001510
3357 #define BCE_EMAC_RX_STAT_IFHCINBROADCASTPKTS		0x00001514
3358 #define BCE_EMAC_RX_STAT_DOT3STATSFCSERRORS		0x00001518
3359 #define BCE_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS	0x0000151c
3360 #define BCE_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS	0x00001520
3361 #define BCE_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED	0x00001524
3362 #define BCE_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED	0x00001528
3363 #define BCE_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED	0x0000152c
3364 #define BCE_EMAC_RX_STAT_XOFFSTATEENTERED		0x00001530
3365 #define BCE_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG	0x00001534
3366 #define BCE_EMAC_RX_STAT_ETHERSTATSJABBERS		0x00001538
3367 #define BCE_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS	0x0000153c
3368 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS	0x00001540
3369 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS	0x00001544
3370 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS	0x00001548
3371 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS	0x0000154c
3372 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS	0x00001550
3373 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS	0x00001554
3374 #define BCE_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS	0x00001558
3375 #define BCE_EMAC_RXMAC_DEBUG0				0x0000155c
3376 #define BCE_EMAC_RXMAC_DEBUG1				0x00001560
3377 #define BCE_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT	 (1L<<0)
3384 #define BCE_EMAC_RXMAC_DEBUG1_BYTE_COUNT		 (0xffffL<<7)
3385 #define BCE_EMAC_RXMAC_DEBUG1_SLOT_TIME		 (0xffL<<23)
3387 #define BCE_EMAC_RXMAC_DEBUG2				0x00001564
3388 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE			 (0x7L<<0)
3389 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE		 (0x0L<<0)
3390 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SFD		 (0x1L<<0)
3391 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DATA		 (0x2L<<0)
3392 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP		 (0x3L<<0)
3393 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_EXT		 (0x4L<<0)
3394 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_DROP		 (0x5L<<0)
3395 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP		 (0x6L<<0)
3396 #define BCE_EMAC_RXMAC_DEBUG2_SM_STATE_FC		 (0x7L<<0)
3397 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE		 (0xfL<<3)
3398 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE		 (0x0L<<3)
3399 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0		 (0x1L<<3)
3400 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1		 (0x2L<<3)
3401 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2		 (0x3L<<3)
3402 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3		 (0x4L<<3)
3403 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT		 (0x5L<<3)
3404 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT		 (0x6L<<3)
3405 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS		 (0x7L<<3)
3406 #define BCE_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST		 (0x8L<<3)
3407 #define BCE_EMAC_RXMAC_DEBUG2_BYTE_IN			 (0xffL<<7)
3411 #define BCE_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE		 (0L<<18)
3413 #define BCE_EMAC_RXMAC_DEBUG2_SE_COUNTER		 (0xfL<<19)
3414 #define BCE_EMAC_RXMAC_DEBUG2_QUANTA			 (0x1fL<<23)
3416 #define BCE_EMAC_RXMAC_DEBUG3				0x00001568
3417 #define BCE_EMAC_RXMAC_DEBUG3_PAUSE_CTR		 (0xffffL<<0)
3418 #define BCE_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR		 (0xffffL<<16)
3420 #define BCE_EMAC_RXMAC_DEBUG4				0x0000156c
3421 #define BCE_EMAC_RXMAC_DEBUG4_TYPE_FIELD		 (0xffffL<<0)
3422 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE		 (0x3fL<<16)
3423 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE		 (0x0L<<16)
3424 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2		 (0x1L<<16)
3425 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3		 (0x2L<<16)
3426 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI		 (0x3L<<16)
3427 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2		 (0x7L<<16)
3428 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3		 (0x5L<<16)
3429 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1		 (0x6L<<16)
3430 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2		 (0x7L<<16)
3431 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3		 (0x8L<<16)
3432 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2		 (0x9L<<16)
3433 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3		 (0xaL<<16)
3434 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1	 (0xeL<<16)
3435 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2	 (0xfL<<16)
3436 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK	 (0x10L<<16)
3437 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MC		 (0x11L<<16)
3438 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2		 (0x12L<<16)
3439 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3		 (0x13L<<16)
3440 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1		 (0x14L<<16)
3441 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2		 (0x15L<<16)
3442 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3		 (0x16L<<16)
3443 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE		 (0x17L<<16)
3444 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_BC		 (0x18L<<16)
3445 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE		 (0x19L<<16)
3446 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD		 (0x1aL<<16)
3447 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC		 (0x1bL<<16)
3448 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH		 (0x1cL<<16)
3449 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF		 (0x1dL<<16)
3450 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_XON		 (0x1eL<<16)
3451 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED	 (0x1fL<<16)
3452 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED	 (0x20L<<16)
3453 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE		 (0x21L<<16)
3454 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL		 (0x22L<<16)
3455 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1		 (0x23L<<16)
3456 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2		 (0x24L<<16)
3457 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3		 (0x25L<<16)
3458 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE		 (0x26L<<16)
3459 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE	 (0x27L<<16)
3460 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL		 (0x28L<<16)
3461 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE		 (0x29L<<16)
3462 #define BCE_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP		 (0x2aL<<16)
3471 #define BCE_EMAC_RXMAC_DEBUG5				0x00001570
3472 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM			 (0x7L<<0)
3473 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE		 (0L<<0)
3474 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF	 (1L<<0)
3475 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT	 (2L<<0)
3476 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC	 (3L<<0)
3477 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE	 (4L<<0)
3478 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL	 (5L<<0)
3479 #define BCE_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT	 (6L<<0)
3480 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1		 (0x7L<<4)
3481 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW		 (0x0L<<4)
3482 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT		 (0x1L<<4)
3483 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF		 (0x2L<<4)
3484 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF		 (0x3L<<4)
3485 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF		 (0x4L<<4)
3486 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF		 (0x6L<<4)
3487 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF		 (0x7L<<4)
3489 #define BCE_EMAC_RXMAC_DEBUG5_CCODE_BUF0		 (0x7L<<8)
3495 #define BCE_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE		 (0x3L<<16)
3497 #define BCE_EMAC_RXMAC_DEBUG5_FMLEN			 (0xfffL<<20)
3499 #define BCE_EMAC_RX_STAT_AC0				0x00001580
3500 #define BCE_EMAC_RX_STAT_AC1				0x00001584
3501 #define BCE_EMAC_RX_STAT_AC2				0x00001588
3502 #define BCE_EMAC_RX_STAT_AC3				0x0000158c
3503 #define BCE_EMAC_RX_STAT_AC4				0x00001590
3504 #define BCE_EMAC_RX_STAT_AC5				0x00001594
3505 #define BCE_EMAC_RX_STAT_AC6				0x00001598
3506 #define BCE_EMAC_RX_STAT_AC7				0x0000159c
3507 #define BCE_EMAC_RX_STAT_AC8				0x000015a0
3508 #define BCE_EMAC_RX_STAT_AC9				0x000015a4
3509 #define BCE_EMAC_RX_STAT_AC10				0x000015a8
3510 #define BCE_EMAC_RX_STAT_AC11				0x000015ac
3511 #define BCE_EMAC_RX_STAT_AC12				0x000015b0
3512 #define BCE_EMAC_RX_STAT_AC13				0x000015b4
3513 #define BCE_EMAC_RX_STAT_AC14				0x000015b8
3514 #define BCE_EMAC_RX_STAT_AC15				0x000015bc
3515 #define BCE_EMAC_RX_STAT_AC16				0x000015c0
3516 #define BCE_EMAC_RX_STAT_AC17				0x000015c4
3517 #define BCE_EMAC_RX_STAT_AC18				0x000015c8
3518 #define BCE_EMAC_RX_STAT_AC19				0x000015cc
3519 #define BCE_EMAC_RX_STAT_AC20				0x000015d0
3520 #define BCE_EMAC_RX_STAT_AC21				0x000015d4
3521 #define BCE_EMAC_RX_STAT_AC22				0x000015d8
3522 #define BCE_EMAC_RXMAC_SUC_DBG_OVERRUNVEC		0x000015dc
3523 #define BCE_EMAC_TX_STAT_IFHCOUTOCTETS			0x00001600
3524 #define BCE_EMAC_TX_STAT_IFHCOUTBADOCTETS		0x00001604
3525 #define BCE_EMAC_TX_STAT_ETHERSTATSCOLLISIONS		0x00001608
3526 #define BCE_EMAC_TX_STAT_OUTXONSENT			0x0000160c
3527 #define BCE_EMAC_TX_STAT_OUTXOFFSENT			0x00001610
3528 #define BCE_EMAC_TX_STAT_FLOWCONTROLDONE		0x00001614
3529 #define BCE_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES	0x00001618
3530 #define BCE_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES	0x0000161c
3531 #define BCE_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS	0x00001620
3532 #define BCE_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS	0x00001624
3533 #define BCE_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS	0x00001628
3534 #define BCE_EMAC_TX_STAT_IFHCOUTUCASTPKTS		0x0000162c
3535 #define BCE_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS		0x00001630
3536 #define BCE_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS		0x00001634
3537 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS	0x00001638
3538 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS	0x0000163c
3539 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS	0x00001640
3540 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS	0x00001644
3541 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS	0x00001648
3542 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS	0x0000164c
3543 #define BCE_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS	0x00001650
3544 #define BCE_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS	0x00001654
3545 #define BCE_EMAC_TXMAC_DEBUG0				0x00001658
3546 #define BCE_EMAC_TXMAC_DEBUG1				0x0000165c
3547 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE		 (0xfL<<0)
3548 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE		 (0x0L<<0)
3549 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_START0		 (0x1L<<0)
3550 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0		 (0x4L<<0)
3551 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1		 (0x5L<<0)
3552 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2		 (0x6L<<0)
3553 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3		 (0x7L<<0)
3554 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0		 (0x8L<<0)
3555 #define BCE_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1		 (0x9L<<0)
3558 #define BCE_EMAC_TXMAC_DEBUG1_SE_COUNTER		 (0xfL<<6)
3564 #define BCE_EMAC_TXMAC_DEBUG1_IPG_TIME			 (0xfL<<15)
3565 #define BCE_EMAC_TXMAC_DEBUG1_SLOT_TIME		 (0xffL<<19)
3567 #define BCE_EMAC_TXMAC_DEBUG2				0x00001660
3568 #define BCE_EMAC_TXMAC_DEBUG2_BACK_OFF			 (0x3ffL<<0)
3569 #define BCE_EMAC_TXMAC_DEBUG2_BYTE_COUNT		 (0xffffL<<10)
3570 #define BCE_EMAC_TXMAC_DEBUG2_COL_COUNT		 (0x1fL<<26)
3573 #define BCE_EMAC_TXMAC_DEBUG3				0x00001664
3574 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE			 (0xfL<<0)
3575 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE		 (0x0L<<0)
3576 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1		 (0x1L<<0)
3577 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2		 (0x2L<<0)
3578 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SFD		 (0x3L<<0)
3579 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_DATA		 (0x4L<<0)
3580 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1		 (0x5L<<0)
3581 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2		 (0x6L<<0)
3582 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EXT		 (0x7L<<0)
3583 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATB		 (0x8L<<0)
3584 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_STATG		 (0x9L<<0)
3585 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_JAM		 (0xaL<<0)
3586 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM		 (0xbL<<0)
3587 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM		 (0xcL<<0)
3588 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT		 (0xdL<<0)
3589 #define BCE_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF		 (0xeL<<0)
3590 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE		 (0x7L<<4)
3591 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE		 (0x0L<<4)
3592 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT		 (0x1L<<4)
3593 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI		 (0x2L<<4)
3594 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_MC		 (0x3L<<4)
3595 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2		 (0x4L<<4)
3596 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3		 (0x5L<<4)
3597 #define BCE_EMAC_TXMAC_DEBUG3_FILT_STATE_BC		 (0x6L<<4)
3600 #define BCE_EMAC_TXMAC_DEBUG3_SE_COUNTER		 (0xfL<<9)
3601 #define BCE_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER		 (0x1fL<<13)
3603 #define BCE_EMAC_TXMAC_DEBUG4				0x00001668
3604 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER		 (0xffffL<<0)
3605 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE		 (0xfL<<16)
3606 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE		 (0x0L<<16)
3607 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1		 (0x2L<<16)
3608 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2		 (0x3L<<16)
3609 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3		 (0x6L<<16)
3610 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1		 (0x7L<<16)
3611 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2		 (0x5L<<16)
3612 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3		 (0x4L<<16)
3613 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE		 (0xcL<<16)
3614 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD		 (0xeL<<16)
3615 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME		 (0xaL<<16)
3616 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1		 (0x8L<<16)
3617 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2		 (0x9L<<16)
3618 #define BCE_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT		 (0xdL<<16)
3632 #define BCE_EMAC_TX_STAT_AC0				0x00001680
3633 #define BCE_EMAC_TX_STAT_AC1				0x00001684
3634 #define BCE_EMAC_TX_STAT_AC2				0x00001688
3635 #define BCE_EMAC_TX_STAT_AC3				0x0000168c
3636 #define BCE_EMAC_TX_STAT_AC4				0x00001690
3637 #define BCE_EMAC_TX_STAT_AC5				0x00001694
3638 #define BCE_EMAC_TX_STAT_AC6				0x00001698
3639 #define BCE_EMAC_TX_STAT_AC7				0x0000169c
3640 #define BCE_EMAC_TX_STAT_AC8				0x000016a0
3641 #define BCE_EMAC_TX_STAT_AC9				0x000016a4
3642 #define BCE_EMAC_TX_STAT_AC10				0x000016a8
3643 #define BCE_EMAC_TX_STAT_AC11				0x000016ac
3644 #define BCE_EMAC_TX_STAT_AC12				0x000016b0
3645 #define BCE_EMAC_TX_STAT_AC13				0x000016b4
3646 #define BCE_EMAC_TX_STAT_AC14				0x000016b8
3647 #define BCE_EMAC_TX_STAT_AC15				0x000016bc
3648 #define BCE_EMAC_TX_STAT_AC16				0x000016c0
3649 #define BCE_EMAC_TX_STAT_AC17				0x000016c4
3650 #define BCE_EMAC_TX_STAT_AC18				0x000016c8
3651 #define BCE_EMAC_TX_STAT_AC19				0x000016cc
3652 #define BCE_EMAC_TX_STAT_AC20				0x000016d0
3653 #define BCE_EMAC_TX_STAT_AC21				0x000016d4
3654 #define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC		0x000016d8
3658  *  offset: 0x1800
3660 #define BCE_RPM_COMMAND				0x00001800
3661 #define BCE_RPM_COMMAND_ENABLED			 (1L<<0)
3664 #define BCE_RPM_STATUS					0x00001804
3665 #define BCE_RPM_STATUS_MBUF_WAIT			 (1L<<0)
3668 #define BCE_RPM_CONFIG					0x00001808
3669 #define BCE_RPM_CONFIG_NO_PSD_HDR_CKSUM		 (1L<<0)
3673 #define BCE_RPM_CONFIG_SORT_VECT_VAL			 (0xfL<<4)
3676 #define BCE_RPM_MGMT_PKT_CTRL					0x0000180c
3680 #define BCE_RPM_VLAN_MATCH0				0x00001810
3681 #define BCE_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE	 (0xfffL<<0)
3683 #define BCE_RPM_VLAN_MATCH1				0x00001814
3684 #define BCE_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE	 (0xfffL<<0)
3686 #define BCE_RPM_VLAN_MATCH2				0x00001818
3687 #define BCE_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE	 (0xfffL<<0)
3689 #define BCE_RPM_VLAN_MATCH3				0x0000181c
3690 #define BCE_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE	 (0xfffL<<0)
3692 #define BCE_RPM_SORT_USER0				0x00001820
3693 #define BCE_RPM_SORT_USER0_PM_EN			 (0xffffL<<0)
3698 #define BCE_RPM_SORT_USER0_VLAN_EN			 (0xfL<<20)
3702 #define BCE_RPM_SORT_USER1				0x00001824
3703 #define BCE_RPM_SORT_USER1_PM_EN			 (0xffffL<<0)
3708 #define BCE_RPM_SORT_USER1_VLAN_EN			 (0xfL<<20)
3712 #define BCE_RPM_SORT_USER2				0x00001828
3713 #define BCE_RPM_SORT_USER2_PM_EN			 (0xffffL<<0)
3718 #define BCE_RPM_SORT_USER2_VLAN_EN			 (0xfL<<20)
3722 #define BCE_RPM_SORT_USER3				0x0000182c
3723 #define BCE_RPM_SORT_USER3_PM_EN			 (0xffffL<<0)
3728 #define BCE_RPM_SORT_USER3_VLAN_EN			 (0xfL<<20)
3732 #define BCE_RPM_STAT_L2_FILTER_DISCARDS		0x00001840
3733 #define BCE_RPM_STAT_RULE_CHECKER_DISCARDS		0x00001844
3734 #define BCE_RPM_STAT_IFINFTQDISCARDS			0x00001848
3735 #define BCE_RPM_STAT_IFINMBUFDISCARD			0x0000184c
3736 #define BCE_RPM_STAT_RULE_CHECKER_P4_HIT		0x00001850
3737 #define BCE_RPM_STAT_AC0				0x00001880
3738 #define BCE_RPM_STAT_AC1				0x00001884
3739 #define BCE_RPM_STAT_AC2				0x00001888
3740 #define BCE_RPM_STAT_AC3				0x0000188c
3741 #define BCE_RPM_STAT_AC4				0x00001890
3742 #define BCE_RPM_RC_CNTL_0				0x00001900
3743 #define BCE_RPM_RC_CNTL_0_OFFSET			 (0xffL<<0)
3744 #define BCE_RPM_RC_CNTL_0_CLASS			 (0x7L<<8)
3747 #define BCE_RPM_RC_CNTL_0_HDR_TYPE			 (0x7L<<13)
3748 #define BCE_RPM_RC_CNTL_0_HDR_TYPE_START		 (0L<<13)
3753 #define BCE_RPM_RC_CNTL_0_COMP				 (0x3L<<16)
3754 #define BCE_RPM_RC_CNTL_0_COMP_EQUAL			 (0L<<16)
3759 #define BCE_RPM_RC_CNTL_0_CMDSEL			 (0xfL<<20)
3768 #define BCE_RPM_RC_VALUE_MASK_0			0x00001904
3769 #define BCE_RPM_RC_VALUE_MASK_0_VALUE			 (0xffffL<<0)
3770 #define BCE_RPM_RC_VALUE_MASK_0_MASK			 (0xffffL<<16)
3772 #define BCE_RPM_RC_CNTL_1				0x00001908
3773 #define BCE_RPM_RC_CNTL_1_A				 (0x3ffffL<<0)
3774 #define BCE_RPM_RC_CNTL_1_B				 (0xfffL<<19)
3776 #define BCE_RPM_RC_VALUE_MASK_1			0x0000190c
3777 #define BCE_RPM_RC_CNTL_2				0x00001910
3778 #define BCE_RPM_RC_CNTL_2_A				 (0x3ffffL<<0)
3779 #define BCE_RPM_RC_CNTL_2_B				 (0xfffL<<19)
3781 #define BCE_RPM_RC_VALUE_MASK_2			0x00001914
3782 #define BCE_RPM_RC_CNTL_3				0x00001918
3783 #define BCE_RPM_RC_CNTL_3_A				 (0x3ffffL<<0)
3784 #define BCE_RPM_RC_CNTL_3_B				 (0xfffL<<19)
3786 #define BCE_RPM_RC_VALUE_MASK_3			0x0000191c
3787 #define BCE_RPM_RC_CNTL_4				0x00001920
3788 #define BCE_RPM_RC_CNTL_4_A				 (0x3ffffL<<0)
3789 #define BCE_RPM_RC_CNTL_4_B				 (0xfffL<<19)
3791 #define BCE_RPM_RC_VALUE_MASK_4			0x00001924
3792 #define BCE_RPM_RC_CNTL_5				0x00001928
3793 #define BCE_RPM_RC_CNTL_5_A				 (0x3ffffL<<0)
3794 #define BCE_RPM_RC_CNTL_5_B				 (0xfffL<<19)
3796 #define BCE_RPM_RC_VALUE_MASK_5			0x0000192c
3797 #define BCE_RPM_RC_CNTL_6				0x00001930
3798 #define BCE_RPM_RC_CNTL_6_A				 (0x3ffffL<<0)
3799 #define BCE_RPM_RC_CNTL_6_B				 (0xfffL<<19)
3801 #define BCE_RPM_RC_VALUE_MASK_6			0x00001934
3802 #define BCE_RPM_RC_CNTL_7				0x00001938
3803 #define BCE_RPM_RC_CNTL_7_A				 (0x3ffffL<<0)
3804 #define BCE_RPM_RC_CNTL_7_B				 (0xfffL<<19)
3806 #define BCE_RPM_RC_VALUE_MASK_7			0x0000193c
3807 #define BCE_RPM_RC_CNTL_8				0x00001940
3808 #define BCE_RPM_RC_CNTL_8_A				 (0x3ffffL<<0)
3809 #define BCE_RPM_RC_CNTL_8_B				 (0xfffL<<19)
3811 #define BCE_RPM_RC_VALUE_MASK_8			0x00001944
3812 #define BCE_RPM_RC_CNTL_9				0x00001948
3813 #define BCE_RPM_RC_CNTL_9_A				 (0x3ffffL<<0)
3814 #define BCE_RPM_RC_CNTL_9_B				 (0xfffL<<19)
3816 #define BCE_RPM_RC_VALUE_MASK_9			0x0000194c
3817 #define BCE_RPM_RC_CNTL_10				0x00001950
3818 #define BCE_RPM_RC_CNTL_10_A				 (0x3ffffL<<0)
3819 #define BCE_RPM_RC_CNTL_10_B				 (0xfffL<<19)
3821 #define BCE_RPM_RC_VALUE_MASK_10			0x00001954
3822 #define BCE_RPM_RC_CNTL_11				0x00001958
3823 #define BCE_RPM_RC_CNTL_11_A				 (0x3ffffL<<0)
3824 #define BCE_RPM_RC_CNTL_11_B				 (0xfffL<<19)
3826 #define BCE_RPM_RC_VALUE_MASK_11			0x0000195c
3827 #define BCE_RPM_RC_CNTL_12				0x00001960
3828 #define BCE_RPM_RC_CNTL_12_A				 (0x3ffffL<<0)
3829 #define BCE_RPM_RC_CNTL_12_B				 (0xfffL<<19)
3831 #define BCE_RPM_RC_VALUE_MASK_12			0x00001964
3832 #define BCE_RPM_RC_CNTL_13				0x00001968
3833 #define BCE_RPM_RC_CNTL_13_A				 (0x3ffffL<<0)
3834 #define BCE_RPM_RC_CNTL_13_B				 (0xfffL<<19)
3836 #define BCE_RPM_RC_VALUE_MASK_13			0x0000196c
3837 #define BCE_RPM_RC_CNTL_14				0x00001970
3838 #define BCE_RPM_RC_CNTL_14_A				 (0x3ffffL<<0)
3839 #define BCE_RPM_RC_CNTL_14_B				 (0xfffL<<19)
3841 #define BCE_RPM_RC_VALUE_MASK_14			0x00001974
3842 #define BCE_RPM_RC_CNTL_15				0x00001978
3843 #define BCE_RPM_RC_CNTL_15_A				 (0x3ffffL<<0)
3844 #define BCE_RPM_RC_CNTL_15_B				 (0xfffL<<19)
3846 #define BCE_RPM_RC_VALUE_MASK_15			0x0000197c
3847 #define BCE_RPM_RC_CONFIG				0x00001980
3848 #define BCE_RPM_RC_CONFIG_RULE_ENABLE			 (0xffffL<<0)
3849 #define BCE_RPM_RC_CONFIG_DEF_CLASS			 (0x7L<<24)
3851 #define BCE_RPM_DEBUG0					0x00001984
3852 #define BCE_RPM_DEBUG0_FM_BCNT				 (0xffffL<<0)
3868 #define BCE_RPM_DEBUG1					0x00001988
3869 #define BCE_RPM_DEBUG1_FSM_CUR_ST			 (0xffffL<<0)
3870 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IDLE			 (0L<<0)
3871 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL		 (1L<<0)
3872 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC	 (2L<<0)
3873 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP		 (4L<<0)
3874 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP		 (8L<<0)
3875 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP_START		 (16L<<0)
3876 #define BCE_RPM_DEBUG1_FSM_CUR_ST_IP			 (32L<<0)
3877 #define BCE_RPM_DEBUG1_FSM_CUR_ST_TCP			 (64L<<0)
3878 #define BCE_RPM_DEBUG1_FSM_CUR_ST_UDP			 (128L<<0)
3879 #define BCE_RPM_DEBUG1_FSM_CUR_ST_AH			 (256L<<0)
3880 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP			 (512L<<0)
3881 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD		 (1024L<<0)
3882 #define BCE_RPM_DEBUG1_FSM_CUR_ST_DATA			 (2048L<<0)
3883 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY		 (0x2000L<<0)
3884 #define BCE_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT		 (0x4000L<<0)
3885 #define BCE_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT		 (0x8000L<<0)
3886 #define BCE_RPM_DEBUG1_HDR_BCNT			 (0x7ffL<<16)
3892 #define BCE_RPM_DEBUG2					0x0000198c
3893 #define BCE_RPM_DEBUG2_CMD_HIT_VEC			 (0xffffL<<0)
3894 #define BCE_RPM_DEBUG2_IP_BCNT				 (0xffL<<16)
3904 #define BCE_RPM_DEBUG3					0x00001990
3905 #define BCE_RPM_DEBUG3_AVAIL_MBUF_PTR			 (0x1ffL<<0)
3913 #define BCE_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT		 (0xfL<<16)
3917 #define BCE_RPM_DEBUG3_FTQ_FSM				 (0x3L<<24)
3918 #define BCE_RPM_DEBUG3_FTQ_FSM_IDLE			 (0x0L<<24)
3919 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_ACK		 (0x1L<<24)
3920 #define BCE_RPM_DEBUG3_FTQ_FSM_WAIT_FREE		 (0x2L<<24)
3921 #define BCE_RPM_DEBUG3_MBWRITE_FSM			 (0x3L<<26)
3922 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF		 (0x0L<<26)
3923 #define BCE_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF		 (0x1L<<26)
3924 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA		 (0x2L<<26)
3925 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA		 (0x3L<<26)
3926 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF		 (0x4L<<26)
3927 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK		 (0x5L<<26)
3928 #define BCE_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD	 (0x6L<<26)
3929 #define BCE_RPM_DEBUG3_MBWRITE_FSM_DONE		 (0x7L<<26)
3931 #define BCE_RPM_DEBUG3_MBFREE_FSM_IDLE			 (0L<<29)
3934 #define BCE_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF		 (0x0L<<30)
3935 #define BCE_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF		 (0x1L<<30)
3938 #define BCE_RPM_DEBUG4					0x00001994
3939 #define BCE_RPM_DEBUG4_DFSM_MBUF_CLUSTER		 (0x1ffffffL<<0)
3940 #define BCE_RPM_DEBUG4_DFIFO_CUR_CCODE			 (0x7L<<25)
3941 #define BCE_RPM_DEBUG4_MBWRITE_FSM			 (0x7L<<28)
3944 #define BCE_RPM_DEBUG5					0x00001998
3945 #define BCE_RPM_DEBUG5_RDROP_WPTR			 (0x1fL<<0)
3946 #define BCE_RPM_DEBUG5_RDROP_ACPI_RPTR			 (0x1fL<<5)
3947 #define BCE_RPM_DEBUG5_RDROP_MC_RPTR			 (0x1fL<<10)
3948 #define BCE_RPM_DEBUG5_RDROP_RC_RPTR			 (0x1fL<<15)
3962 #define BCE_RPM_DEBUG6					0x0000199c
3963 #define BCE_RPM_DEBUG6_ACPI_VEC			 (0xffffL<<0)
3964 #define BCE_RPM_DEBUG6_VEC				 (0xffffL<<16)
3966 #define BCE_RPM_DEBUG7					0x000019a0
3967 #define BCE_RPM_DEBUG7_RPM_DBG7_LAST_CRC		 (0xffffffffL<<0)
3969 #define BCE_RPM_DEBUG8					0x000019a4
3970 #define BCE_RPM_DEBUG8_PS_ACPI_FSM			 (0xfL<<0)
3971 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_IDLE		 (0L<<0)
3972 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR		 (1L<<0)
3973 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR		 (2L<<0)
3974 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR		 (3L<<0)
3975 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF	 (4L<<0)
3976 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA		 (5L<<0)
3977 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR		 (6L<<0)
3978 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR		 (7L<<0)
3979 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR		 (8L<<0)
3980 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR		 (9L<<0)
3981 #define BCE_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF		 (10L<<0)
3994 #define BCE_RPM_DEBUG8_THBUF_ADDR			 (0x7fL<<16)
3995 #define BCE_RPM_DEBUG8_BYTE_CTR			 (0xffL<<24)
3997 #define BCE_RPM_DEBUG9					0x000019a8
3998 #define BCE_RPM_DEBUG9_OUTFIFO_COUNT			 (0x7L<<0)
4000 #define BCE_RPM_DEBUG9_VLD_RD_ENTRY_CT			 (0x7L<<4)
4006 #define BCE_RPM_ACPI_DBG_BUF_W00			0x000019c0
4007 #define BCE_RPM_ACPI_DBG_BUF_W01			0x000019c4
4008 #define BCE_RPM_ACPI_DBG_BUF_W02			0x000019c8
4009 #define BCE_RPM_ACPI_DBG_BUF_W03			0x000019cc
4010 #define BCE_RPM_ACPI_DBG_BUF_W10			0x000019d0
4011 #define BCE_RPM_ACPI_DBG_BUF_W11			0x000019d4
4012 #define BCE_RPM_ACPI_DBG_BUF_W12			0x000019d8
4013 #define BCE_RPM_ACPI_DBG_BUF_W13			0x000019dc
4014 #define BCE_RPM_ACPI_DBG_BUF_W20			0x000019e0
4015 #define BCE_RPM_ACPI_DBG_BUF_W21			0x000019e4
4016 #define BCE_RPM_ACPI_DBG_BUF_W22			0x000019e8
4017 #define BCE_RPM_ACPI_DBG_BUF_W23			0x000019ec
4018 #define BCE_RPM_ACPI_DBG_BUF_W30			0x000019f0
4019 #define BCE_RPM_ACPI_DBG_BUF_W31			0x000019f4
4020 #define BCE_RPM_ACPI_DBG_BUF_W32			0x000019f8
4021 #define BCE_RPM_ACPI_DBG_BUF_W33			0x000019fc
4025  *  offset: 0x2000
4027 #define BCE_RLUP_FTQ_CMD					0x000023f8
4028 #define BCE_RLUP_FTQ_CTL					0x000023fc
4029 #define BCE_RLUP_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4030 #define BCE_RLUP_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4034  *  offset: 0x2400
4036 #define BCE_RV2PCSR_FTQ_CMD					0x000027f8
4037 #define BCE_RV2PCSR_FTQ_CTL					0x000027fc
4038 #define BCE_RV2PCSR_FTQ_CTL_MAX_DEPTH		(0x3ffL<<12)
4039 #define BCE_RV2PCSR_FTQ_CTL_CUR_DEPTH		(0x3ffL<<22)
4043  *  offset: 0x2c00
4045 #define BCE_RDMA_FTQ_CMD					0x00002ff8
4046 #define BCE_RDMA_FTQ_CTL					0x00002ffc
4047 #define BCE_RDMA_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4048 #define BCE_RDMA_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4052  *  offset: 0x4400
4055 #define BCE_TIMER_COMMAND					0x00004400
4056 #define BCE_TIMER_COMMAND_ENABLED			(1L<<0)
4058 #define BCE_TIMER_STATUS					0x00004404
4059 #define BCE_TIMER_STATUS_CMP_FTQ_WAIT 		(1L<<0)
4067 #define BCE_TIMER_25MHZ_FREE_RUN			0x00004448
4071  *  offset: 0x4c00
4074 #define BCE_TSCH_FTQ_CMD					0x00004ff8
4075 #define BCE_TSCH_FTQ_CTL					0x00004ffc
4076 #define BCE_TSCH_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4077 #define BCE_TSCH_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4081  *  offset: 0x200000
4083 #define BCE_RBUF_COMMAND				0x00200000
4084 #define BCE_RBUF_COMMAND_ENABLED			 (1L<<0)
4090 #define BCE_RBUF_STATUS1				0x00200004
4091 #define BCE_RBUF_STATUS1_FREE_COUNT			 (0x3ffL<<0)
4093 #define BCE_RBUF_STATUS2				0x00200008
4094 #define BCE_RBUF_STATUS2_FREE_TAIL			 (0x3ffL<<0)
4095 #define BCE_RBUF_STATUS2_FREE_HEAD			 (0x3ffL<<16)
4097 #define BCE_RBUF_CONFIG				0x0020000c
4098 #define BCE_RBUF_CONFIG_XOFF_TRIP			 (0x3ffL<<0)
4099 #define BCE_RBUF_CONFIG_XON_TRIP			 (0x3ffL<<16)
4101 #define BCE_RBUF_FW_BUF_ALLOC				0x00200010
4102 #define BCE_RBUF_FW_BUF_ALLOC_VALUE			 (0x1ffL<<7)
4104 #define BCE_RBUF_FW_BUF_FREE				0x00200014
4105 #define BCE_RBUF_FW_BUF_FREE_COUNT			 (0x7fL<<0)
4106 #define BCE_RBUF_FW_BUF_FREE_TAIL			 (0x1ffL<<7)
4107 #define BCE_RBUF_FW_BUF_FREE_HEAD			 (0x1ffL<<16)
4109 #define BCE_RBUF_FW_BUF_SEL				0x00200018
4110 #define BCE_RBUF_FW_BUF_SEL_COUNT			 (0x7fL<<0)
4111 #define BCE_RBUF_FW_BUF_SEL_TAIL			 (0x1ffL<<7)
4112 #define BCE_RBUF_FW_BUF_SEL_HEAD			 (0x1ffL<<16)
4114 #define BCE_RBUF_CONFIG2				0x0020001c
4115 #define BCE_RBUF_CONFIG2_MAC_DROP_TRIP			 (0x3ffL<<0)
4116 #define BCE_RBUF_CONFIG2_MAC_KEEP_TRIP			 (0x3ffL<<16)
4118 #define BCE_RBUF_CONFIG3				0x00200020
4119 #define BCE_RBUF_CONFIG3_CU_DROP_TRIP			 (0x3ffL<<0)
4120 #define BCE_RBUF_CONFIG3_CU_KEEP_TRIP			 (0x3ffL<<16)
4122 #define BCE_RBUF_PKT_DATA				0x00208000
4123 #define BCE_RBUF_CLIST_DATA				0x00210000
4124 #define BCE_RBUF_BUF_DATA				0x00220000
4128  *  offset: 0x2800
4130 #define BCE_RV2P_COMMAND				0x00002800
4131 #define BCE_RV2P_COMMAND_ENABLED			 (1L<<0)
4144 #define BCE_RV2P_STATUS				0x00002804
4145 #define BCE_RV2P_STATUS_ALWAYS_0			 (1L<<0)
4153 #define BCE_RV2P_CONFIG				0x00002808
4154 #define BCE_RV2P_CONFIG_STALL_PROC1			 (1L<<0)
4168 #define BCE_RV2P_CONFIG_PAGE_SIZE			 (0xfL<<24)
4169 #define BCE_RV2P_CONFIG_PAGE_SIZE_256			 (0L<<24)
4183 #define BCE_RV2P_GEN_BFR_ADDR_0			0x00002810
4184 #define BCE_RV2P_GEN_BFR_ADDR_0_VALUE			 (0xffffL<<16)
4186 #define BCE_RV2P_GEN_BFR_ADDR_1			0x00002814
4187 #define BCE_RV2P_GEN_BFR_ADDR_1_VALUE			 (0xffffL<<16)
4189 #define BCE_RV2P_GEN_BFR_ADDR_2			0x00002818
4190 #define BCE_RV2P_GEN_BFR_ADDR_2_VALUE			 (0xffffL<<16)
4192 #define BCE_RV2P_GEN_BFR_ADDR_3			0x0000281c
4193 #define BCE_RV2P_GEN_BFR_ADDR_3_VALUE			 (0xffffL<<16)
4195 #define BCE_RV2P_INSTR_HIGH				0x00002830
4196 #define BCE_RV2P_INSTR_HIGH_HIGH			 (0x1fL<<0)
4198 #define BCE_RV2P_INSTR_LOW				0x00002834
4199 #define BCE_RV2P_PROC1_ADDR_CMD			0x00002838
4200 #define BCE_RV2P_PROC1_ADDR_CMD_ADD			 (0x3ffL<<0)
4203 #define BCE_RV2P_PROC2_ADDR_CMD			0x0000283c
4204 #define BCE_RV2P_PROC2_ADDR_CMD_ADD			 (0x3ffL<<0)
4207 #define BCE_RV2P_PROC1_GRC_DEBUG			0x00002840
4208 #define BCE_RV2P_PROC2_GRC_DEBUG			0x00002844
4209 #define BCE_RV2P_GRC_PROC_DEBUG			0x00002848
4210 #define BCE_RV2P_DEBUG_VECT_PEEK			0x0000284c
4211 #define BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE		 (0x7ffL<<0)
4213 #define BCE_RV2P_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)
4214 #define BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE		 (0x7ffL<<16)
4216 #define BCE_RV2P_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)
4218 #define BCE_RV2P_PFTQ_DATA				0x00002b40
4219 #define BCE_RV2P_PFTQ_CMD				0x00002b78
4220 #define BCE_RV2P_PFTQ_CMD_OFFSET			 (0x3ffL<<0)
4222 #define BCE_RV2P_PFTQ_CMD_WR_TOP_0			 (0L<<10)
4232 #define BCE_RV2P_PFTQ_CTL				0x00002b7c
4233 #define BCE_RV2P_PFTQ_CTL_INTERVENE			 (1L<<0)
4236 #define BCE_RV2P_PFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4237 #define BCE_RV2P_PFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4239 #define BCE_RV2P_TFTQ_DATA				0x00002b80
4240 #define BCE_RV2P_TFTQ_CMD				0x00002bb8
4241 #define BCE_RV2P_TFTQ_CMD_OFFSET			 (0x3ffL<<0)
4243 #define BCE_RV2P_TFTQ_CMD_WR_TOP_0			 (0L<<10)
4253 #define BCE_RV2P_TFTQ_CTL				0x00002bbc
4254 #define BCE_RV2P_TFTQ_CTL_INTERVENE			 (1L<<0)
4257 #define BCE_RV2P_TFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4258 #define BCE_RV2P_TFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4260 #define BCE_RV2P_MFTQ_DATA				0x00002bc0
4261 #define BCE_RV2P_MFTQ_CMD				0x00002bf8
4262 #define BCE_RV2P_MFTQ_CMD_OFFSET			 (0x3ffL<<0)
4264 #define BCE_RV2P_MFTQ_CMD_WR_TOP_0			 (0L<<10)
4274 #define BCE_RV2P_MFTQ_CTL				0x00002bfc
4275 #define BCE_RV2P_MFTQ_CTL_INTERVENE			 (1L<<0)
4278 #define BCE_RV2P_MFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4279 #define BCE_RV2P_MFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4283  *  offset: 0x3c00
4285 #define BCE_MQ_COMMAND								0x00003c00
4286 #define BCE_MQ_COMMAND_ENABLED						(1L<<0)
4296 #define BCE_MQ_STATUS								0x00003c04
4302 #define BCE_MQ_CONFIG								0x00003c08
4303 #define BCE_MQ_CONFIG_TX_HIGH_PRI					(1L<<0)
4307 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE				(0x7L<<4)
4308 #define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256			(0L<<4)
4313 #define BCE_MQ_CONFIG_MAX_DEPTH						(0x7fL<<8)
4314 #define BCE_MQ_CONFIG_CUR_DEPTH						(0x7fL<<20)
4316 #define BCE_MQ_ENQUEUE1								0x00003c0c
4317 #define BCE_MQ_ENQUEUE1_OFFSET						(0x3fL<<2)
4318 #define BCE_MQ_ENQUEUE1_CID							(0x3fffL<<8)
4319 #define BCE_MQ_ENQUEUE1_BYTE_MASK					(0xfL<<24)
4322 #define BCE_MQ_ENQUEUE2								0x00003c10
4323 #define BCE_MQ_BAD_WR_ADDR							0x00003c14
4324 #define BCE_MQ_BAD_RD_ADDR							0x00003c18
4325 #define BCE_MQ_KNL_BYP_WIND_START					0x00003c1c
4326 #define BCE_MQ_KNL_BYP_WIND_START_VALUE				(0xfffffL<<12)
4328 #define BCE_MQ_KNL_WIND_END							0x00003c20
4329 #define BCE_MQ_KNL_WIND_END_VALUE					(0xffffffL<<8)
4331 #define BCE_MQ_KNL_WRITE_MASK1						0x00003c24
4332 #define BCE_MQ_KNL_TX_MASK1							0x00003c28
4333 #define BCE_MQ_KNL_CMD_MASK1						0x00003c2c
4334 #define BCE_MQ_KNL_COND_ENQUEUE_MASK1				0x00003c30
4335 #define BCE_MQ_KNL_RX_V2P_MASK1						0x00003c34
4336 #define BCE_MQ_KNL_WRITE_MASK2						0x00003c38
4337 #define BCE_MQ_KNL_TX_MASK2							0x00003c3c
4338 #define BCE_MQ_KNL_CMD_MASK2						0x00003c40
4339 #define BCE_MQ_KNL_COND_ENQUEUE_MASK2				0x00003c44
4340 #define BCE_MQ_KNL_RX_V2P_MASK2						0x00003c48
4341 #define BCE_MQ_KNL_BYP_WRITE_MASK1					0x00003c4c
4342 #define BCE_MQ_KNL_BYP_TX_MASK1						0x00003c50
4343 #define BCE_MQ_KNL_BYP_CMD_MASK1					0x00003c54
4344 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1			0x00003c58
4345 #define BCE_MQ_KNL_BYP_RX_V2P_MASK1					0x00003c5c
4346 #define BCE_MQ_KNL_BYP_WRITE_MASK2					0x00003c60
4347 #define BCE_MQ_KNL_BYP_TX_MASK2						0x00003c64
4348 #define BCE_MQ_KNL_BYP_CMD_MASK2					0x00003c68
4349 #define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2			0x00003c6c
4350 #define BCE_MQ_KNL_BYP_RX_V2P_MASK2					0x00003c70
4351 #define BCE_MQ_MEM_WR_ADDR							0x00003c74
4352 #define BCE_MQ_MEM_WR_ADDR_VALUE					(0x3fL<<0)
4354 #define BCE_MQ_MEM_WR_DATA0							0x00003c78
4355 #define BCE_MQ_MEM_WR_DATA0_VALUE					(0xffffffffL<<0)
4357 #define BCE_MQ_MEM_WR_DATA1							0x00003c7c
4358 #define BCE_MQ_MEM_WR_DATA1_VALUE					(0xffffffffL<<0)
4360 #define BCE_MQ_MEM_WR_DATA2							0x00003c80
4361 #define BCE_MQ_MEM_WR_DATA2_VALUE					(0x3fffffffL<<0)
4362 #define BCE_MQ_MEM_WR_DATA2_VALUE_XI				(0x7fffffffL<<0)
4364 #define BCE_MQ_MEM_RD_ADDR							0x00003c84
4365 #define BCE_MQ_MEM_RD_ADDR_VALUE					(0x3fL<<0)
4367 #define BCE_MQ_MEM_RD_DATA0							0x00003c88
4368 #define BCE_MQ_MEM_RD_DATA0_VALUE					(0xffffffffL<<0)
4370 #define BCE_MQ_MEM_RD_DATA1							0x00003c8c
4371 #define BCE_MQ_MEM_RD_DATA1_VALUE					(0xffffffffL<<0)
4373 #define BCE_MQ_MEM_RD_DATA2							0x00003c90
4374 #define BCE_MQ_MEM_RD_DATA2_VALUE					(0x3fffffffL<<0)
4375 #define BCE_MQ_MEM_RD_DATA2_VALUE_XI				(0x7fffffffL<<0)
4377 #define BCE_MQ_CONFIG2								0x00003d00
4378 #define BCE_MQ_CONFIG2_CONT_SZ						(0x7L<<4)
4379 #define BCE_MQ_CONFIG2_FIRST_L4L5					(0x1fL<<8)
4381 #define BCE_MQ_MAP_L2_3								0x00003d2c
4382 #define BCE_MQ_MAP_L2_3_MQ_OFFSET					(0xffL<<0)
4383 #define BCE_MQ_MAP_L2_3_SZ							(0x3L<<8)
4384 #define BCE_MQ_MAP_L2_3_CTX_OFFSET					(0x2ffL<<10)
4385 #define BCE_MQ_MAP_L2_3_BIN_OFFSET					(0x7L<<23)
4386 #define BCE_MQ_MAP_L2_3_ARM							(0x3L<<26)
4387 #define BCE_MQ_MAP_L2_3_ENA							(0x1L<<31)
4388 #define BCE_MQ_MAP_L2_3_DEFAULT						0x82004646
4390 #define BCE_MQ_MAP_L2_5								0x00003d34
4391 #define BCE_MQ_MAP_L2_5_MQ_OFFSET					(0xffL<<0)
4392 #define BCE_MQ_MAP_L2_5_SZ							(0x3L<<8)
4393 #define BCE_MQ_MAP_L2_5_CTX_OFFSET					(0x2ffL<<10)
4394 #define BCE_MQ_MAP_L2_5_BIN_OFFSET					(0x7L<<23)
4395 #define BCE_MQ_MAP_L2_5_ARM							(0x3L<<26)
4396 #define BCE_MQ_MAP_L2_5_ENA							(0x1L<<31)
4397 #define BCE_MQ_MAP_L2_5_DEFAULT						0x83000b08
4401  *  offset: 0x4000
4403 #define BCE_CSCH_COMMAND				0x00004000
4404 #define BCE_CSCH_CH_FTQ_CMD				0x000043f8
4405 #define BCE_CSCH_CH_FTQ_CTL				0x000043fc
4406 #define BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4407 #define BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4411  *  offset: 0x5000
4413 #define BCE_TBDR_COMMAND				0x00005000
4414 #define BCE_TBDR_COMMAND_ENABLE				(1L<<0)
4418 #define BCE_TBDR_STATUS					0x00005004
4419 #define BCE_TBDR_STATUS_DMA_WAIT			(1L<<0)
4427 #define BCE_TBDR_CONFIG					0x00005008
4428 #define BCE_TBDR_CONFIG_MAX_BDS				(0xffL<<0)
4432 #define BCE_TBDR_CONFIG_PAGE_SIZE			(0xfL<<24)
4433 #define BCE_TBDR_CONFIG_PAGE_SIZE_256			(0L<<24)
4447 #define BCE_TBDR_DEBUG_VECT_PEEK			0x0000500c
4448 #define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE		(0x7ffL<<0)
4450 #define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL			(0xfL<<12)
4451 #define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE		(0x7ffL<<16)
4453 #define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL			(0xfL<<28)
4455 #define BCE_TBDR_FTQ_DATA				0x000053c0
4456 #define BCE_TBDR_FTQ_CMD				0x000053f8
4457 #define BCE_TBDR_FTQ_CMD_OFFSET				(0x3ffL<<0)
4459 #define BCE_TBDR_FTQ_CMD_WR_TOP_0			(0L<<10)
4469 #define BCE_TBDR_FTQ_CTL				0x000053fc
4470 #define BCE_TBDR_FTQ_CTL_INTERVENE			(1L<<0)
4473 #define BCE_TBDR_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
4474 #define BCE_TBDR_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
4478  *  offset: 0x5c00
4480 #define BCE_TDMA_COMMAND				0x00005c00
4481 #define BCE_TDMA_COMMAND_ENABLED			 (1L<<0)
4485 #define BCE_TDMA_STATUS					0x00005c04
4486 #define BCE_TDMA_STATUS_DMA_WAIT			 (1L<<0)
4493 #define BCE_TDMA_CONFIG					0x00005c08
4494 #define BCE_TDMA_CONFIG_ONE_DMA				 (1L<<0)
4496 #define BCE_TDMA_CONFIG_LIMIT_SZ			 (0xfL<<4)
4497 #define BCE_TDMA_CONFIG_LIMIT_SZ_64			 (0L<<4)
4498 #define BCE_TDMA_CONFIG_LIMIT_SZ_128			 (0x4L<<4)
4499 #define BCE_TDMA_CONFIG_LIMIT_SZ_256			 (0x6L<<4)
4500 #define BCE_TDMA_CONFIG_LIMIT_SZ_512			 (0x8L<<4)
4501 #define BCE_TDMA_CONFIG_LINE_SZ				 (0xfL<<8)
4502 #define BCE_TDMA_CONFIG_LINE_SZ_64			 (0L<<8)
4508 #define BCE_TDMA_CONFIG_FIFO_CMP			 (0xfL<<20)
4510 #define BCE_TDMA_PAYLOAD_PROD				0x00005c0c
4511 #define BCE_TDMA_PAYLOAD_PROD_VALUE			 (0x1fffL<<3)
4513 #define BCE_TDMA_DBG_WATCHDOG				0x00005c10
4514 #define BCE_TDMA_DBG_TRIGGER				0x00005c14
4515 #define BCE_TDMA_DMAD_FSM				0x00005c80
4516 #define BCE_TDMA_DMAD_FSM_BD_INVLD			 (1L<<0)
4517 #define BCE_TDMA_DMAD_FSM_PUSH				 (0xfL<<4)
4518 #define BCE_TDMA_DMAD_FSM_ARB_TBDC			 (0x3L<<8)
4521 #define BCE_TDMA_DMAD_FSM_DMAD				 (0x7L<<20)
4522 #define BCE_TDMA_DMAD_FSM_BD				 (0xfL<<24)
4524 #define BCE_TDMA_DMAD_STATUS				0x00005c84
4525 #define BCE_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY		 (0x3L<<0)
4526 #define BCE_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY		 (0x3L<<4)
4527 #define BCE_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY		 (0x3L<<8)
4528 #define BCE_TDMA_DMAD_STATUS_IFTQ_ENUM			 (0xfL<<12)
4530 #define BCE_TDMA_DR_INTF_FSM				0x00005c88
4531 #define BCE_TDMA_DR_INTF_FSM_L2_COMP			 (0x3L<<0)
4532 #define BCE_TDMA_DR_INTF_FSM_TPATQ			 (0x7L<<4)
4533 #define BCE_TDMA_DR_INTF_FSM_TPBUF			 (0x3L<<8)
4534 #define BCE_TDMA_DR_INTF_FSM_DR_BUF			 (0x7L<<12)
4535 #define BCE_TDMA_DR_INTF_FSM_DMAD			 (0x7L<<16)
4537 #define BCE_TDMA_DR_INTF_STATUS				0x00005c8c
4538 #define BCE_TDMA_DR_INTF_STATUS_HOLE_PHASE		 (0x7L<<0)
4539 #define BCE_TDMA_DR_INTF_STATUS_DATA_AVAIL		 (0x3L<<4)
4540 #define BCE_TDMA_DR_INTF_STATUS_SHIFT_ADDR		 (0x7L<<8)
4541 #define BCE_TDMA_DR_INTF_STATUS_NXT_PNTR		 (0xfL<<12)
4542 #define BCE_TDMA_DR_INTF_STATUS_BYTE_COUNT		 (0x7L<<16)
4544 #define BCE_TDMA_FTQ_DATA				0x00005fc0
4545 #define BCE_TDMA_FTQ_CMD				0x00005ff8
4546 #define BCE_TDMA_FTQ_CMD_OFFSET				 (0x3ffL<<0)
4548 #define BCE_TDMA_FTQ_CMD_WR_TOP_0			 (0L<<10)
4558 #define BCE_TDMA_FTQ_CTL				0x00005ffc
4559 #define BCE_TDMA_FTQ_CTL_INTERVENE			 (1L<<0)
4562 #define BCE_TDMA_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
4563 #define BCE_TDMA_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
4567  *  offset: 0x6400
4569 #define BCE_NVM_COMMAND					0x00006400
4570 #define BCE_NVM_COMMAND_RST				 (1L<<0)
4582 #define BCE_NVM_STATUS					0x00006404
4583 #define BCE_NVM_STATUS_PI_FSM_STATE			 (0xfL<<0)
4584 #define BCE_NVM_STATUS_EE_FSM_STATE			 (0xfL<<4)
4585 #define BCE_NVM_STATUS_EQ_FSM_STATE			 (0xfL<<8)
4587 #define BCE_NVM_WRITE					0x00006408
4588 #define BCE_NVM_WRITE_NVM_WRITE_VALUE			 (0xffffffffL<<0)
4589 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG		 (0L<<0)
4590 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK		 (1L<<0)
4591 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA		 (2L<<0)
4592 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK		 (4L<<0)
4593 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B		 (8L<<0)
4594 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO		 (16L<<0)
4595 #define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI		 (32L<<0)
4597 #define BCE_NVM_ADDR					0x0000640c
4598 #define BCE_NVM_ADDR_NVM_ADDR_VALUE			 (0xffffffL<<0)
4599 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG		 (0L<<0)
4600 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK		 (1L<<0)
4601 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA		 (2L<<0)
4602 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK		 (4L<<0)
4603 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B		 (8L<<0)
4604 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO			 (16L<<0)
4605 #define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI			 (32L<<0)
4607 #define BCE_NVM_READ					0x00006410
4608 #define BCE_NVM_READ_NVM_READ_VALUE			 (0xffffffffL<<0)
4609 #define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG		 (0L<<0)
4610 #define BCE_NVM_READ_NVM_READ_VALUE_EECLK		 (1L<<0)
4611 #define BCE_NVM_READ_NVM_READ_VALUE_EEDATA		 (2L<<0)
4612 #define BCE_NVM_READ_NVM_READ_VALUE_SCLK		 (4L<<0)
4613 #define BCE_NVM_READ_NVM_READ_VALUE_CS_B		 (8L<<0)
4614 #define BCE_NVM_READ_NVM_READ_VALUE_SO			 (16L<<0)
4615 #define BCE_NVM_READ_NVM_READ_VALUE_SI			 (32L<<0)
4617 #define BCE_NVM_CFG1					0x00006414
4618 #define BCE_NVM_CFG1_FLASH_MODE				 (1L<<0)
4622 #define BCE_NVM_CFG1_STATUS_BIT				 (0x7L<<4)
4623 #define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY		 (0L<<4)
4625 #define BCE_NVM_CFG1_SPI_CLK_DIV			 (0xfL<<7)
4626 #define BCE_NVM_CFG1_SEE_CLK_DIV			 (0x7ffL<<11)
4631 #define BCE_NVM_CFG2					0x00006418
4632 #define BCE_NVM_CFG2_ERASE_CMD				 (0xffL<<0)
4633 #define BCE_NVM_CFG2_DUMMY				 (0xffL<<8)
4634 #define BCE_NVM_CFG2_STATUS_CMD				 (0xffL<<16)
4636 #define BCE_NVM_CFG3					0x0000641c
4637 #define BCE_NVM_CFG3_BUFFER_RD_CMD			 (0xffL<<0)
4638 #define BCE_NVM_CFG3_WRITE_CMD				 (0xffL<<8)
4639 #define BCE_NVM_CFG3_BUFFER_WRITE_CMD			 (0xffL<<16)
4640 #define BCE_NVM_CFG3_READ_CMD				 (0xffL<<24)
4642 #define BCE_NVM_SW_ARB					0x00006420
4643 #define BCE_NVM_SW_ARB_ARB_REQ_SET0			 (1L<<0)
4660 #define BCE_NVM_ACCESS_ENABLE				0x00006424
4661 #define BCE_NVM_ACCESS_ENABLE_EN			 (1L<<0)
4664 #define BCE_NVM_WRITE1					0x00006428
4665 #define BCE_NVM_WRITE1_WREN_CMD				 (0xffL<<0)
4666 #define BCE_NVM_WRITE1_WRDI_CMD				 (0xffL<<8)
4667 #define BCE_NVM_WRITE1_SR_DATA				 (0xffL<<16)
4671  *  offset: 0x6800
4673 #define BCE_HC_COMMAND					0x00006800
4674 #define BCE_HC_COMMAND_ENABLE				 (1L<<0)
4679 #define BCE_HC_COMMAND_FORCE_INT			 (0x3L<<19)
4680 #define BCE_HC_COMMAND_FORCE_INT_NULL			 (0L<<19)
4688 #define BCE_HC_STATUS					0x00006804
4689 #define BCE_HC_STATUS_MASTER_ABORT			 (1L<<0)
4700 #define BCE_HC_CONFIG					0x00006808
4701 #define BCE_HC_CONFIG_COLLECT_STATS			 (1L<<0)
4708 #define BCE_HC_CONFIG_STAT_MEM_ADDR			 (0xffL<<8)
4713 #define BCE_HC_CONFIG_PER_COLLECT_LIMIT			 (0xfL<<20)
4714 #define BCE_HC_CONFIG_SB_ADDR_INC			 (0x7L<<24)
4715 #define BCE_HC_CONFIG_SB_ADDR_INC_64B			 (0L<<24)
4727 #define BCE_HC_ATTN_BITS_ENABLE				0x0000680c
4728 #define BCE_HC_STATUS_ADDR_L				0x00006810
4729 #define BCE_HC_STATUS_ADDR_H				0x00006814
4730 #define BCE_HC_STATISTICS_ADDR_L			0x00006818
4731 #define BCE_HC_STATISTICS_ADDR_H			0x0000681c
4732 #define BCE_HC_TX_QUICK_CONS_TRIP			0x00006820
4733 #define BCE_HC_TX_QUICK_CONS_TRIP_VALUE			 (0xffL<<0)
4734 #define BCE_HC_TX_QUICK_CONS_TRIP_INT			 (0xffL<<16)
4736 #define BCE_HC_COMP_PROD_TRIP				0x00006824
4737 #define BCE_HC_COMP_PROD_TRIP_VALUE			 (0xffL<<0)
4738 #define BCE_HC_COMP_PROD_TRIP_INT			 (0xffL<<16)
4740 #define BCE_HC_RX_QUICK_CONS_TRIP			0x00006828
4741 #define BCE_HC_RX_QUICK_CONS_TRIP_VALUE			 (0xffL<<0)
4742 #define BCE_HC_RX_QUICK_CONS_TRIP_INT			 (0xffL<<16)
4744 #define BCE_HC_RX_TICKS					0x0000682c
4745 #define BCE_HC_RX_TICKS_VALUE				 (0x3ffL<<0)
4746 #define BCE_HC_RX_TICKS_INT				 (0x3ffL<<16)
4748 #define BCE_HC_TX_TICKS					0x00006830
4749 #define BCE_HC_TX_TICKS_VALUE				 (0x3ffL<<0)
4750 #define BCE_HC_TX_TICKS_INT				 (0x3ffL<<16)
4752 #define BCE_HC_COM_TICKS				0x00006834
4753 #define BCE_HC_COM_TICKS_VALUE				 (0x3ffL<<0)
4754 #define BCE_HC_COM_TICKS_INT				 (0x3ffL<<16)
4756 #define BCE_HC_CMD_TICKS				0x00006838
4757 #define BCE_HC_CMD_TICKS_VALUE				 (0x3ffL<<0)
4758 #define BCE_HC_CMD_TICKS_INT				 (0x3ffL<<16)
4760 #define BCE_HC_PERIODIC_TICKS				0x0000683c
4761 #define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS		 (0xffffL<<0)
4762 #define BCE_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
4764 #define BCE_HC_STAT_COLLECT_TICKS			0x00006840
4765 #define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS	 (0xffL<<4)
4767 #define BCE_HC_STATS_TICKS				0x00006844
4768 #define BCE_HC_STATS_TICKS_HC_STAT_TICKS		 (0xffffL<<8)
4770 #define BCE_HC_STATS_INTERRUPT_STATUS			0x00006848
4771 #define BCE_HC_STATS_INTERRUPT_STATUS_SB_STATUS		 (0x1ffL<<0)
4772 #define BCE_HC_STATS_INTERRUPT_STATUS_INT_STATUS	 (0x1ffL<<16)
4774 #define BCE_HC_STAT_MEM_DATA				0x0000684c
4775 #define BCE_HC_STAT_GEN_SEL_0				0x00006850
4776 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0			 (0x7fL<<0)
4777 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0	 (0L<<0)
4778 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1	 (1L<<0)
4779 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2	 (2L<<0)
4780 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3	 (3L<<0)
4781 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4	 (4L<<0)
4782 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5	 (5L<<0)
4783 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6	 (6L<<0)
4784 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7	 (7L<<0)
4785 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8	 (8L<<0)
4786 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9	 (9L<<0)
4787 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10	 (10L<<0)
4788 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11	 (11L<<0)
4789 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0	 (12L<<0)
4790 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1	 (13L<<0)
4791 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2	 (14L<<0)
4792 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3	 (15L<<0)
4793 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4	 (16L<<0)
4794 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5	 (17L<<0)
4795 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6	 (18L<<0)
4796 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7	 (19L<<0)
4797 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0	 (20L<<0)
4798 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1	 (21L<<0)
4799 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2	 (22L<<0)
4800 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3	 (23L<<0)
4801 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4	 (24L<<0)
4802 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5	 (25L<<0)
4803 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6	 (26L<<0)
4804 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7	 (27L<<0)
4805 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8	 (28L<<0)
4806 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9	 (29L<<0)
4807 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10	 (30L<<0)
4808 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11	 (31L<<0)
4809 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0	 (32L<<0)
4810 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1	 (33L<<0)
4811 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2	 (34L<<0)
4812 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3	 (35L<<0)
4813 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0	 (36L<<0)
4814 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1	 (37L<<0)
4815 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2	 (38L<<0)
4816 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3	 (39L<<0)
4817 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4	 (40L<<0)
4818 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5	 (41L<<0)
4819 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6	 (42L<<0)
4820 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7	 (43L<<0)
4821 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0	 (44L<<0)
4822 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1	 (45L<<0)
4823 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2	 (46L<<0)
4824 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3	 (47L<<0)
4825 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4	 (48L<<0)
4826 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5	 (49L<<0)
4827 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6	 (50L<<0)
4828 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7	 (51L<<0)
4829 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT	 (52L<<0)
4830 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT	 (53L<<0)
4831 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS	 (54L<<0)
4832 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN	 (55L<<0)
4833 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR	 (56L<<0)
4834 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK	 (59L<<0)
4835 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK	 (60L<<0)
4836 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK	 (61L<<0)
4837 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT	 (62L<<0)
4838 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT	 (63L<<0)
4839 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT	 (64L<<0)
4840 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT	 (65L<<0)
4841 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT	 (66L<<0)
4842 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT	 (67L<<0)
4843 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT	 (68L<<0)
4844 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
4845 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
4846 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
4847 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT	 (72L<<0)
4848 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT	 (73L<<0)
4849 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT	 (74L<<0)
4850 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT	 (75L<<0)
4851 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT	 (76L<<0)
4852 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT	 (77L<<0)
4853 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT	 (78L<<0)
4854 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT	 (79L<<0)
4855 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT	 (80L<<0)
4856 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT	 (81L<<0)
4857 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT	 (82L<<0)
4858 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT	 (83L<<0)
4859 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT	 (84L<<0)
4860 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT	 (85L<<0)
4861 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT	 (86L<<0)
4862 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT	 (87L<<0)
4863 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT	 (88L<<0)
4864 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT	 (89L<<0)
4865 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT	 (90L<<0)
4866 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT	 (91L<<0)
4867 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT	 (92L<<0)
4868 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT	 (93L<<0)
4869 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT	 (94L<<0)
4870 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64	 (95L<<0)
4871 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64	 (96L<<0)
4872 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS	 (97L<<0)
4873 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS	 (98L<<0)
4874 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT	 (99L<<0)
4875 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT	 (100L<<0)
4876 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT	 (101L<<0)
4877 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT	 (102L<<0)
4878 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT	 (103L<<0)
4879 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT	 (104L<<0)
4880 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT	 (105L<<0)
4881 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT	 (106L<<0)
4882 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT	 (107L<<0)
4883 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT	 (108L<<0)
4884 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT	 (109L<<0)
4885 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT	 (110L<<0)
4886 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT	 (111L<<0)
4887 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT	 (112L<<0)
4888 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT	 (113L<<0)
4889 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT	 (114L<<0)
4890 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0	 (115L<<0)
4891 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1	 (116L<<0)
4892 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2	 (117L<<0)
4893 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3	 (118L<<0)
4894 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4	 (119L<<0)
4895 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5	 (120L<<0)
4896 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS	 (121L<<0)
4897 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS	 (122L<<0)
4898 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT	 (127L<<0)
4899 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1		 (0x7fL<<8)
4900 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2		 (0x7fL<<16)
4901 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3		 (0x7fL<<24)
4902 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI		 (0xffL<<0)
4903 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI	 (52L<<0)
4904 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI	 (57L<<0)
4905 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI	 (58L<<0)
4906 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI	 (85L<<0)
4907 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI	 (86L<<0)
4908 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI	 (87L<<0)
4909 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI	 (88L<<0)
4910 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI	 (89L<<0)
4911 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI	 (90L<<0)
4912 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI	 (91L<<0)
4913 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI	 (92L<<0)
4914 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI	 (93L<<0)
4915 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI	 (94L<<0)
4916 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI	 (123L<<0)
4917 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI	 (124L<<0)
4918 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI	 (125L<<0)
4919 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI	 (126L<<0)
4920 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI	 (128L<<0)
4921 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI	 (129L<<0)
4922 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI	 (130L<<0)
4923 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI	 (131L<<0)
4924 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI	 (132L<<0)
4925 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI	 (133L<<0)
4926 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI	 (134L<<0)
4927 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI	 (135L<<0)
4928 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI	 (136L<<0)
4929 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI	 (137L<<0)
4930 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI	 (138L<<0)
4931 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI	 (139L<<0)
4932 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI	 (140L<<0)
4933 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI	 (141L<<0)
4934 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI	 (142L<<0)
4935 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI	 (143L<<0)
4936 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI	 (144L<<0)
4937 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI	 (145L<<0)
4938 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI	 (146L<<0)
4939 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI	 (147L<<0)
4940 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI	 (148L<<0)
4941 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI	 (149L<<0)
4942 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI	 (150L<<0)
4943 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI	 (151L<<0)
4944 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI	 (152L<<0)
4945 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI	 (153L<<0)
4946 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI	 (154L<<0)
4947 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI	 (155L<<0)
4948 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI	 (156L<<0)
4949 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI	 (157L<<0)
4950 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI	 (158L<<0)
4951 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI	 (159L<<0)
4952 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI	 (160L<<0)
4953 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI	 (161L<<0)
4954 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI	 (162L<<0)
4955 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI	 (163L<<0)
4956 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI	 (164L<<0)
4957 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI	 (165L<<0)
4958 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI	 (166L<<0)
4959 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI	 (167L<<0)
4960 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI	 (168L<<0)
4961 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI	 (169L<<0)
4962 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI	 (170L<<0)
4963 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI	 (171L<<0)
4964 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI	 (172L<<0)
4965 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI	 (173L<<0)
4966 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI	 (174L<<0)
4967 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI	 (175L<<0)
4968 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI	 (176L<<0)
4969 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI	 (177L<<0)
4970 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI	 (178L<<0)
4971 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI		 (0xffL<<8)
4972 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI		 (0xffL<<16)
4973 #define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI		 (0xffL<<24)
4975 #define BCE_HC_STAT_GEN_SEL_1				0x00006854
4976 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4		 (0x7fL<<0)
4977 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5		 (0x7fL<<8)
4978 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6		 (0x7fL<<16)
4979 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7		 (0x7fL<<24)
4980 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI		 (0xffL<<0)
4981 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI		 (0xffL<<8)
4982 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI		 (0xffL<<16)
4983 #define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI		 (0xffL<<24)
4985 #define BCE_HC_STAT_GEN_SEL_2				0x00006858
4986 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8		 (0x7fL<<0)
4987 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9		 (0x7fL<<8)
4988 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10		 (0x7fL<<16)
4989 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11		 (0x7fL<<24)
4990 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI		 (0xffL<<0)
4991 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI		 (0xffL<<8)
4992 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI		 (0xffL<<16)
4993 #define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI		 (0xffL<<24)
4995 #define BCE_HC_STAT_GEN_SEL_3				0x0000685c
4996 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12		 (0x7fL<<0)
4997 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13		 (0x7fL<<8)
4998 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14		 (0x7fL<<16)
4999 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15		 (0x7fL<<24)
5000 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI		 (0xffL<<0)
5001 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI		 (0xffL<<8)
5002 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI		 (0xffL<<16)
5003 #define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI		 (0xffL<<24)
5005 #define BCE_HC_STAT_GEN_STAT0				0x00006888
5006 #define BCE_HC_STAT_GEN_STAT1				0x0000688c
5007 #define BCE_HC_STAT_GEN_STAT2				0x00006890
5008 #define BCE_HC_STAT_GEN_STAT3				0x00006894
5009 #define BCE_HC_STAT_GEN_STAT4				0x00006898
5010 #define BCE_HC_STAT_GEN_STAT5				0x0000689c
5011 #define BCE_HC_STAT_GEN_STAT6				0x000068a0
5012 #define BCE_HC_STAT_GEN_STAT7				0x000068a4
5013 #define BCE_HC_STAT_GEN_STAT8				0x000068a8
5014 #define BCE_HC_STAT_GEN_STAT9				0x000068ac
5015 #define BCE_HC_STAT_GEN_STAT10				0x000068b0
5016 #define BCE_HC_STAT_GEN_STAT11				0x000068b4
5017 #define BCE_HC_STAT_GEN_STAT12				0x000068b8
5018 #define BCE_HC_STAT_GEN_STAT13				0x000068bc
5019 #define BCE_HC_STAT_GEN_STAT14				0x000068c0
5020 #define BCE_HC_STAT_GEN_STAT15				0x000068c4
5021 #define BCE_HC_STAT_GEN_STAT_AC0			0x000068c8
5022 #define BCE_HC_STAT_GEN_STAT_AC1			0x000068cc
5023 #define BCE_HC_STAT_GEN_STAT_AC2			0x000068d0
5024 #define BCE_HC_STAT_GEN_STAT_AC3			0x000068d4
5025 #define BCE_HC_STAT_GEN_STAT_AC4			0x000068d8
5026 #define BCE_HC_STAT_GEN_STAT_AC5			0x000068dc
5027 #define BCE_HC_STAT_GEN_STAT_AC6			0x000068e0
5028 #define BCE_HC_STAT_GEN_STAT_AC7			0x000068e4
5029 #define BCE_HC_STAT_GEN_STAT_AC8			0x000068e8
5030 #define BCE_HC_STAT_GEN_STAT_AC9			0x000068ec
5031 #define BCE_HC_STAT_GEN_STAT_AC10			0x000068f0
5032 #define BCE_HC_STAT_GEN_STAT_AC11			0x000068f4
5033 #define BCE_HC_STAT_GEN_STAT_AC12			0x000068f8
5034 #define BCE_HC_STAT_GEN_STAT_AC13			0x000068fc
5035 #define BCE_HC_STAT_GEN_STAT_AC14			0x00006900
5036 #define BCE_HC_STAT_GEN_STAT_AC15			0x00006904
5037 #define BCE_HC_STAT_GEN_STAT_AC			0x000068c8
5038 #define BCE_HC_VIS					0x00006908
5039 #define BCE_HC_VIS_STAT_BUILD_STATE			 (0xfL<<0)
5040 #define BCE_HC_VIS_STAT_BUILD_STATE_IDLE		 (0L<<0)
5041 #define BCE_HC_VIS_STAT_BUILD_STATE_START		 (1L<<0)
5042 #define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST		 (2L<<0)
5043 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64		 (3L<<0)
5044 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32		 (4L<<0)
5045 #define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE	 (5L<<0)
5046 #define BCE_HC_VIS_STAT_BUILD_STATE_DMA		 (6L<<0)
5047 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL	 (7L<<0)
5048 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_LOW		 (8L<<0)
5049 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_HIGH		 (9L<<0)
5050 #define BCE_HC_VIS_STAT_BUILD_STATE_MSI_DATA		 (10L<<0)
5051 #define BCE_HC_VIS_DMA_STAT_STATE			 (0xfL<<8)
5052 #define BCE_HC_VIS_DMA_STAT_STATE_IDLE			 (0L<<8)
5063 #define BCE_HC_VIS_DMA_MSI_STATE			 (0x7L<<12)
5064 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE		 (0x3L<<15)
5065 #define BCE_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE		 (0L<<15)
5069 #define BCE_HC_VIS_1					0x0000690c
5071 #define BCE_HC_VIS_1_HW_INTACK_STATE_IDLE		 (0L<<4)
5074 #define BCE_HC_VIS_1_SW_INTACK_STATE_IDLE		 (0L<<5)
5077 #define BCE_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE	 (0L<<6)
5080 #define BCE_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE		 (0L<<7)
5082 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE			 (0xfL<<17)
5083 #define BCE_HC_VIS_1_RAM_RD_ARB_STATE_IDLE		 (0L<<17)
5091 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE			 (0x3L<<21)
5092 #define BCE_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL		 (0L<<21)
5095 #define BCE_HC_VIS_1_INT_GEN_STATE_DLE			 (0L<<23)
5097 #define BCE_HC_VIS_1_STAT_CHAN_ID			 (0x7L<<24)
5100 #define BCE_HC_DEBUG_VECT_PEEK				0x00006910
5101 #define BCE_HC_DEBUG_VECT_PEEK_1_VALUE			 (0x7ffL<<0)
5103 #define BCE_HC_DEBUG_VECT_PEEK_1_SEL			 (0xfL<<12)
5104 #define BCE_HC_DEBUG_VECT_PEEK_2_VALUE			 (0x7ffL<<16)
5106 #define BCE_HC_DEBUG_VECT_PEEK_2_SEL			 (0xfL<<28)
5108 #define BCE_HC_COALESCE_NOW				0x00006914
5109 #define BCE_HC_COALESCE_NOW_COAL_NOW			 (0x1ffL<<1)
5110 #define BCE_HC_COALESCE_NOW_COAL_NOW_WO_INT		 (0x1ffL<<11)
5111 #define BCE_HC_COALESCE_NOW_COAL_ON_NXT_EVENT		 (0x1ffL<<21)
5113 #define BCE_HC_MSIX_BIT_VECTOR				0x00006918
5114 #define BCE_HC_MSIX_BIT_VECTOR_VAL			 (0x1ffL<<0)
5116 #define BCE_HC_SB_CONFIG_1				0x00006a00
5124 #define BCE_HC_SB_CONFIG_1_PER_COLLECT_LIMIT		 (0xfL<<20)
5126 #define BCE_HC_TX_QUICK_CONS_TRIP_1			0x00006a04
5127 #define BCE_HC_TX_QUICK_CONS_TRIP_1_VALUE		 (0xffL<<0)
5128 #define BCE_HC_TX_QUICK_CONS_TRIP_1_INT		 (0xffL<<16)
5130 #define BCE_HC_COMP_PROD_TRIP_1			0x00006a08
5131 #define BCE_HC_COMP_PROD_TRIP_1_VALUE			 (0xffL<<0)
5132 #define BCE_HC_COMP_PROD_TRIP_1_INT			 (0xffL<<16)
5134 #define BCE_HC_RX_QUICK_CONS_TRIP_1			0x00006a0c
5135 #define BCE_HC_RX_QUICK_CONS_TRIP_1_VALUE		 (0xffL<<0)
5136 #define BCE_HC_RX_QUICK_CONS_TRIP_1_INT		 (0xffL<<16)
5138 #define BCE_HC_RX_TICKS_1				0x00006a10
5139 #define BCE_HC_RX_TICKS_1_VALUE			 (0x3ffL<<0)
5140 #define BCE_HC_RX_TICKS_1_INT				 (0x3ffL<<16)
5142 #define BCE_HC_TX_TICKS_1				0x00006a14
5143 #define BCE_HC_TX_TICKS_1_VALUE			 (0x3ffL<<0)
5144 #define BCE_HC_TX_TICKS_1_INT				 (0x3ffL<<16)
5146 #define BCE_HC_COM_TICKS_1				0x00006a18
5147 #define BCE_HC_COM_TICKS_1_VALUE			 (0x3ffL<<0)
5148 #define BCE_HC_COM_TICKS_1_INT				 (0x3ffL<<16)
5150 #define BCE_HC_CMD_TICKS_1				0x00006a1c
5151 #define BCE_HC_CMD_TICKS_1_VALUE			 (0x3ffL<<0)
5152 #define BCE_HC_CMD_TICKS_1_INT				 (0x3ffL<<16)
5154 #define BCE_HC_PERIODIC_TICKS_1			0x00006a20
5155 #define BCE_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS	 (0xffffL<<0)
5156 #define BCE_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5158 #define BCE_HC_SB_CONFIG_2				0x00006a24
5166 #define BCE_HC_SB_CONFIG_2_PER_COLLECT_LIMIT		 (0xfL<<20)
5168 #define BCE_HC_TX_QUICK_CONS_TRIP_2			0x00006a28
5169 #define BCE_HC_TX_QUICK_CONS_TRIP_2_VALUE		 (0xffL<<0)
5170 #define BCE_HC_TX_QUICK_CONS_TRIP_2_INT		 (0xffL<<16)
5172 #define BCE_HC_COMP_PROD_TRIP_2			0x00006a2c
5173 #define BCE_HC_COMP_PROD_TRIP_2_VALUE			 (0xffL<<0)
5174 #define BCE_HC_COMP_PROD_TRIP_2_INT			 (0xffL<<16)
5176 #define BCE_HC_RX_QUICK_CONS_TRIP_2			0x00006a30
5177 #define BCE_HC_RX_QUICK_CONS_TRIP_2_VALUE		 (0xffL<<0)
5178 #define BCE_HC_RX_QUICK_CONS_TRIP_2_INT		 (0xffL<<16)
5180 #define BCE_HC_RX_TICKS_2				0x00006a34
5181 #define BCE_HC_RX_TICKS_2_VALUE			 (0x3ffL<<0)
5182 #define BCE_HC_RX_TICKS_2_INT				 (0x3ffL<<16)
5184 #define BCE_HC_TX_TICKS_2				0x00006a38
5185 #define BCE_HC_TX_TICKS_2_VALUE			 (0x3ffL<<0)
5186 #define BCE_HC_TX_TICKS_2_INT				 (0x3ffL<<16)
5188 #define BCE_HC_COM_TICKS_2				0x00006a3c
5189 #define BCE_HC_COM_TICKS_2_VALUE			 (0x3ffL<<0)
5190 #define BCE_HC_COM_TICKS_2_INT				 (0x3ffL<<16)
5192 #define BCE_HC_CMD_TICKS_2				0x00006a40
5193 #define BCE_HC_CMD_TICKS_2_VALUE			 (0x3ffL<<0)
5194 #define BCE_HC_CMD_TICKS_2_INT				 (0x3ffL<<16)
5196 #define BCE_HC_PERIODIC_TICKS_2			0x00006a44
5197 #define BCE_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS	 (0xffffL<<0)
5198 #define BCE_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5200 #define BCE_HC_SB_CONFIG_3				0x00006a48
5208 #define BCE_HC_SB_CONFIG_3_PER_COLLECT_LIMIT		 (0xfL<<20)
5210 #define BCE_HC_TX_QUICK_CONS_TRIP_3			0x00006a4c
5211 #define BCE_HC_TX_QUICK_CONS_TRIP_3_VALUE		 (0xffL<<0)
5212 #define BCE_HC_TX_QUICK_CONS_TRIP_3_INT		 (0xffL<<16)
5214 #define BCE_HC_COMP_PROD_TRIP_3			0x00006a50
5215 #define BCE_HC_COMP_PROD_TRIP_3_VALUE			 (0xffL<<0)
5216 #define BCE_HC_COMP_PROD_TRIP_3_INT			 (0xffL<<16)
5218 #define BCE_HC_RX_QUICK_CONS_TRIP_3			0x00006a54
5219 #define BCE_HC_RX_QUICK_CONS_TRIP_3_VALUE		 (0xffL<<0)
5220 #define BCE_HC_RX_QUICK_CONS_TRIP_3_INT		 (0xffL<<16)
5222 #define BCE_HC_RX_TICKS_3				0x00006a58
5223 #define BCE_HC_RX_TICKS_3_VALUE			 (0x3ffL<<0)
5224 #define BCE_HC_RX_TICKS_3_INT				 (0x3ffL<<16)
5226 #define BCE_HC_TX_TICKS_3				0x00006a5c
5227 #define BCE_HC_TX_TICKS_3_VALUE			 (0x3ffL<<0)
5228 #define BCE_HC_TX_TICKS_3_INT				 (0x3ffL<<16)
5230 #define BCE_HC_COM_TICKS_3				0x00006a60
5231 #define BCE_HC_COM_TICKS_3_VALUE			 (0x3ffL<<0)
5232 #define BCE_HC_COM_TICKS_3_INT				 (0x3ffL<<16)
5234 #define BCE_HC_CMD_TICKS_3				0x00006a64
5235 #define BCE_HC_CMD_TICKS_3_VALUE			 (0x3ffL<<0)
5236 #define BCE_HC_CMD_TICKS_3_INT				 (0x3ffL<<16)
5238 #define BCE_HC_PERIODIC_TICKS_3			0x00006a68
5239 #define BCE_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS	 (0xffffL<<0)
5240 #define BCE_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5242 #define BCE_HC_SB_CONFIG_4				0x00006a6c
5250 #define BCE_HC_SB_CONFIG_4_PER_COLLECT_LIMIT		 (0xfL<<20)
5252 #define BCE_HC_TX_QUICK_CONS_TRIP_4			0x00006a70
5253 #define BCE_HC_TX_QUICK_CONS_TRIP_4_VALUE		 (0xffL<<0)
5254 #define BCE_HC_TX_QUICK_CONS_TRIP_4_INT		 (0xffL<<16)
5256 #define BCE_HC_COMP_PROD_TRIP_4			0x00006a74
5257 #define BCE_HC_COMP_PROD_TRIP_4_VALUE			 (0xffL<<0)
5258 #define BCE_HC_COMP_PROD_TRIP_4_INT			 (0xffL<<16)
5260 #define BCE_HC_RX_QUICK_CONS_TRIP_4			0x00006a78
5261 #define BCE_HC_RX_QUICK_CONS_TRIP_4_VALUE		 (0xffL<<0)
5262 #define BCE_HC_RX_QUICK_CONS_TRIP_4_INT		 (0xffL<<16)
5264 #define BCE_HC_RX_TICKS_4				0x00006a7c
5265 #define BCE_HC_RX_TICKS_4_VALUE			 (0x3ffL<<0)
5266 #define BCE_HC_RX_TICKS_4_INT				 (0x3ffL<<16)
5268 #define BCE_HC_TX_TICKS_4				0x00006a80
5269 #define BCE_HC_TX_TICKS_4_VALUE			 (0x3ffL<<0)
5270 #define BCE_HC_TX_TICKS_4_INT				 (0x3ffL<<16)
5272 #define BCE_HC_COM_TICKS_4				0x00006a84
5273 #define BCE_HC_COM_TICKS_4_VALUE			 (0x3ffL<<0)
5274 #define BCE_HC_COM_TICKS_4_INT				 (0x3ffL<<16)
5276 #define BCE_HC_CMD_TICKS_4				0x00006a88
5277 #define BCE_HC_CMD_TICKS_4_VALUE			 (0x3ffL<<0)
5278 #define BCE_HC_CMD_TICKS_4_INT				 (0x3ffL<<16)
5280 #define BCE_HC_PERIODIC_TICKS_4			0x00006a8c
5281 #define BCE_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS	 (0xffffL<<0)
5282 #define BCE_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5284 #define BCE_HC_SB_CONFIG_5				0x00006a90
5292 #define BCE_HC_SB_CONFIG_5_PER_COLLECT_LIMIT		 (0xfL<<20)
5294 #define BCE_HC_TX_QUICK_CONS_TRIP_5			0x00006a94
5295 #define BCE_HC_TX_QUICK_CONS_TRIP_5_VALUE		 (0xffL<<0)
5296 #define BCE_HC_TX_QUICK_CONS_TRIP_5_INT		 (0xffL<<16)
5298 #define BCE_HC_COMP_PROD_TRIP_5			0x00006a98
5299 #define BCE_HC_COMP_PROD_TRIP_5_VALUE			 (0xffL<<0)
5300 #define BCE_HC_COMP_PROD_TRIP_5_INT			 (0xffL<<16)
5302 #define BCE_HC_RX_QUICK_CONS_TRIP_5			0x00006a9c
5303 #define BCE_HC_RX_QUICK_CONS_TRIP_5_VALUE		 (0xffL<<0)
5304 #define BCE_HC_RX_QUICK_CONS_TRIP_5_INT		 (0xffL<<16)
5306 #define BCE_HC_RX_TICKS_5				0x00006aa0
5307 #define BCE_HC_RX_TICKS_5_VALUE			 (0x3ffL<<0)
5308 #define BCE_HC_RX_TICKS_5_INT				 (0x3ffL<<16)
5310 #define BCE_HC_TX_TICKS_5				0x00006aa4
5311 #define BCE_HC_TX_TICKS_5_VALUE			 (0x3ffL<<0)
5312 #define BCE_HC_TX_TICKS_5_INT				 (0x3ffL<<16)
5314 #define BCE_HC_COM_TICKS_5				0x00006aa8
5315 #define BCE_HC_COM_TICKS_5_VALUE			 (0x3ffL<<0)
5316 #define BCE_HC_COM_TICKS_5_INT				 (0x3ffL<<16)
5318 #define BCE_HC_CMD_TICKS_5				0x00006aac
5319 #define BCE_HC_CMD_TICKS_5_VALUE			 (0x3ffL<<0)
5320 #define BCE_HC_CMD_TICKS_5_INT				 (0x3ffL<<16)
5322 #define BCE_HC_PERIODIC_TICKS_5			0x00006ab0
5323 #define BCE_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS	 (0xffffL<<0)
5324 #define BCE_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5326 #define BCE_HC_SB_CONFIG_6				0x00006ab4
5334 #define BCE_HC_SB_CONFIG_6_PER_COLLECT_LIMIT		 (0xfL<<20)
5336 #define BCE_HC_TX_QUICK_CONS_TRIP_6			0x00006ab8
5337 #define BCE_HC_TX_QUICK_CONS_TRIP_6_VALUE		 (0xffL<<0)
5338 #define BCE_HC_TX_QUICK_CONS_TRIP_6_INT		 (0xffL<<16)
5340 #define BCE_HC_COMP_PROD_TRIP_6			0x00006abc
5341 #define BCE_HC_COMP_PROD_TRIP_6_VALUE			 (0xffL<<0)
5342 #define BCE_HC_COMP_PROD_TRIP_6_INT			 (0xffL<<16)
5344 #define BCE_HC_RX_QUICK_CONS_TRIP_6			0x00006ac0
5345 #define BCE_HC_RX_QUICK_CONS_TRIP_6_VALUE		 (0xffL<<0)
5346 #define BCE_HC_RX_QUICK_CONS_TRIP_6_INT		 (0xffL<<16)
5348 #define BCE_HC_RX_TICKS_6				0x00006ac4
5349 #define BCE_HC_RX_TICKS_6_VALUE			 (0x3ffL<<0)
5350 #define BCE_HC_RX_TICKS_6_INT				 (0x3ffL<<16)
5352 #define BCE_HC_TX_TICKS_6				0x00006ac8
5353 #define BCE_HC_TX_TICKS_6_VALUE			 (0x3ffL<<0)
5354 #define BCE_HC_TX_TICKS_6_INT				 (0x3ffL<<16)
5356 #define BCE_HC_COM_TICKS_6				0x00006acc
5357 #define BCE_HC_COM_TICKS_6_VALUE			 (0x3ffL<<0)
5358 #define BCE_HC_COM_TICKS_6_INT				 (0x3ffL<<16)
5360 #define BCE_HC_CMD_TICKS_6				0x00006ad0
5361 #define BCE_HC_CMD_TICKS_6_VALUE			 (0x3ffL<<0)
5362 #define BCE_HC_CMD_TICKS_6_INT				 (0x3ffL<<16)
5364 #define BCE_HC_PERIODIC_TICKS_6			0x00006ad4
5365 #define BCE_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS	 (0xffffL<<0)
5366 #define BCE_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5368 #define BCE_HC_SB_CONFIG_7				0x00006ad8
5376 #define BCE_HC_SB_CONFIG_7_PER_COLLECT_LIMIT		 (0xfL<<20)
5378 #define BCE_HC_TX_QUICK_CONS_TRIP_7			0x00006adc
5379 #define BCE_HC_TX_QUICK_CONS_TRIP_7_VALUE		 (0xffL<<0)
5380 #define BCE_HC_TX_QUICK_CONS_TRIP_7_INT		 (0xffL<<16)
5382 #define BCE_HC_COMP_PROD_TRIP_7			0x00006ae0
5383 #define BCE_HC_COMP_PROD_TRIP_7_VALUE			 (0xffL<<0)
5384 #define BCE_HC_COMP_PROD_TRIP_7_INT			 (0xffL<<16)
5386 #define BCE_HC_RX_QUICK_CONS_TRIP_7			0x00006ae4
5387 #define BCE_HC_RX_QUICK_CONS_TRIP_7_VALUE		 (0xffL<<0)
5388 #define BCE_HC_RX_QUICK_CONS_TRIP_7_INT		 (0xffL<<16)
5390 #define BCE_HC_RX_TICKS_7				0x00006ae8
5391 #define BCE_HC_RX_TICKS_7_VALUE			 (0x3ffL<<0)
5392 #define BCE_HC_RX_TICKS_7_INT				 (0x3ffL<<16)
5394 #define BCE_HC_TX_TICKS_7				0x00006aec
5395 #define BCE_HC_TX_TICKS_7_VALUE			 (0x3ffL<<0)
5396 #define BCE_HC_TX_TICKS_7_INT				 (0x3ffL<<16)
5398 #define BCE_HC_COM_TICKS_7				0x00006af0
5399 #define BCE_HC_COM_TICKS_7_VALUE			 (0x3ffL<<0)
5400 #define BCE_HC_COM_TICKS_7_INT				 (0x3ffL<<16)
5402 #define BCE_HC_CMD_TICKS_7				0x00006af4
5403 #define BCE_HC_CMD_TICKS_7_VALUE			 (0x3ffL<<0)
5404 #define BCE_HC_CMD_TICKS_7_INT				 (0x3ffL<<16)
5406 #define BCE_HC_PERIODIC_TICKS_7			0x00006af8
5407 #define BCE_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS	 (0xffffL<<0)
5408 #define BCE_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5410 #define BCE_HC_SB_CONFIG_8				0x00006afc
5418 #define BCE_HC_SB_CONFIG_8_PER_COLLECT_LIMIT		 (0xfL<<20)
5420 #define BCE_HC_TX_QUICK_CONS_TRIP_8			0x00006b00
5421 #define BCE_HC_TX_QUICK_CONS_TRIP_8_VALUE		 (0xffL<<0)
5422 #define BCE_HC_TX_QUICK_CONS_TRIP_8_INT		 (0xffL<<16)
5424 #define BCE_HC_COMP_PROD_TRIP_8			0x00006b04
5425 #define BCE_HC_COMP_PROD_TRIP_8_VALUE			 (0xffL<<0)
5426 #define BCE_HC_COMP_PROD_TRIP_8_INT			 (0xffL<<16)
5428 #define BCE_HC_RX_QUICK_CONS_TRIP_8			0x00006b08
5429 #define BCE_HC_RX_QUICK_CONS_TRIP_8_VALUE		 (0xffL<<0)
5430 #define BCE_HC_RX_QUICK_CONS_TRIP_8_INT		 (0xffL<<16)
5432 #define BCE_HC_RX_TICKS_8				0x00006b0c
5433 #define BCE_HC_RX_TICKS_8_VALUE			 (0x3ffL<<0)
5434 #define BCE_HC_RX_TICKS_8_INT				 (0x3ffL<<16)
5436 #define BCE_HC_TX_TICKS_8				0x00006b10
5437 #define BCE_HC_TX_TICKS_8_VALUE			 (0x3ffL<<0)
5438 #define BCE_HC_TX_TICKS_8_INT				 (0x3ffL<<16)
5440 #define BCE_HC_COM_TICKS_8				0x00006b14
5441 #define BCE_HC_COM_TICKS_8_VALUE			 (0x3ffL<<0)
5442 #define BCE_HC_COM_TICKS_8_INT				 (0x3ffL<<16)
5444 #define BCE_HC_CMD_TICKS_8				0x00006b18
5445 #define BCE_HC_CMD_TICKS_8_VALUE			 (0x3ffL<<0)
5446 #define BCE_HC_CMD_TICKS_8_INT				 (0x3ffL<<16)
5448 #define BCE_HC_PERIODIC_TICKS_8			0x00006b1c
5449 #define BCE_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS	 (0xffffL<<0)
5450 #define BCE_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS	 (0xffffL<<16)
5454  *  offset: 0x40000
5456 #define BCE_TXP_CPU_MODE				0x00045000
5457 #define BCE_TXP_CPU_MODE_LOCAL_RST			 (1L<<0)
5469 #define BCE_TXP_CPU_STATE				0x00045004
5470 #define BCE_TXP_CPU_STATE_BREAKPOINT			 (1L<<0)
5485 #define BCE_TXP_CPU_EVENT_MASK				0x00045008
5486 #define BCE_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
5498 #define BCE_TXP_CPU_PROGRAM_COUNTER			0x0004501c
5499 #define BCE_TXP_CPU_INSTRUCTION			0x00045020
5500 #define BCE_TXP_CPU_DATA_ACCESS			0x00045024
5501 #define BCE_TXP_CPU_INTERRUPT_ENABLE			0x00045028
5502 #define BCE_TXP_CPU_INTERRUPT_VECTOR			0x0004502c
5503 #define BCE_TXP_CPU_INTERRUPT_SAVED_PC			0x00045030
5504 #define BCE_TXP_CPU_HW_BREAKPOINT			0x00045034
5505 #define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5506 #define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5508 #define BCE_TXP_CPU_REG_FILE				0x00045200
5509 #define BCE_TXP_FTQ_DATA				0x000453c0
5510 #define BCE_TXP_FTQ_CMD				0x000453f8
5511 #define BCE_TXP_FTQ_CMD_OFFSET				 (0x3ffL<<0)
5513 #define BCE_TXP_FTQ_CMD_WR_TOP_0			 (0L<<10)
5523 #define BCE_TXP_FTQ_CTL				0x000453fc
5524 #define BCE_TXP_FTQ_CTL_INTERVENE			 (1L<<0)
5527 #define BCE_TXP_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5528 #define BCE_TXP_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5530 #define BCE_TXP_SCRATCH				0x00060000
5534  *  offset: 0x80000
5536 #define BCE_TPAT_CPU_MODE				0x00085000
5537 #define BCE_TPAT_CPU_MODE_LOCAL_RST			 (1L<<0)
5549 #define BCE_TPAT_CPU_STATE				0x00085004
5550 #define BCE_TPAT_CPU_STATE_BREAKPOINT			 (1L<<0)
5565 #define BCE_TPAT_CPU_EVENT_MASK			0x00085008
5566 #define BCE_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK	 (1L<<0)
5578 #define BCE_TPAT_CPU_PROGRAM_COUNTER			0x0008501c
5579 #define BCE_TPAT_CPU_INSTRUCTION			0x00085020
5580 #define BCE_TPAT_CPU_DATA_ACCESS			0x00085024
5581 #define BCE_TPAT_CPU_INTERRUPT_ENABLE			0x00085028
5582 #define BCE_TPAT_CPU_INTERRUPT_VECTOR			0x0008502c
5583 #define BCE_TPAT_CPU_INTERRUPT_SAVED_PC		0x00085030
5584 #define BCE_TPAT_CPU_HW_BREAKPOINT			0x00085034
5585 #define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5586 #define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5587 #define BCE_TPAT_CPU_REG_FILE				0x00085200
5588 #define BCE_TPAT_FTQ_DATA				0x000853c0
5589 #define BCE_TPAT_FTQ_CMD				0x000853f8
5590 #define BCE_TPAT_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5592 #define BCE_TPAT_FTQ_CMD_WR_TOP_0			 (0L<<10)
5602 #define BCE_TPAT_FTQ_CTL				0x000853fc
5603 #define BCE_TPAT_FTQ_CTL_INTERVENE			 (1L<<0)
5606 #define BCE_TPAT_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5607 #define BCE_TPAT_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5609 #define BCE_TPAT_SCRATCH				0x000a0000
5613  *  offset: 0xc0000
5615 #define BCE_RXP_CPU_MODE				0x000c5000
5616 #define BCE_RXP_CPU_MODE_LOCAL_RST			 (1L<<0)
5628 #define BCE_RXP_CPU_STATE				0x000c5004
5629 #define BCE_RXP_CPU_STATE_BREAKPOINT			 (1L<<0)
5644 #define BCE_RXP_CPU_EVENT_MASK				0x000c5008
5645 #define BCE_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
5657 #define BCE_RXP_CPU_PROGRAM_COUNTER			0x000c501c
5658 #define BCE_RXP_CPU_INSTRUCTION			0x000c5020
5659 #define BCE_RXP_CPU_DATA_ACCESS			0x000c5024
5660 #define BCE_RXP_CPU_INTERRUPT_ENABLE			0x000c5028
5661 #define BCE_RXP_CPU_INTERRUPT_VECTOR			0x000c502c
5662 #define BCE_RXP_CPU_INTERRUPT_SAVED_PC			0x000c5030
5663 #define BCE_RXP_CPU_HW_BREAKPOINT			0x000c5034
5664 #define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5665 #define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5667 #define BCE_RXP_CPU_REG_FILE				0x000c5200
5668 #define BCE_RXP_CFTQ_DATA				0x000c5380
5669 #define BCE_RXP_CFTQ_CMD				0x000c53b8
5670 #define BCE_RXP_CFTQ_CMD_OFFSET			 (0x3ffL<<0)
5672 #define BCE_RXP_CFTQ_CMD_WR_TOP_0			 (0L<<10)
5682 #define BCE_RXP_CFTQ_CTL				0x000c53bc
5683 #define BCE_RXP_CFTQ_CTL_INTERVENE			 (1L<<0)
5686 #define BCE_RXP_CFTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5687 #define BCE_RXP_CFTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5689 #define BCE_RXP_FTQ_DATA				0x000c53c0
5690 #define BCE_RXP_FTQ_CMD				0x000c53f8
5691 #define BCE_RXP_FTQ_CMD_OFFSET				 (0x3ffL<<0)
5693 #define BCE_RXP_FTQ_CMD_WR_TOP_0			 (0L<<10)
5703 #define BCE_RXP_FTQ_CTL				0x000c53fc
5704 #define BCE_RXP_FTQ_CTL_INTERVENE			 (1L<<0)
5707 #define BCE_RXP_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5708 #define BCE_RXP_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5710 #define BCE_RXP_SCRATCH				0x000e0000
5714  *  offset: 0x100000
5716 #define BCE_COM_CPU_MODE				0x00105000
5717 #define BCE_COM_CPU_MODE_LOCAL_RST			 (1L<<0)
5729 #define BCE_COM_CPU_STATE				0x00105004
5730 #define BCE_COM_CPU_STATE_BREAKPOINT			 (1L<<0)
5745 #define BCE_COM_CPU_EVENT_MASK				0x00105008
5746 #define BCE_COM_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
5758 #define BCE_COM_CPU_PROGRAM_COUNTER			0x0010501c
5759 #define BCE_COM_CPU_INSTRUCTION			0x00105020
5760 #define BCE_COM_CPU_DATA_ACCESS			0x00105024
5761 #define BCE_COM_CPU_INTERRUPT_ENABLE			0x00105028
5762 #define BCE_COM_CPU_INTERRUPT_VECTOR			0x0010502c
5763 #define BCE_COM_CPU_INTERRUPT_SAVED_PC			0x00105030
5764 #define BCE_COM_CPU_HW_BREAKPOINT			0x00105034
5765 #define BCE_COM_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5766 #define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5768 #define BCE_COM_CPU_REG_FILE				0x00105200
5769 #define BCE_COM_COMXQ_FTQ_DATA				0x00105340
5770 #define BCE_COM_COMXQ_FTQ_CMD				0x00105378
5771 #define BCE_COM_COMXQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5773 #define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
5783 #define BCE_COM_COMXQ_FTQ_CTL				0x0010537c
5784 #define BCE_COM_COMXQ_FTQ_CTL_INTERVENE		 (1L<<0)
5787 #define BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
5788 #define BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
5790 #define BCE_COM_COMTQ_FTQ_DATA				0x00105380
5791 #define BCE_COM_COMTQ_FTQ_CMD				0x001053b8
5792 #define BCE_COM_COMTQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5794 #define BCE_COM_COMTQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
5804 #define BCE_COM_COMTQ_FTQ_CTL				0x001053bc
5805 #define BCE_COM_COMTQ_FTQ_CTL_INTERVENE		 (1L<<0)
5808 #define BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH		 (0x3ffL<<12)
5809 #define BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH		 (0x3ffL<<22)
5811 #define BCE_COM_COMQ_FTQ_DATA				0x001053c0
5812 #define BCE_COM_COMQ_FTQ_CMD				0x001053f8
5813 #define BCE_COM_COMQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5815 #define BCE_COM_COMQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
5825 #define BCE_COM_COMQ_FTQ_CTL				0x001053fc
5826 #define BCE_COM_COMQ_FTQ_CTL_INTERVENE			 (1L<<0)
5829 #define BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5830 #define BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5832 #define BCE_COM_SCRATCH				0x00120000
5836  *  offset: 0x180000
5838 #define BCE_CP_CPU_MODE				0x00185000
5839 #define BCE_CP_CPU_MODE_LOCAL_RST			 (1L<<0)
5851 #define BCE_CP_CPU_STATE				0x00185004
5852 #define BCE_CP_CPU_STATE_BREAKPOINT			 (1L<<0)
5867 #define BCE_CP_CPU_EVENT_MASK				0x00185008
5868 #define BCE_CP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
5880 #define BCE_CP_CPU_PROGRAM_COUNTER			0x0018501c
5881 #define BCE_CP_CPU_INSTRUCTION				0x00185020
5882 #define BCE_CP_CPU_DATA_ACCESS				0x00185024
5883 #define BCE_CP_CPU_INTERRUPT_ENABLE			0x00185028
5884 #define BCE_CP_CPU_INTERRUPT_VECTOR			0x0018502c
5885 #define BCE_CP_CPU_INTERRUPT_SAVED_PC			0x00185030
5886 #define BCE_CP_CPU_HW_BREAKPOINT			0x00185034
5887 #define BCE_CP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5888 #define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5890 #define BCE_CP_CPU_REG_FILE				0x00185200
5891 #define BCE_CP_CPQ_FTQ_DATA				0x001853c0
5892 #define BCE_CP_CPQ_FTQ_CMD				0x001853f8
5893 #define BCE_CP_CPQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5895 #define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
5905 #define BCE_CP_CPQ_FTQ_CTL				0x001853fc
5906 #define BCE_CP_CPQ_FTQ_CTL_INTERVENE			 (1L<<0)
5909 #define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5910 #define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
5912 #define BCE_CP_SCRATCH					0x001a0000
5916  *  offset: 0x1c0000
5918 #define BCE_TAS_FTQ_CMD						0x001c03f8
5919 #define BCE_TAS_FTQ_CTL						0x001c03fc
5920 #define BCE_TAS_FTQ_CTL_MAX_DEPTH			(0x3ffL<<12)
5921 #define BCE_TAS_FTQ_CTL_CUR_DEPTH			(0x3ffL<<22)
5925  *  offset: 0x140000
5927 #define BCE_MCP_CPU_MODE				0x00145000
5928 #define BCE_MCP_CPU_MODE_LOCAL_RST			 (1L<<0)
5940 #define BCE_MCP_CPU_STATE				0x00145004
5941 #define BCE_MCP_CPU_STATE_BREAKPOINT			 (1L<<0)
5956 #define BCE_MCP_CPU_EVENT_MASK				0x00145008
5957 #define BCE_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK		 (1L<<0)
5969 #define BCE_MCP_CPU_PROGRAM_COUNTER			0x0014501c
5970 #define BCE_MCP_CPU_INSTRUCTION			0x00145020
5971 #define BCE_MCP_CPU_DATA_ACCESS			0x00145024
5972 #define BCE_MCP_CPU_INTERRUPT_ENABLE			0x00145028
5973 #define BCE_MCP_CPU_INTERRUPT_VECTOR			0x0014502c
5974 #define BCE_MCP_CPU_INTERRUPT_SAVED_PC			0x00145030
5975 #define BCE_MCP_CPU_HW_BREAKPOINT			0x00145034
5976 #define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE		 (1L<<0)
5977 #define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS		 (0x3fffffffL<<2)
5979 #define BCE_MCP_CPU_REG_FILE				0x00145200
5980 #define BCE_MCP_MCPQ_FTQ_DATA				0x001453c0
5981 #define BCE_MCP_MCPQ_FTQ_CMD				0x001453f8
5982 #define BCE_MCP_MCPQ_FTQ_CMD_OFFSET			 (0x3ffL<<0)
5984 #define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0			 (0L<<10)
5994 #define BCE_MCP_MCPQ_FTQ_CTL				0x001453fc
5995 #define BCE_MCP_MCPQ_FTQ_CTL_INTERVENE			 (1L<<0)
5998 #define BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH			 (0x3ffL<<12)
5999 #define BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH			 (0x3ffL<<22)
6001 #define BCE_MCP_ROM								0x00150000
6002 #define BCE_MCP_SCRATCH							0x00160000
6005 #define BCE_SHM_HDR_SIGNATURE_SIG_MASK			0xffff0000
6006 #define BCE_SHM_HDR_SIGNATURE_SIG				0x53530000
6007 #define BCE_SHM_HDR_SIGNATURE_VER_MASK			0x000000ff
6008 #define BCE_SHM_HDR_SIGNATURE_VER_ONE			0x00000001
6028  * 0 = Default.  All received unicst packets matching MAC address
6029  *     BCE_EMAC_MAC_MATCH[0:1,8:9,10:11,12:13,14:15] are sent to receive queue
6030  *     0, all other perfect match registers are reserved.
6032  *     BCE_EMAC_MAC_MATCH[0:1] are mapped to receive queue 0,
6035  *     are sent to receive queue 0.
6037 #define BCE_RXP_PM_CTRL			0x0e00d0
6044 #define BCE_COM_NO_BUFFERS		0x120084
6146 #define MB_GET_CID_ADDR(_cid)	(0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
6148 #define MAX_CID_CNT		0x4000
6150 #define INVALID_CID_ADDR	0xffffffff
6153 #define RX_CID			0
6225 #define RV2P_PROC1		0
6228 #define BCE_MIREG(x)		((x & 0x1F) << 16)
6229 #define BCE_MIPHY(x)		((x & 0x1F) << 21)
6232 #define BCE_NVRAM_SIZE		0x200
6233 #define BCE_NVRAM_MAGIC		0x669955aa
6234 #define BCE_CRC32_RESIDUAL	0xdebb20e3
6243 #define BCE_DMA_BOUNDARY	0
6250 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
6253 #define BCE_BUS_SPACE_MAXADDR		0xFFFFFFFFFF
6333 #define BCE_PCIX_FLAG				0x00000001
6334 #define BCE_PCI_32BIT_FLAG 			0x00000002
6335 #define BCE_RESERVED_FLAG			0x00000004
6336 #define BCE_NO_WOL_FLAG				0x00000008
6337 #define BCE_USING_DAC_FLAG			0x00000010
6338 #define BCE_USING_MSI_FLAG 			0x00000020
6339 #define BCE_MFW_ENABLE_FLAG			0x00000040
6340 #define BCE_ONE_SHOT_MSI_FLAG			0x00000080
6341 #define BCE_USING_MSIX_FLAG			0x00000100
6342 #define BCE_PCIE_FLAG				0x00000200
6343 #define BCE_USING_TX_FLOW_CONTROL		0x00000400
6344 #define BCE_USING_RX_FLOW_CONTROL		0x00000800
6348 #define BCE_MSI_CAPABLE_FLAG			0x00000001
6349 #define BCE_MSIX_CAPABLE_FLAG			0x00000002
6350 #define BCE_PCIE_CAPABLE_FLAG			0x00000004
6351 #define BCE_PCIX_CAPABLE_FLAG			0x00000008
6355 #define BCE_PHY_SERDES_FLAG			0x00000001
6356 #define BCE_PHY_CRC_FIX_FLAG			0x00000002
6357 #define BCE_PHY_PARALLEL_DETECT_FLAG		0x00000004
6358 #define BCE_PHY_2_5G_CAPABLE_FLAG		0x00000008
6359 #define BCE_PHY_INT_MODE_MASK_FLAG		0x00000300
6360 #define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG	0x00000100
6361 #define BCE_PHY_INT_MODE_LINK_READY_FLAG	0x00000200
6362 #define BCE_PHY_IEEE_CLAUSE_45_FLAG		0x00000400
6363 #define	BCE_PHY_REMOTE_CAP_FLAG			0x00000800
6364 #define	BCE_PHY_REMOTE_PORT_FIBER_FLAG		0x00001000
6400 	 * Tracks the state of the firmware.  0 = Running while any