137 xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)  in xgbe_phy_kr_training_pre()  argument
139 	XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1);  in xgbe_phy_kr_training_pre()
143 xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)  in xgbe_phy_kr_training_post()  argument
145 	XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0);  in xgbe_phy_kr_training_post()
149 xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)  in xgbe_phy_an_outcome()  argument
151 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_an_outcome()
155 	XGBE_SET_LP_ADV(&pdata->phy, Autoneg);  in xgbe_phy_an_outcome()
156 	XGBE_SET_LP_ADV(&pdata->phy, Backplane);  in xgbe_phy_an_outcome()
159 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);  in xgbe_phy_an_outcome()
160 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);  in xgbe_phy_an_outcome()
162 		XGBE_SET_LP_ADV(&pdata->phy, Pause);  in xgbe_phy_an_outcome()
164 		XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);  in xgbe_phy_an_outcome()
167 	    __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);  in xgbe_phy_an_outcome()
169 	if (pdata->phy.pause_autoneg) {  in xgbe_phy_an_outcome()
171 		pdata->phy.tx_pause = 0;  in xgbe_phy_an_outcome()
172 		pdata->phy.rx_pause = 0;  in xgbe_phy_an_outcome()
175 			pdata->phy.tx_pause = 1;  in xgbe_phy_an_outcome()
176 			pdata->phy.rx_pause = 1;  in xgbe_phy_an_outcome()
179 				pdata->phy.rx_pause = 1;  in xgbe_phy_an_outcome()
181 				pdata->phy.tx_pause = 1;  in xgbe_phy_an_outcome()
186 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);  in xgbe_phy_an_outcome()
187 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);  in xgbe_phy_an_outcome()
189 		XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);  in xgbe_phy_an_outcome()
192 			XGBE_SET_LP_ADV(&pdata->phy, 2500baseX_Full);  in xgbe_phy_an_outcome()
194 			XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);  in xgbe_phy_an_outcome()
199 		pdata->phy.speed = SPEED_10000;  in xgbe_phy_an_outcome()
202 		switch (pdata->speed_set) {  in xgbe_phy_an_outcome()
204 			pdata->phy.speed = SPEED_1000;  in xgbe_phy_an_outcome()
209 			pdata->phy.speed = SPEED_2500;  in xgbe_phy_an_outcome()
215 		pdata->phy.speed = SPEED_UNKNOWN;  in xgbe_phy_an_outcome()
219 	ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);  in xgbe_phy_an_outcome()
220 	lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);  in xgbe_phy_an_outcome()
222 		XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);  in xgbe_phy_an_outcome()
228 xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, struct xgbe_phy *dphy)  in xgbe_phy_an_advertising()  argument
230 	XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);  in xgbe_phy_an_advertising()
234 xgbe_phy_an_config(struct xgbe_prv_data *pdata)  in xgbe_phy_an_config()  argument
241 xgbe_phy_an_mode(struct xgbe_prv_data *pdata)  in xgbe_phy_an_mode()  argument
247 xgbe_phy_pcs_power_cycle(struct xgbe_prv_data *pdata)  in xgbe_phy_pcs_power_cycle()  argument
251 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_pcs_power_cycle()
254 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_pcs_power_cycle()
259 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_pcs_power_cycle()
263 xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata)  in xgbe_phy_start_ratechange()  argument
266 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1);  in xgbe_phy_start_ratechange()
270 xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata)  in xgbe_phy_complete_ratechange()  argument
276 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0);  in xgbe_phy_complete_ratechange()
283 		status = XSIR0_IOREAD(pdata, SIR0_STATUS);  in xgbe_phy_complete_ratechange()
293 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0);  in xgbe_phy_complete_ratechange()
294 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1);  in xgbe_phy_complete_ratechange()
298 xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)  in xgbe_phy_kr_mode()  argument
300 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_kr_mode()
304 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);  in xgbe_phy_kr_mode()
307 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);  in xgbe_phy_kr_mode()
309 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_kr_mode()
312 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_kr_mode()
314 	xgbe_phy_pcs_power_cycle(pdata);  in xgbe_phy_kr_mode()
317 	xgbe_phy_start_ratechange(pdata);  in xgbe_phy_kr_mode()
319 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE);  in xgbe_phy_kr_mode()
320 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD);  in xgbe_phy_kr_mode()
321 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL);  in xgbe_phy_kr_mode()
323 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,  in xgbe_phy_kr_mode()
325 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,  in xgbe_phy_kr_mode()
327 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,  in xgbe_phy_kr_mode()
329 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,  in xgbe_phy_kr_mode()
331 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,  in xgbe_phy_kr_mode()
333 	XRXTX_IOWRITE(pdata, RXTX_REG22,  in xgbe_phy_kr_mode()
336 	xgbe_phy_complete_ratechange(pdata);  in xgbe_phy_kr_mode()
342 xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)  in xgbe_phy_kx_2500_mode()  argument
344 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_kx_2500_mode()
348 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);  in xgbe_phy_kx_2500_mode()
351 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);  in xgbe_phy_kx_2500_mode()
353 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_kx_2500_mode()
356 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_kx_2500_mode()
358 	xgbe_phy_pcs_power_cycle(pdata);  in xgbe_phy_kx_2500_mode()
361 	xgbe_phy_start_ratechange(pdata);  in xgbe_phy_kx_2500_mode()
363 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE);  in xgbe_phy_kx_2500_mode()
364 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD);  in xgbe_phy_kx_2500_mode()
365 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL);  in xgbe_phy_kx_2500_mode()
367 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,  in xgbe_phy_kx_2500_mode()
369 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,  in xgbe_phy_kx_2500_mode()
371 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,  in xgbe_phy_kx_2500_mode()
373 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,  in xgbe_phy_kx_2500_mode()
375 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,  in xgbe_phy_kx_2500_mode()
377 	XRXTX_IOWRITE(pdata, RXTX_REG22,  in xgbe_phy_kx_2500_mode()
380 	xgbe_phy_complete_ratechange(pdata);  in xgbe_phy_kx_2500_mode()
386 xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)  in xgbe_phy_kx_1000_mode()  argument
388 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_kx_1000_mode()
392 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);  in xgbe_phy_kx_1000_mode()
395 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);  in xgbe_phy_kx_1000_mode()
397 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_kx_1000_mode()
400 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_kx_1000_mode()
402 	xgbe_phy_pcs_power_cycle(pdata);  in xgbe_phy_kx_1000_mode()
405 	xgbe_phy_start_ratechange(pdata);  in xgbe_phy_kx_1000_mode()
407 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE);  in xgbe_phy_kx_1000_mode()
408 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD);  in xgbe_phy_kx_1000_mode()
409 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL);  in xgbe_phy_kx_1000_mode()
411 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,  in xgbe_phy_kx_1000_mode()
413 	XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,  in xgbe_phy_kx_1000_mode()
415 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,  in xgbe_phy_kx_1000_mode()
417 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,  in xgbe_phy_kx_1000_mode()
419 	XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,  in xgbe_phy_kx_1000_mode()
421 	XRXTX_IOWRITE(pdata, RXTX_REG22,  in xgbe_phy_kx_1000_mode()
424 	xgbe_phy_complete_ratechange(pdata);  in xgbe_phy_kx_1000_mode()
430 xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)  in xgbe_phy_cur_mode()  argument
432 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_cur_mode()
436 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);  in xgbe_phy_cur_mode()
452 xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)  in xgbe_phy_switch_mode()  argument
454 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_switch_mode()
458 	if (xgbe_phy_cur_mode(pdata) == XGBE_MODE_KR) {  in xgbe_phy_switch_mode()
471 xgbe_phy_get_mode(struct xgbe_prv_data *pdata, int speed)  in xgbe_phy_get_mode()  argument
473 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_get_mode()
490 xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)  in xgbe_phy_set_mode()  argument
494 		xgbe_phy_kx_1000_mode(pdata);  in xgbe_phy_set_mode()
497 		xgbe_phy_kx_2500_mode(pdata);  in xgbe_phy_set_mode()
500 		xgbe_phy_kr_mode(pdata);  in xgbe_phy_set_mode()
508 xgbe_phy_get_type(struct xgbe_prv_data *pdata, struct ifmediareq * ifmr)  in xgbe_phy_get_type()  argument
511 	switch (pdata->phy.speed) {  in xgbe_phy_get_type()
528 xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode, bool advert)  in xgbe_phy_check_mode()  argument
531 	if (pdata->phy.autoneg == AUTONEG_ENABLE)  in xgbe_phy_check_mode()
536 		cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);  in xgbe_phy_check_mode()
545 xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)  in xgbe_phy_use_mode()  argument
550 		return (xgbe_phy_check_mode(pdata, mode,  in xgbe_phy_use_mode()
551 		    XGBE_ADV(&pdata->phy, 1000baseKX_Full)));  in xgbe_phy_use_mode()
553 		return (xgbe_phy_check_mode(pdata, mode,  in xgbe_phy_use_mode()
554 		    XGBE_ADV(&pdata->phy, 2500baseX_Full)));  in xgbe_phy_use_mode()
556 		return (xgbe_phy_check_mode(pdata, mode,  in xgbe_phy_use_mode()
557 		    XGBE_ADV(&pdata->phy, 10000baseKR_Full)));  in xgbe_phy_use_mode()
564 xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)  in xgbe_phy_valid_speed()  argument
566 	struct xgbe_phy_data *phy_data = pdata->phy_data;  in xgbe_phy_valid_speed()
585 xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)  in xgbe_phy_link_status()  argument
594 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);  in xgbe_phy_link_status()
595 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);  in xgbe_phy_link_status()
601 xgbe_phy_stop(struct xgbe_prv_data *pdata)  in xgbe_phy_stop()  argument
607 xgbe_phy_start(struct xgbe_prv_data *pdata)  in xgbe_phy_start()  argument
614 xgbe_phy_reset(struct xgbe_prv_data *pdata)  in xgbe_phy_reset()  argument
619 	reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_reset()
621 	XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);  in xgbe_phy_reset()
626 		reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);  in xgbe_phy_reset()
636 xgbe_phy_exit(struct xgbe_prv_data *pdata)  in xgbe_phy_exit()  argument
642 xgbe_phy_init(struct xgbe_prv_data *pdata)  in xgbe_phy_init()  argument
649 	XGBE_ZERO_SUP(&pdata->phy);  in xgbe_phy_init()
650 	XGBE_SET_SUP(&pdata->phy, Autoneg);  in xgbe_phy_init()
651 	XGBE_SET_SUP(&pdata->phy, Pause);  in xgbe_phy_init()
652 	XGBE_SET_SUP(&pdata->phy, Asym_Pause);  in xgbe_phy_init()
653 	XGBE_SET_SUP(&pdata->phy, Backplane);  in xgbe_phy_init()
654 	XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);  in xgbe_phy_init()
657 		XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);  in xgbe_phy_init()
660 		XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);  in xgbe_phy_init()
664 	if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)  in xgbe_phy_init()
665 		XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);  in xgbe_phy_init()
667 	pdata->phy_data = phy_data;  in xgbe_phy_init()