1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
4  * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
44  * by the driver - eg, calls to ath_hal_gettsf32().
136 	struct ath_hal *ah = sc->sc_ah;  in ath_tdma_settimers()
141 	bt.bt_nextdba = (nexttbtt<<3) - sc->sc_tdmadbaprep;  in ath_tdma_settimers()
142 	bt.bt_nextswba = (nexttbtt<<3) - sc->sc_tdmaswbaprep;  in ath_tdma_settimers()
163 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_SET)) {  in ath_tdma_settimers()
171 		t.sc_tdmadbaprep = htobe32(sc->sc_tdmadbaprep);  in ath_tdma_settimers()
172 		t.sc_tdmaswbaprep = htobe32(sc->sc_tdmaswbaprep);  in ath_tdma_settimers()
173 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_SET,  in ath_tdma_settimers()
191  * identically wrt transmit rate so the guard time we calculate
193  * factor in the xmit time because the hardware will schedule
195  * the burst time.  When we get hardware that properly kills
196  * frames in the PCU we can reduce/eliminate the guard time.
198  * Roundup to 1024 is so we have 1 TU buffer in the guard time
208 	sc->sc_tdmaslotlen = tdma->tdma_slotlen;  in ath_tdma_bintvalsetup()
210 	sc->sc_tdmabintval = roundup((sc->sc_tdmaslotlen+sc->sc_tdmaguard) *  in ath_tdma_bintvalsetup()
211 		tdma->tdma_slotcnt, 1024);  in ath_tdma_bintvalsetup()
212 	sc->sc_tdmabintval >>= 10;		/* TSF -> TU */  in ath_tdma_bintvalsetup()
213 	if (sc->sc_tdmabintval & 1)  in ath_tdma_bintvalsetup()
214 		sc->sc_tdmabintval++;  in ath_tdma_bintvalsetup()
216 	if (tdma->tdma_slot == 0) {  in ath_tdma_bintvalsetup()
218 		 * Only slot 0 beacons; other slots respond.  in ath_tdma_bintvalsetup()
220 		sc->sc_imask |= HAL_INT_SWBA;  in ath_tdma_bintvalsetup()
221 		sc->sc_tdmaswba = 0;		/* beacon immediately */  in ath_tdma_bintvalsetup()
223 		/* XXX all vaps must be slot 0 or slot !0 */  in ath_tdma_bintvalsetup()
224 		sc->sc_imask &= ~HAL_INT_SWBA;  in ath_tdma_bintvalsetup()
229  * Max 802.11 overhead.  This assumes no 4-address frames and
245  * timers and enable SWBA if we are slot 0.  Otherwise
246  * we wait for slot 0 to arrive so we can sync up before
252 	struct ath_hal *ah = sc->sc_ah;  in ath_tdma_config()
253 	struct ieee80211com *ic = &sc->sc_ic;  in ath_tdma_config()
259 		vap = TAILQ_FIRST(&ic->ic_vaps);   /* XXX */  in ath_tdma_config()
261 			device_printf(sc->sc_dev, "%s: no vaps?\n", __func__);  in ath_tdma_config()
266 	tp = vap->iv_bss->ni_txparms;  in ath_tdma_config()
268 	 * Calculate the guard time for each slot.  This is the  in ath_tdma_config()
269 	 * time to send a maximal-size frame according to the  in ath_tdma_config()
275 	tdma = vap->iv_tdma;  in ath_tdma_config()
276 	if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)  in ath_tdma_config()
277 		rix = ath_tx_findrix(sc, tp->ucastrate);  in ath_tdma_config()
279 		rix = ath_tx_findrix(sc, tp->mcastrate);  in ath_tdma_config()
285 	if (sc->sc_hasenforcetxop) {  in ath_tdma_config()
286 		sc->sc_tdmaguard = 0;  in ath_tdma_config()
289 		/* XXX non-11n rate assumed */  in ath_tdma_config()
290 		sc->sc_tdmaguard = ath_hal_computetxtime(ah, sc->sc_currates,  in ath_tdma_config()
291 		    if_getmtu(vap->iv_ifp) + IEEE80211_MAXOVERHEAD, rix, AH_TRUE,  in ath_tdma_config()
298 	if (sc->sc_setcca)  in ath_tdma_config()
301 	ath_tdma_settimers(sc, sc->sc_tdmabintval,  in ath_tdma_config()
302 		sc->sc_tdmabintval | HAL_BEACON_RESET_TSF);  in ath_tdma_config()
303 	sc->sc_syncbeacon = 0;  in ath_tdma_config()
305 	sc->sc_avgtsfdeltap = TDMA_DUMMY_MARKER;  in ath_tdma_config()
306 	sc->sc_avgtsfdeltam = TDMA_DUMMY_MARKER;  in ath_tdma_config()
308 	ath_hal_intrset(ah, sc->sc_imask);  in ath_tdma_config()
310 	DPRINTF(sc, ATH_DEBUG_TDMA, "%s: slot %u len %uus cnt %u "  in ath_tdma_config()
312 	    tdma->tdma_slot, tdma->tdma_slotlen, tdma->tdma_slotcnt,  in ath_tdma_config()
313 	    tdma->tdma_bintval, sc->sc_tdmaguard, sc->sc_tdmabintval,  in ath_tdma_config()
314 	    sc->sc_tdmadbaprep);  in ath_tdma_config()
317 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_CONFIG)) {  in ath_tdma_config()
320 		t.tdma_slot = htobe32(tdma->tdma_slot);  in ath_tdma_config()
321 		t.tdma_slotlen = htobe32(tdma->tdma_slotlen);  in ath_tdma_config()
322 		t.tdma_slotcnt = htobe32(tdma->tdma_slotcnt);  in ath_tdma_config()
323 		t.tdma_bintval = htobe32(tdma->tdma_bintval);  in ath_tdma_config()
324 		t.tdma_guard = htobe32(sc->sc_tdmaguard);  in ath_tdma_config()
325 		t.tdma_scbintval = htobe32(sc->sc_tdmabintval);  in ath_tdma_config()
326 		t.tdma_dbaprep = htobe32(sc->sc_tdmadbaprep);  in ath_tdma_config()
328 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TIMER_CONFIG,  in ath_tdma_config()
337  * in the slot immediately preceding us in the bss.  Use
350  * into the timers wrap at (2^31)-1 TSF, all the various terms
360 	struct ieee80211vap *vap = ni->ni_vap;  in ath_tdma_update()
361 	struct ieee80211com *ic = ni->ni_ic;  in ath_tdma_update()
362 	struct ath_softc *sc = ic->ic_softc;  in ath_tdma_update()
363 	struct ath_hal *ah = sc->sc_ah;  in ath_tdma_update()
364 	const HAL_RATE_TABLE *rt = sc->sc_currates;  in ath_tdma_update()
371 	sc->sc_stats.ast_tdma_update++;  in ath_tdma_update()
377 		const struct ieee80211_tdma_state *ts = vap->iv_tdma;  in ath_tdma_update()
384 		    "%s: adopt slot %u slotcnt %u slotlen %u us "  in ath_tdma_update()
386 		    ts->tdma_slot, ts->tdma_slotcnt, ts->tdma_slotlen,  in ath_tdma_update()
387 		    sc->sc_tdmabintval);  in ath_tdma_update()
390 		ath_hal_intrset(ah, sc->sc_imask);  in ath_tdma_update()
395 	rs = sc->sc_lastrs;  in ath_tdma_update()
397 	rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);  in ath_tdma_update()
401 	 * to the host).  To find the start of our next slot we  in ath_tdma_update()
402 	 * must adjust this time by the time required to send  in ath_tdma_update()
405 	rix = rt->rateCodeToIndex[rs->rs_rate];  in ath_tdma_update()
411 	 * For 11n non-aggregate frames, we also need the channel  in ath_tdma_update()
426 	 * For ath_hal_pkt_txtime() - for 11n rates, shortPreamble is  in ath_tdma_update()
430 	txtime = ath_hal_pkt_txtime(ah, rt, rs->rs_datalen,  in ath_tdma_update()
432 	    !! (rs->rs_flags & HAL_RX_2040),  in ath_tdma_update()
434 	      (! (rs->rs_flags & HAL_RX_GI)) : rt->info[rix].shortPreamble,  in ath_tdma_update()
437 	nextslot = (rstamp - txtime) + (sc->sc_tdmabintval << 9);  in ath_tdma_update()
454 	 * but the prr-11n NICs are in TU.  The HAL shifts them  in ath_tdma_update()
457 	 * + The TU->TSF values have 0's for the low 9 bits, and  in ath_tdma_update()
459 	 *   the pre-11n NICs, but not for the 11n NICs.  in ath_tdma_update()
476 	tsfdelta = (int32_t)((nextslot % TU_TO_TSF(HAL_BEACON_PERIOD + 1)) - nexttbtt);  in ath_tdma_update()
479 	    "rs->rstamp %llu rstamp %llu tsf %llu txtime %d, nextslot %llu, "  in ath_tdma_update()
481 	    (unsigned long long) rs->rs_tstamp,  in ath_tdma_update()
488 	    (unsigned long long) le64toh(ni->ni_tstamp.tsf),  in ath_tdma_update()
489 	    (unsigned long long) le64toh(ni->ni_tstamp.tsf));  in ath_tdma_update()
492 	    "nexttbtt %llu (0x%08llx) tsfdelta %d avg +%d/-%d\n",  in ath_tdma_update()
496 	    TDMA_AVG(sc->sc_avgtsfdeltap), TDMA_AVG(sc->sc_avgtsfdeltam));  in ath_tdma_update()
499 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);  in ath_tdma_update()
500 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, -tsfdelta);  in ath_tdma_update()
501 		tsfdelta = -tsfdelta % 1024;  in ath_tdma_update()
504 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, tsfdelta);  in ath_tdma_update()
505 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);  in ath_tdma_update()
506 		tsfdelta = 1024 - (tsfdelta % 1024);  in ath_tdma_update()
509 		TDMA_SAMPLE(sc->sc_avgtsfdeltap, 0);  in ath_tdma_update()
510 		TDMA_SAMPLE(sc->sc_avgtsfdeltam, 0);  in ath_tdma_update()
512 	tudelta = nextslottu - TSF_TO_TU(nexttbtt_full >> 32, nexttbtt_full);  in ath_tdma_update()
515 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_BEACON_STATE)) {  in ath_tdma_update()
518 		t.beacon_tsf = htobe64(le64toh(ni->ni_tstamp.tsf));  in ath_tdma_update()
523 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_BEACON_STATE,  in ath_tdma_update()
527 	if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_TDMA_SLOT_CALC)) {  in ath_tdma_update()
533 		t.avg_plus = htobe32(TDMA_AVG(sc->sc_avgtsfdeltap));  in ath_tdma_update()
534 		t.avg_minus = htobe32(TDMA_AVG(sc->sc_avgtsfdeltam));  in ath_tdma_update()
536 		if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_SLOT_CALC,  in ath_tdma_update()
543 	 * calculate roundtrip time.  We submit a beacon frame  in ath_tdma_update()
550 	 *     slot position changes) because ieee80211_add_tdma  in ath_tdma_update()
553 	memcpy(vap->iv_bcn_off.bo_tdma +  in ath_tdma_update()
555 		&ni->ni_tstamp.data, 8);  in ath_tdma_update()
560 	    (int)(nextslot - tsf), tsfdelta, nextslottu, nexttbtt, tudelta);  in ath_tdma_update()
569 	if (tudelta != 0 && (tudelta > 0 || -tudelta < sc->sc_tdmabintval)) {  in ath_tdma_update()
574 		    sc->sc_tdmabintval);  in ath_tdma_update()
575 		ath_tdma_settimers(sc, nextslottu, sc->sc_tdmabintval);  in ath_tdma_update()
576 		sc->sc_stats.ast_tdma_timers++;  in ath_tdma_update()
591 		if (if_ath_alq_checkdebug(&sc->sc_alq,  in ath_tdma_update()
598 			if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TDMA_TSF_ADJUST,  in ath_tdma_update()
602 		sc->sc_stats.ast_tdma_tsf++;  in ath_tdma_update()
616 	struct ath_hal *ah = sc->sc_ah;  in ath_tdma_beacon_send()
627 	if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {  in ath_tdma_beacon_send()
628 		sc->sc_bmisscount++;  in ath_tdma_beacon_send()
631 			__func__, sc->sc_bmisscount);  in ath_tdma_beacon_send()
632 		if (sc->sc_bmisscount >= ath_bstuck_threshold)  in ath_tdma_beacon_send()
633 			taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);  in ath_tdma_beacon_send()
636 	if (sc->sc_bmisscount != 0) {  in ath_tdma_beacon_send()
639 			__func__, sc->sc_bmisscount);  in ath_tdma_beacon_send()
640 		sc->sc_bmisscount = 0;  in ath_tdma_beacon_send()
644 	 * Check recent per-antenna transmit statistics and flip  in ath_tdma_beacon_send()
646 	 * on the non-default antenna.  in ath_tdma_beacon_send()
649 	if (!sc->sc_diversity) {  in ath_tdma_beacon_send()
650 		otherant = sc->sc_defant & 1 ? 2 : 1;  in ath_tdma_beacon_send()
651 		if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)  in ath_tdma_beacon_send()
653 		sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;  in ath_tdma_beacon_send()
658 	ATH_TXQ_LOCK(sc->sc_cabq);  in ath_tdma_beacon_send()
660 	ATH_TXQ_UNLOCK(sc->sc_cabq);  in ath_tdma_beacon_send()
668 		if ((! sc->sc_isedma) &&  in ath_tdma_beacon_send()
669 		    (! ath_hal_stoptxdma(ah, sc->sc_bhalq))) {  in ath_tdma_beacon_send()
672 				__func__, sc->sc_bhalq);  in ath_tdma_beacon_send()
675 		ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);  in ath_tdma_beacon_send()
676 		ath_hal_txstart(ah, sc->sc_bhalq);  in ath_tdma_beacon_send()
678 		sc->sc_stats.ast_be_xmit++;		/* XXX per-vap? */  in ath_tdma_beacon_send()
682 		 * in arbitrating slot collisions.  in ath_tdma_beacon_send()
685 		vap->iv_bss->ni_tstamp.tsf = ath_hal_gettsf64(ah);  in ath_tdma_beacon_send()