Lines Matching refs:ah
49 ar9285_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset) in ar9285_hw_pa_cal() argument
65 if (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL) == in ar9285_hw_pa_cal()
69 HALDEBUG(ah, HAL_DEBUG_PERCAL, "Running PA Calibration\n"); in ar9285_hw_pa_cal()
72 regList[i][1] = OS_REG_READ(ah, regList[i][0]); in ar9285_hw_pa_cal()
74 regVal = OS_REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
76 OS_REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
77 regVal = OS_REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
79 OS_REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
81 OS_REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1); in ar9285_hw_pa_cal()
82 OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1); in ar9285_hw_pa_cal()
83 OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1); in ar9285_hw_pa_cal()
84 OS_REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1); in ar9285_hw_pa_cal()
85 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0); in ar9285_hw_pa_cal()
86 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0); in ar9285_hw_pa_cal()
87 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0); in ar9285_hw_pa_cal()
88 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0); in ar9285_hw_pa_cal()
89 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0); in ar9285_hw_pa_cal()
90 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); in ar9285_hw_pa_cal()
91 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); in ar9285_hw_pa_cal()
92 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); in ar9285_hw_pa_cal()
93 ccomp_org = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); in ar9285_hw_pa_cal()
94 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf); in ar9285_hw_pa_cal()
96 OS_REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9285_hw_pa_cal()
98 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0); in ar9285_hw_pa_cal()
99 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0); in ar9285_hw_pa_cal()
102 regVal = OS_REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
104 OS_REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
106 regVal = OS_REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
108 reg_field = MS(OS_REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); in ar9285_hw_pa_cal()
110 OS_REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
113 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1); in ar9285_hw_pa_cal()
115 reg_field = MS(OS_REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); in ar9285_hw_pa_cal()
116 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field); in ar9285_hw_pa_cal()
117 offs_6_1 = MS(OS_REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); in ar9285_hw_pa_cal()
118 offs_0 = MS(OS_REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); in ar9285_hw_pa_cal()
125 if ((!is_reset) && (AH9285(ah)->pacal_info.prev_offset == offset)) { in ar9285_hw_pa_cal()
126 if (AH9285(ah)->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT) in ar9285_hw_pa_cal()
127 AH9285(ah)->pacal_info.max_skipcount = in ar9285_hw_pa_cal()
128 2 * AH9285(ah)->pacal_info.max_skipcount; in ar9285_hw_pa_cal()
129 AH9285(ah)->pacal_info.skipcount = AH9285(ah)->pacal_info.max_skipcount; in ar9285_hw_pa_cal()
131 AH9285(ah)->pacal_info.max_skipcount = 1; in ar9285_hw_pa_cal()
132 AH9285(ah)->pacal_info.skipcount = 0; in ar9285_hw_pa_cal()
133 AH9285(ah)->pacal_info.prev_offset = offset; in ar9285_hw_pa_cal()
136 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1); in ar9285_hw_pa_cal()
137 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0); in ar9285_hw_pa_cal()
139 regVal = OS_REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
141 OS_REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
142 regVal = OS_REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
144 OS_REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
147 OS_REG_WRITE(ah, regList[i][0], regList[i][1]); in ar9285_hw_pa_cal()
149 OS_REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org); in ar9285_hw_pa_cal()
153 ar9002_hw_pa_cal(struct ath_hal *ah, HAL_BOOL is_reset) in ar9002_hw_pa_cal() argument
155 if (AR_SREV_KITE_11_OR_LATER(ah)) { in ar9002_hw_pa_cal()
156 if (is_reset || !AH9285(ah)->pacal_info.skipcount) in ar9002_hw_pa_cal()
157 ar9285_hw_pa_cal(ah, is_reset); in ar9002_hw_pa_cal()
159 AH9285(ah)->pacal_info.skipcount--; in ar9002_hw_pa_cal()
165 ar9285_hw_cl_cal(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar9285_hw_cl_cal() argument
167 OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
169 OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
170 OS_REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
171 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
173 OS_REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
174 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
175 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
177 HALDEBUG(ah, HAL_DEBUG_PERCAL, in ar9285_hw_cl_cal()
181 OS_REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
182 OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
183 OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
185 OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
186 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
187 OS_REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
188 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
189 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, in ar9285_hw_cl_cal()
191 HALDEBUG(ah, HAL_DEBUG_PERCAL, in ar9285_hw_cl_cal()
196 OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
197 OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
198 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
204 ar9285_hw_clc(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar9285_hw_clc() argument
216 if (!(ar9285_hw_cl_cal(ah, chan))) in ar9285_hw_clc()
219 txgain_max = MS(OS_REG_READ(ah, AR_PHY_TX_PWRCTRL7), in ar9285_hw_clc()
223 clc_gain = (OS_REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) & in ar9285_hw_clc()
232 reg_clc_I0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) in ar9285_hw_clc()
234 reg_clc_Q0 = (OS_REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) in ar9285_hw_clc()
244 reg_rf2g5_org = OS_REG_READ(ah, AR9285_RF2G5); in ar9285_hw_clc()
245 if (AR_SREV_9285E_20(ah)) { in ar9285_hw_clc()
246 OS_REG_WRITE(ah, AR9285_RF2G5, in ar9285_hw_clc()
250 OS_REG_WRITE(ah, AR9285_RF2G5, in ar9285_hw_clc()
254 retv = ar9285_hw_cl_cal(ah, chan); in ar9285_hw_clc()
255 OS_REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org); in ar9285_hw_clc()
261 ar9285InitCalHardware(struct ath_hal *ah, in ar9285InitCalHardware() argument
264 if (AR_SREV_KITE(ah) && AR_SREV_KITE_10_OR_LATER(ah) && in ar9285InitCalHardware()
265 (! ar9285_hw_clc(ah, chan))) in ar9285InitCalHardware()