Lines Matching refs:ah
42 static void ar5416InitDMA(struct ath_hal *ah);
43 static void ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *);
44 static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode);
45 static void ar5416InitQoS(struct ath_hal *ah);
46 static void ar5416InitUserSettings(struct ath_hal *ah);
47 static void ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *);
54 static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah);
55 static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type);
56 static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah,
62 static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan);
63 static void ar5416MarkPhyInactive(struct ath_hal *ah);
64 static void ar5416SetIFSTiming(struct ath_hal *ah,
76 ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, in ar5416Reset() argument
84 struct ath_hal_5212 *ahp = AH5212(ah); in ar5416Reset()
95 OS_MARK(ah, AH_MARK_RESET, bChannelChange); in ar5416Reset()
98 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { in ar5416Reset()
99 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", in ar5416Reset()
107 ichan = ath_hal_checkchannel(ah, chan); in ar5416Reset()
117 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", in ar5416Reset()
122 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); in ar5416Reset()
125 ath_hal_survey_clear(ah); in ar5416Reset()
133 rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR); in ar5416Reset()
141 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); in ar5416Reset()
155 if ((! AR_SREV_KITE(ah)) && saveDefAntenna == 0) /* XXX magic constants */ in ar5416Reset()
159 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & in ar5416Reset()
163 saveLedState = OS_REG_READ(ah, AR_MAC_LED) & in ar5416Reset()
168 if (AR_SREV_HOWL(ah) || in ar5416Reset()
169 (AR_SREV_MERLIN(ah) && in ar5416Reset()
170 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) || in ar5416Reset()
173 (ah->ah_config.ah_force_full_reset)) in ar5416Reset()
174 tsf = ar5416GetTsf64(ah); in ar5416Reset()
177 ar5416MarkPhyInactive(ah); in ar5416Reset()
179 if (!ar5416ChipReset(ah, chan, resetType)) { in ar5416Reset()
180 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); in ar5416Reset()
186 ar5416SetTsf64(ah, tsf); in ar5416Reset()
188 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); in ar5416Reset()
189 if (AR_SREV_MERLIN_10_OR_LATER(ah)) in ar5416Reset()
190 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ar5416Reset()
192 AH5416(ah)->ah_writeIni(ah, chan); in ar5416Reset()
194 if(AR_SREV_KIWI_13_OR_LATER(ah) ) { in ar5416Reset()
196 OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar5416Reset()
198 OS_REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); in ar5416Reset()
199 OS_REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar5416Reset()
201 OS_REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar5416Reset()
206 ar5416OverrideIni(ah, chan); in ar5416Reset()
209 ar5416Set11nRegs(ah, chan); in ar5416Reset()
211 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); in ar5416Reset()
219 if (AR_SREV_HOWL(ah) && (ar5416GetTsf64(ah) < tsf)) { in ar5416Reset()
221 ar5416SetTsf64(ah, tsf); in ar5416Reset()
224 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n", in ar5416Reset()
225 __func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK)); in ar5416Reset()
226 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n", in ar5416Reset()
227 __func__, OS_REG_READ(ah,AR_PHY_ADC_CTL)); in ar5416Reset()
233 ar5416InitChainMasks(ah); in ar5416Reset()
236 if (ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { in ar5416Reset()
237 AH5416(ah)->ah_olcInit(ah); in ar5416Reset()
238 AH5416(ah)->ah_olcTempCompensation(ah); in ar5416Reset()
242 if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) { in ar5416Reset()
243 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5416Reset()
249 if (!ahp->ah_rfHal->setRfRegs(ah, chan, in ar5416Reset()
251 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5416Reset()
258 ar5416SetDeltaSlope(ah, chan); in ar5416Reset()
260 AH5416(ah)->ah_spurMitigate(ah, chan); in ar5416Reset()
263 if (!ah->ah_setBoardValues(ah, chan)) { in ar5416Reset()
264 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5416Reset()
269 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); in ar5416Reset()
271 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); in ar5416Reset()
272 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) in ar5416Reset()
277 ar5212SetOperatingMode(ah, opmode); in ar5416Reset()
280 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); in ar5416Reset()
281 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); in ar5416Reset()
284 if (AR_SREV_HOWL(ah)) in ar5416Reset()
285 OS_REG_WRITE(ah, AR_MAC_LED, in ar5416Reset()
288 OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | in ar5416Reset()
293 if (AR_SREV_KIWI(ah)) in ar5416Reset()
294 ar5416StartTsf2(ah); in ar5416Reset()
300 if (AH5416(ah)->ah_btCoexConfigType != HAL_BT_COEX_CFG_NONE) in ar5416Reset()
301 ar5416InitBTCoex(ah); in ar5416Reset()
304 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ar5416Reset()
307 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); in ar5416Reset()
308 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | in ar5416Reset()
312 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); in ar5416Reset()
314 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ in ar5416Reset()
317 OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg); in ar5416Reset()
319 if (!ar5212SetChannel(ah, chan)) in ar5416Reset()
322 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); in ar5416Reset()
326 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ar5416Reset()
329 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) in ar5416Reset()
330 ah->ah_resetTxQueue(ah, i); in ar5416Reset()
332 ar5416InitIMR(ah, opmode); in ar5416Reset()
333 ar5416SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); in ar5416Reset()
334 ar5416InitQoS(ah); in ar5416Reset()
336 ar5416InitUserSettings(ah); in ar5416Reset()
340 ar5416SetIFSTiming(ah, chan); in ar5416Reset()
347 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, in ar5416Reset()
353 if (AR_SREV_KIWI_13_OR_LATER(ah)) {
364 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
366 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
368 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
371 OS_REG_WRITE(ah, AR_TIME_OUT,
373 OS_REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
375 OS_REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
377 OS_REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
381 if (AR_SREV_KIWI_13_OR_LATER(ah)) {
383 OS_REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
390 OS_REG_WRITE(ah, AR_STA_ID1,
391 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
393 ar5416InitDMA(ah);
398 OS_REG_WRITE(ah, AR_OBS, 8);
403 OS_REG_WRITE(ah, AR_MIRT, 0);
425 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 250);
426 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 700);
428 ar5416InitBB(ah, chan);
431 ar5212SetCompRegs(ah); /* XXX not needed? */
443 OS_REG_WRITE(ah, AR_TPC, powerVal);
445 if (!ar5416InitCal(ah, chan))
448 ar5416RestoreChainMask(ah);
450 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
455 if (AR_SREV_HOWL(ah)) {
463 reg = (OS_REG_READ(ah, AR_STA_ID1) | (1<<22));
464 OS_REG_WRITE(ah,AR_STA_ID1, reg);
465 ath_hal_printf(ah, "MBSSID Set bit 22 of AR_STA_ID 0x%x\n", reg);
468 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
470 OS_MARK(ah, AH_MARK_RESET_DONE, 0);
474 OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
490 ar5416ChannelChange(struct ath_hal *ah, const structu ieee80211_channel *chan)
495 struct ath_hal_5212 *ahp = AH5212(ah);
501 ichan = ath_hal_checkchannel(ah, chan);
504 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) {
505 if (ar5212NumTxPending(ah, qnum)) {
506 HALDEBUG(ah, HAL_DEBUG_ANY,
515 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST);
516 if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) {
517 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n",
522 ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */
525 if (!ar5212SetChannel(ah, chan))
529 if (!ah->ah_setTxPower(ah, chan, rfXpdGain)) {
530 HALDEBUG(ah, HAL_DEBUG_ANY,
540 data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
550 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
554 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3);
555 ar5212SetSpurMitigation(ah, chan);
556 ar5416SetDeltaSlope(ah, chan);
565 ichan->tsf_last = ar5416GetTsf64(ah);
566 ar5212TxEnable(ah, AH_TRUE);
572 ar5416InitDMA(struct ath_hal *ah) in ar5416InitDMA() argument
574 struct ath_hal_5212 *ahp = AH5212(ah); in ar5416InitDMA()
579 OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); in ar5416InitDMA()
584 OS_REG_WRITE(ah, AR_TXCFG, in ar5416InitDMA()
585 (OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B); in ar5416InitDMA()
594 OS_REG_WRITE(ah, AR_RXCFG, in ar5416InitDMA()
595 (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B); in ar5416InitDMA()
598 OS_REG_WRITE(ah, AR_TXCFG, in ar5416InitDMA()
599 (OS_REG_READ(ah, AR_TXCFG) &~ AR_FTRIG) | in ar5416InitDMA()
605 OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ar5416InitDMA()
611 if (AR_SREV_KITE(ah)) in ar5416InitDMA()
617 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); in ar5416InitDMA()
619 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE); in ar5416InitDMA()
623 ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar5416InitBB() argument
632 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5416InitBB()
640 HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n", in ar5416InitBB()
644 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar5416InitBB()
662 ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode) in ar5416InitIMR() argument
664 struct ath_hal_5212 *ahp = AH5212(ah); in ar5416InitIMR()
685 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); in ar5416InitIMR()
689 if (! AR_SREV_HOWL(ah)) { in ar5416InitIMR()
690 OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); in ar5416InitIMR()
691 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); in ar5416InitIMR()
692 OS_REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); in ar5416InitIMR()
698 OS_REG_WRITE(ah, AR_IMR_S2, in ar5416InitIMR()
699 OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST); in ar5416InitIMR()
704 ar5416InitQoS(struct ath_hal *ah) in ar5416InitQoS() argument
707 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ in ar5416InitQoS()
708 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ in ar5416InitQoS()
711 OS_REG_WRITE(ah, AR_NOACK, in ar5416InitQoS()
719 OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); in ar5416InitQoS()
720 OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ar5416InitQoS()
721 OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ar5416InitQoS()
722 OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ar5416InitQoS()
723 OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ar5416InitQoS()
727 ar5416InitUserSettings(struct ath_hal *ah) in ar5416InitUserSettings() argument
729 struct ath_hal_5212 *ahp = AH5212(ah); in ar5416InitUserSettings()
733 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) in ar5416InitUserSettings()
736 ar5212SetSifsTime(ah, ahp->ah_sifstime); in ar5416InitUserSettings()
738 ar5212SetSlotTime(ah, ahp->ah_slottime); in ar5416InitUserSettings()
740 ar5212SetAckTimeout(ah, ahp->ah_acktimeout); in ar5416InitUserSettings()
742 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); in ar5416InitUserSettings()
743 if (AH_PRIVATE(ah)->ah_diagreg != 0) in ar5416InitUserSettings()
744 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); in ar5416InitUserSettings()
745 if (AH5416(ah)->ah_globaltxtimeout != (u_int) -1) in ar5416InitUserSettings()
746 ar5416SetGlobalTxTimeout(ah, AH5416(ah)->ah_globaltxtimeout); in ar5416InitUserSettings()
750 ar5416SetRfMode(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar5416SetRfMode() argument
761 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { in ar5416SetRfMode()
765 } else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) { in ar5416SetRfMode()
770 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar5416SetRfMode()
777 ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan, in ar5416ChipReset() argument
780 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); in ar5416ChipReset()
784 if (AR_SREV_MERLIN(ah) && in ar5416ChipReset()
785 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { in ar5416ChipReset()
786 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) in ar5416ChipReset()
788 } else if (ah->ah_config.ah_force_full_reset) { in ar5416ChipReset()
789 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) in ar5416ChipReset()
793 HALDEBUG(ah, HAL_DEBUG_RESET, in ar5416ChipReset()
796 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) in ar5416ChipReset()
799 if (!ar5416SetResetReg(ah, HAL_RESET_WARM)) in ar5416ChipReset()
804 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) in ar5416ChipReset()
811 AH5416(ah)->ah_initPLL(ah, chan); in ar5416ChipReset()
819 ar5416SetRfMode(ah, chan); in ar5416ChipReset()
829 ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled, in ar5416GetDeltaSlopeValues() argument
858 ar5416SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar5416SetDeltaSlope() argument
880 ar5416GetChannelCenters(ah, chan, ¢ers); in ar5416SetDeltaSlope()
883 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); in ar5416SetDeltaSlope()
885 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar5416SetDeltaSlope()
887 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar5416SetDeltaSlope()
896 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); in ar5416SetDeltaSlope()
899 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ar5416SetDeltaSlope()
901 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, in ar5416SetDeltaSlope()
913 ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) in ar5416SetTxPowerLimit() argument
917 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); in ar5416SetTxPowerLimit()
918 return ah->ah_setTxPower(ah, AH_PRIVATE(ah)->ah_curchan, in ar5416SetTxPowerLimit()
923 ar5416GetChipPowerLimits(struct ath_hal *ah, in ar5416GetChipPowerLimits() argument
926 struct ath_hal_5212 *ahp = AH5212(ah); in ar5416GetChipPowerLimits()
932 if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { in ar5416GetChipPowerLimits()
937 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5416GetChipPowerLimits()
943 HALDEBUG(ah, HAL_DEBUG_RESET, in ar5416GetChipPowerLimits()
964 ar5416WriteTxPowerRateRegisters(struct ath_hal *ah, in ar5416WriteTxPowerRateRegisters() argument
970 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, in ar5416WriteTxPowerRateRegisters()
976 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, in ar5416WriteTxPowerRateRegisters()
985 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ar5416WriteTxPowerRateRegisters()
991 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, in ar5416WriteTxPowerRateRegisters()
997 HALDEBUG(ah, HAL_DEBUG_RESET, in ar5416WriteTxPowerRateRegisters()
999 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), in ar5416WriteTxPowerRateRegisters()
1000 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); in ar5416WriteTxPowerRateRegisters()
1004 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, in ar5416WriteTxPowerRateRegisters()
1010 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, in ar5416WriteTxPowerRateRegisters()
1019 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, in ar5416WriteTxPowerRateRegisters()
1025 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, in ar5416WriteTxPowerRateRegisters()
1032 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, in ar5416WriteTxPowerRateRegisters()
1044 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER | in ar5416WriteTxPowerRateRegisters()
1045 (AH5212(ah)->ah_tpcEnabled ? AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE : 0)); in ar5416WriteTxPowerRateRegisters()
1056 ar5416SetTransmitPower(struct ath_hal *ah, in ar5416SetTransmitPower() argument
1063 struct ath_hal_5212 *ahp = AH5212(ah); in ar5416SetTransmitPower()
1072 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; in ar5416SetTransmitPower()
1075 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); in ar5416SetTransmitPower()
1080 AH5416(ah)->ah_ht40PowerIncForPdadc = 2; in ar5416SetTransmitPower()
1083 OS_MEMZERO(AH5416(ah)->ah_ratesArray, sizeof(AH5416(ah)->ah_ratesArray)); in ar5416SetTransmitPower()
1084 cfgCtl = ath_hal_getctl(ah, chan); in ar5416SetTransmitPower()
1087 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); in ar5416SetTransmitPower()
1089 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", in ar5416SetTransmitPower()
1092 if (IS_EEP_MINOR_V2(ah)) { in ar5416SetTransmitPower()
1093 AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; in ar5416SetTransmitPower()
1096 if (!ar5416SetPowerPerRateTable(ah, pEepData, chan, in ar5416SetTransmitPower()
1097 &AH5416(ah)->ah_ratesArray[0], in ar5416SetTransmitPower()
1101 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5416SetTransmitPower()
1106 if (!AH5416(ah)->ah_setPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { in ar5416SetTransmitPower()
1107 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", in ar5416SetTransmitPower()
1112 maxPower = AH_MAX(AH5416(ah)->ah_ratesArray[rate6mb], in ar5416SetTransmitPower()
1113 AH5416(ah)->ah_ratesArray[rateHt20_0]); in ar5416SetTransmitPower()
1116 maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rate1l]); in ar5416SetTransmitPower()
1120 maxPower = AH_MAX(maxPower, AH5416(ah)->ah_ratesArray[rateHt40_0]); in ar5416SetTransmitPower()
1124 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; in ar5416SetTransmitPower()
1131 for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) { in ar5416SetTransmitPower()
1132 AH5416(ah)->ah_ratesArray[i] = in ar5416SetTransmitPower()
1133 (int16_t)(txPowerIndexOffset + AH5416(ah)->ah_ratesArray[i]); in ar5416SetTransmitPower()
1134 if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER) in ar5416SetTransmitPower()
1135 AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER; in ar5416SetTransmitPower()
1146 ar5416PrintPowerPerRate(ah, AH5416(ah)->ah_ratesArray); in ar5416SetTransmitPower()
1155 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { in ar5416SetTransmitPower()
1158 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, in ar5416SetTransmitPower()
1162 for (i = 0; i < N(AH5416(ah)->ah_ratesArray); i++) { in ar5416SetTransmitPower()
1167 AH5416(ah)->ah_ratesArray[i] -= (pwr_table_offset * 2); in ar5416SetTransmitPower()
1168 if (AH5416(ah)->ah_ratesArray[i] < 0) in ar5416SetTransmitPower()
1169 AH5416(ah)->ah_ratesArray[i] = 0; in ar5416SetTransmitPower()
1170 else if (AH5416(ah)->ah_ratesArray[i] > AR5416_MAX_RATE_POWER) in ar5416SetTransmitPower()
1171 AH5416(ah)->ah_ratesArray[i] = AR5416_MAX_RATE_POWER; in ar5416SetTransmitPower()
1189 if (AR_SREV_MERLIN_20_OR_LATER(ah) && in ar5416SetTransmitPower()
1190 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { in ar5416SetTransmitPower()
1198 AH5416(ah)->ah_ratesArray[adj[i]] -= cck_ofdm_delta; in ar5416SetTransmitPower()
1199 if (AH5416(ah)->ah_ratesArray[adj[i]] < 0) in ar5416SetTransmitPower()
1200 AH5416(ah)->ah_ratesArray[adj[i]] = 0; in ar5416SetTransmitPower()
1212 AH5416(ah)->ah_ratesArray[rateHt40_0] += in ar5416SetTransmitPower()
1213 AH5416(ah)->ah_ht40PowerIncForPdadc; in ar5416SetTransmitPower()
1214 AH5416(ah)->ah_ratesArray[rateHt40_1] += in ar5416SetTransmitPower()
1215 AH5416(ah)->ah_ht40PowerIncForPdadc; in ar5416SetTransmitPower()
1216 AH5416(ah)->ah_ratesArray[rateHt40_2] += AH5416(ah)->ah_ht40PowerIncForPdadc; in ar5416SetTransmitPower()
1217 AH5416(ah)->ah_ratesArray[rateHt40_3] += AH5416(ah)->ah_ht40PowerIncForPdadc; in ar5416SetTransmitPower()
1218 AH5416(ah)->ah_ratesArray[rateHt40_4] += AH5416(ah)->ah_ht40PowerIncForPdadc; in ar5416SetTransmitPower()
1219 AH5416(ah)->ah_ratesArray[rateHt40_5] += AH5416(ah)->ah_ht40PowerIncForPdadc; in ar5416SetTransmitPower()
1220 AH5416(ah)->ah_ratesArray[rateHt40_6] += AH5416(ah)->ah_ht40PowerIncForPdadc; in ar5416SetTransmitPower()
1221 AH5416(ah)->ah_ratesArray[rateHt40_7] += AH5416(ah)->ah_ht40PowerIncForPdadc; in ar5416SetTransmitPower()
1225 ar5416WriteTxPowerRateRegisters(ah, chan, AH5416(ah)->ah_ratesArray); in ar5416SetTransmitPower()
1228 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, in ar5416SetTransmitPower()
1242 ar5416GetRfgain(struct ath_hal *ah) in ar5416GetRfgain() argument
1252 ar5416Disable(struct ath_hal *ah) in ar5416Disable() argument
1255 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) in ar5416Disable()
1257 if (! ar5416SetResetReg(ah, HAL_RESET_COLD)) in ar5416Disable()
1260 AH5416(ah)->ah_initPLL(ah, AH_NULL); in ar5416Disable()
1271 ar5416PhyDisable(struct ath_hal *ah) in ar5416PhyDisable() argument
1274 if (! ar5416SetResetReg(ah, HAL_RESET_WARM)) in ar5416PhyDisable()
1277 AH5416(ah)->ah_initPLL(ah, AH_NULL); in ar5416PhyDisable()
1285 ar5416SetResetReg(struct ath_hal *ah, uint32_t type) in ar5416SetResetReg() argument
1290 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ar5416SetResetReg()
1295 return ar5416SetResetPowerOn(ah); in ar5416SetResetReg()
1298 return ar5416SetReset(ah, type); in ar5416SetResetReg()
1306 ar5416SetResetPowerOn(struct ath_hal *ah) in ar5416SetResetPowerOn() argument
1319 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ar5416SetResetPowerOn()
1327 if (! AR_SREV_HOWL(ah)) in ar5416SetResetPowerOn()
1328 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); in ar5416SetResetPowerOn()
1332 OS_REG_WRITE(ah, AR_RTC_RESET, 0); in ar5416SetResetPowerOn()
1335 if (! AR_SREV_HOWL(ah)) in ar5416SetResetPowerOn()
1336 OS_REG_WRITE(ah, AR_RC, 0); in ar5416SetResetPowerOn()
1338 OS_REG_WRITE(ah, AR_RTC_RESET, 1); in ar5416SetResetPowerOn()
1343 if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) { in ar5416SetResetPowerOn()
1344 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n", __func__); in ar5416SetResetPowerOn()
1348 return ar5416SetReset(ah, HAL_RESET_COLD); in ar5416SetResetPowerOn()
1352 ar5416SetReset(struct ath_hal *ah, int type) in ar5416SetReset() argument
1358 if (AR_SREV_HOWL(ah)) { in ar5416SetReset()
1359 HALDEBUG(ah, HAL_DEBUG_ANY, "[ath] HOWL: Fiddling with derived clk!\n"); in ar5416SetReset()
1360 uint32_t val = OS_REG_READ(ah, AR_RTC_DERIVED_CLK); in ar5416SetReset()
1363 OS_REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); in ar5416SetReset()
1364 (void) OS_REG_READ(ah, AR_RTC_DERIVED_CLK); in ar5416SetReset()
1371 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ar5416SetReset()
1375 if (AR_SREV_HOWL(ah)) { in ar5416SetReset()
1388 tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); in ar5416SetReset()
1390 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ar5416SetReset()
1391 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF); in ar5416SetReset()
1393 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); in ar5416SetReset()
1402 OS_REG_WRITE(ah, AR_RTC_RC, rst_flags); in ar5416SetReset()
1404 if (AR_SREV_HOWL(ah)) in ar5416SetReset()
1412 OS_REG_WRITE(ah, AR_RTC_RC, 0); in ar5416SetReset()
1413 if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) { in ar5416SetReset()
1414 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n", __func__); in ar5416SetReset()
1419 if (! AR_SREV_HOWL(ah)) in ar5416SetReset()
1420 OS_REG_WRITE(ah, AR_RC, 0); in ar5416SetReset()
1422 if (AR_SREV_HOWL(ah)) in ar5416SetReset()
1425 if (AR_SREV_HOWL(ah)) { in ar5416SetReset()
1427 mask = OS_REG_READ(ah, AR_CFG); in ar5416SetReset()
1429 HALDEBUG(ah, HAL_DEBUG_RESET, in ar5416SetReset()
1434 OS_REG_WRITE(ah, AR_CFG, mask); in ar5416SetReset()
1435 HALDEBUG(ah, HAL_DEBUG_RESET, in ar5416SetReset()
1436 "Setting CFG 0x%x\n", OS_REG_READ(ah, AR_CFG)); in ar5416SetReset()
1448 HALDEBUG(ah, HAL_DEBUG_RESET, in ar5416SetReset()
1450 OS_REG_WRITE(ah, AR_CFG, mask); in ar5416SetReset()
1452 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); in ar5416SetReset()
1460 ar5416InitChainMasks(struct ath_hal *ah) in ar5416InitChainMasks() argument
1462 int rx_chainmask = AH5416(ah)->ah_rx_chainmask; in ar5416InitChainMasks()
1466 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); in ar5416InitChainMasks()
1472 if (IS_5416V1(ah) && (rx_chainmask == 0x5 || rx_chainmask == 0x3)) { in ar5416InitChainMasks()
1473 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); in ar5416InitChainMasks()
1474 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); in ar5416InitChainMasks()
1476 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask); in ar5416InitChainMasks()
1477 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask); in ar5416InitChainMasks()
1479 OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask); in ar5416InitChainMasks()
1481 if (AH5416(ah)->ah_tx_chainmask == 0x5) in ar5416InitChainMasks()
1482 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); in ar5416InitChainMasks()
1484 if (AR_SREV_HOWL(ah)) { in ar5416InitChainMasks()
1485 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, in ar5416InitChainMasks()
1486 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ar5416InitChainMasks()
1498 ar5416RestoreChainMask(struct ath_hal *ah) in ar5416RestoreChainMask() argument
1500 int rx_chainmask = AH5416(ah)->ah_rx_chainmask; in ar5416RestoreChainMask()
1502 if (IS_5416V1(ah) && (rx_chainmask == 0x5 || rx_chainmask == 0x3)) { in ar5416RestoreChainMask()
1503 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); in ar5416RestoreChainMask()
1504 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); in ar5416RestoreChainMask()
1509 ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar5416InitPLL() argument
1525 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ar5416InitPLL()
1533 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); in ar5416InitPLL()
1537 ar5416SetDefGainValues(struct ath_hal *ah, in ar5416SetDefGainValues() argument
1543 if (IS_EEP_MINOR_V3(ah)) { in ar5416SetDefGainValues()
1546 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { in ar5416SetDefGainValues()
1547 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ar5416SetDefGainValues()
1550 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ar5416SetDefGainValues()
1553 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ar5416SetDefGainValues()
1556 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ar5416SetDefGainValues()
1560 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ar5416SetDefGainValues()
1563 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ar5416SetDefGainValues()
1569 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { in ar5416SetDefGainValues()
1570 OS_REG_RMW_FIELD(ah, in ar5416SetDefGainValues()
1573 OS_REG_RMW_FIELD(ah, in ar5416SetDefGainValues()
1577 OS_REG_RMW_FIELD(ah, in ar5416SetDefGainValues()
1580 OS_REG_RMW_FIELD(ah, in ar5416SetDefGainValues()
1595 ar5416GetRegChainOffset(struct ath_hal *ah, int i) in ar5416GetRegChainOffset() argument
1599 if (AR_SREV_5416_V20_OR_LATER(ah) && in ar5416GetRegChainOffset()
1600 (AH5416(ah)->ah_rx_chainmask == 0x5 || in ar5416GetRegChainOffset()
1601 AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { in ar5416GetRegChainOffset()
1618 ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar5416SetBoardValues() argument
1620 const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; in ar5416SetBoardValues()
1626 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); in ar5416SetBoardValues()
1632 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); in ar5416SetBoardValues()
1634 if (AR_SREV_MERLIN(ah)) { in ar5416SetBoardValues()
1637 regChainOffset = ar5416GetRegChainOffset(ah, i); in ar5416SetBoardValues()
1639 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]); in ar5416SetBoardValues()
1641 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, in ar5416SetBoardValues()
1642 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) & in ar5416SetBoardValues()
1654 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) in ar5416SetBoardValues()
1655 ar5416SetDefGainValues(ah, pModal, eep, txRxAttenLocal, regChainOffset, i); in ar5416SetBoardValues()
1658 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { in ar5416SetBoardValues()
1660 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_OB, pModal->ob); in ar5416SetBoardValues()
1661 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH0, AR_AN_RF2G1_CH0_DB, pModal->db); in ar5416SetBoardValues()
1662 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_OB, pModal->ob_ch1); in ar5416SetBoardValues()
1663 OS_A_REG_RMW_FIELD(ah, AR_AN_RF2G1_CH1, AR_AN_RF2G1_CH1_DB, pModal->db_ch1); in ar5416SetBoardValues()
1665 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_OB5, pModal->ob); in ar5416SetBoardValues()
1666 OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH0, AR_AN_RF5G1_CH0_DB5, pModal->db); in ar5416SetBoardValues()
1667 … OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_OB5, pModal->ob_ch1); in ar5416SetBoardValues()
1668 … OS_A_REG_RMW_FIELD(ah, AR_AN_RF5G1_CH1, AR_AN_RF5G1_CH1_DB5, pModal->db_ch1); in ar5416SetBoardValues()
1670 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_XPABIAS_LVL, pModal->xpaBiasLvl); in ar5416SetBoardValues()
1671 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP2, AR_AN_TOP2_LOCALBIAS, in ar5416SetBoardValues()
1673 OS_A_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, in ar5416SetBoardValues()
1677 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling); in ar5416SetBoardValues()
1678 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); in ar5416SetBoardValues()
1680 if (! AR_SREV_MERLIN_10_OR_LATER(ah)) in ar5416SetBoardValues()
1681 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize); in ar5416SetBoardValues()
1683 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, in ar5416SetBoardValues()
1689 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, in ar5416SetBoardValues()
1692 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { in ar5416SetBoardValues()
1693 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, in ar5416SetBoardValues()
1695 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, in ar5416SetBoardValues()
1698 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, in ar5416SetBoardValues()
1700 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, AR_PHY_EXT_CCA_THRESH62, in ar5416SetBoardValues()
1705 if (IS_EEP_MINOR_V2(ah)) { in ar5416SetBoardValues()
1706 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, in ar5416SetBoardValues()
1708 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, in ar5416SetBoardValues()
1712 if (IS_EEP_MINOR_V3(ah) && IEEE80211_IS_CHAN_HT40(chan)) in ar5416SetBoardValues()
1714 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, in ar5416SetBoardValues()
1717 if (AR_SREV_MERLIN_20_OR_LATER(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_19) in ar5416SetBoardValues()
1718 … OS_REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, pModal->miscBits); in ar5416SetBoardValues()
1720 if (AR_SREV_MERLIN_20(ah) && EEP_MINOR(ah) >= AR5416_EEP_MINOR_VER_20) { in ar5416SetBoardValues()
1722 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, in ar5416SetBoardValues()
1725 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); in ar5416SetBoardValues()
1727 OS_A_REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, in ar5416SetBoardValues()
1732 OS_REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, in ar5416SetBoardValues()
1734 OS_REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_DESIRED_SCALE_CCK, in ar5416SetBoardValues()
1753 ar5416SetRatesArrayFromTargetPower(struct ath_hal *ah, in ar5416SetRatesArrayFromTargetPower() argument
1810 ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, in ar5416SetPowerPerRateTable() argument
1845 ar5416GetChannelCenters(ah, chan, ¢ers); in ar5416SetPowerPerRateTable()
1871 ath_hal_eepromSet(ah, in ar5416SetPowerPerRateTable()
1883 switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) { in ar5416SetPowerPerRateTable()
1904 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, in ar5416SetPowerPerRateTable()
1906 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, in ar5416SetPowerPerRateTable()
1908 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, in ar5416SetPowerPerRateTable()
1914 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, in ar5416SetPowerPerRateTable()
1917 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, in ar5416SetPowerPerRateTable()
1919 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, in ar5416SetPowerPerRateTable()
1927 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, in ar5416SetPowerPerRateTable()
1929 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20, in ar5416SetPowerPerRateTable()
1935 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40, in ar5416SetPowerPerRateTable()
1937 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, in ar5416SetPowerPerRateTable()
1972 rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], in ar5416SetPowerPerRateTable()
2024 ar5416SetRatesArrayFromTargetPower(ah, chan, ratesArray, in ar5416SetPowerPerRateTable()
2100 ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, in ar5416GetTargetPowers() argument
2111 ar5416GetChannelCenters(ah, chan, ¢ers); in ar5416GetTargetPowers()
2159 ar5416GetTargetPowersLeg(struct ath_hal *ah, in ar5416GetTargetPowersLeg() argument
2171 ar5416GetChannelCenters(ah, chan, ¢ers); in ar5416GetTargetPowersLeg()
2227 ar5416SetGainBoundariesClosedLoop(struct ath_hal *ah, int i, in ar5416SetGainBoundariesClosedLoop() argument
2232 regChainOffset = ar5416GetRegChainOffset(ah, i); in ar5416SetGainBoundariesClosedLoop()
2234 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: chain %d: gainOverlap_t2: %d," in ar5416SetGainBoundariesClosedLoop()
2238 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, in ar5416SetGainBoundariesClosedLoop()
2255 ar5416GetXpdGainValues(struct ath_hal *ah, uint16_t xpdMask, in ar5416GetXpdGainValues() argument
2286 ar5416WriteDetectorGainBiases(struct ath_hal *ah, uint16_t numXpdGain, in ar5416WriteDetectorGainBiases() argument
2289 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: numXpdGain: %d," in ar5416WriteDetectorGainBiases()
2293 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & in ar5416WriteDetectorGainBiases()
2310 ar5416WritePdadcValues(struct ath_hal *ah, int i, uint8_t pdadcValues[]) in ar5416WritePdadcValues() argument
2316 regChainOffset = ar5416GetRegChainOffset(ah, i); in ar5416WritePdadcValues()
2324 OS_REG_WRITE(ah, regOffset, reg32); in ar5416WritePdadcValues()
2325 HALDEBUG(ah, HAL_DEBUG_EEPROM, "PDADC: Chain %d |" in ar5416WritePdadcValues()
2345 ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, in ar5416SetPowerCalTable() argument
2363 if (IS_EEP_MINOR_V2(ah)) { in ar5416SetPowerCalTable()
2366 … pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); in ar5416SetPowerCalTable()
2378 numXpdGain = ar5416GetXpdGainValues(ah, xpdMask, xpdGainValues); in ar5416SetPowerCalTable()
2381 ar5416WriteDetectorGainBiases(ah, numXpdGain, xpdGainValues); in ar5416SetPowerCalTable()
2384 regChainOffset = ar5416GetRegChainOffset(ah, i); in ar5416SetPowerCalTable()
2394 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, in ar5416SetPowerCalTable()
2400 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { in ar5416SetPowerCalTable()
2401 ar5416SetGainBoundariesClosedLoop(ah, i, pdGainOverlap_t2, in ar5416SetPowerCalTable()
2406 ar5416WritePdadcValues(ah, i, pdadcValues); in ar5416SetPowerCalTable()
2421 ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, in ar5416GetGainBoundariesAndPdadcs() argument
2452 ar5416GetChannelCenters(ah, chan, ¢ers); in ar5416GetGainBoundariesAndPdadcs()
2512 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah) ) { in ar5416GetGainBoundariesAndPdadcs()
2527 if (AR_SREV_MERLIN_10_OR_LATER(ah)) in ar5416GetGainBoundariesAndPdadcs()
2589 ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar5416Set11nRegs() argument
2595 if (AR_SREV_KITE_10_OR_LATER(ah)) in ar5416Set11nRegs()
2596 enableDacFifo = (OS_REG_READ(ah, AR_PHY_TURBO) & AR_PHY_FC_ENABLE_DAC_FIFO); in ar5416Set11nRegs()
2617 OS_REG_WRITE(ah, AR_PHY_TURBO, phymode); in ar5416Set11nRegs()
2620 ar5416Set11nMac2040(ah, macmode); in ar5416Set11nRegs()
2624 OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ; in ar5416Set11nRegs()
2627 OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC); in ar5416Set11nRegs()
2628 OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar5416Set11nRegs()
2632 ar5416GetChannelCenters(struct ath_hal *ah, in ar5416GetChannelCenters() argument
2635 uint16_t freq = ath_hal_gethwchannel(ah, chan); in ar5416GetChannelCenters()
2660 ar5416OverrideIni(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar5416OverrideIni() argument
2669 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar5416OverrideIni()
2671 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { in ar5416OverrideIni()
2672 val = OS_REG_READ(ah, AR_PCU_MISC_MODE2); in ar5416OverrideIni()
2674 if (!AR_SREV_9271(ah)) in ar5416OverrideIni()
2677 if (AR_SREV_KIWI_10_OR_LATER(ah)) in ar5416OverrideIni()
2680 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar5416OverrideIni()
2687 if (AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah)) in ar5416OverrideIni()
2688 (void) ar5416SetRifsDelay(ah, chan, AH_FALSE); in ar5416OverrideIni()
2690 if (!AR_SREV_5416_V20_OR_LATER(ah) || AR_SREV_MERLIN(ah)) in ar5416OverrideIni()
2697 OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); in ar5416OverrideIni()
2710 ar5416EepromSetAddac(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar5416EepromSetAddac() argument
2714 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; in ar5416EepromSetAddac()
2718 if (! AR_SREV_SOWL(ah)) in ar5416EepromSetAddac()
2721 if (EEP_MINOR(ah) < AR5416_EEP_MINOR_VER_7) in ar5416EepromSetAddac()
2732 ar5416GetChannelCenters(ah, chan, ¢ers); in ar5416EepromSetAddac()
2753 HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: overriding XPA bias level = %d\n", in ar5416EepromSetAddac()
2764 HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 7, 1) = in ar5416EepromSetAddac()
2765 (HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 7, 1) & (~0x18)) | biaslevel << 3; in ar5416EepromSetAddac()
2767 HAL_INI_VAL((struct ini *) &AH5416(ah)->ah_ini_addac, 6, 1) = in ar5416EepromSetAddac()
2768 (HAL_INI_VAL(&AH5416(ah)->ah_ini_addac, 6, 1) & (~0xc0)) | biaslevel << 6; in ar5416EepromSetAddac()
2773 ar5416MarkPhyInactive(struct ath_hal *ah) in ar5416MarkPhyInactive() argument
2775 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar5416MarkPhyInactive()
2826 ar5416SetIFSTiming(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar5416SetIFSTiming() argument
2838 IS_5GHZ_FAST_CLOCK_EN(ah, chan)) in ar5416SetIFSTiming()
2845 refClock = OS_REG_READ(ah, AR_USEC) & AR_USEC_USEC32; in ar5416SetIFSTiming()
2894 OS_REG_WRITE(ah, AR_USEC, (usec | refClock | txLat | rxLat)); in ar5416SetIFSTiming()
2895 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); in ar5416SetIFSTiming()
2896 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); in ar5416SetIFSTiming()
2897 OS_REG_RMW_FIELD(ah, AR_D_GBL_IFS_MISC, in ar5416SetIFSTiming()