Lines Matching refs:ah
40 extern HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah,
56 write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia, in write_common() argument
71 OS_REG_WRITE(ah, reg, V(i, 1)); in write_common()
89 ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode, in ar5312Reset() argument
97 struct ath_hal_5212 *ahp = AH5212(ah); in ar5312Reset()
110 HALASSERT(ah->ah_magic == AR5212_MAGIC); in ar5312Reset()
111 ee = AH_PRIVATE(ah)->ah_eeprom; in ar5312Reset()
113 OS_MARK(ah, AH_MARK_RESET, bChannelChange); in ar5312Reset()
117 ichan = ath_hal_checkchannel(ah, chan); in ar5312Reset()
119 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5312Reset()
131 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", in ar5312Reset()
160 saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM); in ar5312Reset()
165 if ((IS_2413(ah) || IS_5413(ah))) { in ar5312Reset()
174 AH_PRIVATE(ah)->ah_curchan != AH_NULL && in ar5312Reset()
175 (chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) && in ar5312Reset()
177 (AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) { in ar5312Reset()
178 if (ar5212ChannelChange(ah, chan)) in ar5312Reset()
187 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); in ar5312Reset()
192 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & in ar5312Reset()
196 if (!IS_5315(ah)) in ar5312Reset()
197 saveLedState = OS_REG_READ(ah, AR5312_PCICFG) & in ar5312Reset()
201 ar5312RestoreClock(ah, opmode); /* move to refclk operation */ in ar5312Reset()
207 (void) ar5212GetRfgain(ah); in ar5312Reset()
209 if (!ar5312ChipReset(ah, chan)) { in ar5312Reset()
210 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); in ar5312Reset()
224 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); in ar5312Reset()
227 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar5312Reset()
229 regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0); in ar5312Reset()
230 regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange, in ar5312Reset()
232 ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); in ar5312Reset()
234 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); in ar5312Reset()
237 ar5212SetIFSTiming(ah, chan); in ar5312Reset()
240 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) { in ar5312Reset()
242 OS_REG_WRITE(ah, AR_PHY_ADC_CTL, in ar5312Reset()
256 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, in ar5312Reset()
260 OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0); in ar5312Reset()
264 OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK, in ar5312Reset()
266 OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK, in ar5312Reset()
270 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); in ar5312Reset()
273 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { in ar5312Reset()
275 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); in ar5312Reset()
277 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) { in ar5312Reset()
280 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... ); in ar5312Reset()
282 OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS); in ar5312Reset()
286 if (IS_5312_2_X(ah)) { in ar5312Reset()
288 OS_REG_WRITE(ah, AR_PHY_SIGMA_DELTA, in ar5312Reset()
295 OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR_PHY_RXGAIN_TXRX_RF_MAX, 0x0F); in ar5312Reset()
299 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_RXCTRL4, AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT, 12); in ar5312Reset()
302 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04); in ar5312Reset()
306 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_AGC, 32); in ar5312Reset()
309 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); in ar5312Reset()
313 if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) { in ar5312Reset()
314 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5312Reset()
320 if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) { in ar5312Reset()
321 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n", in ar5312Reset()
328 if (IS_5413(ah) || in ar5312Reset()
329 AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3) in ar5312Reset()
330 ar5212SetSpurMitigation(ah, chan); in ar5312Reset()
331 ar5212SetDeltaSlope(ah, chan); in ar5312Reset()
335 if (!ar5212SetBoardValues(ah, chan)) { in ar5312Reset()
336 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5312Reset()
343 OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount); in ar5312Reset()
345 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); in ar5312Reset()
347 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); in ar5312Reset()
348 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) in ar5312Reset()
353 ar5212SetOperatingMode(ah, opmode); in ar5312Reset()
356 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); in ar5312Reset()
357 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); in ar5312Reset()
360 if (!IS_5315(ah)) in ar5312Reset()
361 OS_REG_WRITE(ah, AR5312_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState); in ar5312Reset()
364 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ar5312Reset()
367 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); in ar5312Reset()
368 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); in ar5312Reset()
371 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); in ar5312Reset()
373 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ in ar5312Reset()
375 if (!ar5212SetChannel(ah, chan)) in ar5312Reset()
378 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); in ar5312Reset()
380 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); in ar5312Reset()
382 ar5212SetRateDurationTable(ah, chan); in ar5312Reset()
385 if (IS_RAD5112_ANY(ah) && in ar5312Reset()
391 OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL, in ar5312Reset()
413 if (IS_5312_2_X(ah)) { in ar5312Reset()
414 (void) OS_REG_READ(ah, AR_PHY_SLEEP_SCAL); in ar5312Reset()
422 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5312Reset()
430 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar5312Reset()
451 testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL); in ar5312Reset()
453 OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD); in ar5312Reset()
456 (OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200); in ar5312Reset()
457 OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg); in ar5312Reset()
460 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar5312Reset()
461 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) in ar5312Reset()
467 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, in ar5312Reset()
470 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, in ar5312Reset()
477 ar5212SetCompRegs(ah); in ar5312Reset()
481 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ar5312Reset()
484 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) in ar5312Reset()
485 ar5212ResetTxQueue(ah, i); in ar5312Reset()
499 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); in ar5312Reset()
501 OS_REG_WRITE(ah, AR_IMR_S2, in ar5312Reset()
502 OS_REG_READ(ah, AR_IMR_S2) in ar5312Reset()
505 if (AH_PRIVATE(ah)->ah_rfkillEnabled) in ar5312Reset()
506 ar5212EnableRfKill(ah); in ar5312Reset()
508 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { in ar5312Reset()
509 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5312Reset()
518 ar5312SetupClock(ah, opmode); in ar5312Reset()
526 OS_REG_WRITE(ah, AR_BEACON, in ar5312Reset()
527 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF))); in ar5312Reset()
532 if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE || in ar5312Reset()
533 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && in ar5312Reset()
534 AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) { in ar5312Reset()
535 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ in ar5312Reset()
536 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ in ar5312Reset()
540 OS_REG_WRITE(ah, AR_NOACK, in ar5312Reset()
547 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); in ar5312Reset()
549 ar5212SetSlotTime(ah, ahp->ah_slottime); in ar5312Reset()
551 ar5212SetAckTimeout(ah, ahp->ah_acktimeout); in ar5312Reset()
553 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); in ar5312Reset()
555 ar5212SetSifsTime(ah, ahp->ah_sifstime); in ar5312Reset()
556 if (AH_PRIVATE(ah)->ah_diagreg != 0) in ar5312Reset()
557 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); in ar5312Reset()
559 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ in ar5312Reset()
564 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); in ar5312Reset()
566 OS_MARK(ah, AH_MARK_RESET_DONE, 0); in ar5312Reset()
570 OS_MARK(ah, AH_MARK_RESET_DONE, ecode); in ar5312Reset()
585 ar5312PhyDisable(struct ath_hal *ah) in ar5312PhyDisable() argument
587 return ar5312SetResetReg(ah, AR_RC_BB); in ar5312PhyDisable()
594 ar5312Disable(struct ath_hal *ah) in ar5312Disable() argument
596 if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) in ar5312Disable()
602 return ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB); in ar5312Disable()
613 ar5312ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) in ar5312ChipReset() argument
616 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); in ar5312ChipReset()
621 if (!ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB)) { in ar5312ChipReset()
622 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n", in ar5312ChipReset()
628 if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { in ar5312ChipReset()
629 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetPowerMode failed\n", in ar5312ChipReset()
635 if (!ar5312SetResetReg(ah, 0)) { in ar5312ChipReset()
636 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n", in ar5312ChipReset()
654 if (IS_RAD5112_ANY(ah)) { in ar5312ChipReset()
656 if (!IS_5315(ah)) { in ar5312ChipReset()
701 curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL); in ar5312ChipReset()
710 OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); in ar5312ChipReset()
711 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar5312ChipReset()
713 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); in ar5312ChipReset()
719 OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL); in ar5312ChipReset()
723 OS_REG_WRITE(ah, AR_PHY_TURBO, turbo); in ar5312ChipReset()
724 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar5312ChipReset()
734 ar5312SetResetReg(struct ath_hal *ah, uint32_t resetMask) in ar5312SetResetReg() argument
739 if ((rt = ar5312MacReset(ah, mask)) == AH_FALSE) { in ar5312SetResetReg()
753 OS_REG_WRITE(ah, AR_CFG, mask); in ar5312SetResetReg()
755 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS); in ar5312SetResetReg()
767 ar5312MacReset(struct ath_hal *ah, unsigned int RCMask) in ar5312MacReset() argument
769 int wlanNum = AR5312_UNIT(ah); in ar5312MacReset()
776 if (IS_5315(ah)) { in ar5312MacReset()
794 reg = OS_REG_READ(ah, in ar5312MacReset()
795 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5315_RESET)); in ar5312MacReset()
808 OS_REG_WRITE(ah, in ar5312MacReset()
809 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET), in ar5312MacReset()
812 OS_REG_READ(ah, in ar5312MacReset()
813 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5315_RESET)); in ar5312MacReset()
819 OS_REG_READ(ah, in ar5312MacReset()
820 (AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET)); in ar5312MacReset()
821 OS_REG_WRITE(ah, in ar5312MacReset()
822 (AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET), in ar5312MacReset()
825 OS_REG_READ(ah, in ar5312MacReset()
826 (AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET)); in ar5312MacReset()
849 reg = OS_REG_READ(ah, in ar5312MacReset()
850 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5312_RESET)); in ar5312MacReset()
863 OS_REG_WRITE(ah, in ar5312MacReset()
864 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET), in ar5312MacReset()
867 OS_REG_READ(ah, in ar5312MacReset()
868 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5312_RESET)); in ar5312MacReset()
874 OS_REG_READ(ah, in ar5312MacReset()
875 (AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET)); in ar5312MacReset()
876 OS_REG_WRITE(ah, in ar5312MacReset()
877 (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET), in ar5312MacReset()
880 OS_REG_READ(ah, in ar5312MacReset()
881 (AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET)); in ar5312MacReset()