Lines Matching refs:ah
38 ar5312SetLedState(struct ath_hal *ah, HAL_LED_STATE state) in ar5312SetLedState() argument
41 uint32_t resOffset = (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)); in ar5312SetLedState()
42 if(IS_2316(ah)) return; /* not yet */ in ar5312SetLedState()
46 OS_REG_WRITE(ah, resOffset+AR5312_PCICFG, in ar5312SetLedState()
47 (OS_REG_READ(ah, AR5312_PCICFG) &~ in ar5312SetLedState()
57 ar5312DetectCardPresent(struct ath_hal *ah) in ar5312DetectCardPresent() argument
68 if(IS_5315(ah)) in ar5312DetectCardPresent()
70 v = (OS_REG_READ(ah, in ar5312DetectCardPresent()
71 (AR5315_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5315_WREV)) in ar5312DetectCardPresent()
75 return (AH_PRIVATE(ah)->ah_macVersion == macVersion && in ar5312DetectCardPresent()
76 AH_PRIVATE(ah)->ah_macRev == macRev); in ar5312DetectCardPresent()
81 v = (OS_REG_READ(ah, in ar5312DetectCardPresent()
82 (AR5312_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5312_WREV)) in ar5312DetectCardPresent()
86 return (AH_PRIVATE(ah)->ah_macVersion == macVersion && in ar5312DetectCardPresent()
87 AH_PRIVATE(ah)->ah_macRev == macRev); in ar5312DetectCardPresent()
98 ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode) in ar5312SetupClock() argument
100 if (ar5212Use32KHzclock(ah, opmode)) { in ar5312SetupClock()
106 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); in ar5312SetupClock()
107 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0d); in ar5312SetupClock()
108 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c); in ar5312SetupClock()
109 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03); in ar5312SetupClock()
110 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x05); in ar5312SetupClock()
111 OS_REG_WRITE(ah, AR_PHY_REFCLKPD, in ar5312SetupClock()
112 IS_RAD5112_ANY(ah) ? 0x14 : 0x18); in ar5312SetupClock()
114 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1); in ar5312SetupClock()
115 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */ in ar5312SetupClock()
118 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ in ar5312SetupClock()
119 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, in ar5312SetupClock()
120 IS_RAD5112_ANY(ah) ? 39 : 31); in ar5312SetupClock()
122 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); in ar5312SetupClock()
123 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f); in ar5312SetupClock()
125 if (IS_5312_2_X(ah)) { in ar5312SetupClock()
127 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04); in ar5312SetupClock()
129 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); in ar5312SetupClock()
130 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c); in ar5312SetupClock()
131 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff); in ar5312SetupClock()
132 OS_REG_WRITE(ah, AR_PHY_REFCLKPD, in ar5312SetupClock()
133 IS_RAD5112_ANY(ah) ? 0x14 : 0x18); in ar5312SetupClock()
142 ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode) in ar5312RestoreClock() argument
144 if (ar5212Use32KHzclock(ah, opmode)) { in ar5312RestoreClock()
146 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ in ar5312RestoreClock()
147 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, in ar5312RestoreClock()
148 IS_RAD5112_ANY(ah) ? 39 : 31); in ar5312RestoreClock()
153 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); in ar5312RestoreClock()
154 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f); in ar5312RestoreClock()
155 if (IS_5312_2_X(ah)) { in ar5312RestoreClock()
157 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04); in ar5312RestoreClock()
159 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); in ar5312RestoreClock()
160 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c); in ar5312RestoreClock()
161 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff); in ar5312RestoreClock()
162 OS_REG_WRITE(ah, AR_PHY_REFCLKPD, in ar5312RestoreClock()
163 IS_RAD5112_ANY(ah) ? 0x14 : 0x18); in ar5312RestoreClock()