Lines Matching +full:mac +full:-
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
27 #define AR_CR 0x0008 /* MAC control register */
28 #define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */
29 #define AR_CFG 0x0014 /* MAC configuration and status register */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
33 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
36 #define AR_MIBC 0x0040 /* MAC MIB control register */
37 #define AR_TOPS 0x0044 /* MAC timeout prescale count */
38 #define AR_RXNPTO 0x0048 /* MAC no frame received timeout */
39 #define AR_TXNPTO 0x004C /* MAC no frame trasmitted timeout */
40 #define AR_RPGTO 0x0050 /* MAC receive frame gap timeout */
41 #define AR_RPCNT 0x0054 /* MAC receive frame count limit */
42 #define AR_MACMISC 0x0058 /* MAC miscellaneous control/status register */
43 #define AR_SPC_0 0x005c /* MAC sleep performance (awake cycles) */
44 #define AR_SPC_1 0x0060 /* MAC sleep performance (asleep cycles) */
46 #define AR_ISR 0x0080 /* MAC Primary interrupt status register */
47 #define AR_ISR_S0 0x0084 /* MAC Secondary interrupt status register 0 */
48 #define AR_ISR_S1 0x0088 /* MAC Secondary interrupt status register 1 */
49 #define AR_ISR_S2 0x008c /* MAC Secondary interrupt status register 2 */
50 #define AR_ISR_S3 0x0090 /* MAC Secondary interrupt status register 3 */
51 #define AR_ISR_S4 0x0094 /* MAC Secondary interrupt status register 4 */
52 #define AR_IMR 0x00a0 /* MAC Primary interrupt mask register */
53 #define AR_IMR_S0 0x00a4 /* MAC Secondary interrupt mask register 0 */
54 #define AR_IMR_S1 0x00a8 /* MAC Secondary interrupt mask register 1 */
55 #define AR_IMR_S2 0x00ac /* MAC Secondary interrupt mask register 2 */
56 #define AR_IMR_S3 0x00b0 /* MAC Secondary interrupt mask register 3 */
57 #define AR_IMR_S4 0x00b4 /* MAC Secondary interrupt mask register 4 */
58 #define AR_ISR_RAC 0x00c0 /* ISR read-and-clear access */
59 /* Shadow copies with read-and-clear access */
84 #define AR_Q0_TXDP 0x0800 /* MAC Transmit Queue descriptor pointer */
85 #define AR_Q1_TXDP 0x0804 /* MAC Transmit Queue descriptor pointer */
86 #define AR_Q2_TXDP 0x0808 /* MAC Transmit Queue descriptor pointer */
87 #define AR_Q3_TXDP 0x080c /* MAC Transmit Queue descriptor pointer */
88 #define AR_Q4_TXDP 0x0810 /* MAC Transmit Queue descriptor pointer */
89 #define AR_Q5_TXDP 0x0814 /* MAC Transmit Queue descriptor pointer */
90 #define AR_Q6_TXDP 0x0818 /* MAC Transmit Queue descriptor pointer */
91 #define AR_Q7_TXDP 0x081c /* MAC Transmit Queue descriptor pointer */
92 #define AR_Q8_TXDP 0x0820 /* MAC Transmit Queue descriptor pointer */
93 #define AR_Q9_TXDP 0x0824 /* MAC Transmit Queue descriptor pointer */
96 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */
97 #define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
98 #define AR_Q_TXD 0x0880 /* MAC Transmit Queue disable */
99 #define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
101 #define AR_Q0_CBRCFG 0x08c0 /* MAC CBR configuration */
102 #define AR_Q1_CBRCFG 0x08c4 /* MAC CBR configuration */
103 #define AR_Q2_CBRCFG 0x08c8 /* MAC CBR configuration */
104 #define AR_Q3_CBRCFG 0x08cc /* MAC CBR configuration */
105 #define AR_Q4_CBRCFG 0x08d0 /* MAC CBR configuration */
106 #define AR_Q5_CBRCFG 0x08d4 /* MAC CBR configuration */
107 #define AR_Q6_CBRCFG 0x08d8 /* MAC CBR configuration */
108 #define AR_Q7_CBRCFG 0x08dc /* MAC CBR configuration */
109 #define AR_Q8_CBRCFG 0x08e0 /* MAC CBR configuration */
110 #define AR_Q9_CBRCFG 0x08e4 /* MAC CBR configuration */
113 #define AR_Q0_RDYTIMECFG 0x0900 /* MAC ReadyTime configuration */
114 #define AR_Q1_RDYTIMECFG 0x0904 /* MAC ReadyTime configuration */
115 #define AR_Q2_RDYTIMECFG 0x0908 /* MAC ReadyTime configuration */
116 #define AR_Q3_RDYTIMECFG 0x090c /* MAC ReadyTime configuration */
117 #define AR_Q4_RDYTIMECFG 0x0910 /* MAC ReadyTime configuration */
118 #define AR_Q5_RDYTIMECFG 0x0914 /* MAC ReadyTime configuration */
119 #define AR_Q6_RDYTIMECFG 0x0918 /* MAC ReadyTime configuration */
120 #define AR_Q7_RDYTIMECFG 0x091c /* MAC ReadyTime configuration */
121 #define AR_Q8_RDYTIMECFG 0x0920 /* MAC ReadyTime configuration */
122 #define AR_Q9_RDYTIMECFG 0x0924 /* MAC ReadyTime configuration */
125 #define AR_Q_ONESHOTARM_SC 0x0940 /* MAC OneShotArm set control */
126 #define AR_Q_ONESHOTARM_CC 0x0980 /* MAC OneShotArm clear control */
128 #define AR_Q0_MISC 0x09c0 /* MAC Miscellaneous QCU settings */
129 #define AR_Q1_MISC 0x09c4 /* MAC Miscellaneous QCU settings */
130 #define AR_Q2_MISC 0x09c8 /* MAC Miscellaneous QCU settings */
131 #define AR_Q3_MISC 0x09cc /* MAC Miscellaneous QCU settings */
132 #define AR_Q4_MISC 0x09d0 /* MAC Miscellaneous QCU settings */
133 #define AR_Q5_MISC 0x09d4 /* MAC Miscellaneous QCU settings */
134 #define AR_Q6_MISC 0x09d8 /* MAC Miscellaneous QCU settings */
135 #define AR_Q7_MISC 0x09dc /* MAC Miscellaneous QCU settings */
136 #define AR_Q8_MISC 0x09e0 /* MAC Miscellaneous QCU settings */
137 #define AR_Q9_MISC 0x09e4 /* MAC Miscellaneous QCU settings */
140 #define AR_Q0_STS 0x0a00 /* MAC Miscellaneous QCU status */
141 #define AR_Q1_STS 0x0a04 /* MAC Miscellaneous QCU status */
142 #define AR_Q2_STS 0x0a08 /* MAC Miscellaneous QCU status */
143 #define AR_Q3_STS 0x0a0c /* MAC Miscellaneous QCU status */
144 #define AR_Q4_STS 0x0a10 /* MAC Miscellaneous QCU status */
145 #define AR_Q5_STS 0x0a14 /* MAC Miscellaneous QCU status */
146 #define AR_Q6_STS 0x0a18 /* MAC Miscellaneous QCU status */
147 #define AR_Q7_STS 0x0a1c /* MAC Miscellaneous QCU status */
148 #define AR_Q8_STS 0x0a20 /* MAC Miscellaneous QCU status */
149 #define AR_Q9_STS 0x0a24 /* MAC Miscellaneous QCU status */
152 #define AR_Q_RDYTIMESHDN 0x0a40 /* MAC ReadyTimeShutdown status */
157 #define AR_D0_QCUMASK 0x1000 /* MAC QCU Mask */
158 #define AR_D1_QCUMASK 0x1004 /* MAC QCU Mask */
159 #define AR_D2_QCUMASK 0x1008 /* MAC QCU Mask */
160 #define AR_D3_QCUMASK 0x100c /* MAC QCU Mask */
161 #define AR_D4_QCUMASK 0x1010 /* MAC QCU Mask */
162 #define AR_D5_QCUMASK 0x1014 /* MAC QCU Mask */
163 #define AR_D6_QCUMASK 0x1018 /* MAC QCU Mask */
164 #define AR_D7_QCUMASK 0x101c /* MAC QCU Mask */
165 #define AR_D8_QCUMASK 0x1020 /* MAC QCU Mask */
166 #define AR_D9_QCUMASK 0x1024 /* MAC QCU Mask */
169 #define AR_D0_LCL_IFS 0x1040 /* MAC DCU-specific IFS settings */
170 #define AR_D1_LCL_IFS 0x1044 /* MAC DCU-specific IFS settings */
171 #define AR_D2_LCL_IFS 0x1048 /* MAC DCU-specific IFS settings */
172 #define AR_D3_LCL_IFS 0x104c /* MAC DCU-specific IFS settings */
173 #define AR_D4_LCL_IFS 0x1050 /* MAC DCU-specific IFS settings */
174 #define AR_D5_LCL_IFS 0x1054 /* MAC DCU-specific IFS settings */
175 #define AR_D6_LCL_IFS 0x1058 /* MAC DCU-specific IFS settings */
176 #define AR_D7_LCL_IFS 0x105c /* MAC DCU-specific IFS settings */
177 #define AR_D8_LCL_IFS 0x1060 /* MAC DCU-specific IFS settings */
178 #define AR_D9_LCL_IFS 0x1064 /* MAC DCU-specific IFS settings */
181 #define AR_D0_RETRY_LIMIT 0x1080 /* MAC Retry limits */
182 #define AR_D1_RETRY_LIMIT 0x1084 /* MAC Retry limits */
183 #define AR_D2_RETRY_LIMIT 0x1088 /* MAC Retry limits */
184 #define AR_D3_RETRY_LIMIT 0x108c /* MAC Retry limits */
185 #define AR_D4_RETRY_LIMIT 0x1090 /* MAC Retry limits */
186 #define AR_D5_RETRY_LIMIT 0x1094 /* MAC Retry limits */
187 #define AR_D6_RETRY_LIMIT 0x1098 /* MAC Retry limits */
188 #define AR_D7_RETRY_LIMIT 0x109c /* MAC Retry limits */
189 #define AR_D8_RETRY_LIMIT 0x10a0 /* MAC Retry limits */
190 #define AR_D9_RETRY_LIMIT 0x10a4 /* MAC Retry limits */
193 #define AR_D0_CHNTIME 0x10c0 /* MAC ChannelTime settings */
194 #define AR_D1_CHNTIME 0x10c4 /* MAC ChannelTime settings */
195 #define AR_D2_CHNTIME 0x10c8 /* MAC ChannelTime settings */
196 #define AR_D3_CHNTIME 0x10cc /* MAC ChannelTime settings */
197 #define AR_D4_CHNTIME 0x10d0 /* MAC ChannelTime settings */
198 #define AR_D5_CHNTIME 0x10d4 /* MAC ChannelTime settings */
199 #define AR_D6_CHNTIME 0x10d8 /* MAC ChannelTime settings */
200 #define AR_D7_CHNTIME 0x10dc /* MAC ChannelTime settings */
201 #define AR_D8_CHNTIME 0x10e0 /* MAC ChannelTime settings */
202 #define AR_D9_CHNTIME 0x10e4 /* MAC ChannelTime settings */
205 #define AR_D0_MISC 0x1100 /* MAC Miscellaneous DCU-specific settings */
206 #define AR_D1_MISC 0x1104 /* MAC Miscellaneous DCU-specific settings */
207 #define AR_D2_MISC 0x1108 /* MAC Miscellaneous DCU-specific settings */
208 #define AR_D3_MISC 0x110c /* MAC Miscellaneous DCU-specific settings */
209 #define AR_D4_MISC 0x1110 /* MAC Miscellaneous DCU-specific settings */
210 #define AR_D5_MISC 0x1114 /* MAC Miscellaneous DCU-specific settings */
211 #define AR_D6_MISC 0x1118 /* MAC Miscellaneous DCU-specific settings */
212 #define AR_D7_MISC 0x111c /* MAC Miscellaneous DCU-specific settings */
213 #define AR_D8_MISC 0x1120 /* MAC Miscellaneous DCU-specific settings */
214 #define AR_D9_MISC 0x1124 /* MAC Miscellaneous DCU-specific settings */
217 #define AR_D_SEQNUM 0x1140 /* MAC Frame sequence number */
219 /* MAC DCU-global IFS settings */
253 #define AR_STA_ID0 0x8000 /* MAC station ID0 register - low 32 bits */
254 #define AR_STA_ID1 0x8004 /* MAC station ID1 register - upper 16 bits */
255 #define AR_BSS_ID0 0x8008 /* MAC BSSID low 32 bits */
256 #define AR_BSS_ID1 0x800C /* MAC BSSID upper 16 bits / AID */
257 #define AR_SLOT_TIME 0x8010 /* MAC Time-out after a collision */
258 #define AR_TIME_OUT 0x8014 /* MAC ACK & CTS time-out */
259 #define AR_RSSI_THR 0x8018 /* MAC RSSI warning & missed beacon threshold */
260 #define AR_USEC 0x801c /* MAC transmit latency register */
261 #define AR_BEACON 0x8020 /* MAC beacon control value/mode bits */
262 #define AR_CFP_PERIOD 0x8024 /* MAC CFP Interval (TU/msec) */
263 #define AR_TIMER0 0x8028 /* MAC Next beacon time (TU/msec) */
264 #define AR_TIMER1 0x802c /* MAC DMA beacon alert time (1/8 TU) */
265 #define AR_TIMER2 0x8030 /* MAC Software beacon alert (1/8 TU) */
266 #define AR_TIMER3 0x8034 /* MAC ATIM window time */
267 #define AR_CFP_DUR 0x8038 /* MAC maximum CFP duration in TU */
268 #define AR_RX_FILTER 0x803C /* MAC receive filter register */
269 #define AR_MCAST_FIL0 0x8040 /* MAC multicast filter lower 32 bits */
270 #define AR_MCAST_FIL1 0x8044 /* MAC multicast filter upper 32 bits */
271 #define AR_DIAG_SW 0x8048 /* MAC PCU control register */
272 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */
273 #define AR_TSF_U32 0x8050 /* MAC local clock upper 32 bits */
276 #define AR_QOS_MASK 0x805c /* MAC AES mute mask: QoS field */
277 #define AR_SEQ_MASK 0x8060 /* MAC AES mute mask: seqnum field */
281 #define AR_LAST_TSTP 0x8080 /* MAC Time stamp of the last beacon received */
282 #define AR_NAV 0x8084 /* MAC current NAV value */
283 #define AR_RTS_OK 0x8088 /* MAC RTS exchange success counter */
284 #define AR_RTS_FAIL 0x808c /* MAC RTS exchange failure counter */
285 #define AR_ACK_FAIL 0x8090 /* MAC ACK failure counter */
331 #define AR_RATE_DURATION_0 0x8700 /* base of multi-rate retry */
334 #define AR_KEYTABLE_0 0x8800 /* MAC Key Cache */
341 #define AR_CR_SWI 0x00000040 /* One-shot software interrupt */
348 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
375 #define AR_RXCFG_ZLFDMA 0x00000010 /* Enable DMA of zero-length frame */
399 #define AR_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */
400 #define AR_MACMISC_MAC_OBS_BUS_LSB_S 12 /* Shift for MAC observation bus mux select (lsb) */
401 #define AR_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */
402 #define AR_MACMISC_MAC_OBS_BUS_MSB_S 15 /* Shift for MAC observation bus mux select (msb) */
408 * control whether the MAC's INTA# output is asserted. The bits in
413 * and IMR_P is non-zero. The secondary interrupt mask/status
429 #define AR_ISR_MIB 0x00001000 /* MIB interrupt - see MIBC */
432 #define AR_ISR_RXKCM 0x00008000 /* Key-cache miss interrupt */
449 #define AR_ISR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */
451 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
454 #define AR_ISR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */
456 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
459 #define AR_ISR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
472 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
473 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
475 #define AR_ISR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */
481 * Only the bits in the IMR control whether the MAC's INTA#
499 #define AR_IMR_MIB 0x00001000 /* MIB interrupt - see MIBC */
502 #define AR_IMR_RXKCM 0x00008000 /* Key-cache miss interrupt */
517 #define AR_IMR_S0_QCU_TXOK 0x000003FF /* TXOK (QCU 0-9) */
519 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* TXDESC (QCU 0-9) */
522 #define AR_IMR_S1_QCU_TXERR 0x000003FF /* TXERR (QCU 0-9) */
524 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* TXEOL (QCU 0-9) */
527 #define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
547 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
548 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
549 #define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */
551 #define AR_IMR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */
555 #define AR_NUM_QCU 10 /* Only use QCU 0-9 for forward QCU compatibility */
575 /* bits 25-31 are reserved */
582 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
615 #define AR_D_QCUMASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
669 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame */
673 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Post-frame backoff disable */
689 #define AR_RC_MAC 0x00000001 /* MAC reset */
693 #define AR_RC_PCI 0x00000010 /* PCI-core reset */
825 /* EEPROM Registers in the MAC */
851 /* MAC PCU Registers */
853 #define AR_STA_ID1_SADH_MASK 0x0000FFFF /* upper 16 bits of MAC addr */
855 #define AR_STA_ID1_ADHOC 0x00020000 /* Device is ad-hoc */
857 self-generated frames */
867 self-generated frames */
869 #define AR_STA_ID1_KSRCH_MODE 0x10000000 /* Look-up key when keyID != 0 */
880 #define AR_TIME_OUT_ACK 0x00003FFF /* ACK time-out */
882 #define AR_TIME_OUT_CTS 0x3FFF0000 /* CTS time-out */
926 #define AR_DIAG_FRAME_NV0 0x00020000 /* Accept frames of non-zero
978 #define AR_MISC_MODE_TX_ADD_TSF 0x8 /* Beacon/Probe-Rsp timestamp add (not replace) */
980 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */
981 #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */
982 #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */
983 #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */
984 #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */
994 #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */
995 #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */
996 #define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */