Lines Matching full:cbr

101 #define	AR_Q0_CBRCFG	0x08c0	/* MAC CBR configuration */
102 #define	AR_Q1_CBRCFG	0x08c4	/* MAC CBR configuration */
103 #define	AR_Q2_CBRCFG	0x08c8	/* MAC CBR configuration */
104 #define	AR_Q3_CBRCFG	0x08cc	/* MAC CBR configuration */
105 #define	AR_Q4_CBRCFG	0x08d0	/* MAC CBR configuration */
106 #define	AR_Q5_CBRCFG	0x08d4	/* MAC CBR configuration */
107 #define	AR_Q6_CBRCFG	0x08d8	/* MAC CBR configuration */
108 #define	AR_Q7_CBRCFG	0x08dc	/* MAC CBR configuration */
109 #define	AR_Q8_CBRCFG	0x08e0	/* MAC CBR configuration */
110 #define	AR_Q9_CBRCFG	0x08e4	/* MAC CBR configuration */
444 #define	AR_ISR_QCBROVF	0x02000000 /* QCU CBR overflow interrupt */
445 #define	AR_ISR_QCBRURN	0x04000000 /* QCU CBR underrun interrupt */
512 #define	AR_IMR_QCBROVF	0x02000000 /* QCU CBR overflow interrupt */
513 #define	AR_IMR_QCBRURN	0x04000000 /* QCU CBR underrun interrupt */
567 #define	AR_Q_CBRCFG_CBR_INTERVAL	0x00FFFFFF /* Mask for CBR interval (us) */
568 #define AR_Q_CBRCFG_CBR_INTERVAL_S      0   /* Shift for CBR interval */
569 #define	AR_Q_CBRCFG_CBR_OVF_THRESH	0xFF000000 /* Mask for CBR overflow threshold */
570 #define AR_Q_CBRCFG_CBR_OVF_THRESH_S    24  /* Shift for CBR overflow thresh */
572 #define	AR_Q_RDYTIMECFG_INT	0x00FFFFFF /* CBR interval (us) */
574 #define	AR_Q_RDYTIMECFG_ENA	0x01000000 /* CBR enable */
579 #define	AR_Q_MISC_FSP_CBR		1	/* CBR */
585 #define	AR_Q_MISC_CBR_INCR_DIS1	0x00000020 /* Disable CBR expired counter incr
587 #define	AR_Q_MISC_CBR_INCR_DIS0	0x00000040 /* Disable CBR expired counter incr
590 #define	AR_Q_MISC_CBR_EXP_CNTR_LIMIT	0x00000100 /* CBR expired counter limit enable */
592 #define	AR_Q_MISC_RESET_CBR_EXP_CTR	0x00000400 /* Reset CBR expired counter */
599 #define	AR_Q_STS_CBR_EXP_CNT	0x0000FF00 /* Mask for CBR expired counter */