Lines Matching +full:0 +full:x00f00000
32 uint32_t ds_ctl0; /* DMA control 0 */
38 uint32_t status0;/* DMA status 0 */
42 uint32_t status0;/* DMA status 0 */
58 #define AR_FrameLen 0x00000fff /* frame length */
60 #define AR_XmitPower 0x003f0000 /* transmit power control */
62 #define AR_RTSCTSEnable 0x00400000 /* RTS/CTS protocol enable */
63 #define AR_VEOL 0x00800000 /* virtual end-of-list */
64 #define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */
65 #define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */
67 #define AR_TxInterReq 0x20000000 /* TX interrupt request */
68 #define AR_DestIdxValid 0x40000000 /* destination index valid */
69 #define AR_CTSEnable 0x80000000 /* precede frame with CTS */
72 #define AR_BufLen 0x00000fff /* data buffer length */
73 #define AR_More 0x00001000 /* more desc in this frame */
74 #define AR_DestIdx 0x000fe000 /* destination table index */
76 #define AR_FrmType 0x00f00000 /* frame type indication */
78 #define AR_NoAck 0x01000000 /* No ACK flag */
79 #define AR_CompProc 0x06000000 /* compression processing */
81 #define AR_CompIVLen 0x18000000 /* length of frame IV */
83 #define AR_CompICVLen 0x60000000 /* length of frame ICV */
88 #define AR_RTSCTSDuration 0x00007fff /* RTS/CTS duration */
89 #define AR_RTSCTSDuration_S 0
90 #define AR_DurUpdateEna 0x00008000 /* frame duration update ctl */
91 #define AR_XmitDataTries0 0x000f0000 /* series 0 max attempts */
93 #define AR_XmitDataTries1 0x00f00000 /* series 1 max attempts */
95 #define AR_XmitDataTries2 0x0f000000 /* series 2 max attempts */
97 #define AR_XmitDataTries3 0xf0000000 /* series 3 max attempts */
101 #define AR_XmitRate0 0x0000001f /* series 0 tx rate */
102 #define AR_XmitRate0_S 0
103 #define AR_XmitRate1 0x000003e0 /* series 1 tx rate */
105 #define AR_XmitRate2 0x00007c00 /* series 2 tx rate */
107 #define AR_XmitRate3 0x000f8000 /* series 3 tx rate */
109 #define AR_RTSCTSRate 0x01f00000 /* RTS or CTS rate */
114 /* AR_BufLen 0x00000fff data buffer length */
116 #define AR_RxInterReq 0x00002000 /* RX interrupt request */
120 #define AR_FrmXmitOK 0x00000001 /* TX success */
121 #define AR_ExcessiveRetries 0x00000002 /* excessive retries */
122 #define AR_FIFOUnderrun 0x00000004 /* TX FIFO underrun */
123 #define AR_Filtered 0x00000008 /* TX filter indication */
124 #define AR_RTSFailCnt 0x000000f0 /* RTS failure count */
126 #define AR_DataFailCnt 0x00000f00 /* Data failure count */
128 #define AR_VirtCollCnt 0x0000f000 /* virtual collision count */
130 #define AR_SendTimestamp 0xffff0000 /* TX timestamp */
134 #define AR_DataLen 0x00000fff /* RX data length */
135 /* AR_More 0x00001000 more desc in this frame */
136 #define AR_DecompCRCErr 0x00002000 /* decompression CRC error */
138 #define AR_RcvRate 0x000f8000 /* reception rate */
140 #define AR_RcvSigStrength 0x0ff00000 /* receive signal strength */
142 #define AR_RcvAntenna 0xf0000000 /* receive antenaa */
146 #define AR_Done 0x00000001 /* descripter complete */
147 #define AR_SeqNum 0x00001ffe /* TX sequence number */
149 #define AR_AckSigStrength 0x001fe000 /* strength of ACK */
151 #define AR_FinalTSIndex 0x00600000 /* final TX attempt series ix */
153 #define AR_CompSuccess 0x00800000 /* compression status */
154 #define AR_XmitAtenna 0x01000000 /* transmit antenna */
158 /* AR_Done 0x00000001 descripter complete */
159 #define AR_FrmRcvOK 0x00000002 /* frame reception success */
160 #define AR_CRCErr 0x00000004 /* CRC error */
161 #define AR_DecryptCRCErr 0x00000008 /* Decryption CRC fiailure */
162 #define AR_PHYErr 0x00000010 /* PHY error */
163 #define AR_MichaelErr 0x00000020 /* Michae MIC decrypt error */
165 #define AR_KeyIdxValid 0x00000100 /* decryption key index valid */
166 #define AR_KeyIdx 0x0000fe00 /* Decryption key index */
168 #define AR_RcvTimestamp 0x7fff0000 /* timestamp */
170 #define AR_KeyCacheMiss 0x80000000 /* key cache miss indication */
173 #define AR_PHYErrCode 0x0000ff00 /* PHY error code */