Lines Matching +full:1 +full:q
86 ar5212SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo) in ar5212SetTxQueueProps() argument
91 if (q >= pCap->halTotalQueues) { in ar5212SetTxQueueProps()
93 __func__, q); in ar5212SetTxQueueProps()
96 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo); in ar5212SetTxQueueProps()
103 ar5212GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo) in ar5212GetTxQueueProps() argument
108 if (q >= pCap->halTotalQueues) { in ar5212GetTxQueueProps()
110 __func__, q); in ar5212GetTxQueueProps()
113 return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]); in ar5212GetTxQueueProps()
126 int q, defqflags; in ar5212SetupTxQueue() local
136 q = pCap->halTotalQueues-1; /* highest priority */ in ar5212SetupTxQueue()
143 q = pCap->halTotalQueues-2; /* next highest priority */ in ar5212SetupTxQueue()
151 q = pCap->halTotalQueues-3; /* nextest highest priority */ in ar5212SetupTxQueue()
152 if (ahp->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE) { in ar5212SetupTxQueue()
155 return -1; in ar5212SetupTxQueue()
159 for (q = 0; q < pCap->halTotalQueues; q++) in ar5212SetupTxQueue()
160 if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE) in ar5212SetupTxQueue()
162 if (q == pCap->halTotalQueues) { in ar5212SetupTxQueue()
165 return -1; in ar5212SetupTxQueue()
171 return -1; in ar5212SetupTxQueue()
174 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q); in ar5212SetupTxQueue()
176 qi = &ahp->ah_txq[q]; in ar5212SetupTxQueue()
179 __func__, q); in ar5212SetupTxQueue()
180 return -1; in ar5212SetupTxQueue()
194 (void) ar5212SetTxQueueProps(ah, q, qInfo); in ar5212SetupTxQueue()
197 return q; in ar5212SetupTxQueue()
201 * Update the h/w interrupt registers to reflect a tx q's configuration.
230 ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q) in ar5212ReleaseTxQueue() argument
236 if (q >= pCap->halTotalQueues) { in ar5212ReleaseTxQueue()
238 __func__, q); in ar5212ReleaseTxQueue()
241 qi = &ahp->ah_txq[q]; in ar5212ReleaseTxQueue()
244 __func__, q); in ar5212ReleaseTxQueue()
248 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q); in ar5212ReleaseTxQueue()
251 ahp->ah_txOkInterruptMask &= ~(1 << q); in ar5212ReleaseTxQueue()
252 ahp->ah_txErrInterruptMask &= ~(1 << q); in ar5212ReleaseTxQueue()
253 ahp->ah_txDescInterruptMask &= ~(1 << q); in ar5212ReleaseTxQueue()
254 ahp->ah_txEolInterruptMask &= ~(1 << q); in ar5212ReleaseTxQueue()
255 ahp->ah_txUrnInterruptMask &= ~(1 << q); in ar5212ReleaseTxQueue()
268 ar5212ResetTxQueue(struct ath_hal *ah, u_int q) in ar5212ResetTxQueue() argument
276 if (q >= pCap->halTotalQueues) { in ar5212ResetTxQueue()
278 __func__, q); in ar5212ResetTxQueue()
281 qi = &ahp->ah_txq[q]; in ar5212ResetTxQueue()
284 __func__, q); in ar5212ResetTxQueue()
288 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: reset queue %u\n", __func__, q); in ar5212ResetTxQueue()
299 /* make sure that the CWmin is of the form (2^n - 1) */ in ar5212ResetTxQueue()
300 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1) in ar5212ResetTxQueue()
306 OS_REG_WRITE(ah, AR_DLCL_IFS(q), in ar5212ResetTxQueue()
312 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q), in ar5212ResetTxQueue()
334 OS_REG_WRITE(ah, AR_QCBRCFG(q), in ar5212ResetTxQueue()
342 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), in ar5212ResetTxQueue()
347 OS_REG_WRITE(ah, AR_DCHNTIME(q), in ar5212ResetTxQueue()
416 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), in ar5212ResetTxQueue()
444 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), in ar5212ResetTxQueue()
455 OS_REG_WRITE(ah, AR_QMISC(q), qmisc); in ar5212ResetTxQueue()
456 OS_REG_WRITE(ah, AR_DMISC(q), dmisc); in ar5212ResetTxQueue()
466 OS_REG_WRITE(ah, AR_Q_CBBS, (80 + 2*q)); in ar5212ResetTxQueue()
469 OS_REG_WRITE(ah, AR_Q0_MISC + 4*q, in ar5212ResetTxQueue()
470 OS_REG_READ(ah, AR_Q0_MISC + 4*q) in ar5212ResetTxQueue()
485 ahp->ah_txOkInterruptMask |= 1 << q; in ar5212ResetTxQueue()
487 ahp->ah_txOkInterruptMask &= ~(1 << q); in ar5212ResetTxQueue()
489 ahp->ah_txErrInterruptMask |= 1 << q; in ar5212ResetTxQueue()
491 ahp->ah_txErrInterruptMask &= ~(1 << q); in ar5212ResetTxQueue()
493 ahp->ah_txDescInterruptMask |= 1 << q; in ar5212ResetTxQueue()
495 ahp->ah_txDescInterruptMask &= ~(1 << q); in ar5212ResetTxQueue()
497 ahp->ah_txEolInterruptMask |= 1 << q; in ar5212ResetTxQueue()
499 ahp->ah_txEolInterruptMask &= ~(1 << q); in ar5212ResetTxQueue()
501 ahp->ah_txUrnInterruptMask |= 1 << q; in ar5212ResetTxQueue()
503 ahp->ah_txUrnInterruptMask &= ~(1 << q); in ar5212ResetTxQueue()
514 ar5212GetTxDP(struct ath_hal *ah, u_int q) in ar5212GetTxDP() argument
516 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); in ar5212GetTxDP()
517 return OS_REG_READ(ah, AR_QTXDP(q)); in ar5212GetTxDP()
524 ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp) in ar5212SetTxDP() argument
526 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); in ar5212SetTxDP()
527 HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); in ar5212SetTxDP()
533 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0); in ar5212SetTxDP()
535 OS_REG_WRITE(ah, AR_QTXDP(q), txdp); in ar5212SetTxDP()
544 ar5212StartTxDma(struct ath_hal *ah, u_int q) in ar5212StartTxDma() argument
546 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); in ar5212StartTxDma()
548 HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); in ar5212StartTxDma()
550 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q); in ar5212StartTxDma()
552 /* Check to be sure we're not enabling a q that has its TXD bit set. */ in ar5212StartTxDma()
553 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0); in ar5212StartTxDma()
555 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q); in ar5212StartTxDma()
564 ar5212NumTxPending(struct ath_hal *ah, u_int q) in ar5212NumTxPending() argument
568 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); in ar5212NumTxPending()
569 HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); in ar5212NumTxPending()
571 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ar5212NumTxPending()
578 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) in ar5212NumTxPending()
579 npend = 1; /* arbitrarily return 1 */ in ar5212NumTxPending()
588 ar5212StopTxDma(struct ath_hal *ah, u_int q) in ar5212StopTxDma() argument
593 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); in ar5212StopTxDma()
595 HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); in ar5212StopTxDma()
597 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); in ar5212StopTxDma()
599 if (ar5212NumTxPending(ah, q) == 0) in ar5212StopTxDma()
606 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q); in ar5212StopTxDma()
609 OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE), in ar5212StopTxDma()
610 OS_REG_READ(ah, AR_Q_TXD), OS_REG_READ(ah, AR_QCBRCFG(q))); in ar5212StopTxDma()
613 __func__, OS_REG_READ(ah, AR_QMISC(q)), in ar5212StopTxDma()
614 OS_REG_READ(ah, AR_QRDYTIMECFG(q)), in ar5212StopTxDma()
620 if (ar5212NumTxPending(ah, q) && in ar5212StopTxDma()
625 "%s: Num of pending TX Frames %d on Q %d\n", in ar5212StopTxDma()
626 __func__, ar5212NumTxPending(ah, q), q); in ar5212StopTxDma()
642 HALASSERT(j < 1); /* TSF shouldn't count twice or reg access is taking forever */ in ar5212StopTxDma()
651 /* Give at least 1 millisec more to wait */ in ar5212StopTxDma()
655 while (ar5212NumTxPending(ah, q)) { in ar5212StopTxDma()
677 ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
678 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
679 (1<<HAL_PKT_TYPE_BEACON))
680 #define isValidPktType(_t) ((1<<(_t)) & VALID_PKT_TYPES)
682 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
683 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
684 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
685 #define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES)
866 ds->ds_hw[1] = __bswap32(ds->ds_hw[1]); in ar5212SwapTxDesc()
912 case 1: in ar5212ProcTxDesc()
939 case 1: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries0); in ar5212ProcTxDesc()
942 ts->ts_antenna = (ads->ds_txstatus1 & AR_XmitAtenna ? 2 : 1); in ar5212ProcTxDesc()
967 rates[1] = MS(ads->ds_ctl3, AR_XmitRate1); in ar5212GetTxCompletionRates()
972 tries[1] = MS(ads->ds_ctl2, AR_XmitDataTries1); in ar5212GetTxCompletionRates()