Lines Matching refs:ah
36 ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac) in ar5212GetMacAddress() argument
38 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212GetMacAddress()
44 ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac) in ar5212SetMacAddress() argument
46 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212SetMacAddress()
53 ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask) in ar5212GetBssIdMask() argument
55 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212GetBssIdMask()
61 ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask) in ar5212SetBssIdMask() argument
63 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212SetBssIdMask()
68 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); in ar5212SetBssIdMask()
69 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); in ar5212SetBssIdMask()
77 ar5212SetRegulatoryDomain(struct ath_hal *ah, in ar5212SetRegulatoryDomain() argument
82 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) { in ar5212SetRegulatoryDomain()
86 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) { in ar5212SetRegulatoryDomain()
91 if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) { in ar5212SetRegulatoryDomain()
92 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5212SetRegulatoryDomain()
95 AH_PRIVATE(ah)->ah_currentRD = regDomain; in ar5212SetRegulatoryDomain()
113 ar5212GetWirelessModes(struct ath_hal *ah) in ar5212GetWirelessModes() argument
117 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { in ar5212GetWirelessModes()
119 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) in ar5212GetWirelessModes()
121 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate) in ar5212GetWirelessModes()
123 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate) in ar5212GetWirelessModes()
126 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) in ar5212GetWirelessModes()
128 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && in ar5212GetWirelessModes()
129 AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { in ar5212GetWirelessModes()
131 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) in ar5212GetWirelessModes()
133 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate) in ar5212GetWirelessModes()
135 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate) in ar5212GetWirelessModes()
147 ar5212EnableRfKill(struct ath_hal *ah) in ar5212EnableRfKill() argument
149 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent; in ar5212EnableRfKill()
157 ath_hal_gpioCfgInput(ah, select); in ar5212EnableRfKill()
158 OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000); in ar5212EnableRfKill()
167 ath_hal_gpioSetIntr(ah, select, in ar5212EnableRfKill()
168 (ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity)); in ar5212EnableRfKill()
175 ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state) in ar5212SetLedState() argument
189 bits = OS_REG_READ(ah, AR_PCICFG); in ar5212SetLedState()
190 if (IS_2417(ah)) { in ar5212SetLedState()
207 OS_REG_WRITE(ah, AR_PCICFG, bits); in ar5212SetLedState()
217 ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId) in ar5212WriteAssocid() argument
219 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212WriteAssocid()
224 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); in ar5212WriteAssocid()
225 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) | in ar5212WriteAssocid()
233 ar5212GetTsf64(struct ath_hal *ah) in ar5212GetTsf64() argument
238 low1 = OS_REG_READ(ah, AR_TSF_L32); in ar5212GetTsf64()
239 u32 = OS_REG_READ(ah, AR_TSF_U32); in ar5212GetTsf64()
240 low2 = OS_REG_READ(ah, AR_TSF_L32); in ar5212GetTsf64()
261 ar5212GetTsf32(struct ath_hal *ah) in ar5212GetTsf32() argument
263 return OS_REG_READ(ah, AR_TSF_L32); in ar5212GetTsf32()
267 ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64) in ar5212SetTsf64() argument
269 OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); in ar5212SetTsf64()
270 OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); in ar5212SetTsf64()
277 ar5212ResetTsf(struct ath_hal *ah) in ar5212ResetTsf() argument
280 uint32_t val = OS_REG_READ(ah, AR_BEACON); in ar5212ResetTsf()
282 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF); in ar5212ResetTsf()
290 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF); in ar5212ResetTsf()
299 ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs) in ar5212SetBasicRate() argument
301 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; in ar5212SetBasicRate()
319 reg = OS_REG_READ(ah, AR_STA_ID1); in ar5212SetBasicRate()
321 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); in ar5212SetBasicRate()
323 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); in ar5212SetBasicRate()
331 ar5212GetRandomSeed(struct ath_hal *ah) in ar5212GetRandomSeed() argument
335 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; in ar5212GetRandomSeed()
338 return (OS_REG_READ(ah, AR_TSF_U32) ^ in ar5212GetRandomSeed()
339 OS_REG_READ(ah, AR_TSF_L32) ^ nf); in ar5212GetRandomSeed()
346 ar5212DetectCardPresent(struct ath_hal *ah) in ar5212DetectCardPresent() argument
356 v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; in ar5212DetectCardPresent()
359 return (AH_PRIVATE(ah)->ah_macVersion == macVersion && in ar5212DetectCardPresent()
360 AH_PRIVATE(ah)->ah_macRev == macRev); in ar5212DetectCardPresent()
364 ar5212EnableMibCounters(struct ath_hal *ah) in ar5212EnableMibCounters() argument
367 OS_REG_WRITE(ah, AR_MIBC, in ar5212EnableMibCounters()
372 ar5212DisableMibCounters(struct ath_hal *ah) in ar5212DisableMibCounters() argument
374 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC); in ar5212DisableMibCounters()
381 ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats) in ar5212UpdateMibCounters() argument
383 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); in ar5212UpdateMibCounters()
384 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); in ar5212UpdateMibCounters()
385 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); in ar5212UpdateMibCounters()
386 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); in ar5212UpdateMibCounters()
387 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); in ar5212UpdateMibCounters()
394 ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah) in ar5212IsJapanChannelSpreadSupported() argument
403 ar5212GetCurRssi(struct ath_hal *ah) in ar5212GetCurRssi() argument
405 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); in ar5212GetCurRssi()
409 ar5212GetDefAntenna(struct ath_hal *ah) in ar5212GetDefAntenna() argument
411 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); in ar5212GetDefAntenna()
415 ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna) in ar5212SetDefAntenna() argument
417 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ar5212SetDefAntenna()
421 ar5212GetAntennaSwitch(struct ath_hal *ah) in ar5212GetAntennaSwitch() argument
423 return AH5212(ah)->ah_antControl; in ar5212GetAntennaSwitch()
427 ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting) in ar5212SetAntennaSwitch() argument
429 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212SetAntennaSwitch()
430 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; in ar5212SetAntennaSwitch()
438 return ar5212SetAntennaSwitchInternal(ah, setting, chan); in ar5212SetAntennaSwitch()
442 ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah) in ar5212IsSleepAfterBeaconBroken() argument
448 ar5212SetSifsTime(struct ath_hal *ah, u_int us) in ar5212SetSifsTime() argument
450 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212SetSifsTime()
452 if (us > ath_hal_mac_usec(ah, 0xffff)) { in ar5212SetSifsTime()
453 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n", in ar5212SetSifsTime()
459 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2)); in ar5212SetSifsTime()
466 ar5212GetSifsTime(struct ath_hal *ah) in ar5212GetSifsTime() argument
468 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff; in ar5212GetSifsTime()
469 return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */ in ar5212GetSifsTime()
473 ar5212SetSlotTime(struct ath_hal *ah, u_int us) in ar5212SetSlotTime() argument
475 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212SetSlotTime()
477 if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) { in ar5212SetSlotTime()
478 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n", in ar5212SetSlotTime()
484 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us)); in ar5212SetSlotTime()
491 ar5212GetSlotTime(struct ath_hal *ah) in ar5212GetSlotTime() argument
493 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff; in ar5212GetSlotTime()
494 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ in ar5212GetSlotTime()
498 ar5212SetAckTimeout(struct ath_hal *ah, u_int us) in ar5212SetAckTimeout() argument
500 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212SetAckTimeout()
502 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { in ar5212SetAckTimeout()
503 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n", in ar5212SetAckTimeout()
509 OS_REG_RMW_FIELD(ah, AR_TIME_OUT, in ar5212SetAckTimeout()
510 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us)); in ar5212SetAckTimeout()
517 ar5212GetAckTimeout(struct ath_hal *ah) in ar5212GetAckTimeout() argument
519 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); in ar5212GetAckTimeout()
520 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ in ar5212GetAckTimeout()
524 ar5212GetAckCTSRate(struct ath_hal *ah) in ar5212GetAckCTSRate() argument
526 return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0); in ar5212GetAckCTSRate()
530 ar5212SetAckCTSRate(struct ath_hal *ah, u_int high) in ar5212SetAckCTSRate() argument
532 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212SetAckCTSRate()
535 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB); in ar5212SetAckCTSRate()
538 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB); in ar5212SetAckCTSRate()
545 ar5212SetCTSTimeout(struct ath_hal *ah, u_int us) in ar5212SetCTSTimeout() argument
547 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212SetCTSTimeout()
549 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { in ar5212SetCTSTimeout()
550 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n", in ar5212SetCTSTimeout()
556 OS_REG_RMW_FIELD(ah, AR_TIME_OUT, in ar5212SetCTSTimeout()
557 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us)); in ar5212SetCTSTimeout()
564 ar5212GetCTSTimeout(struct ath_hal *ah) in ar5212GetCTSTimeout() argument
566 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS); in ar5212GetCTSTimeout()
567 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */ in ar5212GetCTSTimeout()
572 ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en) in ar5212SetDecompMask() argument
574 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212SetDecompMask()
578 OS_REG_WRITE(ah, AR_DCM_A, keyidx); in ar5212SetDecompMask()
579 OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0); in ar5212SetDecompMask()
587 ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now) in ar5212SetCoverageClass() argument
592 AH_PRIVATE(ah)->ah_coverageClass = coverageclass; in ar5212SetCoverageClass()
595 if (AH_PRIVATE(ah)->ah_coverageClass == 0) in ar5212SetCoverageClass()
599 if (!IEEE80211_IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan)) in ar5212SetCoverageClass()
603 clkRate = ath_hal_mac_clks(ah, 1); in ar5212SetCoverageClass()
608 if (IEEE80211_IS_CHAN_HALF(AH_PRIVATE(ah)->ah_curchan)) { in ar5212SetCoverageClass()
611 } else if (IEEE80211_IS_CHAN_QUARTER(AH_PRIVATE(ah)->ah_curchan)) { in ar5212SetCoverageClass()
628 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot); in ar5212SetCoverageClass()
629 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs); in ar5212SetCoverageClass()
630 OS_REG_WRITE(ah, AR_TIME_OUT, in ar5212SetCoverageClass()
637 ar5212SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration, in ar5212SetQuiet() argument
640 OS_REG_WRITE(ah, AR_QUIET2, period | (duration << AR_QUIET2_QUIET_DUR_S)); in ar5212SetQuiet()
642 OS_REG_WRITE(ah, AR_QUIET1, nextStart | (1 << 16)); in ar5212SetQuiet()
645 OS_REG_WRITE(ah, AR_QUIET1, nextStart); in ar5212SetQuiet()
651 ar5212SetPCUConfig(struct ath_hal *ah) in ar5212SetPCUConfig() argument
653 ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode); in ar5212SetPCUConfig()
663 ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode) in ar5212Use32KHzclock() argument
666 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212Use32KHzclock()
667 return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) && in ar5212Use32KHzclock()
681 ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode) in ar5212SetupClock() argument
683 if (ar5212Use32KHzclock(ah, opmode)) { in ar5212SetupClock()
689 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); in ar5212SetupClock()
690 OS_REG_WRITE(ah, AR_PHY_REFCLKPD, in ar5212SetupClock()
691 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18); in ar5212SetupClock()
692 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1); in ar5212SetupClock()
693 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */ in ar5212SetupClock()
694 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1); in ar5212SetupClock()
696 if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) { in ar5212SetupClock()
697 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x26); in ar5212SetupClock()
698 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0d); in ar5212SetupClock()
699 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x07); in ar5212SetupClock()
700 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x3f); in ar5212SetupClock()
702 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2); in ar5212SetupClock()
704 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0a); in ar5212SetupClock()
705 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c); in ar5212SetupClock()
706 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03); in ar5212SetupClock()
707 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x20); in ar5212SetupClock()
708 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3); in ar5212SetupClock()
711 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0); in ar5212SetupClock()
712 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0); in ar5212SetupClock()
714 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32MHz TSF inc */ in ar5212SetupClock()
716 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); in ar5212SetupClock()
717 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f); in ar5212SetupClock()
719 if (IS_2417(ah)) in ar5212SetupClock()
720 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a); in ar5212SetupClock()
721 else if (IS_HB63(ah)) in ar5212SetupClock()
722 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32); in ar5212SetupClock()
724 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); in ar5212SetupClock()
725 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c); in ar5212SetupClock()
726 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff); in ar5212SetupClock()
727 OS_REG_WRITE(ah, AR_PHY_REFCLKPD, in ar5212SetupClock()
728 IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18); in ar5212SetupClock()
729 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, in ar5212SetupClock()
730 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31); in ar5212SetupClock()
738 ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode) in ar5212RestoreClock() argument
740 if (ar5212Use32KHzclock(ah, opmode)) { in ar5212RestoreClock()
742 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0); in ar5212RestoreClock()
743 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0); in ar5212RestoreClock()
745 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */ in ar5212RestoreClock()
746 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, in ar5212RestoreClock()
747 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31); in ar5212RestoreClock()
752 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f); in ar5212RestoreClock()
753 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f); in ar5212RestoreClock()
754 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); in ar5212RestoreClock()
755 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c); in ar5212RestoreClock()
756 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff); in ar5212RestoreClock()
757 OS_REG_WRITE(ah, AR_PHY_REFCLKPD, in ar5212RestoreClock()
758 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18); in ar5212RestoreClock()
767 ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c) in ar5212GetNfAdjust() argument
793 ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, in ar5212GetCapability() argument
796 #define MACVERSION(ah) AH_PRIVATE(ah)->ah_macVersion in ar5212GetCapability() argument
797 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212GetCapability()
798 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; in ar5212GetCapability()
837 return MACVERSION(ah) > AR_SREV_VERSION_VENICE || in ar5212GetCapability()
838 (MACVERSION(ah) == AR_SREV_VERSION_VENICE && in ar5212GetCapability()
839 AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP; in ar5212GetCapability()
847 *result = OS_REG_READ(ah, AR_PHY_RESTART); in ar5212GetCapability()
853 *result = AH_PRIVATE(ah)->ah_diagreg; in ar5212GetCapability()
866 return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ? in ar5212GetCapability()
869 return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) || in ar5212GetCapability()
870 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ? in ar5212GetCapability()
910 ani = ar5212AniGetCurrentState(ah); in ar5212GetCapability()
924 return ath_hal_getcapability(ah, type, capability, result); in ar5212GetCapability()
930 ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, in ar5212SetCapability() argument
934 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212SetCapability()
935 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; in ar5212SetCapability()
954 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); in ar5212SetCapability()
963 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); in ar5212SetCapability()
968 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); in ar5212SetCapability()
977 v = OS_REG_READ(ah, AR_PHY_RESTART); in ar5212SetCapability()
980 OS_REG_WRITE(ah, AR_PHY_RESTART, v); in ar5212SetCapability()
991 AH_PRIVATE(ah)->ah_diagreg = setting; in ar5212SetCapability()
992 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); in ar5212SetCapability()
1015 OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC); in ar5212SetCapability()
1030 AH5212(ah)->ah_aniControl(ah, cmds[capability], setting) : in ar5212SetCapability()
1043 return ath_hal_setcapability(ah, type, capability, in ar5212SetCapability()
1050 ar5212GetDiagState(struct ath_hal *ah, int request, in ar5212GetDiagState() argument
1054 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212GetDiagState()
1058 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) in ar5212GetDiagState()
1066 return ath_hal_eepromDiag(ah, request, in ar5212GetDiagState()
1082 *result = ar5212AniGetCurrentState(ah); in ar5212GetDiagState()
1088 astats = ar5212AniGetCurrentStats(ah); in ar5212GetDiagState()
1101 AH5212(ah)->ah_aniControl(ah, ((const uint32_t *)args)[0], in ar5212GetDiagState()
1112 ar5212AniGetCurrentState(ah); in ar5212GetDiagState()
1121 return ar5212AniSetParams(ah, args, args); in ar5212GetDiagState()
1135 ar5212IsNFCalInProgress(struct ath_hal *ah) in ar5212IsNFCalInProgress() argument
1137 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) in ar5212IsNFCalInProgress()
1150 ar5212WaitNFCalComplete(struct ath_hal *ah, int i) in ar5212WaitNFCalComplete() argument
1156 if (! ar5212IsNFCalInProgress(ah)) in ar5212WaitNFCalComplete()
1164 ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) in ar5212EnableDfs() argument
1167 val = OS_REG_READ(ah, AR_PHY_RADAR_0); in ar5212EnableDfs()
1194 if (IS_5413(ah)) { in ar5212EnableDfs()
1196 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1199 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1203 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1206 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1210 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1213 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1217 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1220 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1224 OS_REG_SET_BIT(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1227 OS_REG_CLR_BIT(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1231 OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1235 OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1239 OS_REG_RMW_FIELD(ah, AR_PHY_RADAR_2, in ar5212EnableDfs()
1243 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar5212EnableDfs()
1268 ar5212GetDfsDefaultThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) in ar5212GetDfsDefaultThresh() argument
1271 if (IS_5413(ah)) { in ar5212GetDfsDefaultThresh()
1305 ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe) in ar5212GetDfsThresh() argument
1309 val = OS_REG_READ(ah, AR_PHY_RADAR_0); in ar5212GetDfsThresh()
1330 if (IS_5413(ah)) { in ar5212GetDfsThresh()
1331 val = OS_REG_READ(ah, AR_PHY_RADAR_2); in ar5212GetDfsThresh()
1349 ar5212ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs, in ar5212ProcessRadarEvent() argument
1377 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, dur=%d\n", in ar5212ProcessRadarEvent()
1395 ar5212IsFastClockEnabled(struct ath_hal *ah) in ar5212IsFastClockEnabled() argument
1405 ar5212Get11nExtBusy(struct ath_hal *ah) in ar5212Get11nExtBusy() argument
1414 ar5212GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample) in ar5212GetMibCycleCounts() argument
1416 struct ath_hal_5212 *ahp = AH5212(ah); in ar5212GetMibCycleCounts()
1420 uint32_t rc = OS_REG_READ(ah, AR_RCCNT); in ar5212GetMibCycleCounts()
1421 uint32_t rf = OS_REG_READ(ah, AR_RFCNT); in ar5212GetMibCycleCounts()
1422 uint32_t tf = OS_REG_READ(ah, AR_TFCNT); in ar5212GetMibCycleCounts()
1423 uint32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ in ar5212GetMibCycleCounts()
1431 HALDEBUG(ah, HAL_DEBUG_ANY, in ar5212GetMibCycleCounts()
1455 ar5212SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask, in ar5212SetChainMasks() argument
1466 ar5212GetNav(struct ath_hal *ah) in ar5212GetNav() argument
1470 reg = OS_REG_READ(ah, AR_NAV); in ar5212GetNav()
1481 ar5212SetNav(struct ath_hal *ah, u_int val) in ar5212SetNav() argument
1484 OS_REG_WRITE(ah, AR_NAV, val); in ar5212SetNav()