Lines Matching full:mask
55 #define AR_IMR 0x00a0 /* Primary interrupt mask register */
56 #define AR_IMR_S0 0x00a4 /* Secondary interrupt mask reg 0 */
57 #define AR_IMR_S1 0x00a8 /* Secondary interrupt mask reg 1 */
58 #define AR_IMR_S2 0x00ac /* Secondary interrupt mask reg 2 */
59 #define AR_IMR_S3 0x00b0 /* Secondary interrupt mask reg 3 */
60 #define AR_IMR_S4 0x00b4 /* Secondary interrupt mask reg 4 */
136 #define AR_D0_QCUMASK 0x1000 /* QCU Mask */
137 #define AR_D1_QCUMASK 0x1004 /* QCU Mask */
138 #define AR_D2_QCUMASK 0x1008 /* QCU Mask */
139 #define AR_D3_QCUMASK 0x100c /* QCU Mask */
140 #define AR_D4_QCUMASK 0x1010 /* QCU Mask */
141 #define AR_D5_QCUMASK 0x1014 /* QCU Mask */
142 #define AR_D6_QCUMASK 0x1018 /* QCU Mask */
143 #define AR_D7_QCUMASK 0x101c /* QCU Mask */
144 #define AR_D8_QCUMASK 0x1020 /* QCU Mask */
145 #define AR_D9_QCUMASK 0x1024 /* QCU Mask */
287 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_M 0x00060000 /* Mask of PCI core master request queue full t…
323 #define AR_TXCFG_FTRIG_M 0x000003F0 /* Mask for Frame trigger level */
343 #define AR_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
345 #define AR_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */
347 #define AR_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */
348 #define AR_TXNPTO_QCU_MASK 0x03FFFC00 /* Mask indicating the set of QCUs */
352 #define AR_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */
354 #define AR_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */
356 #define AR_MACMISC_DMA_OBS_M 0x000001E0 /* Mask for DMA observation bus mux select */
358 #define AR_MACMISC_MISC_OBS_M 0x00000E00 /* Mask for MISC observation bus mux select */
360 #define AR_MACMISC_MAC_OBS_BUS_LSB_M 0x00007000 /* Mask for MAC observation bus mux select (lsb) */
362 #define AR_MACMISC_MAC_OBS_BUS_MSB_M 0x00038000 /* Mask for MAC observation bus mux select (msb) */
366 #define AR5311_QDCLKGATE_QCU_M 0x0000FFFF /* Mask for QCU clock disable */
367 #define AR5311_QDCLKGATE_DCU_M 0x07FF0000 /* Mask for DCU clock disable */
398 #define AR_ISR_S0_QCU_TXOK_M 0x000003FF /* Mask for TXOK (QCU 0-9) */
399 #define AR_ISR_S0_QCU_TXDESC_M 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
401 #define AR_ISR_S1_QCU_TXERR_M 0x000003FF /* Mask for TXERR (QCU 0-9) */
402 #define AR_ISR_S1_QCU_TXEOL_M 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
404 #define AR_ISR_S2_QCU_TXURN_M 0x000003FF /* Mask for TXURN (QCU 0-9) */
410 #define AR_ISR_S3_QCU_QCBROVF_M 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
411 #define AR_ISR_S3_QCU_QCBRURN_M 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
413 #define AR_ISR_S4_QCU_QTRIG_M 0x000003FF /* Mask for QTRIG (QCU 0-9) */
416 /* Interrupt Mask Registers */
445 #define AR_IMR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */
447 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
450 #define AR_IMR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */
452 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
455 #define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */
462 #define AR_IMR_S3_QCU_QCBROVF_M 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
463 #define AR_IMR_S3_QCU_QCBRURN_M 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
466 #define AR_IMR_S4_QCU_QTRIG_M 0x000003FF /* Mask for QTRIG (QCU 0-9) */
484 #define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */
486 #define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */
488 #define AR_Q_CBRCFG_CBR_INTERVAL 0x00FFFFFF /* Mask for CBR interval (us) */
490 #define AR_Q_CBRCFG_CBR_OVF_THRESH 0xFF000000 /* Mask for CBR overflow threshold */
495 #define AR_Q_RDYTIMECFG_DURATION_M 0x00FFFFFF /* Mask for CBR interval (us) */
499 #define AR_Q_ONESHOTARM_SC_M 0x0000FFFF /* Mask for MAC_Q_ONESHOTARM_SC (QCU 0-15) */
502 #define AR_Q_ONESHOTARM_CC_M 0x0000FFFF /* Mask for MAC_Q_ONESHOTARM_CC (QCU 0-15) */
505 #define AR_Q_MISC_FSP_M 0x0000000F /* Mask for Frame Scheduling Policy */
523 #define AR_Q_STS_PEND_FR_CNT_M 0x00000003 /* Mask for Pending Frame Count */
525 #define AR_Q_STS_CBR_EXP_CNT_M 0x0000FF00 /* Mask for CBR expired counter */
528 #define AR_Q_RDYTIMESHDN_M 0x000003FF /* Mask for ReadyTimeShutdown status (QCU 0-9) */
543 #define AR_D_QCUMASK_M 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
546 #define AR_D_LCL_IFS_CWMIN 0x000003FF /* Mask for CW_MIN */
548 #define AR_D_LCL_IFS_CWMAX 0x000FFC00 /* Mask for CW_MAX */
550 #define AR_D_LCL_IFS_AIFS 0x0FF00000 /* Mask for AIFS */
554 #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F /* Mask for frame short retry limit */
556 #define AR_D_RETRY_LIMIT_FR_LG 0x000000F0 /* Mask for frame long retry limit */
558 #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 /* Mask for station short retry limit */
560 #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 /* Mask for station short retry limit */
566 #define AR_D_CHNTIME_DUR 0x000FFFFF /* Mask for ChannelTime duration (us) */
569 #define AR_D_MISC_BKOFF_THRESH_M 0x000007FF /* Mask for Backoff threshold setting */
574 #define AR_D_MISC_VIR_COL_HANDLING_M 0x0000C000 /* Mask for Virtual collision handling policy */
579 #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 /* Mask for DCU arbiter lockout control */
593 #define AR_D_SEQNUM_M 0x00000FFF /* Mask for value of sequence number */
596 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 /* Mask forLFSR slice select */
598 #define AR_D_GBL_IFS_MISC_SIFS_DURATION_USEC 0x000003F0 /* Mask for SIFS duration (us) */
599 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 /* Mask for microsecond duration */
600 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 /* Mask for DCU arbiter delay */
604 #define AR_D_TXPSE_CTRL_M 0x000003FF /* Mask of DCUs to pause (DCUs 0-9) */
617 #define AR_SCR_SLDUR 0x0000ffff /* sleep duration mask, units of 128us */
619 #define AR_SCR_SLE 0x00030000 /* sleep enable mask */
644 #define AR_PCICFG_EEPROM_SIZE_M 0x00000018 /* Mask for EEPROM size */
645 #define AR_PCICFG_EEPROM_SIZE_S 3 /* Mask for EEPROM size */
654 #define AR_PCICFG_PCI_BUS_SEL_M 0x00000380 /* Mask for PCI observation bus mux select */
660 #define AR_PCICFG_SPWR_DN 0x00010000 /* mask for sleep/awake indication */
698 #define AR_GPIOCR_INT_MASK 0x00007000 /* Interrupt select field mask */
709 #define AR_SREV_ID_M 0x000000FF /* Mask to read SREV info */
743 #define AR_EEPROM_CFG_SIZE_M 0x00000003 /* Mask for EEPROM size determination override */
749 #define AR_EEPROM_CFG_CLOCK_M 0x00000018 /* Mask for EEPROM clock rate control */
755 #define AR_EEPROM_CFG_PROT_KEY_M 0x00FFFF00 /* Mask for EEPROM protection key */
760 #define AR_STA_ID1_SADH_MASK 0x0000FFFF /* Mask for upper 16 bits of MAC addr */
774 #define AR_BSS_ID1_U16_M 0x0000FFFF /* Mask for upper 16 bits of BSSID */
775 #define AR_BSS_ID1_AID_M 0xFFFF0000 /* Mask for association ID */
778 #define AR_SLOT_TIME_MASK 0x000007FF /* Slot time mask */
780 #define AR_TIME_OUT_ACK 0x00001FFF /* Mask for ACK time-out */
782 #define AR_TIME_OUT_CTS 0x1FFF0000 /* Mask for CTS time-out */
785 #define AR_RSSI_THR_MASK 0x000000FF /* Mask for Beacon RSSI warning threshold */
786 #define AR_RSSI_THR_BM_THR 0x0000FF00 /* Mask for Missed beacon threshold */
789 #define AR_USEC_M 0x0000007F /* Mask for clock cycles in 1 usec */
790 #define AR_USEC_32_M 0x00003F80 /* Mask for number of 32MHz clock cycles in 1 usec */
839 #define AR_DIAG_SW_SCRAM_SEED_M 0x0001FC00 /* Fixed scrambler seed mask */