Lines Matching full:cbr

84 #define	AR_Q0_CBRCFG	0x08c0		/* CBR configuration */
85 #define	AR_Q1_CBRCFG	0x08c4		/* CBR configuration */
86 #define	AR_Q2_CBRCFG	0x08c8		/* CBR configuration */
87 #define	AR_Q3_CBRCFG	0x08cc		/* CBR configuration */
88 #define	AR_Q4_CBRCFG	0x08d0		/* CBR configuration */
89 #define	AR_Q5_CBRCFG	0x08d4		/* CBR configuration */
90 #define	AR_Q6_CBRCFG	0x08d8		/* CBR configuration */
91 #define	AR_Q7_CBRCFG	0x08dc		/* CBR configuration */
92 #define	AR_Q8_CBRCFG	0x08e0		/* CBR configuration */
93 #define	AR_Q9_CBRCFG	0x08e4		/* CBR configuration */
393 #define	AR_ISR_QCBROVF	0x02000000	/* QCU CBR overflow interrupt */
394 #define	AR_ISR_QCBRURN	0x04000000	/* QCU CBR underrun interrupt */
440 #define	AR_IMR_QCBROVF	0x02000000	/* QCU CBR overflow interrupt */
441 #define	AR_IMR_QCBRURN	0x04000000	/* QCU CBR underrun interrupt */
488 #define	AR_Q_CBRCFG_CBR_INTERVAL	0x00FFFFFF	/* Mask for CBR interval (us) */
489 #define	AR_Q_CBRCFG_CBR_INTERVAL_S		0	/* Shift for CBR interval */
490 #define	AR_Q_CBRCFG_CBR_OVF_THRESH	0xFF000000	/* Mask for CBR overflow threshold */
493 #define	AR_Q_RDYTIMECFG_INT	0x00FFFFFF 	/* CBR interval (us) */
495 #define	AR_Q_RDYTIMECFG_DURATION_M	0x00FFFFFF	/* Mask for CBR interval (us) */
507 #define	AR_Q_MISC_FSP_CBR		1	/* CBR */
512 #define	AR_Q_MISC_CBR_INCR_DIS1	0x00000020	/* Disable CBR expired counter
514 #define	AR_Q_MISC_CBR_INCR_DIS0	0x00000040	/* Disable CBR expired counter
517 #define	AR_Q_MISC_CBR_EXP_CNTR_LIMIT	0x00000100	/* CBR expired counter limit enable */
519 #define	AR_Q_MISC_RESET_CBR_EXP_CTR	0x00000400	/* Reset CBR expired counter */
525 #define	AR_Q_STS_CBR_EXP_CNT_M	0x0000FF00	/* Mask for CBR expired counter */