Lines Matching +full:dma +full:- +full:33 +full:bits
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
24 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
33 /* DMA Registers */
68 #define AR_STA_ID0 0x8000 /* Lower 32bits of MAC address */
69 #define AR_STA_ID1 0x8004 /* Upper 16bits of MAC address */
70 #define AR_BSS_ID0 0x8008 /* Lower 32bits of BSSID */
71 #define AR_BSS_ID1 0x800c /* Upper 16bits of BSSID */
72 #define AR_SLOT_TIME 0x8010 /* Length of a back-off */
80 #define AR_TIMER1 0x8030 /* Next DMA beacon alert time */
87 #define AR_MCAST_FIL0 0x8050 /* Lower 32bits of mcast filter mask */
88 #define AR_MCAST_FIL1 0x8054 /* Upper 16bits of mcast filter mask */
89 #define AR_TX_MASK0 0x8058 /* Lower 32bits of TX mask */
90 #define AR_TX_MASK1 0x805c /* Upper 16bits of TX mask */
94 #define AR_TSF_L32 0x806c /* Lower 32bits of local clock */
95 #define AR_TSF_U32 0x8070 /* Upper 32bits of local clock */
96 #define AR_LAST_TSTP 0x8080 /* Lower 32bits of last beacon tstamp */
98 #define AR_BACKOFF 0x8088 /* Back-off status */
126 #define AR_CFG_TXFSTAT 0x00008000 /* TX DMA status */
127 #define AR_CFG_TXFSTRT 0x00010000 /* re-enable TX DMA */
184 #define AR_IER_DISABLE 0x00000000 /* pseudo-flag */
189 #define AR_BCR_BDMAE 0x00000002 /* beacon DMA enable */
190 #define AR_BCR_TQ1FV 0x00000004 /* use TXQ1 for non-beacon */
196 #define AR_BSR_BDLYDMA 0x00000002 /* DMA beacon delay */
209 #define AR_TXCFG_SDMAMR 0x00000007 /* DMA burst size 2^(2+x) */
210 #define AR_TXCFG_TXFSTP 0x00000008 /* Stop TX DMA on filtered */
211 #define AR_TXCFG_TXFULL 0x00000070 /* TX DMA desc Q full thresh */
215 #define AR_RXCFG_SDMAMW 0x00000007 /* DMA burst size 2^(2+x) */
216 #define AR_RXCFG_ZLFDMA 0x00000010 /* enable zero length DMA */
218 /* DMA sizes used for both AR_TXCFG_SDMAMR and AR_RXCFG_SDMAMW */
219 #define AR_DMASIZE_4B 0 /* DMA size 4 bytes */
220 #define AR_DMASIZE_8B 1 /* DMA size 8 bytes */
221 #define AR_DMASIZE_16B 2 /* DMA size 16 bytes */
222 #define AR_DMASIZE_32B 3 /* DMA size 32 bytes */
223 #define AR_DMASIZE_64B 4 /* DMA size 64 bytes */
224 #define AR_DMASIZE_128B 5 /* DMA size 128 bytes */
225 #define AR_DMASIZE_256B 6 /* DMA size 256 bytes */
226 #define AR_DMASIZE_512B 7 /* DMA size 512 bytes */
239 #define AR_RC_RDMA 0x00000002 /* DMA Warm Reset */
255 * However, these have been pre-shifted with AR_SCR_SLE_S. The
257 * shifting out any of the set bits completely.
281 #define AR_GPIOCR_IN(n) (0<<((n)*2)) /* input-only */
282 #define AR_GPIOCR_OUT0(n) (1<<((n)*2)) /* output-only if GPIODO = 0 */
283 #define AR_GPIOCR_OUT1(n) (2<<((n)*2)) /* output-only if GPIODO = 1 */
285 #define AR_GPIOCR_ALL(n) (3<<((n)*2)) /* all bits for pin */
306 #define AR_STA_ID1_NO_PSPOLL 0x00100000 /* auto PS-POLL disable */
400 #define AR_KEYTABLE_KEY0(n) (AR_KEYTABLE(n) + 0) /* key bit 0-31 */
401 #define AR_KEYTABLE_KEY1(n) (AR_KEYTABLE(n) + 4) /* key bit 32-47 */
402 #define AR_KEYTABLE_KEY2(n) (AR_KEYTABLE(n) + 8) /* key bit 48-79 */
403 #define AR_KEYTABLE_KEY3(n) (AR_KEYTABLE(n) + 12) /* key bit 80-95 */
404 #define AR_KEYTABLE_KEY4(n) (AR_KEYTABLE(n) + 16) /* key bit 96-127 */
409 #define AR_KEYTABLE_MAC0(n) (AR_KEYTABLE(n) + 24) /* MAC address 1-32 */
410 #define AR_KEYTABLE_MAC1(n) (AR_KEYTABLE(n) + 28) /* MAC address 33-47 */