34 ar5210GetMacAddress(struct ath_hal *ah, uint8_t *mac)  in ar5210GetMacAddress()  argument
36 	struct ath_hal_5210 *ahp = AH5210(ah);  in ar5210GetMacAddress()
42 ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *mac)  in ar5210SetMacAddress()  argument
44 	struct ath_hal_5210 *ahp = AH5210(ah);  in ar5210SetMacAddress()
51 ar5210GetBssIdMask(struct ath_hal *ah, uint8_t *mask)  in ar5210GetBssIdMask()  argument
59 ar5210SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)  in ar5210SetBssIdMask()  argument
68 ar5210EepromRead(struct ath_hal *ah, u_int off, uint16_t *data)  in ar5210EepromRead()  argument
70 	(void) OS_REG_READ(ah, AR_EP_AIR(off));	/* activate read op */  in ar5210EepromRead()
71 	if (!ath_hal_wait(ah, AR_EP_STA,  in ar5210EepromRead()
73 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: read failed for entry 0x%x\n",  in ar5210EepromRead()
77 	*data = OS_REG_READ(ah, AR_EP_RDATA) & 0xffff;  in ar5210EepromRead()
86 ar5210EepromWrite(struct ath_hal *ah, u_int off, uint16_t data)  in ar5210EepromWrite()  argument
96 ar5210SetRegulatoryDomain(struct ath_hal *ah,  in ar5210SetRegulatoryDomain()  argument
101 	if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {  in ar5210SetRegulatoryDomain()
110 	if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {  in ar5210SetRegulatoryDomain()
129 ar5210GetWirelessModes(struct ath_hal *ah)  in ar5210GetWirelessModes()  argument
140 ar5210EnableRfKill(struct ath_hal *ah)  in ar5210EnableRfKill()  argument
142 	uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;  in ar5210EnableRfKill()
154 	ar5210Gpio0SetIntr(ah, select, (ar5210GpioGet(ah, select) == polarity));  in ar5210EnableRfKill()
161 ar5210GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, HAL_GPIO_MUX_TYPE type)  in ar5210GpioCfgOutput()  argument
165 	OS_REG_WRITE(ah, AR_GPIOCR,   in ar5210GpioCfgOutput()
166 		  (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))  in ar5210GpioCfgOutput()
176 ar5210GpioCfgInput(struct ath_hal *ah, uint32_t gpio)  in ar5210GpioCfgInput()  argument
180 	OS_REG_WRITE(ah, AR_GPIOCR,   in ar5210GpioCfgInput()
181 		  (OS_REG_READ(ah, AR_GPIOCR) &~ AR_GPIOCR_ALL(gpio))  in ar5210GpioCfgInput()
191 ar5210GpioSet(struct ath_hal *ah, uint32_t gpio, uint32_t val)  in ar5210GpioSet()  argument
197 	reg =  OS_REG_READ(ah, AR_GPIODO);  in ar5210GpioSet()
201 	OS_REG_WRITE(ah, AR_GPIODO, reg);  in ar5210GpioSet()
209 ar5210GpioGet(struct ath_hal *ah, uint32_t gpio)  in ar5210GpioGet()  argument
212 		uint32_t val = OS_REG_READ(ah, AR_GPIODI);  in ar5210GpioGet()
224 ar5210Gpio0SetIntr(struct ath_hal *ah, u_int gpio, uint32_t ilevel)  in ar5210Gpio0SetIntr()  argument
226 	uint32_t val = OS_REG_READ(ah, AR_GPIOCR);  in ar5210Gpio0SetIntr()
237 	OS_REG_WRITE(ah, AR_GPIOCR, val);  in ar5210Gpio0SetIntr()
240 	ar5210SetInterrupts(ah, AH5210(ah)->ah_maskReg | HAL_INT_GPIO);  in ar5210Gpio0SetIntr()
247 ar5210SetLedState(struct ath_hal *ah, HAL_LED_STATE state)  in ar5210SetLedState()  argument
251 	val = OS_REG_READ(ah, AR_PCICFG);  in ar5210SetLedState()
266 	OS_REG_WRITE(ah, AR_PCICFG, val);  in ar5210SetLedState()
273 ar5210GetDefAntenna(struct ath_hal *ah)  in ar5210GetDefAntenna()  argument
275 	uint32_t val = OS_REG_READ(ah, AR_STA_ID1);  in ar5210GetDefAntenna()
280 ar5210SetDefAntenna(struct ath_hal *ah, u_int antenna)  in ar5210SetDefAntenna()  argument
282 	uint32_t val = OS_REG_READ(ah, AR_STA_ID1);  in ar5210SetDefAntenna()
288 		OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_DEFAULT_ANTENNA);  in ar5210SetDefAntenna()
293 ar5210GetAntennaSwitch(struct ath_hal *ah)  in ar5210GetAntennaSwitch()  argument
299 ar5210SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)  in ar5210SetAntennaSwitch()  argument
312 ar5210WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)  in ar5210WriteAssocid()  argument
314 	struct ath_hal_5210 *ahp = AH5210(ah);  in ar5210WriteAssocid()
319 	OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));  in ar5210WriteAssocid()
320 	OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |  in ar5210WriteAssocid()
323 		OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);  in ar5210WriteAssocid()
325 		OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_NO_PSPOLL);  in ar5210WriteAssocid()
332 ar5210GetTsf64(struct ath_hal *ah)  in ar5210GetTsf64()  argument
337 	low1 = OS_REG_READ(ah, AR_TSF_L32);  in ar5210GetTsf64()
338 	u32 = OS_REG_READ(ah, AR_TSF_U32);  in ar5210GetTsf64()
339 	low2 = OS_REG_READ(ah, AR_TSF_L32);  in ar5210GetTsf64()
360 ar5210GetTsf32(struct ath_hal *ah)  in ar5210GetTsf32()  argument
362 	return OS_REG_READ(ah, AR_TSF_L32);  in ar5210GetTsf32()
369 ar5210ResetTsf(struct ath_hal *ah)  in ar5210ResetTsf()  argument
371 	uint32_t val = OS_REG_READ(ah, AR_BEACON);  in ar5210ResetTsf()
373 	OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);  in ar5210ResetTsf()
381 ar5210GetRandomSeed(struct ath_hal *ah)  in ar5210GetRandomSeed()  argument
385 	nf = (OS_REG_READ(ah, AR_PHY_BASE + (25 << 2)) >> 19) & 0x1ff;  in ar5210GetRandomSeed()
388 	return (OS_REG_READ(ah, AR_TSF_U32) ^  in ar5210GetRandomSeed()
389 		OS_REG_READ(ah, AR_TSF_L32) ^ nf);  in ar5210GetRandomSeed()
396 ar5210DetectCardPresent(struct ath_hal *ah)  in ar5210DetectCardPresent()  argument
403 	return (AH_PRIVATE(ah)->ah_macRev == (OS_REG_READ(ah, AR_SREV) & 0xff));  in ar5210DetectCardPresent()
410 ar5210UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS *stats)  in ar5210UpdateMibCounters()  argument
412 	stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);  in ar5210UpdateMibCounters()
413 	stats->rts_bad	  += OS_REG_READ(ah, AR_RTS_FAIL);  in ar5210UpdateMibCounters()
414 	stats->fcs_bad	  += OS_REG_READ(ah, AR_FCS_FAIL);  in ar5210UpdateMibCounters()
415 	stats->rts_good	  += OS_REG_READ(ah, AR_RTS_OK);  in ar5210UpdateMibCounters()
416 	stats->beacons	  += OS_REG_READ(ah, AR_BEACON_CNT);  in ar5210UpdateMibCounters()
420 ar5210SetSifsTime(struct ath_hal *ah, u_int us)  in ar5210SetSifsTime()  argument
422 	struct ath_hal_5210 *ahp = AH5210(ah);  in ar5210SetSifsTime()
424 	if (us > ath_hal_mac_usec(ah, 0x7ff)) {  in ar5210SetSifsTime()
425 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",  in ar5210SetSifsTime()
431 		OS_REG_RMW_FIELD(ah, AR_IFS0, AR_IFS0_SIFS,  in ar5210SetSifsTime()
432 		    ath_hal_mac_clks(ah, us));  in ar5210SetSifsTime()
439 ar5210GetSifsTime(struct ath_hal *ah)  in ar5210GetSifsTime()  argument
441 	u_int clks = OS_REG_READ(ah, AR_IFS0) & 0x7ff;  in ar5210GetSifsTime()
442 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */  in ar5210GetSifsTime()
446 ar5210SetSlotTime(struct ath_hal *ah, u_int us)  in ar5210SetSlotTime()  argument
448 	struct ath_hal_5210 *ahp = AH5210(ah);  in ar5210SetSlotTime()
450 	if (us < HAL_SLOT_TIME_9 || us > ath_hal_mac_usec(ah, 0xffff)) {  in ar5210SetSlotTime()
451 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",  in ar5210SetSlotTime()
457 		OS_REG_WRITE(ah, AR_SLOT_TIME, ath_hal_mac_clks(ah, us));  in ar5210SetSlotTime()
464 ar5210GetSlotTime(struct ath_hal *ah)  in ar5210GetSlotTime()  argument
466 	u_int clks = OS_REG_READ(ah, AR_SLOT_TIME) & 0xffff;  in ar5210GetSlotTime()
467 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */  in ar5210GetSlotTime()
471 ar5210SetAckTimeout(struct ath_hal *ah, u_int us)  in ar5210SetAckTimeout()  argument
473 	struct ath_hal_5210 *ahp = AH5210(ah);  in ar5210SetAckTimeout()
475 	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {  in ar5210SetAckTimeout()
476 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",  in ar5210SetAckTimeout()
482 		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,  in ar5210SetAckTimeout()
483 			AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));  in ar5210SetAckTimeout()
490 ar5210GetAckTimeout(struct ath_hal *ah)  in ar5210GetAckTimeout()  argument
492 	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);  in ar5210GetAckTimeout()
493 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */  in ar5210GetAckTimeout()
497 ar5210GetAckCTSRate(struct ath_hal *ah)  in ar5210GetAckCTSRate()  argument
499 	return ((AH5210(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);  in ar5210GetAckCTSRate()
503 ar5210SetAckCTSRate(struct ath_hal *ah, u_int high)  in ar5210SetAckCTSRate()  argument
505 	struct ath_hal_5210 *ahp = AH5210(ah);  in ar5210SetAckCTSRate()
508 		OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);  in ar5210SetAckCTSRate()
511 		OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);  in ar5210SetAckCTSRate()
518 ar5210SetCTSTimeout(struct ath_hal *ah, u_int us)  in ar5210SetCTSTimeout()  argument
520 	struct ath_hal_5210 *ahp = AH5210(ah);  in ar5210SetCTSTimeout()
522 	if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {  in ar5210SetCTSTimeout()
523 		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",  in ar5210SetCTSTimeout()
529 		OS_REG_RMW_FIELD(ah, AR_TIME_OUT,  in ar5210SetCTSTimeout()
530 			AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));  in ar5210SetCTSTimeout()
537 ar5210GetCTSTimeout(struct ath_hal *ah)  in ar5210GetCTSTimeout()  argument
539 	u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);  in ar5210GetCTSTimeout()
540 	return ath_hal_mac_usec(ah, clks);	/* convert from system clocks */  in ar5210GetCTSTimeout()
544 ar5210SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)  in ar5210SetDecompMask()  argument
551 ar5210SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)  in ar5210SetCoverageClass()  argument
556 ar5210SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration,  in ar5210SetQuiet()  argument
566 ar5210AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)  in ar5210AniControl()  argument
572 ar5210RxMonitor(struct ath_hal *ah, const HAL_NODE_STATS *stats,  in ar5210RxMonitor()  argument
578 ar5210AniPoll(struct ath_hal *ah, const struct ieee80211_channel *chan)  in ar5210AniPoll()  argument
583 ar5210MibEvent(struct ath_hal *ah, const HAL_NODE_STATS *stats)  in ar5210MibEvent()  argument
588 ar5210GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,  in ar5210GetCapability()  argument
600 		return ath_hal_getcapability(ah, type, capability, result);  in ar5210GetCapability()
605 ar5210SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,  in ar5210SetCapability()  argument
617 		AH_PRIVATE(ah)->ah_diagreg = setting;  in ar5210SetCapability()
619 		AH_PRIVATE(ah)->ah_diagreg = setting & 0x6;	/* ACK+CTS */  in ar5210SetCapability()
621 		ar5210UpdateDiagReg(ah, AH_PRIVATE(ah)->ah_diagreg);  in ar5210SetCapability()
626 		return ath_hal_setcapability(ah, type, capability,  in ar5210SetCapability()
632 ar5210GetDiagState(struct ath_hal *ah, int request,  in ar5210GetDiagState()  argument
647 		pcicfg = OS_REG_READ(ah, AR_PCICFG);  in ar5210GetDiagState()
648 		OS_REG_WRITE(ah, AR_PCICFG, pcicfg | AR_PCICFG_EEPROMSEL);  in ar5210GetDiagState()
649 		ok = ath_hal_eepromRead(ah, *(const uint16_t *)args, *result);  in ar5210GetDiagState()
650 		OS_REG_WRITE(ah, AR_PCICFG, pcicfg);  in ar5210GetDiagState()
656 	return ath_hal_getdiagstate(ah, request,  in ar5210GetDiagState()
665 ar5210Get11nExtBusy(struct ath_hal *ah)  in ar5210Get11nExtBusy()  argument
675 ar5210GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)  in ar5210GetMibCycleCounts()  argument
682 ar5210SetChainMasks(struct ath_hal *ah, uint32_t txchainmask,  in ar5210SetChainMasks()  argument
688 ar5210EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)  in ar5210EnableDfs()  argument
693 ar5210GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)  in ar5210GetDfsThresh()  argument
704 ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val)  in ar5210UpdateDiagReg()  argument
709 	OS_REG_WRITE(ah, AR_DIAG_SW, val);  in ar5210UpdateDiagReg()
716 ar5210GetNav(struct ath_hal *ah)  in ar5210GetNav()  argument
720 	reg = OS_REG_READ(ah, AR_NAV);  in ar5210GetNav()
728 ar5210SetNav(struct ath_hal *ah, u_int val)  in ar5210SetNav()  argument
731 	OS_REG_WRITE(ah, AR_NAV, val);  in ar5210SetNav()