Lines Matching +full:dma +full:- +full:33 +full:bits

1 /*-
2  * SPDX-License-Identifier: ISC
4  * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5  * Copyright (c) 2002-2008 Atheros Communications, Inc.
30  * should be used only if non-zero.
55 	int8_t		ts_rssi_ctl[3];	/* tx ack RSSI [ctl, chain 0-2] */
56 	int8_t		ts_rssi_ext[3];	/* tx ack RSSI [ext, chain 0-2] */
60 /* bits found in ts_status */
67 /* bits found in ts_flags */
88  * at least 15 bits (regardless of what the h/w provides directly).
89  * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
95  * -96dBm absolute power in a 20MHz channel.
108 	int8_t		rs_rssi_ctl[3];	/* rx frame RSSI [ctl, chain 0-2] */
109 	int8_t		rs_rssi_ext[3];	/* rx frame RSSI [ext, chain 0-2] */
125 /* bits found in rs_status */
129 #define	HAL_RXERR_DECRYPT	0x08	/* non-Michael decrypt error */
134 /* bits found in rs_flags */
163 #define	HAL_RX_LNA_CFG_USED	0x30	/* 2 bits; LNA config used on RX */
165 #define	HAL_RX_LNA_CFG_MAIN	0x0c	/* 2 bits; "Main" LNA config */
166 #define	HAL_RX_LNA_CFG_ALT	0x02	/* 2 bits; "Alt" LNA config */
174 #define	HAL_RX_LNA_SWITCH_0	0x30	/* 2 bits; sw_0[1:0] */
175 #define	HAL_RX_LNA_SWITCH_COM	0x0f	/* 4 bits, sw_com[3:0] */
201 	HAL_PHYERR_CCK_POWER_DROP	= 33,	/* */
211 #define	HAL_RXKEYIX_INVALID	((uint8_t) -1)
213 #define	HAL_TXKEYIX_INVALID	((u_int) -1)
219  * the Atheros HAL.  This definition obscures hardware-specific
223  * in a device-independent format.
235 	uint32_t	ds_ctl0;	/* opaque DMA control 0 */
236 	uint32_t	ds_ctl1;	/* opaque DMA control 1 */
262 #define	HAL_TXDESC_INTREQ	0x0010	/* enable per-descriptor interrupt */
275 #define	HAL_RXDESC_INTREQ	0x0020	/* enable per-descriptor interrupt */