Lines Matching +full:0 +full:x00000010
26 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */
44 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */
60 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */
71 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
72 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
74 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
76 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
78 #define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b
80 #define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09
81 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04
82 #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09
83 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02
84 #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06
88 #define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666
90 #define HAL_BT_COEX_HELIUS_CHAINMASK 0x02
92 #define HAL_BT_COEX_LOW_ACK_POWER 0x0
93 #define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f
96 HAL_BT_COEX_NO_STOMP = 0,
160 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
161 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
162 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 /* Check Rx Diversity is allowed */
163 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 /* Check Diversity is on or off */
164 #define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010
165 #define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020
167 #define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */
170 MCI_LNA_CTRL = 0x10, /* len = 0 */
171 MCI_CONT_NACK = 0x20, /* len = 0 */
172 MCI_CONT_INFO = 0x30, /* len = 4 */
173 MCI_CONT_RST = 0x40, /* len = 0 */
174 MCI_SCHD_INFO = 0x50, /* len = 16 */
175 MCI_CPU_INT = 0x60, /* len = 4 */
176 MCI_SYS_WAKING = 0x70, /* len = 0 */
177 MCI_GPM = 0x80, /* len = 16 */
178 MCI_LNA_INFO = 0x90, /* len = 1 */
179 MCI_LNA_STATE = 0x94,
180 MCI_LNA_TAKE = 0x98,
181 MCI_LNA_TRANS = 0x9c,
182 MCI_SYS_SLEEPING = 0xa0, /* len = 0 */
183 MCI_REQ_WAKE = 0xc0, /* len = 0 */
184 MCI_DEBUG_16 = 0xfe, /* len = 2 */
185 MCI_REMOTE_RESET = 0xff /* len = 16 */
190 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
193 #define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
196 MCI_GPM_BT_CAL_REQ = 0,
202 MCI_GPM_COEX_AGENT = 0x0C,
203 MCI_GPM_RSVD_PATTERN = 0xFE,
204 MCI_GPM_RSVD_PATTERN32 = 0xFEFEFEFE,
205 MCI_GPM_BT_DEBUG = 0xFF
209 MCI_GPM_COEX_VERSION_QUERY = 0,
221 MCI_GPM_COEX_QUERY_WLAN_ALL_INFO = 0x01,
223 MCI_GPM_COEX_QUERY_BT_ALL_INFO = 0x01,
224 MCI_GPM_COEX_QUERY_BT_TOPOLOGY = 0x02,
225 MCI_GPM_COEX_QUERY_BT_DEBUG = 0x04
229 MCI_GPM_COEX_BT_GPM_UNHALT = 0,
234 MCI_GPM_COEX_PROFILE_UNKNOWN = 0,
244 MCI_GPM_COEX_PROFILE_STATE_END = 0,
249 MCI_GPM_COEX_PROFILE_SLAVE = 0,
254 MCI_GPM_COEX_BT_NONLINK_STATUS = 0,
259 MCI_GPM_COEX_BT_NORMAL_STATUS = 0,
263 #define MCI_GPM_INVALID_PROFILE_HANDLE 0xff
266 MCI_GPM_COEX_BT_FLAGS_READ = 0x00,
267 MCI_GPM_COEX_BT_FLAGS_SET = 0x01,
268 MCI_GPM_COEX_BT_FLAGS_CLEAR = 0x02
313 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
315 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
319 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \
323 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \
324 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff; \
346 #define HAL_MCI_INTERRUPT_SW_MSG_DONE 0x00000001
347 #define HAL_MCI_INTERRUPT_CPU_INT_MSG 0x00000002
348 #define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL 0x00000004
349 #define HAL_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008
350 #define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010
351 #define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020
352 #define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080
353 #define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100
354 #define HAL_MCI_INTERRUPT_RX_MSG 0x00000200
355 #define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400
356 #define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000
362 #define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001
363 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002
364 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004
365 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008
366 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010
367 #define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020
368 #define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040
369 #define HAL_MCI_INTERRUPT_RX_MSG_GPM 0x00000100
370 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200
371 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400
372 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800
373 #define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000
421 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
422 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
423 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
424 #define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
425 #define HAL_MCI_BT_MCI_FLAGS_DEBUG 0x00000020
426 #define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
427 #define HAL_MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080
428 #define HAL_MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100
429 #define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200
430 #define HAL_MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400
431 #define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE 0x00000800
432 #define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE 0x00001000
433 #define HAL_MCI_BT_MCI_FLAGS_OTHER 0x00010000
435 #define HAL_MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde
441 HAL_MCI_BT_MCI_FLAGS_DEBUG = 0
445 HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG = 0
458 #define HAL_MCI_2G_FLAGS_CLEAR_MASK 0x00000000
463 #define HAL_MCI_5G_FLAGS_SET_MASK 0x00000000
467 #define HAL_MCI_GPM_NOMORE 0
469 #define HAL_MCI_GPM_INVALID 0xffffffff
474 * Default value for Jupiter is 0x00002201
475 * Default value for Aphrodite is 0x00002282
477 #define ATH_MCI_CONFIG_CONCUR_TX 0x00000003
478 #define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004
479 #define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008
480 #define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010
481 #define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020
482 #define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040
483 #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080
484 #define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700
486 #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800
487 #define ATH_MCI_CONFIG_CLK_DIV 0x00003000
489 #define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000
490 #define ATH_MCI_CONFIG_DISABLE_AIC 0x00008000
491 #define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN 0x007f0000
493 #define ATH_MCI_CONFIG_NO_QUIET_ACK 0x00800000
495 #define ATH_MCI_CONFIG_ANT_ARCH 0x07000000
497 #define ATH_MCI_CONFIG_FORCE_QUIET_ACK 0x08000000
499 #define ATH_MCI_CONFIG_FORCE_2CHAIN_ACK 0x10000000
500 #define ATH_MCI_CONFIG_MCI_STAT_DBG 0x20000000
501 #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000
502 #define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000
507 #define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F
509 #define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00
510 #define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED 0x01
511 #define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02
512 #define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED 0x03
513 #define ATH_MCI_ANT_ARCH_3_ANT 0x04
519 #define ATH_MCI_CONCUR_TX_SHARED_CHN 0x01
520 #define ATH_MCI_CONCUR_TX_UNSHARED_CHN 0x02
521 #define ATH_MCI_CONCUR_TX_DEBUG 0x03