Lines Matching +full:0 +full:x0007ffff
70 HAL_OK = 0, /* No error */
92 AH_FALSE = 0, /* NB: lots of code assumes false is zero */
97 HAL_CAP_REG_DMN = 0, /* current regulatory domain */
226 HAL_LED_INIT = 0,
239 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */
257 HAL_RX_QUEUE_HP = 0, /* high priority recv queue */
271 HAL_WME_AC_BK = 0, /* background access category */
289 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */
290 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */
291 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */
292 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */
293 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */
299 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */
306 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020,
312 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */
326 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */
327 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */
338 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000,
342 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */
355 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */
356 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */
358 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */
359 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */
379 #define HAL_TQI_NONVAL 0xffff
397 HAL_PKT_TYPE_NORMAL = 0,
413 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */
414 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */
415 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */
416 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */
417 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */
418 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */
419 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */
420 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */
421 HAL_RX_FILTER_MYBEACON = 0x00000200, /* Filter beacons other than mine */
422 HAL_RX_FILTER_COMPBAR = 0x00000400, /* Allow compressed BAR */
423 HAL_RX_FILTER_COMP_BA = 0x00000800, /* Allow compressed blockack */
424 HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors */
425 HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PS-POLL frames */
426 HAL_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
434 HAL_RX_FILTER_BSSID = 0x40000000, /* Disable BSSID match */
438 HAL_PM_AWAKE = 0,
447 #define AH_ENT_DUAL_BAND_DISABLE 0x00000001
448 #define AH_ENT_CHAIN2_DISABLE 0x00000002
449 #define AH_ENT_5MHZ_DISABLE 0x00000004
450 #define AH_ENT_10MHZ_DISABLE 0x00000008
451 #define AH_ENT_49GHZ_DISABLE 0x00000010
452 #define AH_ENT_LOOPBACK_DISABLE 0x00000020
453 #define AH_ENT_TPC_PERF_DISABLE 0x00000040
454 #define AH_ENT_MIN_PKT_SIZE_DISABLE 0x00000080
455 #define AH_ENT_SPECTRAL_PRECISION 0x00000300
457 #define AH_ENT_RTSCTS_DELIM_WAR 0x00010000
471 HAL_INT_RX = 0x00000001, /* Non-common mapping */
472 HAL_INT_RXDESC = 0x00000002, /* Legacy mapping */
473 HAL_INT_RXERR = 0x00000004,
474 HAL_INT_RXHP = 0x00000001, /* EDMA */
475 HAL_INT_RXLP = 0x00000002, /* EDMA */
476 HAL_INT_RXNOFRM = 0x00000008,
477 HAL_INT_RXEOL = 0x00000010,
478 HAL_INT_RXORN = 0x00000020,
479 HAL_INT_TX = 0x00000040, /* Non-common mapping */
480 HAL_INT_TXDESC = 0x00000080,
481 HAL_INT_TIM_TIMER= 0x00000100,
482 HAL_INT_MCI = 0x00000200,
483 HAL_INT_BBPANIC = 0x00000400,
484 HAL_INT_TXURN = 0x00000800,
485 HAL_INT_MIB = 0x00001000,
486 HAL_INT_RXPHY = 0x00004000,
487 HAL_INT_RXKCM = 0x00008000,
488 HAL_INT_SWBA = 0x00010000,
489 HAL_INT_BRSSI = 0x00020000,
490 HAL_INT_BMISS = 0x00040000,
491 HAL_INT_BNR = 0x00100000,
492 HAL_INT_TIM = 0x00200000, /* Non-common mapping */
493 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */
494 HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */
495 HAL_INT_GPIO = 0x01000000,
496 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */
497 HAL_INT_TSFOOR = 0x04000000, /* Non-common mapping */
498 HAL_INT_TBTT = 0x08000000, /* Non-common mapping */
500 HAL_INT_GENTIMER = 0x08000000, /* Non-common mapping */
501 HAL_INT_CST = 0x10000000, /* Non-common mapping */
502 HAL_INT_GTT = 0x20000000, /* Non-common mapping */
503 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */
504 #define HAL_INT_GLOBAL 0x80000000 /* Set/clear IER */
532 HAL_MSIVEC_MISC = 0,
539 HAL_INT_LINE = 0,
545 HAL_INT_RX_FIRSTPKT=0,
581 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT = 0,
606 HAL_GPIO_INTR_LOW = 0,
616 u_int8_t is_rx_active; // true (1) or false (0)
617 u_int8_t is_tx_active; // true (1) or false (0)
621 HAL_RFGAIN_INACTIVE = 0,
629 #define HAL_ANTENNA_MIN_MODE 0
646 REG_EXT_FCC_MIDBAND = 0,
655 HAL_MODE_11A = 0x001, /* 11a channels */
656 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */
657 HAL_MODE_11B = 0x004, /* 11b channels */
658 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */
660 HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */
662 HAL_MODE_11G = 0x008, /* XXX historical */
664 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */
665 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */
666 HAL_MODE_11A_HALF_RATE = 0x200, /* 11a half width channels */
667 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11a quarter width channels */
668 HAL_MODE_11G_HALF_RATE = 0x800, /* 11g half width channels */
669 HAL_MODE_11G_QUARTER_RATE = 0x1000, /* 11g quarter width channels */
670 HAL_MODE_11NG_HT20 = 0x008000,
671 HAL_MODE_11NA_HT20 = 0x010000,
672 HAL_MODE_11NG_HT40PLUS = 0x020000,
673 HAL_MODE_11NG_HT40MINUS = 0x040000,
674 HAL_MODE_11NA_HT40PLUS = 0x080000,
675 HAL_MODE_11NA_HT40MINUS = 0x100000,
676 HAL_MODE_ALL = 0xffffff
718 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */
719 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */
720 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */
721 #define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */
726 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */
731 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */
736 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */
741 HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */
742 HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */
746 HAL_FREQ_BAND_5GHZ = 0,
757 HAL_ANT_VARIABLE = 0, /* variable by programming */
764 HAL_M_IBSS = 0, /* IBSS (adhoc) station */
770 HAL_RESET_NORMAL = 0, /* Do normal reset */
794 #define AH_KEYTYPE_MASK 0x0F
803 HAL_CIPHER_WEP = 0,
835 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */
836 #define HAL_BEACON_PERIOD_TU8 0x0007ffff /* beacon interval, tu/8 */
837 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */
838 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */
839 #define HAL_TSFOOR_THRESHOLD 0x00004240 /* TSF OOR thresh (16k uS) */
861 #define HAL_BEACON_TBTT_EN 0x00000001
862 #define HAL_BEACON_DBA_EN 0x00000002
863 #define HAL_BEACON_SWBA_EN 0x00000004
899 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
969 HAL_ANI_PRESENT = 0, /* is ANI support present */
975 HAL_ANI_MODE = 6, /* 0 => manual, 1 => auto (XXX do not change) */
981 #define HAL_ANI_ALL 0xffffffff
989 HAL_CAP_INTMIT_PRESENT = 0,
1040 #define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF
1041 #define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */
1047 HAL_DFS_UNINIT_DOMAIN = 0, /* Uninitialized dfs domain */
1057 HAL_MFP_QOSDATA = 0, /* Decrypt MFP frames like QoS data frames. All chips before Merlin. */
1064 HAL_ANT_DIV_COMB_LNA1_MINUS_LNA2 = 0,
1080 #define DEFAULT_ANTDIV_CONFIG_GROUP 0x00
1081 #define HAL_ANTDIV_CONFIG_GROUP_1 0x01
1082 #define HAL_ANTDIV_CONFIG_GROUP_2 0x02
1083 #define HAL_ANTDIV_CONFIG_GROUP_3 0x03
1089 HAL_QUIET_DISABLE = 0x0,
1090 HAL_QUIET_ENABLE = 0x1,
1091 HAL_QUIET_ADD_CURRENT_TSF = 0x2, /* add current TSF to next_start offset */
1092 HAL_QUIET_ADD_SWBA_RESP_TIME = 0x4, /* add beacon response time to next_start offset */
1095 #define HAL_DFS_EVENT_PRICH 0x0000001
1096 #define HAL_DFS_EVENT_EXTCH 0x0000002
1097 #define HAL_DFS_EVENT_EXTEARLY 0x0000004
1098 #define HAL_DFS_EVENT_ISDC 0x0000008
1113 HAL_GEN_TIMER_TSF = 0,
1146 SER_REG_MODE_OFF = 0,
1177 #define AR_PCIE_PLL_PWRSAVE_CONTROL (1<<0)
1192 int ath_hal_beacon_filter_interval; /* ok to be 0 for now? */
1194 /* For now, set this to 0 - net80211 needs to know about hardware MFP support */
1624 * radio. Returns 1 for valid results, 0 for invalid channel.