Lines Matching full:serr
1598 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions.
1649 …gnaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus.
1832 … Received System Error: The bridge sets this bit when it samples SERR# asserted on its se…
1953 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on t…
1955 ** 0b=SERR# is not asserted.
1956 ** 1b=SERR# is asserted.
2028 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR#…
2030 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b).
2717 … 0 2 SERR# Enable - When cleared, the ATU interface is not allowe…
2751 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI …
3540 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST
3555 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR…
3556 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as spec…
3560 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel X…
3561 ** when the ATU detects that SERR# was asserted. When clear,
3562 ** the Intel XScale core is not interrupted when SERR# is detected.
3828 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the settin…
3829 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the…
3832 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another ma…
3849 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU …
3850 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus durin…
3852 ** 0=SERR# Not Asserted due to error
3853 ** 1=SERR# Asserted due to error
4231 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is s…
4490 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI
4516 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus.
4650 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the
4659 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover
4660 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken.
4661 ** When the ATU asserts SERR#, additional actions is taken:
4662 ** Set the SERR# Asserted bit in the ATUSR.
4663 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the
4664 ** SERR# Asserted bit in the ATUISR. When set, no action.
4665 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the
4666 ** SERR# Detected bit in the ATUISR. When clear, no action.