Lines Matching +full:pci +full:- +full:agent +full:- +full:force +full:- +full:enum
11 ** SPDX-License-Identifier: BSD-3-Clause
13 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
43 #define ARCMSR_VIRTUAL_DEVICE_ID (ARCMSR_MAX_TARGETID - 1)
71 #define offsetof(type, member) ((size_t)(&((type *)0)->member))
197 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s,…
198 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(stru…
199 #define READ_CHIP_REG32(b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], r)
200 #define WRITE_CHIP_REG32(b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d)
374 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
486 /* ARC-1884 doorbell sync */
496 /* ARC-1886 doorbell sync */
919 ** 1. Message 0 --> InitThread message and retrun code
920 ** 2. Doorbell is used for RS-232 emulation
921 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK)
922 ** bit1 -- data out has been read (DRIVER DATA READ OK)
923 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK)
924 ** bit1 -- data in has been read (IOP331 DATA READ OK)
930 ** 4. RS-232 emulation
932 ** 1st u_int32_t : Data length (1--124)
933 ** Byte 4--127 : Max 124 bytes of data
937 ** # bit27--bit31 => flag for post ccb
938 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb
946 ** -------------------------------------------------------------------------------
948 ** # bit27--bit31 => flag for reply
949 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb
965 ** 8. Message1 Out - Diag Status Code (????)
968 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to d…
972 ** SDRAM Size 0x00000100(4)-->256 MB
980 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to I…
982 ** UPPER32 of Request Frame (4)-->Driver Only
986 ** 0x06 : Start Background Activity (re-start if background is halted)
988 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver …
989 ** byte 0 : 0xaa <-- signature
990 ** byte 1 : 0x55 <-- signature
1007 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop)
1008 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver)
1010 ** a. Message1: Out - Diag Status Code (????)
1014 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP s…
1018 ** SDRAM Size 0x00000100(4)-->256 MB
1025 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver…
1027 ** UPPER32 of Request Frame (4)-->Driver Only
1031 ** 0x06 : Start Background Activity (re-start if background is halted)
1033 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuff…
1034 ** byte 0 : 0xaa <-- signature
1035 ** byte 1 : 0x55 <-- signature
1043 ** <2> Doorbell Register is used for RS-232 emulation
1050 ** inbound doorbell : bit0 -- reserved
1051 ** bit1 -- data in ready (DRIVER DATA WRITE OK)
1052 ** bit2 -- data out has been read (DRIVER DATA READ OK)
1053 ** bit3 -- inbound message 0 ready
1054 ** bit4 -- more than 12 request completed in a time
1059 ** outbound doorbell : bit0 -- reserved
1060 ** bit1 -- data out ready (IOP DATA WRITE OK)
1061 ** bit2 -- data in has been read (IOP DATA READ OK)
1062 ** bit3 -- outbound message 0 ready
1065 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS…
1066 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS…
1067 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code ms…
1068 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code ms…
1092 ** ----------------------------
1094 ** ----------------------------
1104 ** -----------------------------
1106 ** -----------------------------
1107 ** post addr = addr | ((len-1) >> 6) | 1
1108 ** -----------------------------
1119 ** bit63-4: Completed command address
1133 /* 32bit Scatter-Gather list */
1139 /* 64bit Scatter-Gather list */
1179 u_int32_t signature; /*0,00-03*/
1180 u_int32_t request_len; /*1,04-07*/
1181 u_int32_t numbers_queue; /*2,08-11*/
1182 u_int32_t sdram_size; /*3,12-15*/
1183 u_int32_t ide_channels; /*4,16-19*/
1184 char vendor[40]; /*5,20-59*/
1185 char model[8]; /*15,60-67*/
1186 char firmware_ver[16]; /*17,68-83*/
1187 char device_map[16]; /*21,84-99*/
1188 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
1189 char cfgSerial[16]; /*26,104-119*/
1190 u_int32_t cfgPicStatus; /*30,120-123*/
1226 u_int8_t TargetID; /* 01h should be 0--15 */
1227 u_int8_t LUN; /* 02h should be 0--7 */
1284 …struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descrip…
1285 unsigned long cdb_phyaddr; /* 504-507 */
1287 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */
1288 struct AdapterControlBlock *acb; /* 520-523 524-527 */
1289 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */
1290 u_int16_t srb_flags; /* 536-537 */
1291 u_int16_t srb_state; /* 538-539 */
1292 u_int32_t arc_cdb_size; /* 508-511 */
1373 uint32_t *message_wbuffer; //0x000 - COMPORT_IN (to be sent to ROC)
1374 uint32_t *message_rbuffer; //0x100 - COMPORT_OUT (to be sent to Host)
1375 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
1403 u_int32_t firm_request_len; /*1,04-07*/
1404 u_int32_t firm_numbers_queue; /*2,08-11*/
1405 u_int32_t firm_sdram_size; /*3,12-15*/
1406 u_int32_t firm_ide_channels; /*4,16-19*/
1408 char firm_model[12]; /*15,60-67*/
1409 char firm_version[20]; /*17,68-83*/
1410 char device_map[20]; /*21,84-99 */
1507 #define SCSI_DASD 0x00 /* Direct-access Device */
1508 #define SCSI_SEQACESS 0x01 /* Sequential-access device */
1511 #define SCSI_WRITEONCE 0x04 /* Write-once device */
1512 #define SCSI_CDROM 0x05 /* CD-ROM device */
1521 ** 80331 PCI-to-PCI Bridge
1522 ** PCI Configuration Space
1530 ** -------------------------------------------------------------
1531 ** Standard PCI Configuration 00-3Fh
1532 ** -------------------------------------------------------------
1533 ** Device Specific Registers 40-A7h
1534 ** -------------------------------------------------------------
1535 ** Reserved A8-CBh
1536 ** -------------------------------------------------------------
1537 ** Enhanced Capability List CC-FFh
1539 ** Standard PCI [Type 1] Configuration Space Address Map
1541 … Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
1542 ** ------------------------------------------------------------------------------------------------…
1544 ** ------------------------------------------------------------------------------------------------…
1546 ** ------------------------------------------------------------------------------------------------…
1548 ** ------------------------------------------------------------------------------------------------…
1550 ** ------------------------------------------------------------------------------------------------…
1552 ** ------------------------------------------------------------------------------------------------…
1554 ** ------------------------------------------------------------------------------------------------…
1556 ** ------------------------------------------------------------------------------------------------…
1558 ** ------------------------------------------------------------------------------------------------…
1559 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address …
1560 ** ------------------------------------------------------------------------------------------------…
1562 ** ------------------------------------------------------------------------------------------------…
1564 ** ------------------------------------------------------------------------------------------------…
1566 ** ------------------------------------------------------------------------------------------------…
1568 ** ------------------------------------------------------------------------------------------------…
1570 ** ------------------------------------------------------------------------------------------------…
1572 ** ------------------------------------------------------------------------------------------------…
1578 ** 0x03-0x00 :
1580 … Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG.
1582 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vend…
1589 ** 0x05-0x04 : command register
1611 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible …
1644 ** 0x07-0x06 : status register
1659 ** In PCI-X mode this bit is also set wh…
1660 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-c…
1671 …bilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced c…
1686 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping.
1692 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode )
1695 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI …
1696 … Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge.
1704 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-…
1716 ** 0x0d : latency timer (number of pci clock 00-ff )
1719 …* 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Ind…
1722 ** resulting in a granularity of 1 PCI c…
1725 ** when its PCI bus grant has been deasserted.
1726 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer.
1727 ** Indicates the number of PCI clock cyc…
1730 … All bits are writable, resulting in a granularity of 1 PCI clock cycle.
1742 ** 07 0 Multi-function device (MVD): 80331 is a single-function device.
1745 ** that the register layout conforms to the standard PCI-to-PCI bridge layout.
1756 ** 0x13-0x10 :
1757 ** PCI CFG Base Address #0 (0x10)
1762 ** 0x17-0x14 :
1763 ** PCI CFG Base Address #1 (0x14)
1768 ** 0x1b-0x18 :
1769 ** PCI CFG Base Address #2 (0x18)
1770 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR
1772 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number …
1776 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus.
1777 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to wh…
1780 ** before being executed on bridge's secondary PCI bus.
1785 **-----------------0x1B--Secondary Latency Timer Register - SLTR
1788 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer.
1789 ** Indicates the number of PCI clock cyc…
1792 ** resulting in a granularity of 1 PCI c…
1795 ** when its PCI bus grant has been deasserted.
1796 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer.
1797 ** Indicates the number of PCI clock cyc…
1800 ** resulting in a granularity of 1 PCI c…
1813 ** 0x1f-0x1c :
1814 ** PCI CFG Base Address #3 (0x1C)
1815 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL
1821 … I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit …
1827 … I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bi…
1828 **-----------------0x1F,0x1E--Secondary Status Register - SSR
1842 ** In PCI-X mode this bit is also set wh…
1843 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-c…
1849 … 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridg…
1861 ** 0x23-0x20 :
1862 ** PCI CFG Base Address #4 (0x20)
1863 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL
1884 ** 0x27-0x24 :
1885 ** PCI CFG Base Address #5 (0x24)
1886 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL
1893 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is s…
1900 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is s…
1907 ** 0x2b-0x28 :
1910 ** bridge supports full 64-bit addressin…
1916 ** 0x2f-0x2c :
1919 ** bridge supports full 64-bit addressi…
1925 ** 0x33-0x30 :
1927 … Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration
1934 ** 0x3b-0x35 : reserved
1939 ** 0x3d-0x3c :
1950 ** 0x3f-0x3e :
1959 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock …
1967 … 0b=The secondary master time-out counter is 2 15 PCI clock cyc…
1968 … 1b=The secondary master time-out counter is 2 10 PCI clock cyc…
1969 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock …
1977 … 0b=The primary master time-out counter is 2 15 PCI clock cyc…
1978 … 1b=The primary master time-out counter is 2 10 PCI clock cyc…
1979 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to …
1987 … 0b=The bridge asserts TRDY# in response to a non-locked delayed transa…
1990 ** (e.g.,delayed reads, or non-posted writes),
1995 ** For PCI-X transactions this bit is an enable for the assertion…
2019 ** (i.e., 0000 0000h - 0000 FFFFh).
2030 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b).
2045 ** Device Specific Registers 40-A7h
2047 ** ------------------------------------------------------------------------------------------------…
2048 … Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
2049 ** ------------------------------------------------------------------------------------------------…
2051 ** ------------------------------------------------------------------------------------------------…
2053 ** ------------------------------------------------------------------------------------------------…
2055 ** ------------------------------------------------------------------------------------------------…
2057 ** ------------------------------------------------------------------------------------------------…
2058 ** | Prefetch Policy | Multi-Transaction Timer …
2059 ** ------------------------------------------------------------------------------------------------…
2060 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control …
2061 ** ------------------------------------------------------------------------------------------------…
2063 ** ------------------------------------------------------------------------------------------------…
2065 ** ------------------------------------------------------------------------------------------------…
2067 ** ------------------------------------------------------------------------------------------------…
2069 ** ------------------------------------------------------------------------------------------------…
2072 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR
2074 … 1111b Grant Time-out Violator: This field indicates the agent that violated…
2075 ** (PCI=16 clocks,PCI-X=6 clocks).
2078 ** indicating that a Grant Time-out violation had occurred.
2080 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number)
2088 ** 11 0b Grant Time-out Occurred: When set to 1b,
2089 ** this indicates that a Grant Time-out error had occurred involv…
2106 ** 0x43: Bridge Control Register 0 - BCR0
2117 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus
2118 ** to a Conventional PCI bus.
2121 ** Multiple is enabled when forwarding a PCI-X Memory Read Blo…
2122 ** to an upstream bus operating in Conventional PCI mode.
2123 ** 1b=bridge treats upstream PCI Memory Read requests as though
2124 ** they target non-prefetchable memory and forwards upstream PCI-X Memory
2127 ** in Conventional PCI mode.
2131 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2)
2134 … Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands…
2137 ** re-map to the actual block memory read/write command encoding, or ignore
2140 ** 0 0 Re-map to Memory Read/Write Block bef…
2147 ** or Split Requests (PCI-X mode) is not…
2148 … (��events�� are defined as PCI Clocks when operating in PCI-X mod…
2149 ** and as the number of times being retried when operating in Conventional PCI mode)
2155 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# ti…
2156 … Grant time-out is 16 clocks for conventional PCI, and 6 clocks…
2157 … 0b=The Secondary bus arbiter times out an agent
2160 ** The time-out counter begins as s…
2161 ** An infringing agent does not rec…
2162 ** until it de-asserts its REQ# for at least one clock cycle.
2163 ** 1b=GNT# time-out mechanism is disable…
2169 ** 0b=The secondary master time-out coun…
2172 ** 1b=The secondary master time-out coun…
2179 ** 0b=The primary master time-out counte…
2181 ** 1b=The secondary master time-out coun…
2186 ** 0x47-0x46: Bridge Control Register 2 - BCR2
2190 ** This bit disables all of the secondary PCI clock outputs including
2199 ** secondary PCI clock outputs. Some, or all secondary clock…
2202 ** �E Designs with 100 MHz (or lower) Secondary PCI c…
2204 ** �E Designs with 133 MHz Secondary PCI clock power …
2209 ** 0x49-0x48: Bridge Status Register - BSR
2214 ** Conventional PCI Mode: This bit is set to a …
2216 ** PCI-X Mode: This bit is set to a …
2221 ** Conventional PCI Mode: This bit is set to a …
2223 ** PCI-X Mode: This bit is set to a …
2244 ** Conventional PCI Mode: This bit is set to a …
2247 ** PCI-X Mode: This bit is set to a …
2252 ** Conventional PCI Mode: This bit is set to a …
2255 ** PCI-X Mode: This bit is set to a …
2274 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR
2277 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI c…
2299 ** 0x53-0x52: Read Prefetch Policy Register - RPPR
2301 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplicatio…
2304 … The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory R…
2306 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplicatio…
2309 … The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory R…
2311 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplicatio…
2316 … The default value of 010b correlates to: Command Type Hardwired pre-fetch a
2319 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplicatio…
2322 … The default value of 000b correlates to: Command Type Hardwired pre-fetch amount
2324 … Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch
2329 … 1b: enables the staged pre-fetch feature
2330 … 0b: disables staged pre-fetch,
2331 ** and hardwires read pre-fetch policy to t…
2335 ** Command Type Hardwired Pre-Fetch Amount...
2339 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line c…
2340 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read
2341 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered.
2343 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL
2406 ** 0x56: Pre-Boot Status Register - PBSR
2409 ** 06 - Reserved - value indeterminate
2411 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Se…
2413 ** indicating the maximum secondary bus clock frequency when in PCI-X mode.
2415 ** ** S_133EN PCI-X Mode
2420 ** 0x59-0x58: Secondary Decode Enable Register - SDER
2423 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - wh…
2426 … This creates a private memory space on the Secondary PCI bus
2427 ** that allows peer-to-peer transactions.
2430 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR
2433 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this…
2437 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this…
2441 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this…
2445 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this…
2449 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this…
2453 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this…
2457 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this…
2461 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this…
2465 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this…
2469 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this…
2477 ** Reserved A8-CBh
2482 ** PCI Extended Enhanced Capabilities List CC-FFh
2484 ** ------------------------------------------------------------------------------------------------…
2485 … Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
2486 ** ------------------------------------------------------------------------------------------------…
2488 ** ------------------------------------------------------------------------------------------------…
2490 ** ------------------------------------------------------------------------------------------------…
2492 ** ------------------------------------------------------------------------------------------------…
2494 ** ------------------------------------------------------------------------------------------------…
2496 ** ------------------------------------------------------------------------------------------------…
2497 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID…
2498 ** ------------------------------------------------------------------------------------------------…
2499 ** | PCI-X Bridge Status …
2500 ** ------------------------------------------------------------------------------------------------…
2501 ** | PCI-X Upstream Split Transaction Control …
2502 ** ------------------------------------------------------------------------------------------------…
2503 ** | PCI-X Downstream Split Transaction Control …
2504 ** ------------------------------------------------------------------------------------------------…
2506 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID
2508 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register …
2510 ** 0xDD: Next Item Pointer - PM_NXTP
2512 … Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capabilit…
2514 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR
2519 … (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function.
2520 ** This returns 000b as PME# wake-up for b…
2523 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Po…
2525 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR
2529 …ert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug.
2531 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine t…
2533 ** 00 - D0 state
2534 ** 01 - D1 state
2535 ** 10 - D2 state
2536 ** 11 - D3 hot state
2538 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE
2546 ** 0xE3: Power Management Data Register - PMDR
2550 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID
2552 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities li…
2554 ** 0xF1: Next Item Pointer - PX_NXTP
2559 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS
2565 ** ** 000PCI ModeN/A
2585 … 1b 64-bit Device (D64): Indicates the width of the secondary…
2587 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS
2598 …icates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode.
2601 … the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of…
2602 ** 0=Primary Interface is connected as a 32-bit PCI bus.
2603 ** 1=Primary Interface is connected as a 64-bit PCI bus.
2608 ** May be updated whenever a PCI-X
2612 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC
2620 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates t…
2625 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC
2633 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates t…
2645 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface.
2650 ** ------------------------------------------------------------------------------------------------…
2652 ** ------------------------------------------------------------------------------------------------…
2654 ** ------------------------------------------------------------------------------------------------…
2656 ** ------------------------------------------------------------------------------------------------…
2658 ** ------------------------------------------------------------------------------------------------…
2660 ** ------------------------------------------------------------------------------------------------…
2662 ** ------------------------------------------------------------------------------------------------…
2664 ** ------------------------------------------------------------------------------------------------…
2666 ** ------------------------------------------------------------------------------------------------…
2668 ** ------------------------------------------------------------------------------------------------…
2670 ** ------------------------------------------------------------------------------------------------…
2672 ** ------------------------------------------------------------------------------------------------…
2674 ** ------------------------------------------------------------------------------------------------…
2676 ** ------------------------------------------------------------------------------------------------…
2678 ** ------------------------------------------------------------------------------------------------…
2680 ** ------------------------------------------------------------------------------------------------…
2685 ** ATU Vendor ID Register - ATUVID
2686 ** -----------------------------------------------------------------
2688 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Inte…
2689 ** This register, combined with the DID, uniquely identify the PCI device.
2697 ** ATU Device ID Register - ATUDID
2698 ** -----------------------------------------------------------------
2700 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the …
2701 ** This ID, combined with the VID, uniquely identify any PCI device.
2707 ** ATU Command Register - ATUCMD
2708 ** -----------------------------------------------------------------
2711 ** 10 0 Interrupt Disable - This bit disables 80331 from assert…
2714 ** 09 0 2 Fast Back to Back Enable - When cleared,
2715 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus.
2716 ** Ignored when operating in the PCI-X mode.
2717 …2 SERR# Enable - When cleared, the ATU interface is not allowed to assert …
2718 ** 07 1 2 Address/Data Stepping Control - Address stepping is imp…
2720 ** of address stepping for PCI-X mode.
2721 ** 06 0 2 Parity Error Response - When set, the ATU takes normal …
2723 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not s…
2725 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may …
2726 …When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode.
2727 ** 03 0 2 Special Cycle Enable - The ATU interface does not respo…
2729 … 0 2 Bus Master Enable - The ATU interface can act as a master on the …
2730 ** When cleared, disables the device from generating PCI accesses.
2731 ** When set, allows the device to behave as a PCI bus master.
2732 ** When operating in the PCI-X mode, ATU initiates a split…
2734 …1 0 2 Memory Enable - Controls the ATU interface��s response to P…
2735 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus.
2736 ** 00 0 2 I/O Space Enable - Controls the ATU interface response …
2743 ** ATU Status Register - ATUSR (Sheet 1 of 2)
2744 ** -----------------------------------------------------------------
2746 … Detected Parity Error - set when a parity error is detected in data received by th…
2750 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (i…
2751 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI …
2752 … Master Abort - set when a transaction initiated by the ATU PCI master interfa…
2753 … or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode.
2754 … 0 2 Target Abort (master) - set when a transaction initiated by the ATU …
2755 … abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode.
2756 ** 11 0 2 Target Abort (target) - set when the ATU interface, act…
2757 ** terminates the transaction on the PCI bus with a target abort.
2758 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define th…
2759 ** timing for a target device in Conventional PCI Mode regardless of the operating mode
2766 ** 08 0 2 Master Parity Error - The ATU interface sets this bit u…
2771 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
2774 ** 0 2 (PCI-X mode)
2775 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-t…
2776 ** transactions in Conventional PCI mode when the transactions are not to the same target. …
2777 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI…
2778 ** 06 0 2 UDF Supported - User Definable Features are not support…
2779 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported.
2780 ** 04 1 2 Capabilities - When set, this function implements exten…
2781 ** 03 0 Interrupt Status - reflects the state of the ATU interr…
2786 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU
2794 ** ATU Revision ID Register - ATURID
2795 ** -----------------------------------------------------------------
2797 ** 07:00 00H ATU Revision - identifies the 80331 revision number.
2803 ** ATU Class Code Register - ATUCCR
2804 ** -----------------------------------------------------------------
2806 ** 23:16 05H Base Class - Memory Controller
2807 ** 15:08 80H Sub Class - Other Memory Controller
2808 ** 07:00 00H Programming Interface - None defined
2814 ** ATU Cacheline Size Register - ATUCLSR
2815 ** -----------------------------------------------------------------
2817 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline siz…
2823 ** ATU Latency Timer Register - ATULT
2824 ** -----------------------------------------------------------------
2827 ** 01000 2 (for PCI-X mode)
2828 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to…
2829 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode.
2830 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable …
2836 ** ATU Header Type Register - ATUHTR
2837 ** -----------------------------------------------------------------
2839 … Single Function/Multi-Function Device - Identifies the 80331 as a single-fu…
2840 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of …
2841 ** header conforms to PCI Local Bus Specification, Revisio…
2847 ** ATU BIST Register - ATUBISTR
2852 ** -----------------------------------------------------------------
2854 ** 07 0 2 BIST Capable - This bit value is always equal to the AT…
2855 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit i…
2863 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is…
2865 ** A nonzero value indicates a device-specific error.
2875 … Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus.
2876 …se Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs.
2877 …ster 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus.
2878 … Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs.
2879 … Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus.
2880 … Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs.
2881 … Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus.
2882 … Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs.
2883 …is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-…
2885 **--------------------------------------------------------------------------------------
2887 ** The ATU does not claim any PCI accesses that fall within this range.
2889 … XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus.
2895 ** Inbound ATU Base Address Register 0 - IABAR0
2903 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification.
2905 ** The programmed value within the base address register must comply with the PCI programming re…
2913 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specificat…
2917 ** -----------------------------------------------------------------
2919 ** 31:12 00000H Translation Base Address 0 - These bits define the actu…
2920 ** the translation function is to respond to when addressed from the PCI bus.
2922 ** 03 1 2 Prefetchable Indicator - When set, defines the memory s…
2923 ** 02:01 10 2 Type Indicator - Defines the width of the addressabilit…
2924 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2925 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2926 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
2936 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0
2938 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
2940 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs).
2941 ** The programmed value within the base address register must comply with the PCI programming requ…
2944 ** the IAUBAR0 register attributes are read-only.
2945 ** -----------------------------------------------------------------
2947 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Tr…
2948 …location the translation function is to respond to when addressed from the PCI bus for addresses >…
2954 ** Inbound ATU Base Address Register 1 - IABAR1
2958 … This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PC…
2959 ** . The programmed value within the base address register must comply with the PCI programming re…
2960 …ed, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus.
2962 ** When a non-zero value is not written to IALR1 prior to host configuration,
2965 ** Assuming a non-zero value is written to IALR1,
2974 ** -----------------------------------------------------------------
2976 … Translation Base Address 1 - These bits define the actual location of window 1 o…
2978 ** 03 0 2 Prefetchable Indicator - When set, defines the memory s…
2979 ** 02:01 00 2 Type Indicator - Defines the width of the addressabilit…
2980 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2981 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2982 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
2990 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1
2992 ** This register contains the upper base address when locating this window for PCI addresses beyon…
2994 … This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PC…
2995 ** The programmed value within the base address register must comply with the PCI programming
2998 ** from the PCI bus.
3001 ** the IAUBAR1 register attributes are read-only.
3003 ** -----------------------------------------------------------------
3005 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Tr…
3006 ** these bits define the actual location for this memory window on the PCI bus for addresses >…
3012 ** Inbound ATU Base Address Register 2 - IABAR2
3019 ** The programmed value within the base address register must comply with the PCI programming re…
3021 ** When a non-zero value is not written to IALR2 prior to host configuration,
3025 ** Assuming a non-zero value is written to IALR2,
3034 ** -----------------------------------------------------------------
3036 ** 31:12 00000H Translation Base Address 2 - These bits define the actu…
3037 ** the translation function is to respond to when addressed from the PCI bus.
3039 ** 03 0 2 Prefetchable Indicator - When set, defines the memory s…
3040 ** 02:01 00 2 Type Indicator - Defines the width of the addressabilit…
3041 ** 00 - Memory Window is locatable anywhere in 32 bit address space
3042 ** 10 - Memory Window is locatable anywhere in 64 bit address space
3043 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
3051 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2
3053 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
3055 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GByt…
3056 ** The programmed value within the base address register must comply with the PCI programming
3060 ** the IAUBAR2 register attributes are read-only.
3062 ** -----------------------------------------------------------------
3064 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Tr…
3066 ** when addressed from the PCI bus for addresses > 4GBytes.
3072 ** ATU Subsystem Vendor ID Register - ASVIR
3073 ** -----------------------------------------------------------------
3075 … 0000H Subsystem Vendor ID - This register uniquely identifies the add-…
3081 ** ATU Subsystem ID Register - ASIR
3082 ** -----------------------------------------------------------------
3084 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or …
3090 ** Expansion ROM Base Address Register -ERBAR
3091 ** -----------------------------------------------------------------
3093 ** 31:12 00000H Expansion ROM Base Address - These bits define the actu…
3094 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kby…
3096 ** 00 0 2 Address Decode Enable - This bit field shows the ROM ad…
3104 ** ATU Capabilities Pointer Register - ATU_CAP_PTR
3105 ** -----------------------------------------------------------------
3107 ** 07:00 C0H Capability List Pointer - This provides an offset in th…
3116 ** reading from the registers. By scanning the returned value from the least-significant bit of th…
3118 ** binary-weighted value of the first non-zero bit found indicates the required amount of space.
3124 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value …
3129 ** other PCI devices even though the limit is variable.
3154 ** imple-mented,
3168 ** ATU Interrupt Line Register - ATUILR
3169 ** -----------------------------------------------------------------
3171 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies w…
3172 … request line connects to the device's PCI interrupt request l…
3180 ** ATU Interrupt Pin Register - ATUIPR
3181 ** -----------------------------------------------------------------
3183 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU …
3189 ** ATU Minimum Grant Register - ATUMGNT
3190 ** -----------------------------------------------------------------
3192 … This register specifies how long a burst period the device needs in increments of 8 PCI clocks.
3198 ** ATU Maximum Latency Register - ATUMLAT
3199 ** -----------------------------------------------------------------
3201 …00H Specifies frequency (how often) the device needs to access the PCI bus
3202 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requireme…
3210 ** The ATU allows external PCI bus initiators to directly access the internal bus.
3211 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory …
3214 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is
3216 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI
3217 ** mode and with Decode A DEVSEL# timing in the PCI-X mode.
3219 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-b…
3234 … window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH),
3236 ** Window 3 is intended to be used as a special window into local memory for private PCI
3238 ** PCI-to-PCI Bridge in 80331 or
3239 ** Inbound address detection is determined from the 32-bit PCI address,
3240 ** (64-bit PCI address during DACs) the base address register and the limit register.
3241 ** In the case of DACs none of the upper 32-bits of the address is masked during address c…
3247 ** the PCI Address is claimed by the Inbound ATU.
3249 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise AN…
3251 ** When the result matches the base register (and upper base address matches upper PCI…
3252 ** the inbound PCI address is detected as being within the inbound translation window …
3255 … Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit
3256 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and…
3257 ** lower 32-bits are used during address translation.
3264 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with …
3268 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear
3270 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in…
3278 ** Address Detection (32-bit address)
3295 ** Inbound ATU Limit Register 0 - IALR0
3297 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI
3298 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block conv…
3299 ** PCI addresses to internal bus addresses.
3302 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
3307 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of
3310 ** -----------------------------------------------------------------
3312 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value deter…
3320 ** Inbound ATU Translate Value Register 0 - IATVR0
3323 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of t…
3325 ** -----------------------------------------------------------------
3327 …H Inbound ATU Translation Value 0 - This value is used to convert the PCI a…
3328 ** This value must be 64-bit aligned on the internal bus.
3329 ** The default address allows the ATU to access the internal 80331 memory-mapped registers.
3336 ** Expansion ROM Limit Register - ERLR
3343 ** the corresponding bit within the ERBAR read/write from PCI.
3344 ** -----------------------------------------------------------------
3346 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for…
3354 ** Expansion ROM Translate Value Register - ERTVR
3357 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the
3359 ** -----------------------------------------------------------------
3361 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI a…
3369 ** Inbound ATU Limit Register 1 - IALR1
3374 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of
3378 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does
3379 ** not process any PCI bus transactions to this memory range.
3380 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1,
3382 ** -----------------------------------------------------------------
3384 ** 31:12 00000H Inbound Translation Limit 1 - This readback value deter…
3392 ** Inbound ATU Limit Register 2 - IALR2
3394 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI
3395 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block conv…
3396 ** PCI addresses to internal bus addresses.
3403 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
3408 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of
3412 ** -----------------------------------------------------------------
3414 ** 31:12 00000H Inbound Translation Limit 2 - This readback value deter…
3422 ** Inbound ATU Translate Value Register 2 - IATVR2
3425 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of t…
3427 ** -----------------------------------------------------------------
3429 …H Inbound ATU Translation Value 2 - This value is used to convert the PCI a…
3430 … This value must be 64-bit aligned on the in…
3431 ** The default address allows the ATU to access the internal 80331 ** ** memory-m…
3438 ** Outbound I/O Window Translate Value Register - OIOWTVR
3440 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address
3441 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus…
3445 ** -----------------------------------------------------------------
3447 … Outbound I/O Window Translate Value - Used to convert internal bus addresses to P…
3454 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0
3456 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI
3458 ** driven on the PCI bus as a result of the outbound ATU address translation.
3461 ** -----------------------------------------------------------------
3463 … Outbound MW Translate Value - Used to convert 80331 internal bus addresses t…
3465 ** 01:00 00 2 Burst Order - This bit field shows the address sequence…
3472 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
3474 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines
3475 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3476 ** directly address anywhere within the 64-bit host address space. When this register is all-zero,…
3477 ** a SAC is generated on the PCI bus.
3480 ** -----------------------------------------------------------------
3482 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven d…
3488 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1
3490 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI
3492 ** driven on the PCI bus as a result of the outbound ATU address translation.
3495 ** -----------------------------------------------------------------
3497 … Outbound MW Translate Value - Used to convert 80331 internal bus addresses t…
3499 ** 01:00 00 2 Burst Order - This bit field shows the address sequence…
3506 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
3508 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines
3509 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3510 ** directly address anywhere within the 64-bit host address space. When this register is all-zero,…
3511 ** a SAC is generated on the PCI bus.
3514 ** -----------------------------------------------------------------
3516 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven d…
3522 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR
3524 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the
3525 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addre…
3526 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host
3527 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus.
3528 ** -----------------------------------------------------------------
3530 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven d…
3536 ** ATU Configuration Register - ATUCR
3539 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard
3542 ** -----------------------------------------------------------------
3545 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish …
3546 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a cu…
3548 ** applicable in the PCI-X mode.
3549 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - Wh…
3552 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH).
3555 … SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on …
3557 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 disca…
3560 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel X…
3563 ** 08 0 2 Direct Addressing Enable - Setting this bit enables dir…
3565 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 …
3568 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interr…
3572 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound ad…
3580 ** PCI Configuration and Status Register - PCSR
3582 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring
3583 ** various features of the PCI bus interface.
3584 ** -----------------------------------------------------------------
3587 ** 18 0 2 Detected Address or Attribute Parity Error - set when a…
3588 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Er…
3590 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated …
3598 ** PCI-X capability - These two bits define the mode of
3599 ** the PCI bus (conventional or PCI-X) as well as the
3600 ** operating frequency in the case of PCI-X mode.
3601 ** 00 - Conventional PCI mode
3602 ** 01 - PCI-X 66
3603 ** 10 - PCI-X 100
3604 ** 11 - PCI-X 133
3605 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification,
3607 ** mode is determined by an initialization pattern on the PCI bus during
3611 ** Deasserted Deasserted Asserted PCI-X 66
3612 ** Deasserted Asserted Deasserted PCI-X 100
3613 ** Deasserted Asserted Asserted PCI-X 133
3624 ** 12 0 2 Discard Timer Value - This bit controls the time-out value
3626 ** A value of 0 indicates the time-out valu…
3627 ** A value of 1 indicates the time-out valu…
3634 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66…
3635 ** Conventional PCI mode by the assertion of M66EN during bus initialization.
3638 …:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode.
3645 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been
3646 ** configured as 64-bit capable by
3648 ** the PCI interface is configured as
3649 ** 32-bit only.
3651 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale cor…
3656 ** When operating in the conventional PCI mode:
3657 ** �E All current PCI transactions being mastered by the ATU completes,
3661 ** �E All current transactions being slaved by the ATU on either the PCI bus
3672 ** When operating in the PCI-X mode:
3673 ** The ATU hardware responds the same as in Conventional PCI-X mode.
3674 ** However, this may create a problem in PCI-X mode for split requests in
3698 ** Private Device Enable - This bit indicates the state of the reset strap which enables the pr…
3699 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register.
3700 ** 0=Private Device control Disabled - SISR register bits default to zero
3701 ** 1=Private Device control Enabled - SISR register bits default to one
3703 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to…
3710 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RS…
3718 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the pr…
3719 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register.
3720 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero
3721 ** 1=Private Memory control Enabled - SDER register bits 2 default to one
3727 ** ATU Interrupt Status Register - ATUISR
3738 ** -----------------------------------------------------------------
3741 … 0 2 VPD Address Register Updated - This bit is set when a PCI bus con…
3745 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bu…
3747 … ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus con…
3751 ** 13 0 2 Initiated Split Completion Error Message - This bit is …
3752 ** Message on the PCI Bus with the Split C…
3753 ** 12 0 2 Received Split Completion Error Message - This bit is s…
3754 ** Message from the PCI Bus with the Split…
3755 ** 11 0 2 Power State Transition - When the Power State Field of …
3758 …0 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI …
3759 … 0 2 Detected Parity Error - set when a parity error is detected on the P…
3763 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus.
3764 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST S…
3770 … Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator i…
3772 …4 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI …
3773 … PCI Master Abort - set when a transaction initiated by the ATU PCI initiat…
3774 … PCI Target Abort (master) - set when a transaction initiated by the ATU PCI m…
3775 … PCI Target Abort (target) - set when the ATU interface, acting as a target, te…
3776 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU…
3781 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
3788 ** ATU Interrupt Mask Register - ATUIMR
3792 ** -----------------------------------------------------------------
3795 ** 14 0 2 VPD Address Register Updated Mask - Controls the settin…
3796 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR regist…
3800 ** 12 0 2 Configuration Register Write Mask - Controls the settin…
3801 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configur…
3805 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Control…
3806 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs t…
3810 … Initiated Split Completion Error Message Interrupt Mask - Controls the setting…
3814 ** 09 0 2 Received Split Completion Error Message Interrupt Mask-…
3819 ** 08 1 2 Power State Transition Interrupt Mask - Controls the se…
3824 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the…
3825 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of th…
3828 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the settin…
3829 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the…
3833 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the sett…
3837 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls …
3841 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls …
3845 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls t…
3849 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU …
3850 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus durin…
3854 … 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI in…
3861 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2…
3862 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus,
3869 ** Inbound ATU Base Address Register 3 - IABAR3
3876 ** The programmed value within the base address register must comply with the PCI programming re…
3878 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - …
3881 ** When a non-zero value is not written to IALR3,
3885 ** Assuming a non-zero value is written to IALR3,
3894 ** -----------------------------------------------------------------
3896 ** 31:12 00000H Translation Base Address 3 - These bits define the actu…
3897 … the translation function is to respond to when addressed from the PCI bus.
3899 ** 03 0 2 Prefetchable Indicator - When set, defines the memory s…
3900 ** 02:01 00 2 Type Indicator - Defines the width of the addressabilit…
3901 ** 00 - Memory Window is locatable anywhere in 32 bit address space
3902 ** 10 - Memory Window is locatable anywhere in 64 bit address space
3903 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
3911 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3
3913 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes.
3915 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GByt…
3916 ** The programmed value within the base address register must comply with the PCI programming
3920 ** the IAUBAR3 register attributes are read-only.
3922 ** -----------------------------------------------------------------
3924 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Tr…
3925 …location the translation function is to respond to when addressed from the PCI bus for addresses >…
3931 ** Inbound ATU Limit Register 3 - IALR3
3933 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI
3934 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block conv…
3935 ** PCI addresses to internal bus addresses.
3942 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus
3947 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of
3951 ** -----------------------------------------------------------------
3953 ** 31:12 00000H Inbound Translation Limit 3 - This readback value deter…
3961 ** Inbound ATU Translate Value Register 3 - IATVR3
3964 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of t…
3966 ** -----------------------------------------------------------------
3968 …H Inbound ATU Translation Value 3 - This value is used to convert the PCI a…
3969 ** This value must be 64-bit aligned on th…
3970 ** access the internal 80331 memory-mapped…
3977 ** Outbound Configuration Cycle Address Register - OCCAR
3979 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration
3980 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then
3983 ** PCI bus.
3985 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a
3986 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for
3988 … bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X
3989 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats.
3990 ** -----------------------------------------------------------------
3992 …0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI addr…
3999 ** Outbound Configuration Cycle Data Register - OCCDR
4002 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a
4003 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to
4004 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a
4010 ** -----------------------------------------------------------------
4012 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data u…
4019 ** VPD Capability Identifier Register - VPD_CAPID
4021 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specific…
4022 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extend…
4024 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3.
4025 ** -----------------------------------------------------------------
4027 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in …
4034 ** VPD Next Item Pointer Register - VPD_NXTP
4036 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specificatio…
4039 ** -----------------------------------------------------------------
4041 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the func…
4049 ** VPD Address Register - VPD_AR
4051 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be
4052 ** accessed. The register is read/write and the initial value at power-up is indeterminate.
4053 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use
4056 ** -----------------------------------------------------------------
4058 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the …
4061 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte a…
4068 ** VPD Data Register - VPD_DR
4071 ** -----------------------------------------------------------------
4073 ** 31:00 0000H VPD Data - Four bytes are always read or written throug…
4079 ** Power Management Capability Identifier Register -PM_CAPID
4081 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specific…
4082 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extend…
4083 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power
4084 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management
4086 ** -----------------------------------------------------------------
4088 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies thi…
4089 ** Headers as being the PCI Power Management Registers.
4095 ** Power Management Next Item Pointer Register - PM_NXTP
4097 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specificatio…
4099 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H.
4100 ** -----------------------------------------------------------------
4102 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset int…
4109 ** Power Management Capabilities Register - PM_CAP
4111 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management
4112 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provi…
4114 ** -----------------------------------------------------------------
4116 ** 15:11 00000 2 PME_Support - This function is not capable of asserting…
4118 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the…
4119 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the…
4120 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating tha…
4121 ** 3.3Vaux signal as defined in the PCI Bu…
4122 ** 5 0 2 DSI - This field is set to 0 2 meaning that this functi…
4125 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signa…
4126 … 010 2 Version - Setting these bits to 010 2 means that this function com…
4133 ** Power Management Control/Status Register - PM_CSR
4135 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power
4136 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status
4138 ** -----------------------------------------------------------------
4140 ** 15 0 2 PME_Status - This function is not capable of asserting …
4143 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since t…
4146 ** 1:0 00 2 Power State - This 2-bit field is used both to determin…
4148 ** 00 2 - D0
4149 ** 01 2 - D1
4150 ** 10 2 - D2 (Unsupported)
4151 ** 11 2 - D3 hot
4159 ** PCI-X Capability Identifier Register - PX_CAPID
4161 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specific…
4162 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extend…
4163 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capab…
4164 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
4165 ** -----------------------------------------------------------------
4167 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies thi…
4168 ** Headers as being the PCI-X capability registers.
4174 ** PCI-X Next Item Pointer Register - PX_NXTP
4176 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specificatio…
4178 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this registe…
4181 ** capability located at off-set B8H.
4187 …this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register -
4189 ** -----------------------------------------------------------------
4191 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset int…
4192 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in t…
4201 ** PCI-X Command Register - PX_CMD
4204 ** PCI-X mode.
4205 ** -----------------------------------------------------------------
4208 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register …
4219 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the…
4227 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester A…
4229 ** 0 0 2 Data Parity Error Recovery Enable - The device driver s…
4230 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the dev…
4237 ** PCI-X Status Register - PX_SR
4240 ** Unit when operating in the PCI-X mode.
4241 ** -----------------------------------------------------------------
4244 ** 29 0 2 Received Split Completion Error Message - This bit is s…
4249 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The val…
4256 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 8…
4257 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can…
4260 ** 19 0 2 Unexpected Split Completion - This bit is set when an u…
4264 ** 18 0 2 Split Completion Discarded - This bit is set when the d…
4265 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus
4273 …with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus…
4276 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-c…
4278 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap.
4281 ** 15:8 FFH Bus Number - This register is read for diagnostic purpo…
4292 ** 7:3 1FH Device Number - This register is read for diagnostic pu…
4305 ** 2:0 000 2 Function Number - This register is read for diagnostic …
4318 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local
4319 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through
4322 ** When operating in the conventional PCI mode, all inbound read transactions are processed as
4323 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are
4324 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards
4325 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow…
4326 ** an inbound read transaction on the PCI bus is summarized in the following statements:
4327 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound
4330 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction
4333 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a
4334 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a
4341 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from
4343 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the
4348 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to
4350 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and
4353 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned
4355 ** before returning read data by generating the split completion transaction on the PCI-X bus.
4358 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it
4364 ** Message (message class=2h - completer error, and message index=81h - target abort) to
4368 ** Message (message class=2h - completer error, and message index=80h - Master abort) to
4371 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI
4372 ** bus, the ATU PCI slave interface waits with no premature disconnects.
4375 ** �E When operating in the conventional PCI mode, when the read on the internal bus is
4376 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. Th…
4379 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h
4381 ** a Split Completion Message (message class=2h - completer error, and message index=81h -
4386 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus
4389 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a
4390 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer
4391 ** error, and message index=80h - internal bus master abort) to inform the requester about the
4393 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with
4394 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that
4400 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in
4401 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the
4403 ** always uses conventional PCI ordering rules.
4407 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI
4414 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal
4415 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is
4417 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from
4419 ** Completion Message (message class=2h - completer error, and message index=81h -
4420 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The
4422 ** �X When operating in the conventional PCI mode, a single data phase disconnection is
4426 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from
4429 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received
4431 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the
4434 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to
4440 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address
4443 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read
4451 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local
4452 ** memory or a 80331 memory-mapped register.
4453 ** Data flow for an inbound write transaction on the PCI bus is summarized as:
4454 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound
4459 ** �E The PCI interface continues to accept write data until one of the following is true:
4465 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute
4468 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2…
4470 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient
4471 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus
4475 …nternal master interface. The ATU does not insert target wait states nor do data merging on the PCI
4476 ** interface, when operating in the PCI mode.
4477 ** In the PCI-X mode memory writes are always executed as immediate transactions, while
4479 ** Completion Message, (with Message class=0h - Write Completion Class and Message index =
4480 ** 00h - Write Completion Message) once a configuration write is successfully executed.
4481 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transaction…
4490 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI
4492 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When
4493 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the
4494 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred
4501 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to
4516 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus.
4525 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
4536 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
4547 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X m…
4553 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
4564 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
4566 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the w…
4569 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode)
4583 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
4585 ** Conventional PCI Mode
4591 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the
4593 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status
4595 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for
4607 …or the original write transaction to be completed, the initiator retries the transaction on the PCI
4609 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and
4620 ** PCI-X Mode
4623 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error
4629 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and
4630 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus
4648 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
4650 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the
4657 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the
4658 ** PCI Master Parity Error bit in the ATUISR. When set, no action.
4667 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during
4679 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on
4688 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331
4690 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translatio…
4699 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Proce…
4700 **-------------------------------------------------------------------------------------------------…
4703 **-------------------------------------------------------------------------------------------------…
4706 **-------------------------------------------------------------------------------------------------…
4708 **-------------------------------------------------------------------------------------------------…
4709 ** Index Registers 1004 32-bit Memory Locations No Option…
4711 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space
4717 **------------------------------------------------------------------------
4722 **------------------------------------------------------------------------
4729 **------------------------------------------------------------------------
4732 **------------------------------------------------------------------------
4735 **------------------------------------------------------------------------
4738 **------------------------------------------------------------------------
4750 **--------------------
4757 ** Each holds a 32-bit value and generates an interrupt when written.
4758 **--------------------
4763 **--------------------
4772 **--------------------
4778 **--------------------
4779 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit,
4780 ** with the exception of Multi-DWORD reads to the index registers.
4781 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions
4783 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Resp…
4786 …his includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus.
4787 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect
4789 **--------------------
4790 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers.
4792 ** This PCI address window is used for PCI transactions that access the 80331 local memory.
4793 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Addr…
4794 **--------------------
4795 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit.
4796 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status in…
4797 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Con…
4798 ** The Messaging Unit reports all PCI errors in the ATU Status Register.
4799 **--------------------
4800 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device.
4802 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface.
4804 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert …
4819 ** -----------------
4820 ** . When an inbound message register is written by an external PCI agent, an interrupt may be gen…
4827 ** ------------------------------------------------------------------------
4828 ** Inbound Message Register - IMRx
4834 ** -----------------------------------------------------------------
4836 …0000 0000H Inbound Message - This is a 32-bit message written by an external P…
4844 ** Outbound Message Register - OMRx
4845 ** --------------------------------
4847 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt
4852 ** 31:00 00000000H Outbound Message - This is 32-bit message written by th…
4853 … interrupt may be generated on the PCI Interrupt pin deter…
4865 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R …
4866 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt.
4870 ** ------------------
4871 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be g…
4874 …nce a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent.
4883 ** ------------------------------------------------------------------------
4884 ** Inbound Doorbell Register - IDR
4891 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared…
4892 ** ------------------------------------------------------------------------
4894 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the In…
4895 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Norm…
4902 ** Inbound Interrupt Status Register - IISR
4916 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware
4917 ** when an Index Register has been written after a PCI transaction.
4918 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set
4921 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware …
4927 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrup…
4929 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one
4932 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware w…
4933 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware w…
4946 ** Inbound Interrupt Mask Register - IIMR
4952 ** ------------------------------------------------------------------------
4955 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interr…
4956 ** when an Index Register has been written after a PCI transaction.
4957 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks …
4959 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the in…
4961 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error …
4963 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the inte…
4965 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inb…
4967 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set,
4981 ** Outbound Doorbell Register - ODR
4984 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The
4985 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the
4988 ** be cleared by an external PCI agent.
4989 ** ----------------------------------------------------------------------
4994 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# …
4996 ** signal to be asserted or a Message-sig…
5000 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# …
5002 ** signal is asserted or a Message-signaled Interrupt is …
5010 ** Outbound Interrupt Status Register - OISR
5013 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circul…
5014 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may
5018 ** ----------------------------------------------------------------------
5021 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt …
5022 … To clear this bit (and the interrupt), the PCI Interrupt bit must …
5023 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when da…
5025 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at l…
5028 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the M…
5030 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the M…
5042 ** Outbound Interrupt Mask Register - OIMR
5043 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI
5045 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI
5048 ** only affect the generation of the PCI interrupt.
5049 ** ----------------------------------------------------------------------
5052 … 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt gen…
5054 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit…
5056 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit m…
5058 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit …
5060 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit m…
5101 …ame | Purpose | Action on PCI Interface|
5119 ** The circular queues are accessed by external PCI agents through two port locations in the PCI
5123 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write …
5124 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and writ…
5125 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/…
5127 ** This is treated as when the PCI transaction did not occur.
5128 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface.
5134 ** Each entry in the queue is a 32-bit data value.
5136 ** . Multi-DWORD accesses to the circular queues are not allowed.
5137 ** Sub-DWORD accesses are promoted to DWORD accesses.
5149 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt …
5169 ** ------------------
5171 …m the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents.
5173 ** For a PCI write transaction that accesses the Inbound Queue Port,
5188 ** From the time that the PCI write transaction is received until the data is written
5190 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry.
5195 ** the hardware retries any PCI writes until a slot in the queue becomes available.
5199 ** ------------------
5201 ** This queue is read from the queue tail by external PCI agents.
5205 ** For a PCI read transaction that accesses the Inbound Queue Port,
5210 ** the value of -1 (FFFF.FFFFH) is returned.
5213 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate…
5215 ** When the PCI read access occurs, the data is read directly from the prefetch register.
5216 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register
5218 …der to update the prefetch register when messages are added to the queue and it becomes non-empty,
5222 ** A prefetch must appear atomic from the perspective of the external PCI agent.
5223 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue …
5229 ** -------------------
5231 ** core for other processors to process. This queue is read from the queue tail by external PCI ag…
5234 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the
5238 ** pointers are equal and the head pointer was last updated by hardware), the value of -1
5242 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate
5244 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access
5246 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head
5248 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically
5252 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is
5253 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Ret…
5255 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch
5265 ** -----------------------
5268 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel
5270 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the
5281 ** From the time that a PCI write transaction is received until the data is written in local memor…
5282 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to
5287 ** the hardware must retry any PCI writes until a slot in the queue becomes available.
5291 ** ----------------------
5293 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head…
5303 ** ----------------------
5318 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent ca…
5322 ** PCI write accesses to the Index Registers write the data to local memory.
5323 ** PCI read accesses to the Index Registers read the data from local memory.
5330 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the addres…
5333 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes.
5349 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI addr…
5351 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address
5364 ** FFFF E35CH reserved | must translate PCI addr…
5366 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address
5382 ** MU Configuration Register - MUCR FFFF.E350H
5387 ** and tail pointer registers before any PCI accesses to the Queue Ports.
5389 ** ------------------------------------------------------------------------
5392 ** 05:01 00001 2 Circular Queue Size - This field determines the size of…
5394 ** �E 00001 2 - 4K Entries (16 Kbytes)
5395 ** �E 00010 2 - 8K Entries (32 Kbytes)
5396 ** �E 00100 2 - 16K Entries (64 Kbytes)
5397 ** �E 01000 2 - 32K Entries (128 Kbytes)
5398 ** �E 10000 2 - 64K Entries (256 Kbytes)
5399 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Ci…
5400 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but i…
5414 ** Queue Base Address Register - QBAR
5423 ** ------------------------------------------------------------------------
5425 ** 31:20 000H Queue Base Address - Local memory address of the circul…
5432 ** Inbound Free Head Pointer Register - IFHPR
5440 ** ------------------------------------------------------------------------
5442 ** 31:20 000H Queue Base Address - Local memory address of the circul…
5443 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the …
5450 ** Inbound Free Tail Pointer Register - IFTPR
5456 ** ------------------------------------------------------------------------
5458 ** 31:20 000H Queue Base Address - Local memory address of the circul…
5459 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the …
5466 ** Inbound Post Head Pointer Register - IPHPR
5472 ** ------------------------------------------------------------------------
5474 ** 31:20 000H Queue Base Address - Local memory address of the circul…
5475 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the …
5482 ** Inbound Post Tail Pointer Register - IPTPR
5488 ** ------------------------------------------------------------------------
5490 ** 31:20 000H Queue Base Address - Local memory address of the circul…
5491 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the …
5498 ** Index Address Register - IAR
5501 ** It is written by the MU when the Index Registers are written by a PCI agent.
5505 ** ------------------------------------------------------------------------
5508 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index…
5515 ** RS-232 Interface for Areca Raid Controller
5517 ** --------------------------------------------------------------------
5519 ** --------------------------------------------------------------------
5523 ** --------------------------------------------------------------------
5525 ** --------------------------------------------------------------------
5532 ** --------------------------------------------------------------------
5534 ** --------------------------------------------------------------------
5535 ** The following are command code defined in raid controller Command code 0x10--0x1? are used f…
5537 ** Command code 0x20--0x?? always check the password, password must be entered to enable these …
5538 ** enum
5596 ** byte 4-0x13 : should be "ArEcATecHnoLogY"
5597 ** byte 0x14--0x23 : Serial number string (must be 16 bytes)
5602 ** byte 4-0x13 : should be "ArEcAvAr"
5603 ** byte 0x14--0x3B : vendor string (must be 40 bytes)
5608 ** byte 4-0x13 : should be "ArEcAvAr"
5609 ** byte 0x14--0x1B : model string (must be 8 bytes)
5618 ** byte 4-0x?? : user password to be checked
5619 ** GUI_LOGOUT : Logout GUI (force password checking on next command)
5628 ** byte 4-0x13 : should be "ArEcAvAr"
5629 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes)
5633 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo)
5729 ** byte 3 : drive # (from 0 to max-channels - 1)
5809 ** byte 3 : 0->disable, 1->enable
5815 ** byte 4 : password (must be alpha-numerical)
5820 ** byte 3 : 0->Independent, 1->cluster
5825 ** byte 3 : 0/1/2/3 (low->high)
5840 ** byte 3 : 0->COMA (term port), 1->COMB (debug port)
5862 ** byte 5 : scsi id (0-->15)
5863 ** byte 6 : scsi lun (0-->7)
5874 ** byte 5 : scsi id (0-->15)
5875 ** byte 6 : scsi lun (0-->7)
5897 ** byte 7-22 : raidset name (if byte 7 == 0:use default)
5909 …nge, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K )
5931 ** byte 4-19 : volume set name (if byte4 == 0, use default)
5932 ** byte 20-27 : volume capacity (blocks)
5934 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5940 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5941 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5948 ** byte 4-19 : new volume set name (if byte4 == 0, not change)
5949 ** byte 20-27 : new volume capacity (reserved)
5951 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5957 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5958 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5973 ** ---------------------------------------------------------------------
5975 ** ---------------------------------------------------------------------