Lines Matching full:outbound
299 /* outbound firmware ok */
363 …UTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrup…
364 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post…
369 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
370 …** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or throug…
374 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
375 ** value. This bit clears only when Outbound Doorbell bits
376 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
377 ** Clear register clears bits in the Outbound Doorbell register.
381 ** Set whenever the Outbound Post List Producer/Consumer
382 ** Register (FIFO) is not empty. It clears when the Outbound
396 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr…
398 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr …
399 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 read…
400 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd is…
455 /*outbound message 0 ready*/
460 /*outbound message cmd isr door bell clear*/
463 /*outbound list */
484 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */
609 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
618 …u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer cons…
619 …u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer cons…
639 …u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port …
640 …u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port …
753 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
783 …u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port …
784 …u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port …
831 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/
861 …u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port …
862 …u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port …
929 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver)
968 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to d…
1003 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Stat…
1004 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound mess…
1008 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver)
1014 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP s…
1056 ** outbound doorbell : at offset 0x9C
1057 ** outbound doorbell clear : at offset 0xA0
1059 ** outbound doorbell : bit0 -- reserved
1062 ** bit3 -- outbound message 0 ready
1067 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code ms…
1074 ** outbound queue port32 at offset 0x44
1075 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper)
1078 ** same for outbound queue port
1081 ** to retrieve outbound request in a single instruction.
1083 ** then write low part. For receiving outbound request, read high part first
1114 ** <D> Outbound Posting
2749 ** �E Read Data Parity Error when the ATU is a requester (outbound read).
3438 ** Outbound I/O Window Translate Value Register - OIOWTVR
3440 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address
3442 ** result of the outbound ATU address translation.
3447 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert i…
3454 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0
3456 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI
3457 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is
3458 ** driven on the PCI bus as a result of the outbound ATU address translation.
3463 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 int…
3472 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
3474 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines
3475 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3488 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1
3490 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI
3491 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is
3492 ** driven on the PCI bus as a result of the outbound ATU address translation.
3497 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 int…
3506 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
3508 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines
3509 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3522 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR
3524 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the
3526 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host
3538 ** The ATU Configuration Register controls the outbound address translation for address translation
3563 … Direct Addressing Enable - Setting this bit enables direct outbound addressing throug…
3572 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound ad…
3573 ** When cleared, disables the outbound ATU.
3616 ** Outbound Transaction Queue Busy:
3617 ** 0=Outbound Transaction Queue Empty
3618 ** 1=Outbound Transaction Queue Busy
3676 ** ATU is either waiting to receive (Outbound Request) or initiate
3681 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueue…
3682 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) T…
3686 ** however the user is now assured that the ATU no longer has any pending inbound or outbound spl…
3762 ** �E Read Data Parity Error when the ATU is an initiator (outbound read).
3977 ** Outbound Configuration Cycle Address Register - OCCAR
3979 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration
3981 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or
3982 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on …
3988 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI…
3992 … Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound
3999 ** Outbound Configuration Cycle Data Register - OCCDR
4001 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write
4012 … Configuration Cycle Data - These bits define the data used during an outbound configuration rea…
4702 ** 2 Outbound
4705 ** 1 Outbound
4720 ** 0018H Outbound Message Register 0 ]
4721 ** 001CH Outbound Message Register 1 ] 4 Message Registers
4726 ** 002CH Outbound Doorbell Register ]
4727 ** 0030H Outbound Interrupt Status Register ]
4728 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Regis…
4734 ** 0044H Outbound Queue Port ] 2 Queue Ports
4770 ** Two queues are used for inbound messages and two are used for outbound messages.
4776 …interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status …
4804 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert …
4814 ** Outbound messages are sent by the 80331 and received by the host processor.
4815 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Regis…
4844 ** Outbound Message Register - OMRx
4846 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is
4847 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt
4848 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound
4852 ** 31:00 00000000H Outbound Message - This is 32-bit message written by th…
4864 ** Outbound Doorbell Register
4866 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt.
4907 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt;
4918 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set
4919 ** when the Outbound Free Head Pointer becomes equal to the Tail Poin…
4957 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks …
4958 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full.
4981 ** Outbound Doorbell Register - ODR
4983 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel
4985 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the
4986 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register.
5010 ** Outbound Interrupt Status Register - OISR
5012 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the
5014 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may
5015 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the
5021 …upt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register.
5023 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when da…
5024 … cleared when any prefetch data has been read from the Outbound Queue Port.
5025 … Outbound Doorbell Interrupt - This bit is set when at least one Software …
5026 …Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound
5028 …1 0 2 Outbound Message 1 Interrupt - This bit is set by the MU wh…
5030 …0 0 2 Outbound Message 0 Interrupt - This bit is set by the MU wh…
5042 ** Outbound Interrupt Mask Register - OIMR
5043 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI
5045 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI
5047 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Registe…
5053 ** in the Outbound Doorbell Register …
5054 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit…
5056 … 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interru…
5058 …01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit mas…
5059 … generated by a write to the Outbound Message 1 Registe…
5060 …00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit mask…
5061 … generated by a write to the Outbound Message 0 Registe…
5082 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In
5083 ** this case, inbound and outbound refer to the direction of the flow of posted messages.
5087 ** Outbound messages are either:
5090 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow towar…
5093 ** and the two outbound queues are used to handle outbound messages.
5096 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound qu…
5107 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | …
5109 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | …
5122 ** and Outbound Queue Port.
5124 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and writ…
5125 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/…
5128 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface.
5165 ** Outbound Post Queue QBAR + 2 * Queue Size
5166 ** Outbound Free Queue QBAR + 3 * Queue Size
5228 ** Outbound Post Queue
5230 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale
5234 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the
5235 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is …
5240 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer
5243 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the
5244 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access
5249 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head
5250 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head
5253 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Ret…
5256 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound
5258 …interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound
5259 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register.
5260 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to
5261 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then
5262 ** increment the Outbound Post Head Pointer Register.
5264 ** Outbound Free Queue
5266 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel
5270 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the
5271 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the
5272 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free
5276 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound F…
5279 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the
5282 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to
5283 ** access the Outbound Free Queue Port is signalled a retry.
5284 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data
5285 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must
5286 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full,
5346 ** FFFF E318H Outbound Message Register 0 |
5347 ** FFFF E31CH Outbound Message Register 1 | or
5351 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address
5352 ** FFFF E330H Outbound Interrupt Status Register |
5353 ** FFFF E334H Outbound Interrupt Mask Register |
5369 ** FFFF E370H Outbound Free Head Pointer Register |
5370 ** FFFF E374H Outbound Free Tail Pointer Register |
5371 ** FFFF E378H Outbound Post Head pointer Register |
5372 ** FFFF E37CH Outbound Post Tail Pointer Register |