Lines Matching +full:mu +full:- +full:side +full:- +full:b
11 ** SPDX-License-Identifier: BSD-3-Clause
13 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
43 #define ARCMSR_VIRTUAL_DEVICE_ID (ARCMSR_MAX_TARGETID - 1)
71 #define offsetof(type, member) ((size_t)(&((type *)0)->member))
197 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s,… argument
198 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(stru… argument
199 #define READ_CHIP_REG32(b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], r) argument
200 #define WRITE_CHIP_REG32(b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d) argument
374 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
486 /* ARC-1884 doorbell sync */
496 /* ARC-1886 doorbell sync */
505 ** Messaging Unit (MU) of Type A processor
513 u_int32_t outbound_msgaddr0; /*0018 001B*/
517 u_int32_t inbound_intmask; /*0028 002B*/
569 ** Messaging Unit (MU) of Type B processor(MARVEL)
588 ** Messaging Unit (MU) of Type C processor(LSI)
594 u_int32_t slave_error_address; /*0008 000B*/
598 u_int32_t master_error_address_high; /*0018 001B*/
602 u_int32_t diagnostic_rw_address_low; /*0028 002B*/
606 u_int32_t dcr_data; /*0038 003B*/
610 u_int32_t hcb_pci_address_low; /*0048 004B*/
614 u_int32_t iop_inbound_queue_port; /*0058 005B*/
618 …u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer cons…
622 u_int32_t last_used_message_source_address_low; /*0078 007B*/
627 u_int32_t utility_A_int_counter_timer; /*0098 009B*/
663 ** Messaging Unit (MU) of Type D processor
732 ** Messaging Unit (MU) of Type E processor(LSI)
738 u_int32_t host_diagnostic_3xxx; /*0008 000B*/
742 u_int32_t master_error_address_high; /*0018 001B*/
746 u_int32_t diagnostic_rw_address_low; /*0028 002B*/
750 u_int32_t dcr_data; /*0038 003B*/
754 u_int32_t hcb_pci_address_low; /*0048 004B*/
758 u_int32_t iop_inbound_queue_port; /*0058 005B*/
762 u_int32_t outbound_free_list_index; /*0068 006B*/
766 u_int32_t last_used_message_source_address_low; /*0078 007B*/
771 u_int32_t utility_A_int_counter_timer; /*0098 009B*/
810 ** Messaging Unit (MU) of Type F processor(LSI)
816 u_int32_t host_diagnostic_3xxx; /*0008 000B*/
820 u_int32_t master_error_address_high; /*0018 001B*/
824 u_int32_t diagnostic_rw_address_low; /*0028 002B*/
828 u_int32_t dcr_data; /*0038 003B*/
832 u_int32_t hcb_pci_address_low; /*0048 004B*/
836 u_int32_t iop_inbound_queue_port; /*0058 005B*/
840 u_int32_t reply_post_producer_index; /*0068 006B*/
844 u_int32_t last_used_message_source_address_low; /*0078 007B*/
849 u_int32_t utility_A_int_counter_timer; /*0098 009B*/
919 ** 1. Message 0 --> InitThread message and retrun code
920 ** 2. Doorbell is used for RS-232 emulation
921 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK)
922 ** bit1 -- data out has been read (DRIVER DATA READ OK)
923 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK)
924 ** bit1 -- data in has been read (IOP331 DATA READ OK)
930 ** 4. RS-232 emulation
932 ** 1st u_int32_t : Data length (1--124)
933 ** Byte 4--127 : Max 124 bytes of data
937 ** # bit27--bit31 => flag for post ccb
938 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb
946 ** -------------------------------------------------------------------------------
948 ** # bit27--bit31 => flag for reply
949 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb
965 ** 8. Message1 Out - Diag Status Code (????)
968 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to d…
972 ** SDRAM Size 0x00000100(4)-->256 MB
980 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to I…
982 ** UPPER32 of Request Frame (4)-->Driver Only
986 ** 0x06 : Start Background Activity (re-start if background is halted)
988 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver …
989 ** byte 0 : 0xaa <-- signature
990 ** byte 1 : 0x55 <-- signature
1007 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop)
1008 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver)
1010 ** a. Message1: Out - Diag Status Code (????)
1012 ** b. Message0: message code
1014 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP s…
1018 ** SDRAM Size 0x00000100(4)-->256 MB
1025 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver…
1027 ** UPPER32 of Request Frame (4)-->Driver Only
1031 ** 0x06 : Start Background Activity (re-start if background is halted)
1033 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuff…
1034 ** byte 0 : 0xaa <-- signature
1035 ** byte 1 : 0x55 <-- signature
1043 ** <2> Doorbell Register is used for RS-232 emulation
1045 ** <B> different bit0 definition (bit0 is reserved)
1050 ** inbound doorbell : bit0 -- reserved
1051 ** bit1 -- data in ready (DRIVER DATA WRITE OK)
1052 ** bit2 -- data out has been read (DRIVER DATA READ OK)
1053 ** bit3 -- inbound message 0 ready
1054 ** bit4 -- more than 12 request completed in a time
1059 ** outbound doorbell : bit0 -- reserved
1060 ** bit1 -- data out ready (IOP DATA WRITE OK)
1061 ** bit2 -- data in has been read (IOP DATA READ OK)
1062 ** bit3 -- outbound message 0 ready
1065 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS…
1066 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS…
1067 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code ms…
1068 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code ms…
1079 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction
1092 ** ----------------------------
1094 ** ----------------------------
1104 ** -----------------------------
1106 ** -----------------------------
1107 ** post addr = addr | ((len-1) >> 6) | 1
1108 ** -----------------------------
1119 ** bit63-4: Completed command address
1133 /* 32bit Scatter-Gather list */
1139 /* 64bit Scatter-Gather list */
1179 u_int32_t signature; /*0,00-03*/
1180 u_int32_t request_len; /*1,04-07*/
1181 u_int32_t numbers_queue; /*2,08-11*/
1182 u_int32_t sdram_size; /*3,12-15*/
1183 u_int32_t ide_channels; /*4,16-19*/
1184 char vendor[40]; /*5,20-59*/
1185 char model[8]; /*15,60-67*/
1186 char firmware_ver[16]; /*17,68-83*/
1187 char device_map[16]; /*21,84-99*/
1188 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
1189 char cfgSerial[16]; /*26,104-119*/
1190 u_int32_t cfgPicStatus; /*30,120-123*/
1204 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages
1226 u_int8_t TargetID; /* 01h should be 0--15 */
1227 u_int8_t LUN; /* 02h should be 0--7 */
1284 …struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descrip…
1285 unsigned long cdb_phyaddr; /* 504-507 */
1287 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */
1288 struct AdapterControlBlock *acb; /* 520-523 524-527 */
1289 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */
1290 u_int16_t srb_flags; /* 536-537 */
1291 u_int16_t srb_state; /* 538-539 */
1292 u_int32_t arc_cdb_size; /* 508-511 */
1337 u_int32_t adapter_type; /* adapter A,B..... */
1364 }B; member
1373 uint32_t *message_wbuffer; //0x000 - COMPORT_IN (to be sent to ROC)
1374 uint32_t *message_rbuffer; //0x100 - COMPORT_OUT (to be sent to Host)
1375 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA
1403 u_int32_t firm_request_len; /*1,04-07*/
1404 u_int32_t firm_numbers_queue; /*2,08-11*/
1405 u_int32_t firm_sdram_size; /*3,12-15*/
1406 u_int32_t firm_ide_channels; /*4,16-19*/
1408 char firm_model[12]; /*15,60-67*/
1409 char firm_version[20]; /*17,68-83*/
1410 char device_map[20]; /*21,84-99 */
1507 #define SCSI_DASD 0x00 /* Direct-access Device */
1508 #define SCSI_SEQACESS 0x01 /* Sequential-access device */
1511 #define SCSI_WRITEONCE 0x04 /* Write-once device */
1512 #define SCSI_CDROM 0x05 /* CD-ROM device */
1521 ** 80331 PCI-to-PCI Bridge
1530 ** -------------------------------------------------------------
1531 ** Standard PCI Configuration 00-3Fh
1532 ** -------------------------------------------------------------
1533 ** Device Specific Registers 40-A7h
1534 ** -------------------------------------------------------------
1535 ** Reserved A8-CBh
1536 ** -------------------------------------------------------------
1537 ** Enhanced Capability List CC-FFh
1541 … Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
1542 ** ------------------------------------------------------------------------------------------------…
1544 ** ------------------------------------------------------------------------------------------------…
1546 ** ------------------------------------------------------------------------------------------------…
1548 ** ------------------------------------------------------------------------------------------------…
1550 ** ------------------------------------------------------------------------------------------------…
1552 ** ------------------------------------------------------------------------------------------------…
1554 ** ------------------------------------------------------------------------------------------------…
1556 ** ------------------------------------------------------------------------------------------------…
1558 ** ------------------------------------------------------------------------------------------------…
1559 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address …
1560 ** ------------------------------------------------------------------------------------------------…
1562 ** ------------------------------------------------------------------------------------------------…
1564 ** ------------------------------------------------------------------------------------------------…
1566 ** ------------------------------------------------------------------------------------------------…
1568 ** ------------------------------------------------------------------------------------------------…
1570 ** ------------------------------------------------------------------------------------------------…
1572 ** ------------------------------------------------------------------------------------------------…
1578 ** 0x03-0x00 :
1582 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vend…
1589 ** 0x05-0x04 : command register
1611 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible …
1624 … MWI transactions targeting resources on the opposite side of the bridge,
1644 ** 0x07-0x06 : status register
1646 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b when…
1649 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b when…
1650 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when…
1654 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when…
1657 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when…
1659 ** In PCI-X mode this bit is also set wh…
1660 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-c…
1661 ** Returns ��01b�� when read, indicating…
1662 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when…
1666 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating tha…
1669 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating tha…
1671 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that …
1686 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping.
1692 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode )
1695 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI …
1696 … Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge.
1704 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-…
1716 ** 0x0d : latency timer (number of pci clock 00-ff )
1726 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer.
1742 ** 07 0 Multi-function device (MVD): 80331 is a single-function device.
1745 ** that the register layout conforms to the standard PCI-to-PCI bridge layout.
1756 ** 0x13-0x10 :
1762 ** 0x17-0x14 :
1768 ** 0x1b-0x18 :
1770 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR
1785 **-----------------0x1B--Secondary Latency Timer Register - SLTR
1796 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer.
1813 ** 0x1f-0x1c :
1815 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL
1821 … I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit …
1827 … I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bi…
1828 **-----------------0x1F,0x1E--Secondary Status Register - SSR
1830 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b when…
1832 ** 14 0b Received System Error: The bridge sets this bit when it samp…
1833 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when…
1837 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when…
1840 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when…
1842 ** In PCI-X mode this bit is also set wh…
1843 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-c…
1844 ** Returns ��01b�� when read, indicating…
1845 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when…
1849 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interfac…
1850 ** 06 0b Reserved
1851 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of …
1861 ** 0x23-0x20 :
1863 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL
1884 ** 0x27-0x24 :
1886 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL
1893 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is s…
1900 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is s…
1907 ** 0x2b-0x28 :
1910 ** bridge supports full 64-bit addressin…
1916 ** 0x2f-0x2c :
1919 ** bridge supports full 64-bit addressi…
1925 ** 0x33-0x30 :
1934 ** 0x3b-0x35 : reserved
1939 ** 0x3d-0x3c :
1950 ** 0x3f-0x3e :
1953 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on t…
1955 ** 0b=SERR# is not asserted.
1956 ** 1b=SERR# is asserted.
1957 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either…
1959 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock …
1967 ** 0b=The secondary master time-out coun…
1968 ** 1b=The secondary master time-out coun…
1969 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock …
1977 ** 0b=The primary master time-out counte…
1978 ** 1b=The primary master time-out counte…
1979 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to …
1980 ** 06 0b Secondary Bus Reset (SBR):
1981 ** When cleared to 0b: The bridge deasse…
1982 ** when it had been asserted by writing this bit to a 1b.
1983 ** When set to 1b: The bridge assert…
1984 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initi…
1987 … 0b=The bridge asserts TRDY# in response to a no…
1989 ** 1b=When the transaction had not yet b…
1990 ** (e.g.,delayed reads, or non-posted writes),
1995 ** For PCI-X transactions this bit is an enable for the assertion…
1997 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in …
2000 … When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b)
2002 ** 0b=Ignores address bits AD[15:10] whe…
2003 … 1b=Ensures that address bits AD[15:10] equal 000…
2004 …en all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b),
2006 ** 03 0b VGA Enable: Setting this bit enables address deco…
2011 ** or must be ��000000b��
2015 ** 02 0b ISA Enable: Setting this bit enables special hand…
2019 ** (i.e., 0000 0000h - 0000 FFFFh).
2020 ** 0b=All I/O transactions that fall wit…
2023 ** 1b=Blocks the forwarding from primary…
2028 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR#…
2029 ** 1b=The bridge asserts P_SERR# wheneve…
2030 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b).
2031 ** 00 0b Parity Error Response: This bit controls bridge response to …
2033 ** 0b=When a data parity error is detect…
2036 ** 1b=When a data parity error is detect…
2045 ** Device Specific Registers 40-A7h
2047 ** ------------------------------------------------------------------------------------------------…
2048 … Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
2049 ** ------------------------------------------------------------------------------------------------…
2051 ** ------------------------------------------------------------------------------------------------…
2053 ** ------------------------------------------------------------------------------------------------…
2055 ** ------------------------------------------------------------------------------------------------…
2057 ** ------------------------------------------------------------------------------------------------…
2058 ** | Prefetch Policy | Multi-Transaction Timer …
2059 ** ------------------------------------------------------------------------------------------------…
2060 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control …
2061 ** ------------------------------------------------------------------------------------------------…
2063 ** ------------------------------------------------------------------------------------------------…
2065 ** ------------------------------------------------------------------------------------------------…
2067 ** ------------------------------------------------------------------------------------------------…
2069 ** ------------------------------------------------------------------------------------------------…
2072 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR
2074 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that v…
2075 ** (PCI=16 clocks,PCI-X=6 clocks).
2077 … # Bit[11] of this register is set to 1b,
2078 ** indicating that a Grant Time-out violation had occurred.
2081 ** 0000b REQ#/GNT#[0]
2082 ** 0001b REQ#/GNT#[1]
2083 ** 0010b REQ#/GNT#[2]
2084 ** 0011b REQ#/GNT#[3]
2085 ** 1111b Default Value (no violation detected)
2088 ** 11 0b Grant Time-out Occurred: When set to 1b,
2089 ** this indicates that a Grant Time-out error had occurred involv…
2090 ** Software clears this bit by writing a 1b to it.
2091 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the b…
2094 ** 09:08 00b Reserved
2095 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbite…
2097 ** bus master to either the high priority arbiter ring (1b)
2098 ** or to the low priority arbiter ring (0b).
2103 ** 0b=Indicates that the maste…
2104 ** 1b=Indicates that the maste…
2106 ** 0x43: Bridge Control Register 0 - BCR0
2108 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transact…
2113 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability
2117 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus
2119 ** 0b=bridge treats all upstream Memory Read requests as though the…
2121 ** Multiple is enabled when forwarding a PCI-X Memory Read Blo…
2123 ** 1b=bridge treats upstream PCI Memory Read requests as though
2124 ** they target non-prefetchable memory and forwards upstream PCI-X Memory
2131 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2)
2133 ** 15:08 0000000b Reserved
2134 ** 07:06 00b Alias Command Mapping: This two bit field determines how bri…
2137 ** re-map to the actual block memory read/write command encoding, or ignore
2140 ** 0 0 Re-map to Memory Read/Write Block bef…
2144 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog…
2147 ** or Split Requests (PCI-X mode) is not…
2148 … (��events�� are defined as PCI Clocks when operating in PCI-X mode,
2150 ** 0b=All 2 24 watchdog timers are enabl…
2151 ** 1b=All 2 24 watchdog timers are disab…
2155 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# ti…
2156 … Grant time-out is 16 clocks for conventional PCI, and 6 clocks…
2157 ** 0b=The Secondary bus arbiter times ou…
2160 ** The time-out counter begins as s…
2162 ** until it de-asserts its REQ# for at least one clock cycle.
2163 ** 1b=GNT# time-out mechanism is disable…
2164 ** 03 00b Reserved.
2165 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge seco…
2169 ** 0b=The secondary master time-out coun…
2172 ** 1b=The secondary master time-out coun…
2175 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge prim…
2179 ** 0b=The primary master time-out counte…
2181 ** 1b=The secondary master time-out coun…
2184 ** 00 0b Reserved
2186 ** 0x47-0x46: Bridge Control Register 2 - BCR2
2188 ** 15:07 0000b Reserved.
2189 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable):
2209 ** 0x49-0x48: Bridge Status Register - BSR
2211 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and…
2213 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired:
2214 … Conventional PCI Mode: This bit is set to a 1b and P_SERR#
2216 … PCI-X Mode: This bit is set to a 1b and P…
2220 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired:
2221 … Conventional PCI Mode: This bit is set to a 1b and P_SERR#
2223 … PCI-X Mode: This bit is set to a 1b and P…
2226 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and…
2229 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and…
2232 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and…
2235 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and…
2238 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and…
2241 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b an…
2243 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired:
2244 … Conventional PCI Mode: This bit is set to a 1b and P_SERR#
2247 … PCI-X Mode: This bit is set to a 1b and P…
2251 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired:
2252 … Conventional PCI Mode: This bit is set to a 1b and P_SERR# is condi…
2255 … PCI-X Mode: This bit is set to a 1b and P…
2259 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b an…
2262 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b an…
2265 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b an…
2268 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b an…
2271 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b an…
2274 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR
2276 ** 15:13 000b Reserved
2277 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI c…
2289 ** 09:08 00b Reserved
2295 ** When a given bit is set to 1b, its correspondin…
2297 ** When a given bit is cleared to 0b, its correspo…
2299 ** 0x53-0x52: Read Prefetch Policy Register - RPPR
2301 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplicatio…
2304 … The default value of 000b correlates to: Command Type Hardwired pre-…
2306 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplicatio…
2309 … The default value of 000b correlates to: Command Type Hardwired pre-…
2311 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplicatio…
2316 … The default value of 010b correlates to: Command Type Hardwired pre-…
2319 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplicatio…
2322 … The default value of 000b correlates to: Command Type Hardwired pre-…
2324 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRea…
2329 … 1b: enables the staged pre-fetch fea…
2330 … 0b: disables staged pre-fetch,
2331 ** and hardwires read pre-fetch policy to t…
2335 ** Command Type Hardwired Pre-Fetch Amount...
2339 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line c…
2340 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read
2341 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered.
2343 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL
2345 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavi…
2347 ** 0b=bridge asserts P_SERR#.
2348 ** 1b=bridge does not assert …
2349 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior f…
2350 ** 0b=bridge asserts P_SERR#.
2351 ** 1b=bridge does not assert …
2352 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior …
2353 ** 0b=bridge asserts P_SERR#.
2354 ** 1b=bridge does not assert …
2355 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior …
2357 ** 0b=bridge asserts P_SERR#.
2358 ** 1b=bridge does not assert …
2359 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior …
2361 ** 0b=bridge asserts P_SERR#.
2362 ** 1b=bridge does not assert …
2363 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior …
2365 ** 0b=bridge asserts P_SERR#.
2366 ** 1b=bridge does not assert …
2367 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior
2369 ** 0b=bridge asserts P_SERR#.
2370 ** 1b=bridge does not assert …
2371 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge …
2373 ** 0b=bridge asserts P_SERR#.
2374 ** 1b=bridge does not assert …
2375 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior …
2377 ** 0b=bridge asserts P_SERR#.
2378 ** 1b=bridge does not assert …
2379 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior …
2380 ** 0b=bridge asserts P_SERR#.
2381 ** 1b=bridge does not assert …
2382 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior …
2383 ** 0b=bridge asserts P_SERR#.
2384 ** 1b=bridge does not assert …
2385 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior …
2387 ** 0b=bridge asserts P_SERR#.
2388 ** 1b=bridge does not assert …
2389 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior …
2391 ** 0b=bridge asserts P_SERR#.
2392 ** 1b=bridge does not assert …
2393 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior …
2395 ** 0b=bridge asserts P_SERR#.
2396 ** 1b=bridge does not assert …
2397 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior
2399 ** 0b=bridge asserts P_SERR#.
2400 ** 1b=bridge does not assert …
2401 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge …
2403 ** 0b=bridge asserts P_SERR#.
2404 ** 1b=bridge does not assert …
2406 ** 0x56: Pre-Boot Status Register - PBSR
2409 ** 06 - Reserved - value indeterminate
2413 ** indicating the maximum secondary bus clock frequency when in PCI-X mode.
2415 ** ** S_133EN PCI-X Mode
2418 ** 00 0b Reserved
2420 ** 0x59-0x58: Secondary Decode Enable Register - SDER
2423 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - wh…
2425 … forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b.
2427 ** that allows peer-to-peer transactions.
2430 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR
2433 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this…
2437 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this…
2441 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this…
2445 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this…
2449 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this…
2453 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this…
2457 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this…
2461 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this…
2465 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this…
2469 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this…
2477 ** Reserved A8-CBh
2482 ** PCI Extended Enhanced Capabilities List CC-FFh
2484 ** ------------------------------------------------------------------------------------------------…
2485 … Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset
2486 ** ------------------------------------------------------------------------------------------------…
2488 ** ------------------------------------------------------------------------------------------------…
2490 ** ------------------------------------------------------------------------------------------------…
2492 ** ------------------------------------------------------------------------------------------------…
2494 ** ------------------------------------------------------------------------------------------------…
2496 ** ------------------------------------------------------------------------------------------------…
2497 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID…
2498 ** ------------------------------------------------------------------------------------------------…
2499 ** | PCI-X Bridge Status …
2500 ** ------------------------------------------------------------------------------------------------…
2501 ** | PCI-X Upstream Split Transaction Control …
2502 ** ------------------------------------------------------------------------------------------------…
2503 ** | PCI-X Downstream Split Transaction Control …
2504 ** ------------------------------------------------------------------------------------------------…
2506 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID
2508 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register …
2510 ** 0xDD: Next Item Pointer - PM_NXTP
2512 …Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability…
2514 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR
2520 ** This returns 000b as PME# wake-up for b…
2525 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR
2528 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to a…
2529 …ert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug.
2531 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine t…
2533 ** 00 - D0 state
2534 ** 01 - D1 state
2535 ** 10 - D2 state
2536 ** 11 - D3 hot state
2538 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE
2546 ** 0xE3: Power Management Data Register - PMDR
2550 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID
2552 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities li…
2554 ** 0xF1: Next Item Pointer - PX_NXTP
2559 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS
2571 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set …
2575 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set w…
2577 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpect…
2581 ** 02 0b Split Completion Discarded (SCD): This bit is set
2584 ** 01 1b 133 MHz Capable: Indicates that bridge is capable…
2585 ** 00 1b 64-bit Device (D64): Indicates the width of the secon…
2587 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS
2592 ** because bridge throttles traffic on the completion side.
2593 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b
2595 ** this bit by writing a 1b to it.
2596 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b
2597 … it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it.
2598 …icates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode.
2601 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indica…
2602 ** 0=Primary Interface is connected as a 32-bit PCI bus.
2603 ** 1=Primary Interface is connected as a 64-bit PCI bus.
2608 ** May be updated whenever a PCI-X
2612 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC
2620 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates t…
2625 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC
2633 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates t…
2650 ** ------------------------------------------------------------------------------------------------…
2652 ** ------------------------------------------------------------------------------------------------…
2654 ** ------------------------------------------------------------------------------------------------…
2656 ** ------------------------------------------------------------------------------------------------…
2658 ** ------------------------------------------------------------------------------------------------…
2660 ** ------------------------------------------------------------------------------------------------…
2662 ** ------------------------------------------------------------------------------------------------…
2664 ** ------------------------------------------------------------------------------------------------…
2666 ** ------------------------------------------------------------------------------------------------…
2668 ** ------------------------------------------------------------------------------------------------…
2670 ** ------------------------------------------------------------------------------------------------…
2672 ** ------------------------------------------------------------------------------------------------…
2674 ** ------------------------------------------------------------------------------------------------…
2676 ** ------------------------------------------------------------------------------------------------…
2678 ** ------------------------------------------------------------------------------------------------…
2680 ** ------------------------------------------------------------------------------------------------…
2685 ** ATU Vendor ID Register - ATUVID
2686 ** -----------------------------------------------------------------
2688 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Inte…
2697 ** ATU Device ID Register - ATUDID
2698 ** -----------------------------------------------------------------
2700 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the …
2707 ** ATU Command Register - ATUCMD
2708 ** -----------------------------------------------------------------
2711 ** 10 0 Interrupt Disable - This bit disables 80331 from assert…
2714 ** 09 0 2 Fast Back to Back Enable - When cleared,
2715 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus.
2716 ** Ignored when operating in the PCI-X mode.
2717 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not a…
2718 ** 07 1 2 Address/Data Stepping Control - Address stepping is imp…
2720 ** of address stepping for PCI-X mode.
2721 ** 06 0 2 Parity Error Response - When set, the ATU takes normal …
2723 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not s…
2725 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may …
2726 …When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode.
2727 ** 03 0 2 Special Cycle Enable - The ATU interface does not respo…
2729 ** 02 0 2 Bus Master Enable - The ATU interface can act as a mast…
2732 ** When operating in the PCI-X mode, ATU initiates a split…
2734 ** 01 0 2 Memory Enable - Controls the ATU interface��s response …
2736 ** 00 0 2 I/O Space Enable - Controls the ATU interface response …
2743 ** ATU Status Register - ATUSR (Sheet 1 of 2)
2744 ** -----------------------------------------------------------------
2746 ** 15 0 2 Detected Parity Error - set when a parity error is dete…
2750 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (i…
2751 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI …
2752 … Master Abort - set when a transaction initiated by the ATU PCI master interfa…
2753 … or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode.
2754 ** 12 0 2 Target Abort (master) - set when a transaction initiate…
2755 … abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode.
2756 ** 11 0 2 Target Abort (target) - set when the ATU interface, act…
2758 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define th…
2766 ** 08 0 2 Master Parity Error - The ATU interface sets this bit u…
2771 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
2774 ** 0 2 (PCI-X mode)
2775 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-t…
2777 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI…
2778 ** 06 0 2 UDF Supported - User Definable Features are not support…
2779 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported.
2780 ** 04 1 2 Capabilities - When set, this function implements exten…
2781 ** 03 0 Interrupt Status - reflects the state of the ATU interr…
2786 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU
2794 ** ATU Revision ID Register - ATURID
2795 ** -----------------------------------------------------------------
2797 ** 07:00 00H ATU Revision - identifies the 80331 revision number.
2803 ** ATU Class Code Register - ATUCCR
2804 ** -----------------------------------------------------------------
2806 ** 23:16 05H Base Class - Memory Controller
2807 ** 15:08 80H Sub Class - Other Memory Controller
2808 ** 07:00 00H Programming Interface - None defined
2814 ** ATU Cacheline Size Register - ATUCLSR
2815 ** -----------------------------------------------------------------
2817 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline siz…
2823 ** ATU Latency Timer Register - ATULT
2824 ** -----------------------------------------------------------------
2827 ** 01000 2 (for PCI-X mode)
2828 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to…
2829 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode.
2830 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable …
2836 ** ATU Header Type Register - ATUHTR
2837 ** -----------------------------------------------------------------
2839 … 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a sin…
2840 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of …
2847 ** ATU BIST Register - ATUBISTR
2852 ** -----------------------------------------------------------------
2854 ** 07 0 2 BIST Capable - This bit value is always equal to the AT…
2855 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit i…
2863 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is…
2865 ** A nonzero value indicates a device-specific error.
2883 … private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH).
2885 **--------------------------------------------------------------------------------------
2895 ** Inbound ATU Base Address Register 0 - IABAR0
2913 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specificat…
2917 ** -----------------------------------------------------------------
2919 ** 31:12 00000H Translation Base Address 0 - These bits define the actu…
2922 ** 03 1 2 Prefetchable Indicator - When set, defines the memory s…
2923 ** 02:01 10 2 Type Indicator - Defines the width of the addressabilit…
2924 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2925 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2926 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
2936 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0
2944 ** the IAUBAR0 register attributes are read-only.
2945 ** -----------------------------------------------------------------
2947 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Tr…
2954 ** Inbound ATU Base Address Register 1 - IABAR1
2962 ** When a non-zero value is not written to IALR1 prior to host configuration,
2965 ** Assuming a non-zero value is written to IALR1,
2972 ** b. when the Prefetchable Indicator is set prior to host configuration,
2974 ** -----------------------------------------------------------------
2976 ** 31:12 00000H Translation Base Address 1 - These bits define the actu…
2978 ** 03 0 2 Prefetchable Indicator - When set, defines the memory s…
2979 ** 02:01 00 2 Type Indicator - Defines the width of the addressabilit…
2980 ** 00 - Memory Window is locatable anywhere in 32 bit address space
2981 ** 10 - Memory Window is locatable anywhere in 64 bit address space
2982 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
2990 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1
3001 ** the IAUBAR1 register attributes are read-only.
3003 ** -----------------------------------------------------------------
3005 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Tr…
3012 ** Inbound ATU Base Address Register 2 - IABAR2
3021 ** When a non-zero value is not written to IALR2 prior to host configuration,
3025 ** Assuming a non-zero value is written to IALR2,
3032 ** b. when the Prefetchable Indicator is set prior to host configuration,
3034 ** -----------------------------------------------------------------
3036 ** 31:12 00000H Translation Base Address 2 - These bits define the actu…
3039 ** 03 0 2 Prefetchable Indicator - When set, defines the memory s…
3040 ** 02:01 00 2 Type Indicator - Defines the width of the addressabilit…
3041 ** 00 - Memory Window is locatable anywhere in 32 bit address space
3042 ** 10 - Memory Window is locatable anywhere in 64 bit address space
3043 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
3051 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2
3060 ** the IAUBAR2 register attributes are read-only.
3062 ** -----------------------------------------------------------------
3064 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Tr…
3072 ** ATU Subsystem Vendor ID Register - ASVIR
3073 ** -----------------------------------------------------------------
3075 … 0000H Subsystem Vendor ID - This register uniquely identifies the add-…
3081 ** ATU Subsystem ID Register - ASIR
3082 ** -----------------------------------------------------------------
3084 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or …
3090 ** Expansion ROM Base Address Register -ERBAR
3091 ** -----------------------------------------------------------------
3093 ** 31:12 00000H Expansion ROM Base Address - These bits define the actu…
3096 ** 00 0 2 Address Decode Enable - This bit field shows the ROM ad…
3104 ** ATU Capabilities Pointer Register - ATU_CAP_PTR
3105 ** -----------------------------------------------------------------
3107 ** 07:00 C0H Capability List Pointer - This provides an offset in th…
3116 ** reading from the registers. By scanning the returned value from the least-significant bit of th…
3118 ** binary-weighted value of the first non-zero bit found indicates the required amount of space.
3124 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value …
3154 ** imple-mented,
3168 ** ATU Interrupt Line Register - ATUILR
3169 ** -----------------------------------------------------------------
3171 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies w…
3180 ** ATU Interrupt Pin Register - ATUIPR
3181 ** -----------------------------------------------------------------
3183 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU …
3189 ** ATU Minimum Grant Register - ATUMGNT
3190 ** -----------------------------------------------------------------
3198 ** ATU Maximum Latency Register - ATUMLAT
3199 ** -----------------------------------------------------------------
3211 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory …
3214 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is
3217 ** mode and with Decode A DEVSEL# timing in the PCI-X mode.
3219 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-b…
3234 … window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH),
3238 ** PCI-to-PCI Bridge in 80331 or
3239 ** Inbound address detection is determined from the 32-bit PCI address,
3240 ** (64-bit PCI address during DACs) the base address register and the limit register.
3241 ** In the case of DACs none of the upper 32-bits of the address is masked during address c…
3249 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise AN…
3255 … Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit
3256 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and…
3257 ** lower 32-bits are used during address translation.
3264 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with …
3270 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in…
3278 ** Address Detection (32-bit address)
3295 ** Inbound ATU Limit Register 0 - IALR0
3310 ** -----------------------------------------------------------------
3312 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value deter…
3320 ** Inbound ATU Translate Value Register 0 - IATVR0
3325 ** -----------------------------------------------------------------
3327 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to…
3328 ** This value must be 64-bit aligned on the internal bus.
3329 ** The default address allows the ATU to access the internal 80331 memory-mapped registers.
3336 ** Expansion ROM Limit Register - ERLR
3344 ** -----------------------------------------------------------------
3346 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for…
3354 ** Expansion ROM Translate Value Register - ERTVR
3359 ** -----------------------------------------------------------------
3361 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI a…
3369 ** Inbound ATU Limit Register 1 - IALR1
3382 ** -----------------------------------------------------------------
3384 ** 31:12 00000H Inbound Translation Limit 1 - This readback value deter…
3392 ** Inbound ATU Limit Register 2 - IALR2
3412 ** -----------------------------------------------------------------
3414 ** 31:12 00000H Inbound Translation Limit 2 - This readback value deter…
3422 ** Inbound ATU Translate Value Register 2 - IATVR2
3427 ** -----------------------------------------------------------------
3429 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to…
3430 … This value must be 64-bit aligned on the in…
3431 ** The default address allows the ATU to access the internal 80331 ** ** memory-m…
3438 ** Outbound I/O Window Translate Value Register - OIOWTVR
3445 ** -----------------------------------------------------------------
3447 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert i…
3454 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0
3461 ** -----------------------------------------------------------------
3463 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 int…
3465 ** 01:00 00 2 Burst Order - This bit field shows the address sequence…
3472 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0
3474 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines
3475 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3476 ** directly address anywhere within the 64-bit host address space. When this register is all-zero,…
3480 ** -----------------------------------------------------------------
3482 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven d…
3488 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1
3495 ** -----------------------------------------------------------------
3497 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 int…
3499 ** 01:00 00 2 Burst Order - This bit field shows the address sequence…
3506 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1
3508 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines
3509 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to
3510 ** directly address anywhere within the 64-bit host address space. When this register is all-zero,…
3514 ** -----------------------------------------------------------------
3516 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven d…
3522 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR
3524 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the
3525 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addre…
3526 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host
3527 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus.
3528 ** -----------------------------------------------------------------
3530 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven d…
3536 ** ATU Configuration Register - ATUCR
3542 ** -----------------------------------------------------------------
3545 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish …
3548 ** applicable in the PCI-X mode.
3549 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - Wh…
3552 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH).
3555 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR…
3557 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 disca…
3560 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel X…
3563 ** 08 0 2 Direct Addressing Enable - Setting this bit enables dir…
3568 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interr…
3572 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound ad…
3580 ** PCI Configuration and Status Register - PCSR
3584 ** -----------------------------------------------------------------
3587 ** 18 0 2 Detected Address or Attribute Parity Error - set when a…
3590 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated …
3598 ** PCI-X capability - These two bits define the mode of
3599 ** the PCI bus (conventional or PCI-X) as well as the
3600 ** operating frequency in the case of PCI-X mode.
3601 ** 00 - Conventional PCI mode
3602 ** 01 - PCI-X 66
3603 ** 10 - PCI-X 100
3604 ** 11 - PCI-X 133
3605 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification,
3611 ** Deasserted Deasserted Asserted PCI-X 66
3612 ** Deasserted Asserted Deasserted PCI-X 100
3613 ** Deasserted Asserted Asserted PCI-X 133
3624 ** 12 0 2 Discard Timer Value - This bit controls the time-out value
3626 ** A value of 0 indicates the time-out valu…
3627 ** A value of 1 indicates the time-out valu…
3634 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66…
3638 …:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode.
3645 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been
3646 ** configured as 64-bit capable by
3649 ** 32-bit only.
3651 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale cor…
3672 ** When operating in the PCI-X mode:
3673 ** The ATU hardware responds the same as in Conventional PCI-X mode.
3674 ** However, this may create a problem in PCI-X mode for split requests in
3698 ** Private Device Enable - This bit indicates the state of the reset strap which enables the pr…
3699 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register.
3700 ** 0=Private Device control Disabled - SISR register bits default to zero
3701 ** 1=Private Device control Enabled - SISR register bits default to one
3703 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to…
3710 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RS…
3718 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the pr…
3719 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register.
3720 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero
3721 ** 1=Private Memory control Enabled - SDER register bits 2 default to one
3727 ** ATU Interrupt Status Register - ATUISR
3738 ** -----------------------------------------------------------------
3741 ** 17 0 2 VPD Address Register Updated - This bit is set when a P…
3745 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bu…
3747 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is …
3751 ** 13 0 2 Initiated Split Completion Error Message - This bit is …
3753 ** 12 0 2 Received Split Completion Error Message - This bit is s…
3755 ** 11 0 2 Power State Transition - When the Power State Field of …
3758 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the …
3759 ** 09 0 2 Detected Parity Error - set when a parity error is dete…
3763 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus.
3764 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST S…
3770 … Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator i…
3772 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the …
3773 … PCI Master Abort - set when a transaction initiated by the ATU PCI initiator inter…
3774 … PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interfa…
3775 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface,…
3776 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU…
3781 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message
3788 ** ATU Interrupt Mask Register - ATUIMR
3792 ** -----------------------------------------------------------------
3795 ** 14 0 2 VPD Address Register Updated Mask - Controls the settin…
3800 ** 12 0 2 Configuration Register Write Mask - Controls the settin…
3805 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Control…
3810 … Initiated Split Completion Error Message Interrupt Mask - Controls the setting…
3814 ** 09 0 2 Received Split Completion Error Message Interrupt Mask-…
3819 ** 08 1 2 Power State Transition Interrupt Mask - Controls the se…
3824 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the…
3828 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the settin…
3833 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the sett…
3837 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls …
3841 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls …
3845 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls t…
3849 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU …
3854 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response…
3861 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2…
3862 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus,
3869 ** Inbound ATU Base Address Register 3 - IABAR3
3878 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - …
3881 ** When a non-zero value is not written to IALR3,
3885 ** Assuming a non-zero value is written to IALR3,
3892 ** b. when the Prefetchable Indicator is set,
3894 ** -----------------------------------------------------------------
3896 ** 31:12 00000H Translation Base Address 3 - These bits define the actu…
3899 ** 03 0 2 Prefetchable Indicator - When set, defines the memory s…
3900 ** 02:01 00 2 Type Indicator - Defines the width of the addressabilit…
3901 ** 00 - Memory Window is locatable anywhere in 32 bit address space
3902 ** 10 - Memory Window is locatable anywhere in 64 bit address space
3903 ** 00 0 2 Memory Space Indicator - This bit field describes memor…
3911 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3
3920 ** the IAUBAR3 register attributes are read-only.
3922 ** -----------------------------------------------------------------
3924 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Tr…
3931 ** Inbound ATU Limit Register 3 - IALR3
3951 ** -----------------------------------------------------------------
3953 ** 31:12 00000H Inbound Translation Limit 3 - This readback value deter…
3961 ** Inbound ATU Translate Value Register 3 - IATVR3
3966 ** -----------------------------------------------------------------
3968 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to…
3969 ** This value must be 64-bit aligned on th…
3970 ** access the internal 80331 memory-mapped…
3977 ** Outbound Configuration Cycle Address Register - OCCAR
3979 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration
3985 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a
3986 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for
3988 … bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X
3990 ** -----------------------------------------------------------------
3992 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-…
3999 ** Outbound Configuration Cycle Data Register - OCCDR
4003 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to
4010 ** -----------------------------------------------------------------
4012 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data u…
4019 ** VPD Capability Identifier Register - VPD_CAPID
4025 ** -----------------------------------------------------------------
4027 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in …
4034 ** VPD Next Item Pointer Register - VPD_NXTP
4039 ** -----------------------------------------------------------------
4041 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the func…
4049 ** VPD Address Register - VPD_AR
4051 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be
4052 ** accessed. The register is read/write and the initial value at power-up is indeterminate.
4056 ** -----------------------------------------------------------------
4058 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the …
4061 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte a…
4068 ** VPD Data Register - VPD_DR
4071 ** -----------------------------------------------------------------
4073 ** 31:00 0000H VPD Data - Four bytes are always read or written throug…
4079 ** Power Management Capability Identifier Register -PM_CAPID
4086 ** -----------------------------------------------------------------
4088 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies thi…
4095 ** Power Management Next Item Pointer Register - PM_NXTP
4099 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H.
4100 ** -----------------------------------------------------------------
4102 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset int…
4109 ** Power Management Capabilities Register - PM_CAP
4112 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provi…
4114 ** -----------------------------------------------------------------
4116 ** 15:11 00000 2 PME_Support - This function is not capable of asserting…
4118 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the…
4119 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the…
4120 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating tha…
4122 ** 5 0 2 DSI - This field is set to 0 2 meaning that this functi…
4125 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signa…
4126 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this f…
4133 ** Power Management Control/Status Register - PM_CSR
4136 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status
4138 ** -----------------------------------------------------------------
4140 ** 15 0 2 PME_Status - This function is not capable of asserting …
4143 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since t…
4146 ** 1:0 00 2 Power State - This 2-bit field is used both to determin…
4148 ** 00 2 - D0
4149 ** 01 2 - D1
4150 ** 10 2 - D2 (Unsupported)
4151 ** 11 2 - D3 hot
4159 ** PCI-X Capability Identifier Register - PX_CAPID
4163 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capab…
4164 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
4165 ** -----------------------------------------------------------------
4167 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies thi…
4168 ** Headers as being the PCI-X capability registers.
4174 ** PCI-X Next Item Pointer Register - PX_NXTP
4178 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this registe…
4181 ** capability located at off-set B8H.
4187 …this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register -
4189 ** -----------------------------------------------------------------
4191 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset int…
4192 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in t…
4201 ** PCI-X Command Register - PX_CMD
4204 ** PCI-X mode.
4205 ** -----------------------------------------------------------------
4208 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register …
4219 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the…
4227 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester A…
4229 ** 0 0 2 Data Parity Error Recovery Enable - The device driver s…
4230 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the dev…
4237 ** PCI-X Status Register - PX_SR
4240 ** Unit when operating in the PCI-X mode.
4241 ** -----------------------------------------------------------------
4244 ** 29 0 2 Received Split Completion Error Message - This bit is s…
4249 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The val…
4256 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 8…
4257 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can…
4260 ** 19 0 2 Unexpected Split Completion - This bit is set when an u…
4264 ** 18 0 2 Split Completion Discarded - This bit is set when the d…
4265 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus
4271 ** Requests with Split Responses (Memory or Register) that has ��read side effects.��
4273 …_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the …
4276 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-c…
4278 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap.
4281 ** 15:8 FFH Bus Number - This register is read for diagnostic purpo…
4290 ** 3. AD[1::0] are 00b (Type 0 configuration transaction).
4292 ** 7:3 1FH Device Number - This register is read for diagnostic pu…
4303 ** 3. AD[1::0] are 00b (Type 0 configuration transaction).
4305 ** 2:0 000 2 Function Number - This register is read for diagnostic …
4319 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through
4323 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are
4333 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a
4350 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and
4353 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned
4355 ** before returning read data by generating the split completion transaction on the PCI-X bus.
4358 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it
4364 ** Message (message class=2h - completer error, and message index=81h - target abort) to
4368 ** Message (message class=2h - completer error, and message index=80h - Master abort) to
4376 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. Th…
4379 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h
4381 ** a Split Completion Message (message class=2h - completer error, and message index=81h -
4382 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU
4389 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a
4390 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer
4391 ** error, and message index=80h - internal bus master abort) to inform the requester about the
4393 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with
4394 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that
4396 ** addresses a location that has no read side effects, the completer must discard the Split
4401 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the
4415 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is
4417 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from
4419 ** Completion Message (message class=2h - completer error, and message index=81h -
4426 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from
4431 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the
4452 ** memory or a 80331 memory-mapped register.
4465 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute
4477 ** In the PCI-X mode memory writes are always executed as immediate transactions, while
4479 ** Completion Message, (with Message class=0h - Write Completion Class and Message index =
4480 ** 00h - Write Completion Message) once a configuration write is successfully executed.
4481 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transaction…
4492 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When
4493 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the
4494 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred
4501 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to
4525 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
4536 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode.
4547 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X m…
4553 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
4564 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
4569 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode)
4583 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes.
4620 ** PCI-X Mode
4629 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and
4630 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus
4648 ** As a target, the ATU may encounter this error when operating in the PCI-X mode.
4667 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during
4679 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on
4686 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331)
4688 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331
4700 **-------------------------------------------------------------------------------------------------…
4703 **-------------------------------------------------------------------------------------------------…
4706 **-------------------------------------------------------------------------------------------------…
4708 **-------------------------------------------------------------------------------------------------…
4709 ** Index Registers 1004 32-bit Memory Locations No Option…
4717 **------------------------------------------------------------------------
4722 **------------------------------------------------------------------------
4729 **------------------------------------------------------------------------
4732 **------------------------------------------------------------------------
4735 **------------------------------------------------------------------------
4738 **------------------------------------------------------------------------
4748 ** Theory of MU Operation
4750 **--------------------
4755 ** . The MU has four independent messaging mechanisms.
4757 ** Each holds a 32-bit value and generates an interrupt when written.
4758 **--------------------
4763 **--------------------
4772 **--------------------
4778 **--------------------
4779 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit,
4780 ** with the exception of Multi-DWORD reads to the index registers.
4781 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions
4783 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Resp…
4786 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately o…
4787 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect
4788 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#)…
4789 **--------------------
4790 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers.
4791 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation …
4794 **--------------------
4799 **--------------------
4800 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device.
4804 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert …
4819 ** -----------------
4824 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software.
4827 ** ------------------------------------------------------------------------
4828 ** Inbound Message Register - IMRx
4834 ** -----------------------------------------------------------------
4836 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by a…
4844 ** Outbound Message Register - OMRx
4845 ** --------------------------------
4852 ** 31:00 00000000H Outbound Message - This is 32-bit message written by th…
4870 ** ------------------
4883 ** ------------------------------------------------------------------------
4884 ** Inbound Doorbell Register - IDR
4892 ** ------------------------------------------------------------------------
4894 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the In…
4895 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Norm…
4902 ** Inbound Interrupt Status Register - IISR
4916 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware
4918 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set
4921 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware …
4927 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrup…
4929 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one
4932 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware w…
4933 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware w…
4946 ** Inbound Interrupt Mask Register - IIMR
4952 ** ------------------------------------------------------------------------
4955 …2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated b…
4957 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks …
4959 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the in…
4960 ** by the MU hardware when the Inbound Post Queue has been written.
4961 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error …
4963 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the inte…
4965 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inb…
4967 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set,
4981 ** Outbound Doorbell Register - ODR
4989 ** ----------------------------------------------------------------------
4994 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# …
4996 ** signal to be asserted or a Message-sig…
5000 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# …
5002 ** signal is asserted or a Message-signaled Interrupt is …
5010 ** Outbound Interrupt Status Register - OISR
5018 ** ----------------------------------------------------------------------
5021 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt …
5023 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when da…
5025 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at l…
5028 … 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when th…
5030 … 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when th…
5042 ** Outbound Interrupt Mask Register - OIMR
5049 ** ----------------------------------------------------------------------
5052 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the inter…
5054 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit…
5056 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit m…
5058 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit …
5060 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit m…
5082 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In
5126 ** does not cause the MU hardware to increment the queue pointers.
5134 ** Each entry in the queue is a 32-bit data value.
5136 ** . Multi-DWORD accesses to the circular queues are not allowed.
5137 ** Sub-DWORD accesses are promoted to DWORD accesses.
5154 ** The Queue size is determined by the Queue Size field in the MU Configuration Register.
5169 ** ------------------
5172 … pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware.
5174 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Re…
5175 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware inc…
5199 ** ------------------
5203 ** The tail pointer is maintained by the MU hardware.
5206 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer.
5210 ** the value of -1 (FFFF.FFFFH) is returned.
5211 ** When the queue was not empty and the MU succeeded in returning the data at the tail,
5212 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register.
5213 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate…
5214 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an i…
5216 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register
5218 …der to update the prefetch register when messages are added to the queue and it becomes non-empty,
5229 ** -------------------
5233 ** MU hardware. The head pointer is maintained by the Intel XScale core.
5234 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the
5238 ** pointers are equal and the head pointer was last updated by hardware), the value of -1
5239 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the
5240 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer
5242 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate
5243 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the
5246 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head
5248 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically
5265 ** -----------------------
5269 ** XScale core. The head pointer is maintained by the MU hardware.
5270 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the
5272 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free
5274 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal
5291 ** ----------------------
5296 … | NO | Yes, when queue is written | MU hardware | …
5299 … | NO | Intel XScale | MU hardware |
5303 ** ----------------------
5328 ** Once updated by the MU, the Index Address Register is not updated until the Index Register
5330 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the addres…
5333 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes.
5351 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address
5361 ** FFFF E350H MU Configuration Register |
5366 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address
5382 ** MU Configuration Register - MUCR FFFF.E350H
5384 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of o…
5389 ** ------------------------------------------------------------------------
5392 ** 05:01 00001 2 Circular Queue Size - This field determines the size of…
5394 ** �E 00001 2 - 4K Entries (16 Kbytes)
5395 ** �E 00010 2 - 8K Entries (32 Kbytes)
5396 ** �E 00100 2 - 16K Entries (64 Kbytes)
5397 ** �E 01000 2 - 32K Entries (128 Kbytes)
5398 ** �E 10000 2 - 64K Entries (256 Kbytes)
5399 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Ci…
5400 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but i…
5414 ** Queue Base Address Register - QBAR
5423 ** ------------------------------------------------------------------------
5425 ** 31:20 000H Queue Base Address - Local memory address of the circul…
5432 ** Inbound Free Head Pointer Register - IFHPR
5440 ** ------------------------------------------------------------------------
5442 ** 31:20 000H Queue Base Address - Local memory address of the circul…
5443 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the …
5450 ** Inbound Free Tail Pointer Register - IFTPR
5456 ** ------------------------------------------------------------------------
5458 ** 31:20 000H Queue Base Address - Local memory address of the circul…
5459 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the …
5466 ** Inbound Post Head Pointer Register - IPHPR
5472 ** ------------------------------------------------------------------------
5474 ** 31:20 000H Queue Base Address - Local memory address of the circul…
5475 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the …
5482 ** Inbound Post Tail Pointer Register - IPTPR
5488 ** ------------------------------------------------------------------------
5490 ** 31:20 000H Queue Base Address - Local memory address of the circul…
5491 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the …
5498 ** Index Address Register - IAR
5501 ** It is written by the MU when the Index Registers are written by a PCI agent.
5505 ** ------------------------------------------------------------------------
5508 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index…
5515 ** RS-232 Interface for Areca Raid Controller
5517 ** --------------------------------------------------------------------
5519 ** --------------------------------------------------------------------
5521 ** (B) Command block : variable length of data including length, command code, data and checksu…
5523 ** --------------------------------------------------------------------
5525 ** --------------------------------------------------------------------
5527 ** (B) 2nd byte : command block length (high byte)
5532 ** --------------------------------------------------------------------
5534 ** --------------------------------------------------------------------
5535 ** The following are command code defined in raid controller Command code 0x10--0x1? are used f…
5537 ** Command code 0x20--0x?? always check the password, password must be entered to enable these …
5596 ** byte 4-0x13 : should be "ArEcATecHnoLogY"
5597 ** byte 0x14--0x23 : Serial number string (must be 16 bytes)
5602 ** byte 4-0x13 : should be "ArEcAvAr"
5603 ** byte 0x14--0x3B : vendor string (must be 40 bytes)
5608 ** byte 4-0x13 : should be "ArEcAvAr"
5609 ** byte 0x14--0x1B : model string (must be 8 bytes)
5618 ** byte 4-0x?? : user password to be checked
5628 ** byte 4-0x13 : should be "ArEcAvAr"
5629 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes)
5633 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo)
5729 ** byte 3 : drive # (from 0 to max-channels - 1)
5809 ** byte 3 : 0->disable, 1->enable
5815 ** byte 4 : password (must be alpha-numerical)
5820 ** byte 3 : 0->Independent, 1->cluster
5825 ** byte 3 : 0/1/2/3 (low->high)
5840 ** byte 3 : 0->COMA (term port), 1->COMB (debug port)
5862 ** byte 5 : scsi id (0-->15)
5863 ** byte 6 : scsi lun (0-->7)
5874 ** byte 5 : scsi id (0-->15)
5875 ** byte 6 : scsi lun (0-->7)
5897 ** byte 7-22 : raidset name (if byte 7 == 0:use default)
5909 …nge, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K )
5931 ** byte 4-19 : volume set name (if byte4 == 0, use default)
5932 ** byte 20-27 : volume capacity (blocks)
5934 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5940 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5941 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5948 ** byte 4-19 : new volume set name (if byte4 == 0, not change)
5949 ** byte 20-27 : new volume capacity (reserved)
5951 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K)
5957 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi)
5958 ** (0/1/2/3/4->33/66/100/133/150 for IDE )
5973 ** ---------------------------------------------------------------------
5975 ** ---------------------------------------------------------------------
5977 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte)